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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018-2020 Christoph Hellwig.
4 *
5 * DMA operations that map physical memory directly without using an IOMMU.
6 */
7#include <linux/memblock.h> /* for max_pfn */
8#include <linux/export.h>
9#include <linux/mm.h>
10#include <linux/dma-map-ops.h>
11#include <linux/scatterlist.h>
12#include <linux/pfn.h>
13#include <linux/vmalloc.h>
14#include <linux/set_memory.h>
15#include <linux/slab.h>
16#include "direct.h"
17
18/*
19 * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
20 * it for entirely different regions. In that case the arch code needs to
21 * override the variable below for dma-direct to work properly.
22 */
23unsigned int zone_dma_bits __ro_after_init = 24;
24
25static inline dma_addr_t phys_to_dma_direct(struct device *dev,
26 phys_addr_t phys)
27{
28 if (force_dma_unencrypted(dev))
29 return phys_to_dma_unencrypted(dev, phys);
30 return phys_to_dma(dev, phys);
31}
32
33static inline struct page *dma_direct_to_page(struct device *dev,
34 dma_addr_t dma_addr)
35{
36 return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
37}
38
39u64 dma_direct_get_required_mask(struct device *dev)
40{
41 phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
42 u64 max_dma = phys_to_dma_direct(dev, phys);
43
44 return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
45}
46
47static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 *phys_limit)
48{
49 u64 dma_limit = min_not_zero(
50 dev->coherent_dma_mask,
51 dev->bus_dma_limit);
52
53 /*
54 * Optimistically try the zone that the physical address mask falls
55 * into first. If that returns memory that isn't actually addressable
56 * we will fallback to the next lower zone and try again.
57 *
58 * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
59 * zones.
60 */
61 *phys_limit = dma_to_phys(dev, dma_limit);
62 if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
63 return GFP_DMA;
64 if (*phys_limit <= DMA_BIT_MASK(32))
65 return GFP_DMA32;
66 return 0;
67}
68
69bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
70{
71 dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
72
73 if (dma_addr == DMA_MAPPING_ERROR)
74 return false;
75 return dma_addr + size - 1 <=
76 min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
77}
78
79static int dma_set_decrypted(struct device *dev, void *vaddr, size_t size)
80{
81 if (!force_dma_unencrypted(dev))
82 return 0;
83 return set_memory_decrypted((unsigned long)vaddr, PFN_UP(size));
84}
85
86static int dma_set_encrypted(struct device *dev, void *vaddr, size_t size)
87{
88 int ret;
89
90 if (!force_dma_unencrypted(dev))
91 return 0;
92 ret = set_memory_encrypted((unsigned long)vaddr, PFN_UP(size));
93 if (ret)
94 pr_warn_ratelimited("leaking DMA memory that can't be re-encrypted\n");
95 return ret;
96}
97
98static void __dma_direct_free_pages(struct device *dev, struct page *page,
99 size_t size)
100{
101 if (swiotlb_free(dev, page, size))
102 return;
103 dma_free_contiguous(dev, page, size);
104}
105
106static struct page *dma_direct_alloc_swiotlb(struct device *dev, size_t size)
107{
108 struct page *page = swiotlb_alloc(dev, size);
109
110 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
111 swiotlb_free(dev, page, size);
112 return NULL;
113 }
114
115 return page;
116}
117
118static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
119 gfp_t gfp, bool allow_highmem)
120{
121 int node = dev_to_node(dev);
122 struct page *page = NULL;
123 u64 phys_limit;
124
125 WARN_ON_ONCE(!PAGE_ALIGNED(size));
126
127 if (is_swiotlb_for_alloc(dev))
128 return dma_direct_alloc_swiotlb(dev, size);
129
130 gfp |= dma_direct_optimal_gfp_mask(dev, &phys_limit);
131 page = dma_alloc_contiguous(dev, size, gfp);
132 if (page) {
133 if (!dma_coherent_ok(dev, page_to_phys(page), size) ||
134 (!allow_highmem && PageHighMem(page))) {
135 dma_free_contiguous(dev, page, size);
136 page = NULL;
137 }
138 }
139again:
140 if (!page)
141 page = alloc_pages_node(node, gfp, get_order(size));
142 if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
143 dma_free_contiguous(dev, page, size);
144 page = NULL;
145
146 if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
147 phys_limit < DMA_BIT_MASK(64) &&
148 !(gfp & (GFP_DMA32 | GFP_DMA))) {
149 gfp |= GFP_DMA32;
150 goto again;
151 }
152
153 if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
154 gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
155 goto again;
156 }
157 }
158
159 return page;
160}
161
162/*
163 * Check if a potentially blocking operations needs to dip into the atomic
164 * pools for the given device/gfp.
165 */
166static bool dma_direct_use_pool(struct device *dev, gfp_t gfp)
167{
168 return !gfpflags_allow_blocking(gfp) && !is_swiotlb_for_alloc(dev);
169}
170
171static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
172 dma_addr_t *dma_handle, gfp_t gfp)
173{
174 struct page *page;
175 u64 phys_limit;
176 void *ret;
177
178 if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_DMA_COHERENT_POOL)))
179 return NULL;
180
181 gfp |= dma_direct_optimal_gfp_mask(dev, &phys_limit);
182 page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
183 if (!page)
184 return NULL;
185 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
186 return ret;
187}
188
189static void *dma_direct_alloc_no_mapping(struct device *dev, size_t size,
190 dma_addr_t *dma_handle, gfp_t gfp)
191{
192 struct page *page;
193
194 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO, true);
195 if (!page)
196 return NULL;
197
198 /* remove any dirty cache lines on the kernel alias */
199 if (!PageHighMem(page))
200 arch_dma_prep_coherent(page, size);
201
202 /* return the page pointer as the opaque cookie */
203 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
204 return page;
205}
206
207void *dma_direct_alloc(struct device *dev, size_t size,
208 dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
209{
210 bool remap = false, set_uncached = false;
211 struct page *page;
212 void *ret;
213
214 size = PAGE_ALIGN(size);
215 if (attrs & DMA_ATTR_NO_WARN)
216 gfp |= __GFP_NOWARN;
217
218 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
219 !force_dma_unencrypted(dev) && !is_swiotlb_for_alloc(dev))
220 return dma_direct_alloc_no_mapping(dev, size, dma_handle, gfp);
221
222 if (!dev_is_dma_coherent(dev)) {
223 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_ALLOC) &&
224 !is_swiotlb_for_alloc(dev))
225 return arch_dma_alloc(dev, size, dma_handle, gfp,
226 attrs);
227
228 /*
229 * If there is a global pool, always allocate from it for
230 * non-coherent devices.
231 */
232 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL))
233 return dma_alloc_from_global_coherent(dev, size,
234 dma_handle);
235
236 /*
237 * Otherwise we require the architecture to either be able to
238 * mark arbitrary parts of the kernel direct mapping uncached,
239 * or remapped it uncached.
240 */
241 set_uncached = IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED);
242 remap = IS_ENABLED(CONFIG_DMA_DIRECT_REMAP);
243 if (!set_uncached && !remap) {
244 pr_warn_once("coherent DMA allocations not supported on this platform.\n");
245 return NULL;
246 }
247 }
248
249 /*
250 * Remapping or decrypting memory may block, allocate the memory from
251 * the atomic pools instead if we aren't allowed block.
252 */
253 if ((remap || force_dma_unencrypted(dev)) &&
254 dma_direct_use_pool(dev, gfp))
255 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
256
257 /* we always manually zero the memory once we are done */
258 page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO, true);
259 if (!page)
260 return NULL;
261
262 /*
263 * dma_alloc_contiguous can return highmem pages depending on a
264 * combination the cma= arguments and per-arch setup. These need to be
265 * remapped to return a kernel virtual address.
266 */
267 if (PageHighMem(page)) {
268 remap = true;
269 set_uncached = false;
270 }
271
272 if (remap) {
273 pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
274
275 if (force_dma_unencrypted(dev))
276 prot = pgprot_decrypted(prot);
277
278 /* remove any dirty cache lines on the kernel alias */
279 arch_dma_prep_coherent(page, size);
280
281 /* create a coherent mapping */
282 ret = dma_common_contiguous_remap(page, size, prot,
283 __builtin_return_address(0));
284 if (!ret)
285 goto out_free_pages;
286 } else {
287 ret = page_address(page);
288 if (dma_set_decrypted(dev, ret, size))
289 goto out_free_pages;
290 }
291
292 memset(ret, 0, size);
293
294 if (set_uncached) {
295 arch_dma_prep_coherent(page, size);
296 ret = arch_dma_set_uncached(ret, size);
297 if (IS_ERR(ret))
298 goto out_encrypt_pages;
299 }
300
301 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
302 return ret;
303
304out_encrypt_pages:
305 if (dma_set_encrypted(dev, page_address(page), size))
306 return NULL;
307out_free_pages:
308 __dma_direct_free_pages(dev, page, size);
309 return NULL;
310}
311
312void dma_direct_free(struct device *dev, size_t size,
313 void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
314{
315 unsigned int page_order = get_order(size);
316
317 if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
318 !force_dma_unencrypted(dev) && !is_swiotlb_for_alloc(dev)) {
319 /* cpu_addr is a struct page cookie, not a kernel address */
320 dma_free_contiguous(dev, cpu_addr, size);
321 return;
322 }
323
324 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_ALLOC) &&
325 !dev_is_dma_coherent(dev) &&
326 !is_swiotlb_for_alloc(dev)) {
327 arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
328 return;
329 }
330
331 if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
332 !dev_is_dma_coherent(dev)) {
333 if (!dma_release_from_global_coherent(page_order, cpu_addr))
334 WARN_ON_ONCE(1);
335 return;
336 }
337
338 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
339 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
340 dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
341 return;
342
343 if (is_vmalloc_addr(cpu_addr)) {
344 vunmap(cpu_addr);
345 } else {
346 if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
347 arch_dma_clear_uncached(cpu_addr, size);
348 if (dma_set_encrypted(dev, cpu_addr, size))
349 return;
350 }
351
352 __dma_direct_free_pages(dev, dma_direct_to_page(dev, dma_addr), size);
353}
354
355struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
356 dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
357{
358 struct page *page;
359 void *ret;
360
361 if (force_dma_unencrypted(dev) && dma_direct_use_pool(dev, gfp))
362 return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
363
364 page = __dma_direct_alloc_pages(dev, size, gfp, false);
365 if (!page)
366 return NULL;
367
368 ret = page_address(page);
369 if (dma_set_decrypted(dev, ret, size))
370 goto out_free_pages;
371 memset(ret, 0, size);
372 *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
373 return page;
374out_free_pages:
375 __dma_direct_free_pages(dev, page, size);
376 return NULL;
377}
378
379void dma_direct_free_pages(struct device *dev, size_t size,
380 struct page *page, dma_addr_t dma_addr,
381 enum dma_data_direction dir)
382{
383 void *vaddr = page_address(page);
384
385 /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
386 if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
387 dma_free_from_pool(dev, vaddr, size))
388 return;
389
390 if (dma_set_encrypted(dev, vaddr, size))
391 return;
392 __dma_direct_free_pages(dev, page, size);
393}
394
395#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
396 defined(CONFIG_SWIOTLB)
397void dma_direct_sync_sg_for_device(struct device *dev,
398 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
399{
400 struct scatterlist *sg;
401 int i;
402
403 for_each_sg(sgl, sg, nents, i) {
404 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
405
406 if (unlikely(is_swiotlb_buffer(dev, paddr)))
407 swiotlb_sync_single_for_device(dev, paddr, sg->length,
408 dir);
409
410 if (!dev_is_dma_coherent(dev))
411 arch_sync_dma_for_device(paddr, sg->length,
412 dir);
413 }
414}
415#endif
416
417#if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
418 defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
419 defined(CONFIG_SWIOTLB)
420void dma_direct_sync_sg_for_cpu(struct device *dev,
421 struct scatterlist *sgl, int nents, enum dma_data_direction dir)
422{
423 struct scatterlist *sg;
424 int i;
425
426 for_each_sg(sgl, sg, nents, i) {
427 phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
428
429 if (!dev_is_dma_coherent(dev))
430 arch_sync_dma_for_cpu(paddr, sg->length, dir);
431
432 if (unlikely(is_swiotlb_buffer(dev, paddr)))
433 swiotlb_sync_single_for_cpu(dev, paddr, sg->length,
434 dir);
435
436 if (dir == DMA_FROM_DEVICE)
437 arch_dma_mark_clean(paddr, sg->length);
438 }
439
440 if (!dev_is_dma_coherent(dev))
441 arch_sync_dma_for_cpu_all();
442}
443
444/*
445 * Unmaps segments, except for ones marked as pci_p2pdma which do not
446 * require any further action as they contain a bus address.
447 */
448void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
449 int nents, enum dma_data_direction dir, unsigned long attrs)
450{
451 struct scatterlist *sg;
452 int i;
453
454 for_each_sg(sgl, sg, nents, i) {
455 if (sg_dma_is_bus_address(sg))
456 sg_dma_unmark_bus_address(sg);
457 else
458 dma_direct_unmap_page(dev, sg->dma_address,
459 sg_dma_len(sg), dir, attrs);
460 }
461}
462#endif
463
464int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
465 enum dma_data_direction dir, unsigned long attrs)
466{
467 struct pci_p2pdma_map_state p2pdma_state = {};
468 enum pci_p2pdma_map_type map;
469 struct scatterlist *sg;
470 int i, ret;
471
472 for_each_sg(sgl, sg, nents, i) {
473 if (is_pci_p2pdma_page(sg_page(sg))) {
474 map = pci_p2pdma_map_segment(&p2pdma_state, dev, sg);
475 switch (map) {
476 case PCI_P2PDMA_MAP_BUS_ADDR:
477 continue;
478 case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
479 /*
480 * Any P2P mapping that traverses the PCI
481 * host bridge must be mapped with CPU physical
482 * address and not PCI bus addresses. This is
483 * done with dma_direct_map_page() below.
484 */
485 break;
486 default:
487 ret = -EREMOTEIO;
488 goto out_unmap;
489 }
490 }
491
492 sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
493 sg->offset, sg->length, dir, attrs);
494 if (sg->dma_address == DMA_MAPPING_ERROR) {
495 ret = -EIO;
496 goto out_unmap;
497 }
498 sg_dma_len(sg) = sg->length;
499 }
500
501 return nents;
502
503out_unmap:
504 dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
505 return ret;
506}
507
508dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
509 size_t size, enum dma_data_direction dir, unsigned long attrs)
510{
511 dma_addr_t dma_addr = paddr;
512
513 if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
514 dev_err_once(dev,
515 "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
516 &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
517 WARN_ON_ONCE(1);
518 return DMA_MAPPING_ERROR;
519 }
520
521 return dma_addr;
522}
523
524int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
525 void *cpu_addr, dma_addr_t dma_addr, size_t size,
526 unsigned long attrs)
527{
528 struct page *page = dma_direct_to_page(dev, dma_addr);
529 int ret;
530
531 ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
532 if (!ret)
533 sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
534 return ret;
535}
536
537bool dma_direct_can_mmap(struct device *dev)
538{
539 return dev_is_dma_coherent(dev) ||
540 IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
541}
542
543int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
544 void *cpu_addr, dma_addr_t dma_addr, size_t size,
545 unsigned long attrs)
546{
547 unsigned long user_count = vma_pages(vma);
548 unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
549 unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
550 int ret = -ENXIO;
551
552 vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
553 if (force_dma_unencrypted(dev))
554 vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
555
556 if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
557 return ret;
558 if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
559 return ret;
560
561 if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
562 return -ENXIO;
563 return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
564 user_count << PAGE_SHIFT, vma->vm_page_prot);
565}
566
567int dma_direct_supported(struct device *dev, u64 mask)
568{
569 u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
570
571 /*
572 * Because 32-bit DMA masks are so common we expect every architecture
573 * to be able to satisfy them - either by not supporting more physical
574 * memory, or by providing a ZONE_DMA32. If neither is the case, the
575 * architecture needs to use an IOMMU instead of the direct mapping.
576 */
577 if (mask >= DMA_BIT_MASK(32))
578 return 1;
579
580 /*
581 * This check needs to be against the actual bit mask value, so use
582 * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
583 * part of the check.
584 */
585 if (IS_ENABLED(CONFIG_ZONE_DMA))
586 min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
587 return mask >= phys_to_dma_unencrypted(dev, min_mask);
588}
589
590/*
591 * To check whether all ram resource ranges are covered by dma range map
592 * Returns 0 when further check is needed
593 * Returns 1 if there is some RAM range can't be covered by dma_range_map
594 */
595static int check_ram_in_range_map(unsigned long start_pfn,
596 unsigned long nr_pages, void *data)
597{
598 unsigned long end_pfn = start_pfn + nr_pages;
599 const struct bus_dma_region *bdr = NULL;
600 const struct bus_dma_region *m;
601 struct device *dev = data;
602
603 while (start_pfn < end_pfn) {
604 for (m = dev->dma_range_map; PFN_DOWN(m->size); m++) {
605 unsigned long cpu_start_pfn = PFN_DOWN(m->cpu_start);
606
607 if (start_pfn >= cpu_start_pfn &&
608 start_pfn - cpu_start_pfn < PFN_DOWN(m->size)) {
609 bdr = m;
610 break;
611 }
612 }
613 if (!bdr)
614 return 1;
615
616 start_pfn = PFN_DOWN(bdr->cpu_start) + PFN_DOWN(bdr->size);
617 }
618
619 return 0;
620}
621
622bool dma_direct_all_ram_mapped(struct device *dev)
623{
624 if (!dev->dma_range_map)
625 return true;
626 return !walk_system_ram_range(0, PFN_DOWN(ULONG_MAX) + 1, dev,
627 check_ram_in_range_map);
628}
629
630size_t dma_direct_max_mapping_size(struct device *dev)
631{
632 /* If SWIOTLB is active, use its maximum mapping size */
633 if (is_swiotlb_active(dev) &&
634 (dma_addressing_limited(dev) || is_swiotlb_force_bounce(dev)))
635 return swiotlb_max_mapping_size(dev);
636 return SIZE_MAX;
637}
638
639bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
640{
641 return !dev_is_dma_coherent(dev) ||
642 is_swiotlb_buffer(dev, dma_to_phys(dev, dma_addr));
643}
644
645/**
646 * dma_direct_set_offset - Assign scalar offset for a single DMA range.
647 * @dev: device pointer; needed to "own" the alloced memory.
648 * @cpu_start: beginning of memory region covered by this offset.
649 * @dma_start: beginning of DMA/PCI region covered by this offset.
650 * @size: size of the region.
651 *
652 * This is for the simple case of a uniform offset which cannot
653 * be discovered by "dma-ranges".
654 *
655 * It returns -ENOMEM if out of memory, -EINVAL if a map
656 * already exists, 0 otherwise.
657 *
658 * Note: any call to this from a driver is a bug. The mapping needs
659 * to be described by the device tree or other firmware interfaces.
660 */
661int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
662 dma_addr_t dma_start, u64 size)
663{
664 struct bus_dma_region *map;
665 u64 offset = (u64)cpu_start - (u64)dma_start;
666
667 if (dev->dma_range_map) {
668 dev_err(dev, "attempt to add DMA range to existing map\n");
669 return -EINVAL;
670 }
671
672 if (!offset)
673 return 0;
674
675 map = kcalloc(2, sizeof(*map), GFP_KERNEL);
676 if (!map)
677 return -ENOMEM;
678 map[0].cpu_start = cpu_start;
679 map[0].dma_start = dma_start;
680 map[0].size = size;
681 dev->dma_range_map = map;
682 return 0;
683}