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1/* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _CORESIGHT_PRIV_H
14#define _CORESIGHT_PRIV_H
15
16#include <linux/bitops.h>
17#include <linux/io.h>
18#include <linux/coresight.h>
19
20/*
21 * Coresight management registers (0xf00-0xfcc)
22 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
23 * Trace registers in PFTv1.1
24 */
25#define CORESIGHT_ITCTRL 0xf00
26#define CORESIGHT_CLAIMSET 0xfa0
27#define CORESIGHT_CLAIMCLR 0xfa4
28#define CORESIGHT_LAR 0xfb0
29#define CORESIGHT_LSR 0xfb4
30#define CORESIGHT_AUTHSTATUS 0xfb8
31#define CORESIGHT_DEVID 0xfc8
32#define CORESIGHT_DEVTYPE 0xfcc
33
34#define TIMEOUT_US 100
35#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
36
37#define ETM_MODE_EXCL_KERN BIT(30)
38#define ETM_MODE_EXCL_USER BIT(31)
39
40enum cs_mode {
41 CS_MODE_DISABLED,
42 CS_MODE_SYSFS,
43 CS_MODE_PERF,
44};
45
46static inline void CS_LOCK(void __iomem *addr)
47{
48 do {
49 /* Wait for things to settle */
50 mb();
51 writel_relaxed(0x0, addr + CORESIGHT_LAR);
52 } while (0);
53}
54
55static inline void CS_UNLOCK(void __iomem *addr)
56{
57 do {
58 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
59 /* Make sure everyone has seen this */
60 mb();
61 } while (0);
62}
63
64void coresight_disable_path(struct list_head *path);
65int coresight_enable_path(struct list_head *path, u32 mode);
66struct coresight_device *coresight_get_sink(struct list_head *path);
67struct list_head *coresight_build_path(struct coresight_device *csdev);
68void coresight_release_path(struct list_head *path);
69
70#ifdef CONFIG_CORESIGHT_SOURCE_ETM3X
71extern int etm_readl_cp14(u32 off, unsigned int *val);
72extern int etm_writel_cp14(u32 off, u32 val);
73#else
74static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
75static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
76#endif
77
78#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _CORESIGHT_PRIV_H
7#define _CORESIGHT_PRIV_H
8
9#include <linux/amba/bus.h>
10#include <linux/bitops.h>
11#include <linux/io.h>
12#include <linux/coresight.h>
13#include <linux/pm_runtime.h>
14
15/*
16 * Coresight management registers (0xf00-0xfcc)
17 * 0xfa0 - 0xfa4: Management registers in PFTv1.0
18 * Trace registers in PFTv1.1
19 */
20#define CORESIGHT_ITCTRL 0xf00
21#define CORESIGHT_CLAIMSET 0xfa0
22#define CORESIGHT_CLAIMCLR 0xfa4
23#define CORESIGHT_LAR 0xfb0
24#define CORESIGHT_LSR 0xfb4
25#define CORESIGHT_DEVARCH 0xfbc
26#define CORESIGHT_AUTHSTATUS 0xfb8
27#define CORESIGHT_DEVID 0xfc8
28#define CORESIGHT_DEVTYPE 0xfcc
29
30
31/*
32 * Coresight device CLAIM protocol.
33 * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and restore.
34 */
35#define CORESIGHT_CLAIM_SELF_HOSTED BIT(1)
36
37#define TIMEOUT_US 100
38#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
39
40#define ETM_MODE_EXCL_KERN BIT(30)
41#define ETM_MODE_EXCL_USER BIT(31)
42struct cs_pair_attribute {
43 struct device_attribute attr;
44 u32 lo_off;
45 u32 hi_off;
46};
47
48struct cs_off_attribute {
49 struct device_attribute attr;
50 u32 off;
51};
52
53extern ssize_t coresight_simple_show32(struct device *_dev,
54 struct device_attribute *attr, char *buf);
55extern ssize_t coresight_simple_show_pair(struct device *_dev,
56 struct device_attribute *attr, char *buf);
57
58#define coresight_simple_reg32(name, offset) \
59 (&((struct cs_off_attribute[]) { \
60 { \
61 __ATTR(name, 0444, coresight_simple_show32, NULL), \
62 offset \
63 } \
64 })[0].attr.attr)
65
66#define coresight_simple_reg64(name, lo_off, hi_off) \
67 (&((struct cs_pair_attribute[]) { \
68 { \
69 __ATTR(name, 0444, coresight_simple_show_pair, NULL), \
70 lo_off, hi_off \
71 } \
72 })[0].attr.attr)
73
74extern const u32 coresight_barrier_pkt[4];
75#define CORESIGHT_BARRIER_PKT_SIZE (sizeof(coresight_barrier_pkt))
76
77enum etm_addr_type {
78 ETM_ADDR_TYPE_NONE,
79 ETM_ADDR_TYPE_SINGLE,
80 ETM_ADDR_TYPE_RANGE,
81 ETM_ADDR_TYPE_START,
82 ETM_ADDR_TYPE_STOP,
83};
84
85/**
86 * struct cs_buffer - keep track of a recording session' specifics
87 * @cur: index of the current buffer
88 * @nr_pages: max number of pages granted to us
89 * @pid: PID this cs_buffer belongs to
90 * @offset: offset within the current buffer
91 * @data_size: how much we collected in this run
92 * @snapshot: is this run in snapshot mode
93 * @data_pages: a handle the ring buffer
94 */
95struct cs_buffers {
96 unsigned int cur;
97 unsigned int nr_pages;
98 pid_t pid;
99 unsigned long offset;
100 local_t data_size;
101 bool snapshot;
102 void **data_pages;
103};
104
105static inline void coresight_insert_barrier_packet(void *buf)
106{
107 if (buf)
108 memcpy(buf, coresight_barrier_pkt, CORESIGHT_BARRIER_PKT_SIZE);
109}
110
111static inline void CS_LOCK(void __iomem *addr)
112{
113 do {
114 /* Wait for things to settle */
115 mb();
116 writel_relaxed(0x0, addr + CORESIGHT_LAR);
117 } while (0);
118}
119
120static inline void CS_UNLOCK(void __iomem *addr)
121{
122 do {
123 writel_relaxed(CORESIGHT_UNLOCK, addr + CORESIGHT_LAR);
124 /* Make sure everyone has seen this */
125 mb();
126 } while (0);
127}
128
129void coresight_disable_path(struct list_head *path);
130int coresight_enable_path(struct list_head *path, enum cs_mode mode,
131 void *sink_data);
132struct coresight_device *coresight_get_sink(struct list_head *path);
133struct coresight_device *
134coresight_get_enabled_sink(struct coresight_device *source);
135struct coresight_device *coresight_get_sink_by_id(u32 id);
136struct coresight_device *
137coresight_find_default_sink(struct coresight_device *csdev);
138struct list_head *coresight_build_path(struct coresight_device *csdev,
139 struct coresight_device *sink);
140void coresight_release_path(struct list_head *path);
141int coresight_add_sysfs_link(struct coresight_sysfs_link *info);
142void coresight_remove_sysfs_link(struct coresight_sysfs_link *info);
143int coresight_create_conns_sysfs_group(struct coresight_device *csdev);
144void coresight_remove_conns_sysfs_group(struct coresight_device *csdev);
145int coresight_make_links(struct coresight_device *orig,
146 struct coresight_connection *conn,
147 struct coresight_device *target);
148void coresight_remove_links(struct coresight_device *orig,
149 struct coresight_connection *conn);
150
151#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X)
152extern int etm_readl_cp14(u32 off, unsigned int *val);
153extern int etm_writel_cp14(u32 off, u32 val);
154#else
155static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
156static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
157#endif
158
159struct cti_assoc_op {
160 void (*add)(struct coresight_device *csdev);
161 void (*remove)(struct coresight_device *csdev);
162};
163
164extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op);
165extern void coresight_remove_cti_ops(void);
166
167/*
168 * Macros and inline functions to handle CoreSight UCI data and driver
169 * private data in AMBA ID table entries, and extract data values.
170 */
171
172/* coresight AMBA ID, no UCI, no driver data: id table entry */
173#define CS_AMBA_ID(pid) \
174 { \
175 .id = pid, \
176 .mask = 0x000fffff, \
177 }
178
179/* coresight AMBA ID, UCI with driver data only: id table entry. */
180#define CS_AMBA_ID_DATA(pid, dval) \
181 { \
182 .id = pid, \
183 .mask = 0x000fffff, \
184 .data = (void *)&(struct amba_cs_uci_id) \
185 { \
186 .data = (void *)dval, \
187 } \
188 }
189
190/* coresight AMBA ID, full UCI structure: id table entry. */
191#define __CS_AMBA_UCI_ID(pid, m, uci_ptr) \
192 { \
193 .id = pid, \
194 .mask = m, \
195 .data = (void *)uci_ptr \
196 }
197#define CS_AMBA_UCI_ID(pid, uci) __CS_AMBA_UCI_ID(pid, 0x000fffff, uci)
198/*
199 * PIDR2[JEDEC], BIT(3) must be 1 (Read As One) to indicate that rest of the
200 * PIDR1, PIDR2 DES_* fields follow JEDEC encoding for the designer. Use that
201 * as a match value for blanket matching all devices in the given CoreSight
202 * device type and architecture.
203 */
204#define PIDR2_JEDEC BIT(3)
205#define PID_PIDR2_JEDEC (PIDR2_JEDEC << 16)
206/*
207 * Match all PIDs in a given CoreSight device type and architecture, defined
208 * by the uci.
209 */
210#define CS_AMBA_MATCH_ALL_UCI(uci) \
211 __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
212
213/* extract the data value from a UCI structure given amba_id pointer. */
214static inline void *coresight_get_uci_data(const struct amba_id *id)
215{
216 struct amba_cs_uci_id *uci_id = id->data;
217
218 if (!uci_id)
219 return NULL;
220
221 return uci_id->data;
222}
223
224void coresight_release_platform_data(struct coresight_device *csdev,
225 struct device *dev,
226 struct coresight_platform_data *pdata);
227struct coresight_device *
228coresight_find_csdev_by_fwnode(struct fwnode_handle *r_fwnode);
229void coresight_add_helper(struct coresight_device *csdev,
230 struct coresight_device *helper);
231
232void coresight_set_percpu_sink(int cpu, struct coresight_device *csdev);
233struct coresight_device *coresight_get_percpu_sink(int cpu);
234int coresight_enable_source(struct coresight_device *csdev, enum cs_mode mode,
235 void *data);
236bool coresight_disable_source(struct coresight_device *csdev, void *data);
237
238#endif