Loading...
1/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef _CORESIGHT_CORESIGHT_ETM_H
14#define _CORESIGHT_CORESIGHT_ETM_H
15
16#include <linux/spinlock.h>
17#include "coresight-priv.h"
18
19/*
20 * Device registers:
21 * 0x000 - 0x2FC: Trace registers
22 * 0x300 - 0x314: Management registers
23 * 0x318 - 0xEFC: Trace registers
24 * 0xF00: Management registers
25 * 0xFA0 - 0xFA4: Trace registers
26 * 0xFA8 - 0xFFC: Management registers
27 */
28/* Trace registers (0x000-0x2FC) */
29/* Main control and configuration registers */
30#define TRCPRGCTLR 0x004
31#define TRCPROCSELR 0x008
32#define TRCSTATR 0x00C
33#define TRCCONFIGR 0x010
34#define TRCAUXCTLR 0x018
35#define TRCEVENTCTL0R 0x020
36#define TRCEVENTCTL1R 0x024
37#define TRCSTALLCTLR 0x02C
38#define TRCTSCTLR 0x030
39#define TRCSYNCPR 0x034
40#define TRCCCCTLR 0x038
41#define TRCBBCTLR 0x03C
42#define TRCTRACEIDR 0x040
43#define TRCQCTLR 0x044
44/* Filtering control registers */
45#define TRCVICTLR 0x080
46#define TRCVIIECTLR 0x084
47#define TRCVISSCTLR 0x088
48#define TRCVIPCSSCTLR 0x08C
49#define TRCVDCTLR 0x0A0
50#define TRCVDSACCTLR 0x0A4
51#define TRCVDARCCTLR 0x0A8
52/* Derived resources registers */
53#define TRCSEQEVRn(n) (0x100 + (n * 4))
54#define TRCSEQRSTEVR 0x118
55#define TRCSEQSTR 0x11C
56#define TRCEXTINSELR 0x120
57#define TRCCNTRLDVRn(n) (0x140 + (n * 4))
58#define TRCCNTCTLRn(n) (0x150 + (n * 4))
59#define TRCCNTVRn(n) (0x160 + (n * 4))
60/* ID registers */
61#define TRCIDR8 0x180
62#define TRCIDR9 0x184
63#define TRCIDR10 0x188
64#define TRCIDR11 0x18C
65#define TRCIDR12 0x190
66#define TRCIDR13 0x194
67#define TRCIMSPEC0 0x1C0
68#define TRCIMSPECn(n) (0x1C0 + (n * 4))
69#define TRCIDR0 0x1E0
70#define TRCIDR1 0x1E4
71#define TRCIDR2 0x1E8
72#define TRCIDR3 0x1EC
73#define TRCIDR4 0x1F0
74#define TRCIDR5 0x1F4
75#define TRCIDR6 0x1F8
76#define TRCIDR7 0x1FC
77/* Resource selection registers */
78#define TRCRSCTLRn(n) (0x200 + (n * 4))
79/* Single-shot comparator registers */
80#define TRCSSCCRn(n) (0x280 + (n * 4))
81#define TRCSSCSRn(n) (0x2A0 + (n * 4))
82#define TRCSSPCICRn(n) (0x2C0 + (n * 4))
83/* Management registers (0x300-0x314) */
84#define TRCOSLAR 0x300
85#define TRCOSLSR 0x304
86#define TRCPDCR 0x310
87#define TRCPDSR 0x314
88/* Trace registers (0x318-0xEFC) */
89/* Comparator registers */
90#define TRCACVRn(n) (0x400 + (n * 8))
91#define TRCACATRn(n) (0x480 + (n * 8))
92#define TRCDVCVRn(n) (0x500 + (n * 16))
93#define TRCDVCMRn(n) (0x580 + (n * 16))
94#define TRCCIDCVRn(n) (0x600 + (n * 8))
95#define TRCVMIDCVRn(n) (0x640 + (n * 8))
96#define TRCCIDCCTLR0 0x680
97#define TRCCIDCCTLR1 0x684
98#define TRCVMIDCCTLR0 0x688
99#define TRCVMIDCCTLR1 0x68C
100/* Management register (0xF00) */
101/* Integration control registers */
102#define TRCITCTRL 0xF00
103/* Trace registers (0xFA0-0xFA4) */
104/* Claim tag registers */
105#define TRCCLAIMSET 0xFA0
106#define TRCCLAIMCLR 0xFA4
107/* Management registers (0xFA8-0xFFC) */
108#define TRCDEVAFF0 0xFA8
109#define TRCDEVAFF1 0xFAC
110#define TRCLAR 0xFB0
111#define TRCLSR 0xFB4
112#define TRCAUTHSTATUS 0xFB8
113#define TRCDEVARCH 0xFBC
114#define TRCDEVID 0xFC8
115#define TRCDEVTYPE 0xFCC
116#define TRCPIDR4 0xFD0
117#define TRCPIDR5 0xFD4
118#define TRCPIDR6 0xFD8
119#define TRCPIDR7 0xFDC
120#define TRCPIDR0 0xFE0
121#define TRCPIDR1 0xFE4
122#define TRCPIDR2 0xFE8
123#define TRCPIDR3 0xFEC
124#define TRCCIDR0 0xFF0
125#define TRCCIDR1 0xFF4
126#define TRCCIDR2 0xFF8
127#define TRCCIDR3 0xFFC
128
129/* ETMv4 resources */
130#define ETM_MAX_NR_PE 8
131#define ETMv4_MAX_CNTR 4
132#define ETM_MAX_SEQ_STATES 4
133#define ETM_MAX_EXT_INP_SEL 4
134#define ETM_MAX_EXT_INP 256
135#define ETM_MAX_EXT_OUT 4
136#define ETM_MAX_SINGLE_ADDR_CMP 16
137#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
138#define ETM_MAX_DATA_VAL_CMP 8
139#define ETMv4_MAX_CTXID_CMP 8
140#define ETM_MAX_VMID_CMP 8
141#define ETM_MAX_PE_CMP 8
142#define ETM_MAX_RES_SEL 16
143#define ETM_MAX_SS_CMP 8
144
145#define ETM_ARCH_V4 0x40
146#define ETMv4_SYNC_MASK 0x1F
147#define ETM_CYC_THRESHOLD_MASK 0xFFF
148#define ETMv4_EVENT_MASK 0xFF
149#define ETM_CNTR_MAX_VAL 0xFFFF
150#define ETM_TRACEID_MASK 0x3f
151
152/* ETMv4 programming modes */
153#define ETM_MODE_EXCLUDE BIT(0)
154#define ETM_MODE_LOAD BIT(1)
155#define ETM_MODE_STORE BIT(2)
156#define ETM_MODE_LOAD_STORE BIT(3)
157#define ETM_MODE_BB BIT(4)
158#define ETMv4_MODE_CYCACC BIT(5)
159#define ETMv4_MODE_CTXID BIT(6)
160#define ETM_MODE_VMID BIT(7)
161#define ETM_MODE_COND(val) BMVAL(val, 8, 10)
162#define ETMv4_MODE_TIMESTAMP BIT(11)
163#define ETM_MODE_RETURNSTACK BIT(12)
164#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
165#define ETM_MODE_DATA_TRACE_ADDR BIT(15)
166#define ETM_MODE_DATA_TRACE_VAL BIT(16)
167#define ETM_MODE_ISTALL BIT(17)
168#define ETM_MODE_DSTALL BIT(18)
169#define ETM_MODE_ATB_TRIGGER BIT(19)
170#define ETM_MODE_LPOVERRIDE BIT(20)
171#define ETM_MODE_ISTALL_EN BIT(21)
172#define ETM_MODE_DSTALL_EN BIT(22)
173#define ETM_MODE_INSTPRIO BIT(23)
174#define ETM_MODE_NOOVERFLOW BIT(24)
175#define ETM_MODE_TRACE_RESET BIT(25)
176#define ETM_MODE_TRACE_ERR BIT(26)
177#define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
178#define ETMv4_MODE_ALL 0xFFFFFFF
179
180#define TRCSTATR_IDLE_BIT 0
181
182/**
183 * struct etm4_drvdata - specifics associated to an ETM component
184 * @base: Memory mapped base address for this component.
185 * @dev: The device entity associated to this component.
186 * @csdev: Component vitals needed by the framework.
187 * @spinlock: Only one at a time pls.
188 * @cpu: The cpu this component is affined to.
189 * @arch: ETM version number.
190 * @enable: Is this ETM currently tracing.
191 * @sticky_enable: true if ETM base configuration has been done.
192 * @boot_enable:True if we should start tracing at boot time.
193 * @os_unlock: True if access to management registers is allowed.
194 * @nr_pe: The number of processing entity available for tracing.
195 * @nr_pe_cmp: The number of processing entity comparator inputs that are
196 * available for tracing.
197 * @nr_addr_cmp:Number of pairs of address comparators available
198 * as found in ETMIDR4 0-3.
199 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
200 * @nr_ext_inp: Number of external input.
201 * @numcidc: Number of contextID comparators.
202 * @numvmidc: Number of VMID comparators.
203 * @nrseqstate: The number of sequencer states that are implemented.
204 * @nr_event: Indicates how many events the trace unit support.
205 * @nr_resource:The number of resource selection pairs available for tracing.
206 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
207 * @mode: Controls various modes supported by this ETM.
208 * @trcid: value of the current ID for this component.
209 * @trcid_size: Indicates the trace ID width.
210 * @instrp0: Tracing of load and store instructions
211 * as P0 elements is supported.
212 * @trccond: If the trace unit supports conditional
213 * instruction tracing.
214 * @retstack: Indicates if the implementation supports a return stack.
215 * @trc_error: Whether a trace unit can trace a system
216 * error exception.
217 * @atbtrig: If the implementation can support ATB triggers
218 * @lpoverride: If the implementation can support low-power state over.
219 * @pe_sel: Controls which PE to trace.
220 * @cfg: Controls the tracing options.
221 * @eventctrl0: Controls the tracing of arbitrary events.
222 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
223 * @stallctl: If functionality that prevents trace unit buffer overflows
224 * is available.
225 * @sysstall: Does the system support stall control of the PE?
226 * @nooverflow: Indicate if overflow prevention is supported.
227 * @stall_ctrl: Enables trace unit functionality that prevents trace
228 * unit buffer overflows.
229 * @ts_size: Global timestamp size field.
230 * @ts_ctrl: Controls the insertion of global timestamps in the
231 * trace streams.
232 * @syncpr: Indicates if an implementation has a fixed
233 * synchronization period.
234 * @syncfreq: Controls how often trace synchronization requests occur.
235 * @trccci: Indicates if the trace unit supports cycle counting
236 * for instruction.
237 * @ccsize: Indicates the size of the cycle counter in bits.
238 * @ccitmin: minimum value that can be programmed in
239 * the TRCCCCTLR register.
240 * @ccctlr: Sets the threshold value for cycle counting.
241 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
242 * @q_support: Q element support characteristics.
243 * @vinst_ctrl: Controls instruction trace filtering.
244 * @viiectlr: Set or read, the address range comparators.
245 * @vissctlr: Set, or read, the single address comparators that control the
246 * ViewInst start-stop logic.
247 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
248 * ViewInst start-stop logic.
249 * @seq_idx: Sequencor index selector.
250 * @seq_ctrl: Control for the sequencer state transition control register.
251 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
252 * @seq_state: Set, or read the sequencer state.
253 * @cntr_idx: Counter index seletor.
254 * @cntrldvr: Sets or returns the reload count value for a counter.
255 * @cntr_ctrl: Controls the operation of a counter.
256 * @cntr_val: Sets or returns the value for a counter.
257 * @res_idx: Resource index selector.
258 * @res_ctrl: Controls the selection of the resources in the trace unit.
259 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
260 * @ss_status: The status of the corresponding single-shot comparator.
261 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
262 * @addr_idx: Address comparator index selector.
263 * @addr_val: Value for address comparator.
264 * @addr_acc: Address comparator access type.
265 * @addr_type: Current status of the comparator register.
266 * @ctxid_idx: Context ID index selector.
267 * @ctxid_size: Size of the context ID field to consider.
268 * @ctxid_pid: Value of the context ID comparator.
269 * @ctxid_vpid: Virtual PID seen by users if PID namespace is enabled, otherwise
270 * the same value of ctxid_pid.
271 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
272 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
273 * @vmid_idx: VM ID index selector.
274 * @vmid_size: Size of the VM ID comparator to consider.
275 * @vmid_val: Value of the VM ID comparator.
276 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
277 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
278 * @s_ex_level: In secure state, indicates whether instruction tracing is
279 * supported for the corresponding Exception level.
280 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
281 * supported for the corresponding Exception level.
282 * @ext_inp: External input selection.
283 */
284struct etmv4_drvdata {
285 void __iomem *base;
286 struct device *dev;
287 struct coresight_device *csdev;
288 spinlock_t spinlock;
289 int cpu;
290 u8 arch;
291 bool enable;
292 bool sticky_enable;
293 bool boot_enable;
294 bool os_unlock;
295 u8 nr_pe;
296 u8 nr_pe_cmp;
297 u8 nr_addr_cmp;
298 u8 nr_cntr;
299 u8 nr_ext_inp;
300 u8 numcidc;
301 u8 numvmidc;
302 u8 nrseqstate;
303 u8 nr_event;
304 u8 nr_resource;
305 u8 nr_ss_cmp;
306 u32 mode;
307 u8 trcid;
308 u8 trcid_size;
309 bool instrp0;
310 bool trccond;
311 bool retstack;
312 bool trc_error;
313 bool atbtrig;
314 bool lpoverride;
315 u32 pe_sel;
316 u32 cfg;
317 u32 eventctrl0;
318 u32 eventctrl1;
319 bool stallctl;
320 bool sysstall;
321 bool nooverflow;
322 u32 stall_ctrl;
323 u8 ts_size;
324 u32 ts_ctrl;
325 bool syncpr;
326 u32 syncfreq;
327 bool trccci;
328 u8 ccsize;
329 u8 ccitmin;
330 u32 ccctlr;
331 bool trcbb;
332 u32 bb_ctrl;
333 bool q_support;
334 u32 vinst_ctrl;
335 u32 viiectlr;
336 u32 vissctlr;
337 u32 vipcssctlr;
338 u8 seq_idx;
339 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
340 u32 seq_rst;
341 u32 seq_state;
342 u8 cntr_idx;
343 u32 cntrldvr[ETMv4_MAX_CNTR];
344 u32 cntr_ctrl[ETMv4_MAX_CNTR];
345 u32 cntr_val[ETMv4_MAX_CNTR];
346 u8 res_idx;
347 u32 res_ctrl[ETM_MAX_RES_SEL];
348 u32 ss_ctrl[ETM_MAX_SS_CMP];
349 u32 ss_status[ETM_MAX_SS_CMP];
350 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
351 u8 addr_idx;
352 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
353 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
354 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
355 u8 ctxid_idx;
356 u8 ctxid_size;
357 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
358 u64 ctxid_vpid[ETMv4_MAX_CTXID_CMP];
359 u32 ctxid_mask0;
360 u32 ctxid_mask1;
361 u8 vmid_idx;
362 u8 vmid_size;
363 u64 vmid_val[ETM_MAX_VMID_CMP];
364 u32 vmid_mask0;
365 u32 vmid_mask1;
366 u8 s_ex_level;
367 u8 ns_ex_level;
368 u32 ext_inp;
369};
370
371/* Address comparator access types */
372enum etm_addr_acctype {
373 ETM_INSTR_ADDR,
374 ETM_DATA_LOAD_ADDR,
375 ETM_DATA_STORE_ADDR,
376 ETM_DATA_LOAD_STORE_ADDR,
377};
378
379/* Address comparator context types */
380enum etm_addr_ctxtype {
381 ETM_CTX_NONE,
382 ETM_CTX_CTXID,
383 ETM_CTX_VMID,
384 ETM_CTX_CTXID_VMID,
385};
386
387enum etm_addr_type {
388 ETM_ADDR_TYPE_NONE,
389 ETM_ADDR_TYPE_SINGLE,
390 ETM_ADDR_TYPE_RANGE,
391 ETM_ADDR_TYPE_START,
392 ETM_ADDR_TYPE_STOP,
393};
394#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _CORESIGHT_CORESIGHT_ETM_H
7#define _CORESIGHT_CORESIGHT_ETM_H
8
9#include <asm/local.h>
10#include <linux/const.h>
11#include <linux/spinlock.h>
12#include <linux/types.h>
13#include "coresight-priv.h"
14
15/*
16 * Device registers:
17 * 0x000 - 0x2FC: Trace registers
18 * 0x300 - 0x314: Management registers
19 * 0x318 - 0xEFC: Trace registers
20 * 0xF00: Management registers
21 * 0xFA0 - 0xFA4: Trace registers
22 * 0xFA8 - 0xFFC: Management registers
23 */
24/* Trace registers (0x000-0x2FC) */
25/* Main control and configuration registers */
26#define TRCPRGCTLR 0x004
27#define TRCPROCSELR 0x008
28#define TRCSTATR 0x00C
29#define TRCCONFIGR 0x010
30#define TRCAUXCTLR 0x018
31#define TRCEVENTCTL0R 0x020
32#define TRCEVENTCTL1R 0x024
33#define TRCRSR 0x028
34#define TRCSTALLCTLR 0x02C
35#define TRCTSCTLR 0x030
36#define TRCSYNCPR 0x034
37#define TRCCCCTLR 0x038
38#define TRCBBCTLR 0x03C
39#define TRCTRACEIDR 0x040
40#define TRCQCTLR 0x044
41/* Filtering control registers */
42#define TRCVICTLR 0x080
43#define TRCVIIECTLR 0x084
44#define TRCVISSCTLR 0x088
45#define TRCVIPCSSCTLR 0x08C
46#define TRCVDCTLR 0x0A0
47#define TRCVDSACCTLR 0x0A4
48#define TRCVDARCCTLR 0x0A8
49/* Derived resources registers */
50#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */
51#define TRCSEQRSTEVR 0x118
52#define TRCSEQSTR 0x11C
53#define TRCEXTINSELR 0x120
54#define TRCEXTINSELRn(n) (0x120 + (n * 4)) /* n = 0-3 */
55#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */
56#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */
57#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */
58/* ID registers */
59#define TRCIDR8 0x180
60#define TRCIDR9 0x184
61#define TRCIDR10 0x188
62#define TRCIDR11 0x18C
63#define TRCIDR12 0x190
64#define TRCIDR13 0x194
65#define TRCIMSPEC0 0x1C0
66#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */
67#define TRCIDR0 0x1E0
68#define TRCIDR1 0x1E4
69#define TRCIDR2 0x1E8
70#define TRCIDR3 0x1EC
71#define TRCIDR4 0x1F0
72#define TRCIDR5 0x1F4
73#define TRCIDR6 0x1F8
74#define TRCIDR7 0x1FC
75/*
76 * Resource selection registers, n = 2-31.
77 * First pair (regs 0, 1) is always present and is reserved.
78 */
79#define TRCRSCTLRn(n) (0x200 + (n * 4))
80/* Single-shot comparator registers, n = 0-7 */
81#define TRCSSCCRn(n) (0x280 + (n * 4))
82#define TRCSSCSRn(n) (0x2A0 + (n * 4))
83#define TRCSSPCICRn(n) (0x2C0 + (n * 4))
84/* Management registers (0x300-0x314) */
85#define TRCOSLAR 0x300
86#define TRCOSLSR 0x304
87#define TRCPDCR 0x310
88#define TRCPDSR 0x314
89/* Trace registers (0x318-0xEFC) */
90/* Address Comparator registers n = 0-15 */
91#define TRCACVRn(n) (0x400 + (n * 8))
92#define TRCACATRn(n) (0x480 + (n * 8))
93/* Data Value Comparator Value registers, n = 0-7 */
94#define TRCDVCVRn(n) (0x500 + (n * 16))
95#define TRCDVCMRn(n) (0x580 + (n * 16))
96/* ContextID/Virtual ContextID comparators, n = 0-7 */
97#define TRCCIDCVRn(n) (0x600 + (n * 8))
98#define TRCVMIDCVRn(n) (0x640 + (n * 8))
99#define TRCCIDCCTLR0 0x680
100#define TRCCIDCCTLR1 0x684
101#define TRCVMIDCCTLR0 0x688
102#define TRCVMIDCCTLR1 0x68C
103/* Management register (0xF00) */
104/* Integration control registers */
105#define TRCITCTRL 0xF00
106/* Trace registers (0xFA0-0xFA4) */
107/* Claim tag registers */
108#define TRCCLAIMSET 0xFA0
109#define TRCCLAIMCLR 0xFA4
110/* Management registers (0xFA8-0xFFC) */
111#define TRCDEVAFF0 0xFA8
112#define TRCDEVAFF1 0xFAC
113#define TRCLAR 0xFB0
114#define TRCLSR 0xFB4
115#define TRCAUTHSTATUS 0xFB8
116#define TRCDEVARCH 0xFBC
117#define TRCDEVID 0xFC8
118#define TRCDEVTYPE 0xFCC
119#define TRCPIDR4 0xFD0
120#define TRCPIDR5 0xFD4
121#define TRCPIDR6 0xFD8
122#define TRCPIDR7 0xFDC
123#define TRCPIDR0 0xFE0
124#define TRCPIDR1 0xFE4
125#define TRCPIDR2 0xFE8
126#define TRCPIDR3 0xFEC
127#define TRCCIDR0 0xFF0
128#define TRCCIDR1 0xFF4
129#define TRCCIDR2 0xFF8
130#define TRCCIDR3 0xFFC
131
132#define TRCRSR_TA BIT(12)
133
134/*
135 * Bit positions of registers that are defined above, in the sysreg.h style
136 * of _MASK for multi bit fields and BIT() for single bits.
137 */
138#define TRCIDR0_INSTP0_MASK GENMASK(2, 1)
139#define TRCIDR0_TRCBB BIT(5)
140#define TRCIDR0_TRCCOND BIT(6)
141#define TRCIDR0_TRCCCI BIT(7)
142#define TRCIDR0_RETSTACK BIT(9)
143#define TRCIDR0_NUMEVENT_MASK GENMASK(11, 10)
144#define TRCIDR0_QSUPP_MASK GENMASK(16, 15)
145#define TRCIDR0_TSSIZE_MASK GENMASK(28, 24)
146
147#define TRCIDR2_CIDSIZE_MASK GENMASK(9, 5)
148#define TRCIDR2_VMIDSIZE_MASK GENMASK(14, 10)
149#define TRCIDR2_CCSIZE_MASK GENMASK(28, 25)
150
151#define TRCIDR3_CCITMIN_MASK GENMASK(11, 0)
152#define TRCIDR3_EXLEVEL_S_MASK GENMASK(19, 16)
153#define TRCIDR3_EXLEVEL_NS_MASK GENMASK(23, 20)
154#define TRCIDR3_TRCERR BIT(24)
155#define TRCIDR3_SYNCPR BIT(25)
156#define TRCIDR3_STALLCTL BIT(26)
157#define TRCIDR3_SYSSTALL BIT(27)
158#define TRCIDR3_NUMPROC_LO_MASK GENMASK(30, 28)
159#define TRCIDR3_NUMPROC_HI_MASK GENMASK(13, 12)
160#define TRCIDR3_NOOVERFLOW BIT(31)
161
162#define TRCIDR4_NUMACPAIRS_MASK GENMASK(3, 0)
163#define TRCIDR4_NUMPC_MASK GENMASK(15, 12)
164#define TRCIDR4_NUMRSPAIR_MASK GENMASK(19, 16)
165#define TRCIDR4_NUMSSCC_MASK GENMASK(23, 20)
166#define TRCIDR4_NUMCIDC_MASK GENMASK(27, 24)
167#define TRCIDR4_NUMVMIDC_MASK GENMASK(31, 28)
168
169#define TRCIDR5_NUMEXTIN_MASK GENMASK(8, 0)
170#define TRCIDR5_TRACEIDSIZE_MASK GENMASK(21, 16)
171#define TRCIDR5_ATBTRIG BIT(22)
172#define TRCIDR5_LPOVERRIDE BIT(23)
173#define TRCIDR5_NUMSEQSTATE_MASK GENMASK(27, 25)
174#define TRCIDR5_NUMCNTR_MASK GENMASK(30, 28)
175
176#define TRCCONFIGR_INSTP0_LOAD BIT(1)
177#define TRCCONFIGR_INSTP0_STORE BIT(2)
178#define TRCCONFIGR_INSTP0_LOAD_STORE (TRCCONFIGR_INSTP0_LOAD | TRCCONFIGR_INSTP0_STORE)
179#define TRCCONFIGR_BB BIT(3)
180#define TRCCONFIGR_CCI BIT(4)
181#define TRCCONFIGR_CID BIT(6)
182#define TRCCONFIGR_VMID BIT(7)
183#define TRCCONFIGR_COND_MASK GENMASK(10, 8)
184#define TRCCONFIGR_TS BIT(11)
185#define TRCCONFIGR_RS BIT(12)
186#define TRCCONFIGR_QE_W_COUNTS BIT(13)
187#define TRCCONFIGR_QE_WO_COUNTS BIT(14)
188#define TRCCONFIGR_VMIDOPT BIT(15)
189#define TRCCONFIGR_DA BIT(16)
190#define TRCCONFIGR_DV BIT(17)
191
192#define TRCEVENTCTL1R_INSTEN_MASK GENMASK(3, 0)
193#define TRCEVENTCTL1R_INSTEN_0 BIT(0)
194#define TRCEVENTCTL1R_INSTEN_1 BIT(1)
195#define TRCEVENTCTL1R_INSTEN_2 BIT(2)
196#define TRCEVENTCTL1R_INSTEN_3 BIT(3)
197#define TRCEVENTCTL1R_ATB BIT(11)
198#define TRCEVENTCTL1R_LPOVERRIDE BIT(12)
199
200#define TRCSTALLCTLR_ISTALL BIT(8)
201#define TRCSTALLCTLR_INSTPRIORITY BIT(10)
202#define TRCSTALLCTLR_NOOVERFLOW BIT(13)
203
204#define TRCVICTLR_EVENT_MASK GENMASK(7, 0)
205#define TRCVICTLR_SSSTATUS BIT(9)
206#define TRCVICTLR_TRCRESET BIT(10)
207#define TRCVICTLR_TRCERR BIT(11)
208#define TRCVICTLR_EXLEVEL_MASK GENMASK(22, 16)
209#define TRCVICTLR_EXLEVEL_S_MASK GENMASK(19, 16)
210#define TRCVICTLR_EXLEVEL_NS_MASK GENMASK(22, 20)
211
212#define TRCACATRn_TYPE_MASK GENMASK(1, 0)
213#define TRCACATRn_CONTEXTTYPE_MASK GENMASK(3, 2)
214#define TRCACATRn_CONTEXTTYPE_CTXID BIT(2)
215#define TRCACATRn_CONTEXTTYPE_VMID BIT(3)
216#define TRCACATRn_CONTEXT_MASK GENMASK(6, 4)
217#define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8)
218
219#define TRCSSCSRn_STATUS BIT(31)
220#define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0)
221
222#define TRCSSPCICRn_PC_MASK GENMASK(7, 0)
223
224#define TRCBBCTLR_MODE BIT(8)
225#define TRCBBCTLR_RANGE_MASK GENMASK(7, 0)
226
227#define TRCRSCTLRn_PAIRINV BIT(21)
228#define TRCRSCTLRn_INV BIT(20)
229#define TRCRSCTLRn_GROUP_MASK GENMASK(19, 16)
230#define TRCRSCTLRn_SELECT_MASK GENMASK(15, 0)
231
232/*
233 * System instructions to access ETM registers.
234 * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
235 */
236#define ETM4x_OFFSET_TO_REG(x) ((x) >> 2)
237
238#define ETM4x_CRn(n) (((n) >> 7) & 0x7)
239#define ETM4x_Op2(n) (((n) >> 4) & 0x7)
240#define ETM4x_CRm(n) ((n) & 0xf)
241
242#include <asm/sysreg.h>
243#define ETM4x_REG_NUM_TO_SYSREG(n) \
244 sys_reg(2, 1, ETM4x_CRn(n), ETM4x_CRm(n), ETM4x_Op2(n))
245
246#define READ_ETM4x_REG(reg) \
247 read_sysreg_s(ETM4x_REG_NUM_TO_SYSREG((reg)))
248#define WRITE_ETM4x_REG(val, reg) \
249 write_sysreg_s(val, ETM4x_REG_NUM_TO_SYSREG((reg)))
250
251#define read_etm4x_sysreg_const_offset(offset) \
252 READ_ETM4x_REG(ETM4x_OFFSET_TO_REG(offset))
253
254#define write_etm4x_sysreg_const_offset(val, offset) \
255 WRITE_ETM4x_REG(val, ETM4x_OFFSET_TO_REG(offset))
256
257#define CASE_READ(res, x) \
258 case (x): { (res) = read_etm4x_sysreg_const_offset((x)); break; }
259
260#define CASE_WRITE(val, x) \
261 case (x): { write_etm4x_sysreg_const_offset((val), (x)); break; }
262
263#define CASE_NOP(__unused, x) \
264 case (x): /* fall through */
265
266#define ETE_ONLY_SYSREG_LIST(op, val) \
267 CASE_##op((val), TRCRSR) \
268 CASE_##op((val), TRCEXTINSELRn(1)) \
269 CASE_##op((val), TRCEXTINSELRn(2)) \
270 CASE_##op((val), TRCEXTINSELRn(3))
271
272/* List of registers accessible via System instructions */
273#define ETM4x_ONLY_SYSREG_LIST(op, val) \
274 CASE_##op((val), TRCPROCSELR) \
275 CASE_##op((val), TRCVDCTLR) \
276 CASE_##op((val), TRCVDSACCTLR) \
277 CASE_##op((val), TRCVDARCCTLR) \
278 CASE_##op((val), TRCOSLAR)
279
280#define ETM_COMMON_SYSREG_LIST(op, val) \
281 CASE_##op((val), TRCPRGCTLR) \
282 CASE_##op((val), TRCSTATR) \
283 CASE_##op((val), TRCCONFIGR) \
284 CASE_##op((val), TRCAUXCTLR) \
285 CASE_##op((val), TRCEVENTCTL0R) \
286 CASE_##op((val), TRCEVENTCTL1R) \
287 CASE_##op((val), TRCSTALLCTLR) \
288 CASE_##op((val), TRCTSCTLR) \
289 CASE_##op((val), TRCSYNCPR) \
290 CASE_##op((val), TRCCCCTLR) \
291 CASE_##op((val), TRCBBCTLR) \
292 CASE_##op((val), TRCTRACEIDR) \
293 CASE_##op((val), TRCQCTLR) \
294 CASE_##op((val), TRCVICTLR) \
295 CASE_##op((val), TRCVIIECTLR) \
296 CASE_##op((val), TRCVISSCTLR) \
297 CASE_##op((val), TRCVIPCSSCTLR) \
298 CASE_##op((val), TRCSEQEVRn(0)) \
299 CASE_##op((val), TRCSEQEVRn(1)) \
300 CASE_##op((val), TRCSEQEVRn(2)) \
301 CASE_##op((val), TRCSEQRSTEVR) \
302 CASE_##op((val), TRCSEQSTR) \
303 CASE_##op((val), TRCEXTINSELR) \
304 CASE_##op((val), TRCCNTRLDVRn(0)) \
305 CASE_##op((val), TRCCNTRLDVRn(1)) \
306 CASE_##op((val), TRCCNTRLDVRn(2)) \
307 CASE_##op((val), TRCCNTRLDVRn(3)) \
308 CASE_##op((val), TRCCNTCTLRn(0)) \
309 CASE_##op((val), TRCCNTCTLRn(1)) \
310 CASE_##op((val), TRCCNTCTLRn(2)) \
311 CASE_##op((val), TRCCNTCTLRn(3)) \
312 CASE_##op((val), TRCCNTVRn(0)) \
313 CASE_##op((val), TRCCNTVRn(1)) \
314 CASE_##op((val), TRCCNTVRn(2)) \
315 CASE_##op((val), TRCCNTVRn(3)) \
316 CASE_##op((val), TRCIDR8) \
317 CASE_##op((val), TRCIDR9) \
318 CASE_##op((val), TRCIDR10) \
319 CASE_##op((val), TRCIDR11) \
320 CASE_##op((val), TRCIDR12) \
321 CASE_##op((val), TRCIDR13) \
322 CASE_##op((val), TRCIMSPECn(0)) \
323 CASE_##op((val), TRCIMSPECn(1)) \
324 CASE_##op((val), TRCIMSPECn(2)) \
325 CASE_##op((val), TRCIMSPECn(3)) \
326 CASE_##op((val), TRCIMSPECn(4)) \
327 CASE_##op((val), TRCIMSPECn(5)) \
328 CASE_##op((val), TRCIMSPECn(6)) \
329 CASE_##op((val), TRCIMSPECn(7)) \
330 CASE_##op((val), TRCIDR0) \
331 CASE_##op((val), TRCIDR1) \
332 CASE_##op((val), TRCIDR2) \
333 CASE_##op((val), TRCIDR3) \
334 CASE_##op((val), TRCIDR4) \
335 CASE_##op((val), TRCIDR5) \
336 CASE_##op((val), TRCIDR6) \
337 CASE_##op((val), TRCIDR7) \
338 CASE_##op((val), TRCRSCTLRn(2)) \
339 CASE_##op((val), TRCRSCTLRn(3)) \
340 CASE_##op((val), TRCRSCTLRn(4)) \
341 CASE_##op((val), TRCRSCTLRn(5)) \
342 CASE_##op((val), TRCRSCTLRn(6)) \
343 CASE_##op((val), TRCRSCTLRn(7)) \
344 CASE_##op((val), TRCRSCTLRn(8)) \
345 CASE_##op((val), TRCRSCTLRn(9)) \
346 CASE_##op((val), TRCRSCTLRn(10)) \
347 CASE_##op((val), TRCRSCTLRn(11)) \
348 CASE_##op((val), TRCRSCTLRn(12)) \
349 CASE_##op((val), TRCRSCTLRn(13)) \
350 CASE_##op((val), TRCRSCTLRn(14)) \
351 CASE_##op((val), TRCRSCTLRn(15)) \
352 CASE_##op((val), TRCRSCTLRn(16)) \
353 CASE_##op((val), TRCRSCTLRn(17)) \
354 CASE_##op((val), TRCRSCTLRn(18)) \
355 CASE_##op((val), TRCRSCTLRn(19)) \
356 CASE_##op((val), TRCRSCTLRn(20)) \
357 CASE_##op((val), TRCRSCTLRn(21)) \
358 CASE_##op((val), TRCRSCTLRn(22)) \
359 CASE_##op((val), TRCRSCTLRn(23)) \
360 CASE_##op((val), TRCRSCTLRn(24)) \
361 CASE_##op((val), TRCRSCTLRn(25)) \
362 CASE_##op((val), TRCRSCTLRn(26)) \
363 CASE_##op((val), TRCRSCTLRn(27)) \
364 CASE_##op((val), TRCRSCTLRn(28)) \
365 CASE_##op((val), TRCRSCTLRn(29)) \
366 CASE_##op((val), TRCRSCTLRn(30)) \
367 CASE_##op((val), TRCRSCTLRn(31)) \
368 CASE_##op((val), TRCSSCCRn(0)) \
369 CASE_##op((val), TRCSSCCRn(1)) \
370 CASE_##op((val), TRCSSCCRn(2)) \
371 CASE_##op((val), TRCSSCCRn(3)) \
372 CASE_##op((val), TRCSSCCRn(4)) \
373 CASE_##op((val), TRCSSCCRn(5)) \
374 CASE_##op((val), TRCSSCCRn(6)) \
375 CASE_##op((val), TRCSSCCRn(7)) \
376 CASE_##op((val), TRCSSCSRn(0)) \
377 CASE_##op((val), TRCSSCSRn(1)) \
378 CASE_##op((val), TRCSSCSRn(2)) \
379 CASE_##op((val), TRCSSCSRn(3)) \
380 CASE_##op((val), TRCSSCSRn(4)) \
381 CASE_##op((val), TRCSSCSRn(5)) \
382 CASE_##op((val), TRCSSCSRn(6)) \
383 CASE_##op((val), TRCSSCSRn(7)) \
384 CASE_##op((val), TRCSSPCICRn(0)) \
385 CASE_##op((val), TRCSSPCICRn(1)) \
386 CASE_##op((val), TRCSSPCICRn(2)) \
387 CASE_##op((val), TRCSSPCICRn(3)) \
388 CASE_##op((val), TRCSSPCICRn(4)) \
389 CASE_##op((val), TRCSSPCICRn(5)) \
390 CASE_##op((val), TRCSSPCICRn(6)) \
391 CASE_##op((val), TRCSSPCICRn(7)) \
392 CASE_##op((val), TRCOSLSR) \
393 CASE_##op((val), TRCACVRn(0)) \
394 CASE_##op((val), TRCACVRn(1)) \
395 CASE_##op((val), TRCACVRn(2)) \
396 CASE_##op((val), TRCACVRn(3)) \
397 CASE_##op((val), TRCACVRn(4)) \
398 CASE_##op((val), TRCACVRn(5)) \
399 CASE_##op((val), TRCACVRn(6)) \
400 CASE_##op((val), TRCACVRn(7)) \
401 CASE_##op((val), TRCACVRn(8)) \
402 CASE_##op((val), TRCACVRn(9)) \
403 CASE_##op((val), TRCACVRn(10)) \
404 CASE_##op((val), TRCACVRn(11)) \
405 CASE_##op((val), TRCACVRn(12)) \
406 CASE_##op((val), TRCACVRn(13)) \
407 CASE_##op((val), TRCACVRn(14)) \
408 CASE_##op((val), TRCACVRn(15)) \
409 CASE_##op((val), TRCACATRn(0)) \
410 CASE_##op((val), TRCACATRn(1)) \
411 CASE_##op((val), TRCACATRn(2)) \
412 CASE_##op((val), TRCACATRn(3)) \
413 CASE_##op((val), TRCACATRn(4)) \
414 CASE_##op((val), TRCACATRn(5)) \
415 CASE_##op((val), TRCACATRn(6)) \
416 CASE_##op((val), TRCACATRn(7)) \
417 CASE_##op((val), TRCACATRn(8)) \
418 CASE_##op((val), TRCACATRn(9)) \
419 CASE_##op((val), TRCACATRn(10)) \
420 CASE_##op((val), TRCACATRn(11)) \
421 CASE_##op((val), TRCACATRn(12)) \
422 CASE_##op((val), TRCACATRn(13)) \
423 CASE_##op((val), TRCACATRn(14)) \
424 CASE_##op((val), TRCACATRn(15)) \
425 CASE_##op((val), TRCDVCVRn(0)) \
426 CASE_##op((val), TRCDVCVRn(1)) \
427 CASE_##op((val), TRCDVCVRn(2)) \
428 CASE_##op((val), TRCDVCVRn(3)) \
429 CASE_##op((val), TRCDVCVRn(4)) \
430 CASE_##op((val), TRCDVCVRn(5)) \
431 CASE_##op((val), TRCDVCVRn(6)) \
432 CASE_##op((val), TRCDVCVRn(7)) \
433 CASE_##op((val), TRCDVCMRn(0)) \
434 CASE_##op((val), TRCDVCMRn(1)) \
435 CASE_##op((val), TRCDVCMRn(2)) \
436 CASE_##op((val), TRCDVCMRn(3)) \
437 CASE_##op((val), TRCDVCMRn(4)) \
438 CASE_##op((val), TRCDVCMRn(5)) \
439 CASE_##op((val), TRCDVCMRn(6)) \
440 CASE_##op((val), TRCDVCMRn(7)) \
441 CASE_##op((val), TRCCIDCVRn(0)) \
442 CASE_##op((val), TRCCIDCVRn(1)) \
443 CASE_##op((val), TRCCIDCVRn(2)) \
444 CASE_##op((val), TRCCIDCVRn(3)) \
445 CASE_##op((val), TRCCIDCVRn(4)) \
446 CASE_##op((val), TRCCIDCVRn(5)) \
447 CASE_##op((val), TRCCIDCVRn(6)) \
448 CASE_##op((val), TRCCIDCVRn(7)) \
449 CASE_##op((val), TRCVMIDCVRn(0)) \
450 CASE_##op((val), TRCVMIDCVRn(1)) \
451 CASE_##op((val), TRCVMIDCVRn(2)) \
452 CASE_##op((val), TRCVMIDCVRn(3)) \
453 CASE_##op((val), TRCVMIDCVRn(4)) \
454 CASE_##op((val), TRCVMIDCVRn(5)) \
455 CASE_##op((val), TRCVMIDCVRn(6)) \
456 CASE_##op((val), TRCVMIDCVRn(7)) \
457 CASE_##op((val), TRCCIDCCTLR0) \
458 CASE_##op((val), TRCCIDCCTLR1) \
459 CASE_##op((val), TRCVMIDCCTLR0) \
460 CASE_##op((val), TRCVMIDCCTLR1) \
461 CASE_##op((val), TRCCLAIMSET) \
462 CASE_##op((val), TRCCLAIMCLR) \
463 CASE_##op((val), TRCAUTHSTATUS) \
464 CASE_##op((val), TRCDEVARCH) \
465 CASE_##op((val), TRCDEVID)
466
467/* List of registers only accessible via memory-mapped interface */
468#define ETM_MMAP_LIST(op, val) \
469 CASE_##op((val), TRCDEVTYPE) \
470 CASE_##op((val), TRCPDCR) \
471 CASE_##op((val), TRCPDSR) \
472 CASE_##op((val), TRCDEVAFF0) \
473 CASE_##op((val), TRCDEVAFF1) \
474 CASE_##op((val), TRCLAR) \
475 CASE_##op((val), TRCLSR) \
476 CASE_##op((val), TRCITCTRL) \
477 CASE_##op((val), TRCPIDR4) \
478 CASE_##op((val), TRCPIDR0) \
479 CASE_##op((val), TRCPIDR1) \
480 CASE_##op((val), TRCPIDR2) \
481 CASE_##op((val), TRCPIDR3)
482
483#define ETM4x_READ_SYSREG_CASES(res) \
484 ETM_COMMON_SYSREG_LIST(READ, (res)) \
485 ETM4x_ONLY_SYSREG_LIST(READ, (res))
486
487#define ETM4x_WRITE_SYSREG_CASES(val) \
488 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
489 ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
490
491#define ETM_COMMON_SYSREG_LIST_CASES \
492 ETM_COMMON_SYSREG_LIST(NOP, __unused)
493
494#define ETM4x_ONLY_SYSREG_LIST_CASES \
495 ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
496
497#define ETM4x_SYSREG_LIST_CASES \
498 ETM_COMMON_SYSREG_LIST_CASES \
499 ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
500
501#define ETM4x_MMAP_LIST_CASES ETM_MMAP_LIST(NOP, __unused)
502
503/* ETE only supports system register access */
504#define ETE_READ_CASES(res) \
505 ETM_COMMON_SYSREG_LIST(READ, (res)) \
506 ETE_ONLY_SYSREG_LIST(READ, (res))
507
508#define ETE_WRITE_CASES(val) \
509 ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
510 ETE_ONLY_SYSREG_LIST(WRITE, (val))
511
512#define ETE_ONLY_SYSREG_LIST_CASES \
513 ETE_ONLY_SYSREG_LIST(NOP, __unused)
514
515#define read_etm4x_sysreg_offset(offset, _64bit) \
516 ({ \
517 u64 __val; \
518 \
519 if (__is_constexpr((offset))) \
520 __val = read_etm4x_sysreg_const_offset((offset)); \
521 else \
522 __val = etm4x_sysreg_read((offset), true, (_64bit)); \
523 __val; \
524 })
525
526#define write_etm4x_sysreg_offset(val, offset, _64bit) \
527 do { \
528 if (__builtin_constant_p((offset))) \
529 write_etm4x_sysreg_const_offset((val), \
530 (offset)); \
531 else \
532 etm4x_sysreg_write((val), (offset), true, \
533 (_64bit)); \
534 } while (0)
535
536
537#define etm4x_relaxed_read32(csa, offset) \
538 ((u32)((csa)->io_mem ? \
539 readl_relaxed((csa)->base + (offset)) : \
540 read_etm4x_sysreg_offset((offset), false)))
541
542#define etm4x_relaxed_read64(csa, offset) \
543 ((u64)((csa)->io_mem ? \
544 readq_relaxed((csa)->base + (offset)) : \
545 read_etm4x_sysreg_offset((offset), true)))
546
547#define etm4x_read32(csa, offset) \
548 ({ \
549 u32 __val = etm4x_relaxed_read32((csa), (offset)); \
550 __io_ar(__val); \
551 __val; \
552 })
553
554#define etm4x_read64(csa, offset) \
555 ({ \
556 u64 __val = etm4x_relaxed_read64((csa), (offset)); \
557 __io_ar(__val); \
558 __val; \
559 })
560
561#define etm4x_relaxed_write32(csa, val, offset) \
562 do { \
563 if ((csa)->io_mem) \
564 writel_relaxed((val), (csa)->base + (offset)); \
565 else \
566 write_etm4x_sysreg_offset((val), (offset), \
567 false); \
568 } while (0)
569
570#define etm4x_relaxed_write64(csa, val, offset) \
571 do { \
572 if ((csa)->io_mem) \
573 writeq_relaxed((val), (csa)->base + (offset)); \
574 else \
575 write_etm4x_sysreg_offset((val), (offset), \
576 true); \
577 } while (0)
578
579#define etm4x_write32(csa, val, offset) \
580 do { \
581 __io_bw(); \
582 etm4x_relaxed_write32((csa), (val), (offset)); \
583 } while (0)
584
585#define etm4x_write64(csa, val, offset) \
586 do { \
587 __io_bw(); \
588 etm4x_relaxed_write64((csa), (val), (offset)); \
589 } while (0)
590
591
592/* ETMv4 resources */
593#define ETM_MAX_NR_PE 8
594#define ETMv4_MAX_CNTR 4
595#define ETM_MAX_SEQ_STATES 4
596#define ETM_MAX_EXT_INP_SEL 4
597#define ETM_MAX_EXT_INP 256
598#define ETM_MAX_EXT_OUT 4
599#define ETM_MAX_SINGLE_ADDR_CMP 16
600#define ETM_MAX_ADDR_RANGE_CMP (ETM_MAX_SINGLE_ADDR_CMP / 2)
601#define ETM_MAX_DATA_VAL_CMP 8
602#define ETMv4_MAX_CTXID_CMP 8
603#define ETM_MAX_VMID_CMP 8
604#define ETM_MAX_PE_CMP 8
605#define ETM_MAX_RES_SEL 32
606#define ETM_MAX_SS_CMP 8
607
608#define ETMv4_SYNC_MASK 0x1F
609#define ETM_CYC_THRESHOLD_MASK 0xFFF
610#define ETM_CYC_THRESHOLD_DEFAULT 0x100
611#define ETMv4_EVENT_MASK 0xFF
612#define ETM_CNTR_MAX_VAL 0xFFFF
613#define ETM_TRACEID_MASK 0x3f
614
615/* ETMv4 programming modes */
616#define ETM_MODE_EXCLUDE BIT(0)
617#define ETM_MODE_LOAD BIT(1)
618#define ETM_MODE_STORE BIT(2)
619#define ETM_MODE_LOAD_STORE BIT(3)
620#define ETM_MODE_BB BIT(4)
621#define ETMv4_MODE_CYCACC BIT(5)
622#define ETMv4_MODE_CTXID BIT(6)
623#define ETM_MODE_VMID BIT(7)
624#define ETM_MODE_COND(val) BMVAL(val, 8, 10)
625#define ETMv4_MODE_TIMESTAMP BIT(11)
626#define ETM_MODE_RETURNSTACK BIT(12)
627#define ETM_MODE_QELEM(val) BMVAL(val, 13, 14)
628#define ETM_MODE_DATA_TRACE_ADDR BIT(15)
629#define ETM_MODE_DATA_TRACE_VAL BIT(16)
630#define ETM_MODE_ISTALL BIT(17)
631#define ETM_MODE_DSTALL BIT(18)
632#define ETM_MODE_ATB_TRIGGER BIT(19)
633#define ETM_MODE_LPOVERRIDE BIT(20)
634#define ETM_MODE_ISTALL_EN BIT(21)
635#define ETM_MODE_DSTALL_EN BIT(22)
636#define ETM_MODE_INSTPRIO BIT(23)
637#define ETM_MODE_NOOVERFLOW BIT(24)
638#define ETM_MODE_TRACE_RESET BIT(25)
639#define ETM_MODE_TRACE_ERR BIT(26)
640#define ETM_MODE_VIEWINST_STARTSTOP BIT(27)
641#define ETMv4_MODE_ALL (GENMASK(27, 0) | \
642 ETM_MODE_EXCL_KERN | \
643 ETM_MODE_EXCL_USER)
644
645/*
646 * TRCOSLSR.OSLM advertises the OS Lock model.
647 * OSLM[2:0] = TRCOSLSR[4:3,0]
648 *
649 * 0b000 - Trace OS Lock is not implemented.
650 * 0b010 - Trace OS Lock is implemented.
651 * 0b100 - Trace OS Lock is not implemented, unit is controlled by PE OS Lock.
652 */
653#define ETM_OSLOCK_NI 0b000
654#define ETM_OSLOCK_PRESENT 0b010
655#define ETM_OSLOCK_PE 0b100
656
657#define ETM_OSLSR_OSLM(oslsr) ((((oslsr) & GENMASK(4, 3)) >> 2) | (oslsr & 0x1))
658
659/*
660 * TRCDEVARCH Bit field definitions
661 * Bits[31:21] - ARCHITECT = Always Arm Ltd.
662 * * Bits[31:28] = 0x4
663 * * Bits[27:21] = 0b0111011
664 * Bit[20] - PRESENT, Indicates the presence of this register.
665 *
666 * Bit[19:16] - REVISION, Revision of the architecture.
667 *
668 * Bit[15:0] - ARCHID, Identifies this component as an ETM
669 * * Bits[15:12] - architecture version of ETM
670 * * = 4 for ETMv4
671 * * Bits[11:0] = 0xA13, architecture part number for ETM.
672 */
673#define ETM_DEVARCH_ARCHITECT_MASK GENMASK(31, 21)
674#define ETM_DEVARCH_ARCHITECT_ARM ((0x4 << 28) | (0b0111011 << 21))
675#define ETM_DEVARCH_PRESENT BIT(20)
676#define ETM_DEVARCH_REVISION_SHIFT 16
677#define ETM_DEVARCH_REVISION_MASK GENMASK(19, 16)
678#define ETM_DEVARCH_REVISION(x) \
679 (((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT)
680#define ETM_DEVARCH_ARCHID_MASK GENMASK(15, 0)
681#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT 12
682#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK GENMASK(15, 12)
683#define ETM_DEVARCH_ARCHID_ARCH_VER(x) \
684 (((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)
685
686#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver) \
687 (((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK)
688
689#define ETM_DEVARCH_ARCHID_ARCH_PART(x) ((x) & 0xfffUL)
690
691#define ETM_DEVARCH_MAKE_ARCHID(major) \
692 ((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))
693
694#define ETM_DEVARCH_ARCHID_ETMv4x ETM_DEVARCH_MAKE_ARCHID(0x4)
695#define ETM_DEVARCH_ARCHID_ETE ETM_DEVARCH_MAKE_ARCHID(0x5)
696
697#define ETM_DEVARCH_ID_MASK \
698 (ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)
699#define ETM_DEVARCH_ETMv4x_ARCH \
700 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)
701#define ETM_DEVARCH_ETE_ARCH \
702 (ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETE | ETM_DEVARCH_PRESENT)
703
704#define CS_DEVTYPE_PE_TRACE 0x00000013
705
706#define TRCSTATR_IDLE_BIT 0
707#define TRCSTATR_PMSTABLE_BIT 1
708#define ETM_DEFAULT_ADDR_COMP 0
709
710#define TRCSSCSRn_PC BIT(3)
711
712/* PowerDown Control Register bits */
713#define TRCPDCR_PU BIT(3)
714
715#define TRCACATR_EXLEVEL_SHIFT 8
716
717/*
718 * Exception level mask for Secure and Non-Secure ELs.
719 * ETM defines the bits for EL control (e.g, TRVICTLR, TRCACTRn).
720 * The Secure and Non-Secure ELs are always to gether.
721 * Non-secure EL3 is never implemented.
722 * We use the following generic mask as they appear in different
723 * registers and this can be shifted for the appropriate
724 * fields.
725 */
726#define ETM_EXLEVEL_S_APP BIT(0) /* Secure EL0 */
727#define ETM_EXLEVEL_S_OS BIT(1) /* Secure EL1 */
728#define ETM_EXLEVEL_S_HYP BIT(2) /* Secure EL2 */
729#define ETM_EXLEVEL_S_MON BIT(3) /* Secure EL3/Monitor */
730#define ETM_EXLEVEL_NS_APP BIT(4) /* NonSecure EL0 */
731#define ETM_EXLEVEL_NS_OS BIT(5) /* NonSecure EL1 */
732#define ETM_EXLEVEL_NS_HYP BIT(6) /* NonSecure EL2 */
733
734/* access level controls in TRCACATRn */
735#define TRCACATR_EXLEVEL_SHIFT 8
736
737#define ETM_TRCIDR1_ARCH_MAJOR_SHIFT 8
738#define ETM_TRCIDR1_ARCH_MAJOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
739#define ETM_TRCIDR1_ARCH_MAJOR(x) \
740 (((x) & ETM_TRCIDR1_ARCH_MAJOR_MASK) >> ETM_TRCIDR1_ARCH_MAJOR_SHIFT)
741#define ETM_TRCIDR1_ARCH_MINOR_SHIFT 4
742#define ETM_TRCIDR1_ARCH_MINOR_MASK (0xfU << ETM_TRCIDR1_ARCH_MINOR_SHIFT)
743#define ETM_TRCIDR1_ARCH_MINOR(x) \
744 (((x) & ETM_TRCIDR1_ARCH_MINOR_MASK) >> ETM_TRCIDR1_ARCH_MINOR_SHIFT)
745#define ETM_TRCIDR1_ARCH_SHIFT ETM_TRCIDR1_ARCH_MINOR_SHIFT
746#define ETM_TRCIDR1_ARCH_MASK \
747 (ETM_TRCIDR1_ARCH_MAJOR_MASK | ETM_TRCIDR1_ARCH_MINOR_MASK)
748
749#define ETM_TRCIDR1_ARCH_ETMv4 0x4
750
751/*
752 * Driver representation of the ETM architecture.
753 * The version of an ETM component can be detected from
754 *
755 * TRCDEVARCH - CoreSight architected register
756 * - Bits[15:12] - Major version
757 * - Bits[19:16] - Minor version
758 *
759 * We must rely only on TRCDEVARCH for the version information. Even though,
760 * TRCIDR1 also provides the architecture version, it is a "Trace" register
761 * and as such must be accessed only with Trace power domain ON. This may
762 * not be available at probe time.
763 *
764 * Now to make certain decisions easier based on the version
765 * we use an internal representation of the version in the
766 * driver, as follows :
767 *
768 * ETM_ARCH_VERSION[7:0], where :
769 * Bits[7:4] - Major version
770 * Bits[3:0] - Minro version
771 */
772#define ETM_ARCH_VERSION(major, minor) \
773 ((((major) & 0xfU) << 4) | (((minor) & 0xfU)))
774#define ETM_ARCH_MAJOR_VERSION(arch) (((arch) >> 4) & 0xfU)
775#define ETM_ARCH_MINOR_VERSION(arch) ((arch) & 0xfU)
776
777#define ETM_ARCH_V4 ETM_ARCH_VERSION(4, 0)
778#define ETM_ARCH_ETE ETM_ARCH_VERSION(5, 0)
779
780/* Interpretation of resource numbers change at ETM v4.3 architecture */
781#define ETM_ARCH_V4_3 ETM_ARCH_VERSION(4, 3)
782
783static inline u8 etm_devarch_to_arch(u32 devarch)
784{
785 return ETM_ARCH_VERSION(ETM_DEVARCH_ARCHID_ARCH_VER(devarch),
786 ETM_DEVARCH_REVISION(devarch));
787}
788
789enum etm_impdef_type {
790 ETM4_IMPDEF_HISI_CORE_COMMIT,
791 ETM4_IMPDEF_FEATURE_MAX,
792};
793
794/**
795 * struct etmv4_config - configuration information related to an ETMv4
796 * @mode: Controls various modes supported by this ETM.
797 * @pe_sel: Controls which PE to trace.
798 * @cfg: Controls the tracing options.
799 * @eventctrl0: Controls the tracing of arbitrary events.
800 * @eventctrl1: Controls the behavior of the events that @event_ctrl0 selects.
801 * @stallctl: If functionality that prevents trace unit buffer overflows
802 * is available.
803 * @ts_ctrl: Controls the insertion of global timestamps in the
804 * trace streams.
805 * @syncfreq: Controls how often trace synchronization requests occur.
806 * the TRCCCCTLR register.
807 * @ccctlr: Sets the threshold value for cycle counting.
808 * @vinst_ctrl: Controls instruction trace filtering.
809 * @viiectlr: Set or read, the address range comparators.
810 * @vissctlr: Set, or read, the single address comparators that control the
811 * ViewInst start-stop logic.
812 * @vipcssctlr: Set, or read, which PE comparator inputs can control the
813 * ViewInst start-stop logic.
814 * @seq_idx: Sequencor index selector.
815 * @seq_ctrl: Control for the sequencer state transition control register.
816 * @seq_rst: Moves the sequencer to state 0 when a programmed event occurs.
817 * @seq_state: Set, or read the sequencer state.
818 * @cntr_idx: Counter index seletor.
819 * @cntrldvr: Sets or returns the reload count value for a counter.
820 * @cntr_ctrl: Controls the operation of a counter.
821 * @cntr_val: Sets or returns the value for a counter.
822 * @res_idx: Resource index selector.
823 * @res_ctrl: Controls the selection of the resources in the trace unit.
824 * @ss_idx: Single-shot index selector.
825 * @ss_ctrl: Controls the corresponding single-shot comparator resource.
826 * @ss_status: The status of the corresponding single-shot comparator.
827 * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
828 * @addr_idx: Address comparator index selector.
829 * @addr_val: Value for address comparator.
830 * @addr_acc: Address comparator access type.
831 * @addr_type: Current status of the comparator register.
832 * @ctxid_idx: Context ID index selector.
833 * @ctxid_pid: Value of the context ID comparator.
834 * @ctxid_mask0:Context ID comparator mask for comparator 0-3.
835 * @ctxid_mask1:Context ID comparator mask for comparator 4-7.
836 * @vmid_idx: VM ID index selector.
837 * @vmid_val: Value of the VM ID comparator.
838 * @vmid_mask0: VM ID comparator mask for comparator 0-3.
839 * @vmid_mask1: VM ID comparator mask for comparator 4-7.
840 * @ext_inp: External input selection.
841 * @s_ex_level: Secure ELs where tracing is supported.
842 */
843struct etmv4_config {
844 u32 mode;
845 u32 pe_sel;
846 u32 cfg;
847 u32 eventctrl0;
848 u32 eventctrl1;
849 u32 stall_ctrl;
850 u32 ts_ctrl;
851 u32 syncfreq;
852 u32 ccctlr;
853 u32 bb_ctrl;
854 u32 vinst_ctrl;
855 u32 viiectlr;
856 u32 vissctlr;
857 u32 vipcssctlr;
858 u8 seq_idx;
859 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
860 u32 seq_rst;
861 u32 seq_state;
862 u8 cntr_idx;
863 u32 cntrldvr[ETMv4_MAX_CNTR];
864 u32 cntr_ctrl[ETMv4_MAX_CNTR];
865 u32 cntr_val[ETMv4_MAX_CNTR];
866 u8 res_idx;
867 u32 res_ctrl[ETM_MAX_RES_SEL];
868 u8 ss_idx;
869 u32 ss_ctrl[ETM_MAX_SS_CMP];
870 u32 ss_status[ETM_MAX_SS_CMP];
871 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
872 u8 addr_idx;
873 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
874 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
875 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
876 u8 ctxid_idx;
877 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
878 u32 ctxid_mask0;
879 u32 ctxid_mask1;
880 u8 vmid_idx;
881 u64 vmid_val[ETM_MAX_VMID_CMP];
882 u32 vmid_mask0;
883 u32 vmid_mask1;
884 u32 ext_inp;
885 u8 s_ex_level;
886};
887
888/**
889 * struct etm4_save_state - state to be preserved when ETM is without power
890 */
891struct etmv4_save_state {
892 u32 trcprgctlr;
893 u32 trcprocselr;
894 u32 trcconfigr;
895 u32 trcauxctlr;
896 u32 trceventctl0r;
897 u32 trceventctl1r;
898 u32 trcstallctlr;
899 u32 trctsctlr;
900 u32 trcsyncpr;
901 u32 trcccctlr;
902 u32 trcbbctlr;
903 u32 trctraceidr;
904 u32 trcqctlr;
905
906 u32 trcvictlr;
907 u32 trcviiectlr;
908 u32 trcvissctlr;
909 u32 trcvipcssctlr;
910 u32 trcvdctlr;
911 u32 trcvdsacctlr;
912 u32 trcvdarcctlr;
913
914 u32 trcseqevr[ETM_MAX_SEQ_STATES];
915 u32 trcseqrstevr;
916 u32 trcseqstr;
917 u32 trcextinselr;
918 u32 trccntrldvr[ETMv4_MAX_CNTR];
919 u32 trccntctlr[ETMv4_MAX_CNTR];
920 u32 trccntvr[ETMv4_MAX_CNTR];
921
922 u32 trcrsctlr[ETM_MAX_RES_SEL];
923
924 u32 trcssccr[ETM_MAX_SS_CMP];
925 u32 trcsscsr[ETM_MAX_SS_CMP];
926 u32 trcsspcicr[ETM_MAX_SS_CMP];
927
928 u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
929 u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
930 u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
931 u64 trcvmidcvr[ETM_MAX_VMID_CMP];
932 u32 trccidcctlr0;
933 u32 trccidcctlr1;
934 u32 trcvmidcctlr0;
935 u32 trcvmidcctlr1;
936
937 u32 trcclaimset;
938
939 u32 cntr_val[ETMv4_MAX_CNTR];
940 u32 seq_state;
941 u32 vinst_ctrl;
942 u32 ss_status[ETM_MAX_SS_CMP];
943
944 u32 trcpdcr;
945};
946
947/**
948 * struct etm4_drvdata - specifics associated to an ETM component
949 * @pclk APB clock if present, otherwise NULL
950 * @base: Memory mapped base address for this component.
951 * @csdev: Component vitals needed by the framework.
952 * @spinlock: Only one at a time pls.
953 * @mode: This tracer's mode, i.e sysFS, Perf or disabled.
954 * @cpu: The cpu this component is affined to.
955 * @arch: ETM architecture version.
956 * @nr_pe: The number of processing entity available for tracing.
957 * @nr_pe_cmp: The number of processing entity comparator inputs that are
958 * available for tracing.
959 * @nr_addr_cmp:Number of pairs of address comparators available
960 * as found in ETMIDR4 0-3.
961 * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30.
962 * @nr_ext_inp: Number of external input.
963 * @numcidc: Number of contextID comparators.
964 * @numvmidc: Number of VMID comparators.
965 * @nrseqstate: The number of sequencer states that are implemented.
966 * @nr_event: Indicates how many events the trace unit support.
967 * @nr_resource:The number of resource selection pairs available for tracing.
968 * @nr_ss_cmp: Number of single-shot comparator controls that are available.
969 * @trcid: value of the current ID for this component.
970 * @trcid_size: Indicates the trace ID width.
971 * @ts_size: Global timestamp size field.
972 * @ctxid_size: Size of the context ID field to consider.
973 * @vmid_size: Size of the VM ID comparator to consider.
974 * @ccsize: Indicates the size of the cycle counter in bits.
975 * @ccitmin: minimum value that can be programmed in
976 * @s_ex_level: In secure state, indicates whether instruction tracing is
977 * supported for the corresponding Exception level.
978 * @ns_ex_level:In non-secure state, indicates whether instruction tracing is
979 * supported for the corresponding Exception level.
980 * @sticky_enable: true if ETM base configuration has been done.
981 * @boot_enable:True if we should start tracing at boot time.
982 * @os_unlock: True if access to management registers is allowed.
983 * @instrp0: Tracing of load and store instructions
984 * as P0 elements is supported.
985 * @trcbb: Indicates if the trace unit supports branch broadcast tracing.
986 * @trccond: If the trace unit supports conditional
987 * instruction tracing.
988 * @retstack: Indicates if the implementation supports a return stack.
989 * @trccci: Indicates if the trace unit supports cycle counting
990 * for instruction.
991 * @q_support: Q element support characteristics.
992 * @trc_error: Whether a trace unit can trace a system
993 * error exception.
994 * @syncpr: Indicates if an implementation has a fixed
995 * synchronization period.
996 * @stall_ctrl: Enables trace unit functionality that prevents trace
997 * unit buffer overflows.
998 * @sysstall: Does the system support stall control of the PE?
999 * @nooverflow: Indicate if overflow prevention is supported.
1000 * @atbtrig: If the implementation can support ATB triggers
1001 * @lpoverride: If the implementation can support low-power state over.
1002 * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that
1003 * allows tracing at all ELs. We don't want to compute this
1004 * at runtime, due to the additional setting of TRFCR_CX when
1005 * in EL2. Otherwise, 0.
1006 * @config: structure holding configuration parameters.
1007 * @save_trfcr: Saved TRFCR_EL1 register during a CPU PM event.
1008 * @save_state: State to be preserved across power loss
1009 * @state_needs_restore: True when there is context to restore after PM exit
1010 * @skip_power_up: Indicates if an implementation can skip powering up
1011 * the trace unit.
1012 * @arch_features: Bitmap of arch features of etmv4 devices.
1013 */
1014struct etmv4_drvdata {
1015 struct clk *pclk;
1016 void __iomem *base;
1017 struct coresight_device *csdev;
1018 spinlock_t spinlock;
1019 local_t mode;
1020 int cpu;
1021 u8 arch;
1022 u8 nr_pe;
1023 u8 nr_pe_cmp;
1024 u8 nr_addr_cmp;
1025 u8 nr_cntr;
1026 u8 nr_ext_inp;
1027 u8 numcidc;
1028 u8 numvmidc;
1029 u8 nrseqstate;
1030 u8 nr_event;
1031 u8 nr_resource;
1032 u8 nr_ss_cmp;
1033 u8 trcid;
1034 u8 trcid_size;
1035 u8 ts_size;
1036 u8 ctxid_size;
1037 u8 vmid_size;
1038 u8 ccsize;
1039 u16 ccitmin;
1040 u8 s_ex_level;
1041 u8 ns_ex_level;
1042 u8 q_support;
1043 u8 os_lock_model;
1044 bool sticky_enable;
1045 bool boot_enable;
1046 bool os_unlock;
1047 bool instrp0;
1048 bool trcbb;
1049 bool trccond;
1050 bool retstack;
1051 bool trccci;
1052 bool trc_error;
1053 bool syncpr;
1054 bool stallctl;
1055 bool sysstall;
1056 bool nooverflow;
1057 bool atbtrig;
1058 bool lpoverride;
1059 u64 trfcr;
1060 struct etmv4_config config;
1061 u64 save_trfcr;
1062 struct etmv4_save_state *save_state;
1063 bool state_needs_restore;
1064 bool skip_power_up;
1065 DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX);
1066};
1067
1068/* Address comparator access types */
1069enum etm_addr_acctype {
1070 TRCACATRn_TYPE_ADDR,
1071 TRCACATRn_TYPE_DATA_LOAD_ADDR,
1072 TRCACATRn_TYPE_DATA_STORE_ADDR,
1073 TRCACATRn_TYPE_DATA_LOAD_STORE_ADDR,
1074};
1075
1076/* Address comparator context types */
1077enum etm_addr_ctxtype {
1078 ETM_CTX_NONE,
1079 ETM_CTX_CTXID,
1080 ETM_CTX_VMID,
1081 ETM_CTX_CTXID_VMID,
1082};
1083
1084extern const struct attribute_group *coresight_etmv4_groups[];
1085void etm4_config_trace_mode(struct etmv4_config *config);
1086
1087u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit);
1088void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool _64bit);
1089
1090static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata)
1091{
1092 return drvdata->arch >= ETM_ARCH_ETE;
1093}
1094
1095int etm4_read_alloc_trace_id(struct etmv4_drvdata *drvdata);
1096void etm4_release_trace_id(struct etmv4_drvdata *drvdata);
1097#endif