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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright © 2021 Intel Corporation
4 */
5
6#ifndef _ABI_GUC_KLVS_ABI_H
7#define _ABI_GUC_KLVS_ABI_H
8
9#include <linux/types.h>
10
11/**
12 * DOC: GuC KLV
13 *
14 * +---+-------+--------------------------------------------------------------+
15 * | | Bits | Description |
16 * +===+=======+==============================================================+
17 * | 0 | 31:16 | **KEY** - KLV key identifier |
18 * | | | - `GuC Self Config KLVs`_ |
19 * | | | - `GuC VGT Policy KLVs`_ |
20 * | | | - `GuC VF Configuration KLVs`_ |
21 * | | | |
22 * | +-------+--------------------------------------------------------------+
23 * | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) |
24 * +---+-------+--------------------------------------------------------------+
25 * | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) |
26 * +---+-------+ |
27 * |...| | |
28 * +---+-------+ |
29 * | n | 31:0 | |
30 * +---+-------+--------------------------------------------------------------+
31 */
32
33#define GUC_KLV_LEN_MIN 1u
34#define GUC_KLV_0_KEY (0xffffu << 16)
35#define GUC_KLV_0_LEN (0xffffu << 0)
36#define GUC_KLV_n_VALUE (0xffffffffu << 0)
37
38/**
39 * DOC: GuC Self Config KLVs
40 *
41 * `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.
42 *
43 * _`GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR` : 0x0900
44 * Refers to 64 bit Global Gfx address (in bytes) of memory based interrupts
45 * status vector for use by the GuC.
46 *
47 * _`GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR` : 0x0901
48 * Refers to 64 bit Global Gfx address (in bytes) of memory based interrupts
49 * source vector for use by the GuC.
50 *
51 * _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902
52 * Refers to 64 bit Global Gfx address of H2G `CT Buffer`_.
53 * Should be above WOPCM address but below APIC base address for native mode.
54 *
55 * _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR : 0x0903
56 * Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_.
57 * Should be above WOPCM address but below APIC base address for native mode.
58 *
59 * _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE : 0x0904
60 * Refers to size of H2G `CT Buffer`_ in bytes.
61 * Should be a multiple of 4K.
62 *
63 * _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR : 0x0905
64 * Refers to 64 bit Global Gfx address of G2H `CT Buffer`_.
65 * Should be above WOPCM address but below APIC base address for native mode.
66 *
67 * _GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR : 0x0906
68 * Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_.
69 * Should be above WOPCM address but below APIC base address for native mode.
70 *
71 * _GUC_KLV_SELF_CFG_G2H_CTB_SIZE : 0x0907
72 * Refers to size of G2H `CT Buffer`_ in bytes.
73 * Should be a multiple of 4K.
74 */
75
76#define GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR_KEY 0x0900
77#define GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR_LEN 2u
78
79#define GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR_KEY 0x0901
80#define GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR_LEN 2u
81
82#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_KEY 0x0902
83#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_LEN 2u
84
85#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_KEY 0x0903
86#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_LEN 2u
87
88#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_KEY 0x0904
89#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_LEN 1u
90
91#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_KEY 0x0905
92#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_LEN 2u
93
94#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_KEY 0x0906
95#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_LEN 2u
96
97#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY 0x0907
98#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN 1u
99
100/*
101 * Per context scheduling policy update keys.
102 */
103enum {
104 GUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM = 0x2001,
105 GUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT = 0x2002,
106 GUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY = 0x2003,
107 GUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY = 0x2004,
108 GUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY = 0x2005,
109
110 GUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,
111};
112
113/**
114 * DOC: GuC VGT Policy KLVs
115 *
116 * `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VGT_POLICY.
117 *
118 * _`GUC_KLV_VGT_POLICY_SCHED_IF_IDLE` : 0x8001
119 * This config sets whether strict scheduling is enabled whereby any VF
120 * that doesn’t have work to submit is still allocated a fixed execution
121 * time-slice to ensure active VFs execution is always consitent even
122 * during other VF reprovisiong / rebooting events. Changing this KLV
123 * impacts all VFs and takes effect on the next VF-Switch event.
124 *
125 * :0: don't schedule idle (default)
126 * :1: schedule if idle
127 *
128 * _`GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD` : 0x8002
129 * This config sets the sample period for tracking adverse event counters.
130 * A sample period is the period in millisecs during which events are counted.
131 * This is applicable for all the VFs.
132 *
133 * :0: adverse events are not counted (default)
134 * :n: sample period in milliseconds
135 *
136 * _`GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH` : 0x8D00
137 * This enum is to reset utilized HW engine after VF Switch (i.e to clean
138 * up Stale HW register left behind by previous VF)
139 *
140 * :0: don't reset (default)
141 * :1: reset
142 */
143
144#define GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_KEY 0x8001
145#define GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_LEN 1u
146
147#define GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD_KEY 0x8002
148#define GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD_LEN 1u
149
150#define GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH_KEY 0x8D00
151#define GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH_LEN 1u
152
153/**
154 * DOC: GuC VF Configuration KLVs
155 *
156 * `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VF_CFG.
157 *
158 * _`GUC_KLV_VF_CFG_GGTT_START` : 0x0001
159 * A 4K aligned start GTT address/offset assigned to VF.
160 * Value is 64 bits.
161 *
162 * _`GUC_KLV_VF_CFG_GGTT_SIZE` : 0x0002
163 * A 4K aligned size of GGTT assigned to VF.
164 * Value is 64 bits.
165 *
166 * _`GUC_KLV_VF_CFG_LMEM_SIZE` : 0x0003
167 * A 2M aligned size of local memory assigned to VF.
168 * Value is 64 bits.
169 *
170 * _`GUC_KLV_VF_CFG_NUM_CONTEXTS` : 0x0004
171 * Refers to the number of contexts allocated to this VF.
172 *
173 * :0: no contexts (default)
174 * :1-65535: number of contexts (Gen12)
175 *
176 * _`GUC_KLV_VF_CFG_TILE_MASK` : 0x0005
177 * For multi-tiled products, this field contains the bitwise-OR of tiles
178 * assigned to the VF. Bit-0-set means VF has access to Tile-0,
179 * Bit-31-set means VF has access to Tile-31, and etc.
180 * At least one tile will always be allocated.
181 * If all bits are zero, VF KMD should treat this as a fatal error.
182 * For, single-tile products this KLV config is ignored.
183 *
184 * _`GUC_KLV_VF_CFG_NUM_DOORBELLS` : 0x0006
185 * Refers to the number of doorbells allocated to this VF.
186 *
187 * :0: no doorbells (default)
188 * :1-255: number of doorbells (Gen12)
189 *
190 * _`GUC_KLV_VF_CFG_EXEC_QUANTUM` : 0x8A01
191 * This config sets the VFs-execution-quantum in milliseconds.
192 * GUC will attempt to obey the maximum values as much as HW is capable
193 * of and this will never be perfectly-exact (accumulated nano-second
194 * granularity) since the GPUs clock time runs off a different crystal
195 * from the CPUs clock. Changing this KLV on a VF that is currently
196 * running a context wont take effect until a new context is scheduled in.
197 * That said, when the PF is changing this value from 0xFFFFFFFF to
198 * something else, it might never take effect if the VF is running an
199 * inifinitely long compute or shader kernel. In such a scenario, the
200 * PF would need to trigger a VM PAUSE and then change the KLV to force
201 * it to take effect. Such cases might typically happen on a 1PF+1VF
202 * Virtualization config enabled for heavier workloads like AI/ML.
203 *
204 * :0: infinite exec quantum (default)
205 *
206 * _`GUC_KLV_VF_CFG_PREEMPT_TIMEOUT` : 0x8A02
207 * This config sets the VF-preemption-timeout in microseconds.
208 * GUC will attempt to obey the minimum and maximum values as much as
209 * HW is capable and this will never be perfectly-exact (accumulated
210 * nano-second granularity) since the GPUs clock time runs off a
211 * different crystal from the CPUs clock. Changing this KLV on a VF
212 * that is currently running a context wont take effect until a new
213 * context is scheduled in.
214 * That said, when the PF is changing this value from 0xFFFFFFFF to
215 * something else, it might never take effect if the VF is running an
216 * inifinitely long compute or shader kernel.
217 * In this case, the PF would need to trigger a VM PAUSE and then change
218 * the KLV to force it to take effect. Such cases might typically happen
219 * on a 1PF+1VF Virtualization config enabled for heavier workloads like
220 * AI/ML.
221 *
222 * :0: no preemption timeout (default)
223 *
224 * _`GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR` : 0x8A03
225 * This config sets threshold for CAT errors caused by the VF.
226 *
227 * :0: adverse events or error will not be reported (default)
228 * :n: event occurrence count per sampling interval
229 *
230 * _`GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET` : 0x8A04
231 * This config sets threshold for engine reset caused by the VF.
232 *
233 * :0: adverse events or error will not be reported (default)
234 * :n: event occurrence count per sampling interval
235 *
236 * _`GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT` : 0x8A05
237 * This config sets threshold for page fault errors caused by the VF.
238 *
239 * :0: adverse events or error will not be reported (default)
240 * :n: event occurrence count per sampling interval
241 *
242 * _`GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM` : 0x8A06
243 * This config sets threshold for H2G interrupts triggered by the VF.
244 *
245 * :0: adverse events or error will not be reported (default)
246 * :n: time (us) per sampling interval
247 *
248 * _`GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM` : 0x8A07
249 * This config sets threshold for GT interrupts triggered by the VF's
250 * workloads.
251 *
252 * :0: adverse events or error will not be reported (default)
253 * :n: time (us) per sampling interval
254 *
255 * _`GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM` : 0x8A08
256 * This config sets threshold for doorbell's ring triggered by the VF.
257 *
258 * :0: adverse events or error will not be reported (default)
259 * :n: time (us) per sampling interval
260 *
261 * _`GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID` : 0x8A0A
262 * Refers to the start index of doorbell assigned to this VF.
263 *
264 * :0: (default)
265 * :1-255: number of doorbells (Gen12)
266 *
267 * _`GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID` : 0x8A0B
268 * Refers to the start index in context array allocated to this VF’s use.
269 *
270 * :0: (default)
271 * :1-65535: number of contexts (Gen12)
272 */
273
274#define GUC_KLV_VF_CFG_GGTT_START_KEY 0x0001
275#define GUC_KLV_VF_CFG_GGTT_START_LEN 2u
276
277#define GUC_KLV_VF_CFG_GGTT_SIZE_KEY 0x0002
278#define GUC_KLV_VF_CFG_GGTT_SIZE_LEN 2u
279
280#define GUC_KLV_VF_CFG_LMEM_SIZE_KEY 0x0003
281#define GUC_KLV_VF_CFG_LMEM_SIZE_LEN 2u
282
283#define GUC_KLV_VF_CFG_NUM_CONTEXTS_KEY 0x0004
284#define GUC_KLV_VF_CFG_NUM_CONTEXTS_LEN 1u
285
286#define GUC_KLV_VF_CFG_TILE_MASK_KEY 0x0005
287#define GUC_KLV_VF_CFG_TILE_MASK_LEN 1u
288
289#define GUC_KLV_VF_CFG_NUM_DOORBELLS_KEY 0x0006
290#define GUC_KLV_VF_CFG_NUM_DOORBELLS_LEN 1u
291
292#define GUC_KLV_VF_CFG_EXEC_QUANTUM_KEY 0x8a01
293#define GUC_KLV_VF_CFG_EXEC_QUANTUM_LEN 1u
294
295#define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_KEY 0x8a02
296#define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_LEN 1u
297
298#define GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR_KEY 0x8a03
299#define GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR_LEN 1u
300
301#define GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET_KEY 0x8a04
302#define GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET_LEN 1u
303
304#define GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT_KEY 0x8a05
305#define GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT_LEN 1u
306
307#define GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM_KEY 0x8a06
308#define GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM_LEN 1u
309
310#define GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM_KEY 0x8a07
311#define GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM_LEN 1u
312
313#define GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM_KEY 0x8a08
314#define GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM_LEN 1u
315
316#define GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID_KEY 0x8a0a
317#define GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID_LEN 1u
318
319#define GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID_KEY 0x8a0b
320#define GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID_LEN 1u
321
322#endif