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1/*
2 * HDMI PLL
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
9 */
10
11#define DSS_SUBSYS_NAME "HDMIPLL"
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/err.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18#include <linux/clk.h>
19
20#include <video/omapdss.h>
21
22#include "dss.h"
23#include "hdmi.h"
24
25void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
26{
27#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
28 hdmi_read_reg(pll->base, r))
29
30 DUMPPLL(PLLCTRL_PLL_CONTROL);
31 DUMPPLL(PLLCTRL_PLL_STATUS);
32 DUMPPLL(PLLCTRL_PLL_GO);
33 DUMPPLL(PLLCTRL_CFG1);
34 DUMPPLL(PLLCTRL_CFG2);
35 DUMPPLL(PLLCTRL_CFG3);
36 DUMPPLL(PLLCTRL_SSC_CFG1);
37 DUMPPLL(PLLCTRL_SSC_CFG2);
38 DUMPPLL(PLLCTRL_CFG4);
39}
40
41void hdmi_pll_compute(struct hdmi_pll_data *pll,
42 unsigned long target_tmds, struct dss_pll_clock_info *pi)
43{
44 unsigned long fint, clkdco, clkout;
45 unsigned long target_bitclk, target_clkdco;
46 unsigned long min_dco;
47 unsigned n, m, mf, m2, sd;
48 unsigned long clkin;
49 const struct dss_pll_hw *hw = pll->pll.hw;
50
51 clkin = clk_get_rate(pll->pll.clkin);
52
53 DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds);
54
55 target_bitclk = target_tmds * 10;
56
57 /* Fint */
58 n = DIV_ROUND_UP(clkin, hw->fint_max);
59 fint = clkin / n;
60
61 /* adjust m2 so that the clkdco will be high enough */
62 min_dco = roundup(hw->clkdco_min, fint);
63 m2 = DIV_ROUND_UP(min_dco, target_bitclk);
64 if (m2 == 0)
65 m2 = 1;
66
67 target_clkdco = target_bitclk * m2;
68 m = target_clkdco / fint;
69
70 clkdco = fint * m;
71
72 /* adjust clkdco with fractional mf */
73 if (WARN_ON(target_clkdco - clkdco > fint))
74 mf = 0;
75 else
76 mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint);
77
78 if (mf > 0)
79 clkdco += (u32)div_u64((u64)mf * fint, 262144);
80
81 clkout = clkdco / m2;
82
83 /* sigma-delta */
84 sd = DIV_ROUND_UP(fint * m, 250000000);
85
86 DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n",
87 n, m, mf, m2, sd);
88 DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout);
89
90 pi->n = n;
91 pi->m = m;
92 pi->mf = mf;
93 pi->mX[0] = m2;
94 pi->sd = sd;
95
96 pi->fint = fint;
97 pi->clkdco = clkdco;
98 pi->clkout[0] = clkout;
99}
100
101static int hdmi_pll_enable(struct dss_pll *dsspll)
102{
103 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
104 struct hdmi_wp_data *wp = pll->wp;
105 u16 r = 0;
106
107 dss_ctrl_pll_enable(DSS_PLL_HDMI, true);
108
109 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
110 if (r)
111 return r;
112
113 return 0;
114}
115
116static void hdmi_pll_disable(struct dss_pll *dsspll)
117{
118 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
119 struct hdmi_wp_data *wp = pll->wp;
120
121 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
122
123 dss_ctrl_pll_enable(DSS_PLL_HDMI, false);
124}
125
126static const struct dss_pll_ops dsi_pll_ops = {
127 .enable = hdmi_pll_enable,
128 .disable = hdmi_pll_disable,
129 .set_config = dss_pll_write_config_type_b,
130};
131
132static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
133 .n_max = 255,
134 .m_min = 20,
135 .m_max = 4095,
136 .mX_max = 127,
137 .fint_min = 500000,
138 .fint_max = 2500000,
139
140 .clkdco_min = 500000000,
141 .clkdco_low = 1000000000,
142 .clkdco_max = 2000000000,
143
144 .n_msb = 8,
145 .n_lsb = 1,
146 .m_msb = 20,
147 .m_lsb = 9,
148
149 .mX_msb[0] = 24,
150 .mX_lsb[0] = 18,
151
152 .has_selfreqdco = true,
153};
154
155static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
156 .n_max = 255,
157 .m_min = 20,
158 .m_max = 2045,
159 .mX_max = 127,
160 .fint_min = 620000,
161 .fint_max = 2500000,
162
163 .clkdco_min = 750000000,
164 .clkdco_low = 1500000000,
165 .clkdco_max = 2500000000UL,
166
167 .n_msb = 8,
168 .n_lsb = 1,
169 .m_msb = 20,
170 .m_lsb = 9,
171
172 .mX_msb[0] = 24,
173 .mX_lsb[0] = 18,
174
175 .has_selfreqdco = true,
176 .has_refsel = true,
177};
178
179static int dsi_init_pll_data(struct platform_device *pdev, struct hdmi_pll_data *hpll)
180{
181 struct dss_pll *pll = &hpll->pll;
182 struct clk *clk;
183 int r;
184
185 clk = devm_clk_get(&pdev->dev, "sys_clk");
186 if (IS_ERR(clk)) {
187 DSSERR("can't get sys_clk\n");
188 return PTR_ERR(clk);
189 }
190
191 pll->name = "hdmi";
192 pll->id = DSS_PLL_HDMI;
193 pll->base = hpll->base;
194 pll->clkin = clk;
195
196 switch (omapdss_get_version()) {
197 case OMAPDSS_VER_OMAP4430_ES1:
198 case OMAPDSS_VER_OMAP4430_ES2:
199 case OMAPDSS_VER_OMAP4:
200 pll->hw = &dss_omap4_hdmi_pll_hw;
201 break;
202
203 case OMAPDSS_VER_OMAP5:
204 case OMAPDSS_VER_DRA7xx:
205 pll->hw = &dss_omap5_hdmi_pll_hw;
206 break;
207
208 default:
209 return -ENODEV;
210 }
211
212 pll->ops = &dsi_pll_ops;
213
214 r = dss_pll_register(pll);
215 if (r)
216 return r;
217
218 return 0;
219}
220
221int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll,
222 struct hdmi_wp_data *wp)
223{
224 int r;
225 struct resource *res;
226
227 pll->wp = wp;
228
229 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
230 if (!res) {
231 DSSERR("can't get PLL mem resource\n");
232 return -EINVAL;
233 }
234
235 pll->base = devm_ioremap_resource(&pdev->dev, res);
236 if (IS_ERR(pll->base)) {
237 DSSERR("can't ioremap PLLCTRL\n");
238 return PTR_ERR(pll->base);
239 }
240
241 r = dsi_init_pll_data(pdev, pll);
242 if (r) {
243 DSSERR("failed to init HDMI PLL\n");
244 return r;
245 }
246
247 return 0;
248}
249
250void hdmi_pll_uninit(struct hdmi_pll_data *hpll)
251{
252 struct dss_pll *pll = &hpll->pll;
253
254 dss_pll_unregister(pll);
255}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * HDMI PLL
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#define DSS_SUBSYS_NAME "HDMIPLL"
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/seq_file.h>
17#include <linux/pm_runtime.h>
18
19#include "omapdss.h"
20#include "dss.h"
21#include "hdmi.h"
22
23void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
24{
25#define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
26 hdmi_read_reg(pll->base, r))
27
28 DUMPPLL(PLLCTRL_PLL_CONTROL);
29 DUMPPLL(PLLCTRL_PLL_STATUS);
30 DUMPPLL(PLLCTRL_PLL_GO);
31 DUMPPLL(PLLCTRL_CFG1);
32 DUMPPLL(PLLCTRL_CFG2);
33 DUMPPLL(PLLCTRL_CFG3);
34 DUMPPLL(PLLCTRL_SSC_CFG1);
35 DUMPPLL(PLLCTRL_SSC_CFG2);
36 DUMPPLL(PLLCTRL_CFG4);
37}
38
39static int hdmi_pll_enable(struct dss_pll *dsspll)
40{
41 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
42 struct hdmi_wp_data *wp = pll->wp;
43 int r;
44
45 r = pm_runtime_get_sync(&pll->pdev->dev);
46 WARN_ON(r < 0);
47
48 dss_ctrl_pll_enable(dsspll, true);
49
50 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
51 if (r)
52 return r;
53
54 return 0;
55}
56
57static void hdmi_pll_disable(struct dss_pll *dsspll)
58{
59 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll);
60 struct hdmi_wp_data *wp = pll->wp;
61 int r;
62
63 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
64
65 dss_ctrl_pll_enable(dsspll, false);
66
67 r = pm_runtime_put_sync(&pll->pdev->dev);
68 WARN_ON(r < 0 && r != -ENOSYS);
69}
70
71static const struct dss_pll_ops hdmi_pll_ops = {
72 .enable = hdmi_pll_enable,
73 .disable = hdmi_pll_disable,
74 .set_config = dss_pll_write_config_type_b,
75};
76
77static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = {
78 .type = DSS_PLL_TYPE_B,
79
80 .n_max = 255,
81 .m_min = 20,
82 .m_max = 4095,
83 .mX_max = 127,
84 .fint_min = 500000,
85 .fint_max = 2500000,
86
87 .clkdco_min = 500000000,
88 .clkdco_low = 1000000000,
89 .clkdco_max = 2000000000,
90
91 .n_msb = 8,
92 .n_lsb = 1,
93 .m_msb = 20,
94 .m_lsb = 9,
95
96 .mX_msb[0] = 24,
97 .mX_lsb[0] = 18,
98
99 .has_selfreqdco = true,
100};
101
102static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = {
103 .type = DSS_PLL_TYPE_B,
104
105 .n_max = 255,
106 .m_min = 20,
107 .m_max = 2045,
108 .mX_max = 127,
109 .fint_min = 620000,
110 .fint_max = 2500000,
111
112 .clkdco_min = 750000000,
113 .clkdco_low = 1500000000,
114 .clkdco_max = 2500000000UL,
115
116 .n_msb = 8,
117 .n_lsb = 1,
118 .m_msb = 20,
119 .m_lsb = 9,
120
121 .mX_msb[0] = 24,
122 .mX_lsb[0] = 18,
123
124 .has_selfreqdco = true,
125 .has_refsel = true,
126};
127
128static int hdmi_init_pll_data(struct dss_device *dss,
129 struct platform_device *pdev,
130 struct hdmi_pll_data *hpll)
131{
132 struct dss_pll *pll = &hpll->pll;
133 struct clk *clk;
134 int r;
135
136 clk = devm_clk_get(&pdev->dev, "sys_clk");
137 if (IS_ERR(clk)) {
138 DSSERR("can't get sys_clk\n");
139 return PTR_ERR(clk);
140 }
141
142 pll->name = "hdmi";
143 pll->id = DSS_PLL_HDMI;
144 pll->base = hpll->base;
145 pll->clkin = clk;
146
147 if (hpll->wp->version == 4)
148 pll->hw = &dss_omap4_hdmi_pll_hw;
149 else
150 pll->hw = &dss_omap5_hdmi_pll_hw;
151
152 pll->ops = &hdmi_pll_ops;
153
154 r = dss_pll_register(dss, pll);
155 if (r)
156 return r;
157
158 return 0;
159}
160
161int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev,
162 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
163{
164 int r;
165
166 pll->pdev = pdev;
167 pll->wp = wp;
168
169 pll->base = devm_platform_ioremap_resource_byname(pdev, "pll");
170 if (IS_ERR(pll->base))
171 return PTR_ERR(pll->base);
172
173 r = hdmi_init_pll_data(dss, pdev, pll);
174 if (r) {
175 DSSERR("failed to init HDMI PLL\n");
176 return r;
177 }
178
179 return 0;
180}
181
182void hdmi_pll_uninit(struct hdmi_pll_data *hpll)
183{
184 struct dss_pll *pll = &hpll->pll;
185
186 dss_pll_unregister(pll);
187}