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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Jie Qiu <jie.qiu@mediatek.com>
5 */
6
7#include <linux/arm-smccc.h>
8#include <linux/clk.h>
9#include <linux/delay.h>
10#include <linux/hdmi.h>
11#include <linux/i2c.h>
12#include <linux/io.h>
13#include <linux/kernel.h>
14#include <linux/mfd/syscon.h>
15#include <linux/module.h>
16#include <linux/mutex.h>
17#include <linux/of_platform.h>
18#include <linux/of.h>
19#include <linux/of_graph.h>
20#include <linux/phy/phy.h>
21#include <linux/platform_device.h>
22#include <linux/regmap.h>
23
24#include <sound/hdmi-codec.h>
25
26#include <drm/drm_atomic_helper.h>
27#include <drm/drm_bridge.h>
28#include <drm/drm_crtc.h>
29#include <drm/drm_edid.h>
30#include <drm/drm_print.h>
31#include <drm/drm_probe_helper.h>
32
33#include "mtk_cec.h"
34#include "mtk_hdmi.h"
35#include "mtk_hdmi_regs.h"
36
37#define NCTS_BYTES 7
38
39enum mtk_hdmi_clk_id {
40 MTK_HDMI_CLK_HDMI_PIXEL,
41 MTK_HDMI_CLK_HDMI_PLL,
42 MTK_HDMI_CLK_AUD_BCLK,
43 MTK_HDMI_CLK_AUD_SPDIF,
44 MTK_HDMI_CLK_COUNT
45};
46
47enum hdmi_aud_input_type {
48 HDMI_AUD_INPUT_I2S = 0,
49 HDMI_AUD_INPUT_SPDIF,
50};
51
52enum hdmi_aud_i2s_fmt {
53 HDMI_I2S_MODE_RJT_24BIT = 0,
54 HDMI_I2S_MODE_RJT_16BIT,
55 HDMI_I2S_MODE_LJT_24BIT,
56 HDMI_I2S_MODE_LJT_16BIT,
57 HDMI_I2S_MODE_I2S_24BIT,
58 HDMI_I2S_MODE_I2S_16BIT
59};
60
61enum hdmi_aud_mclk {
62 HDMI_AUD_MCLK_128FS,
63 HDMI_AUD_MCLK_192FS,
64 HDMI_AUD_MCLK_256FS,
65 HDMI_AUD_MCLK_384FS,
66 HDMI_AUD_MCLK_512FS,
67 HDMI_AUD_MCLK_768FS,
68 HDMI_AUD_MCLK_1152FS,
69};
70
71enum hdmi_aud_channel_type {
72 HDMI_AUD_CHAN_TYPE_1_0 = 0,
73 HDMI_AUD_CHAN_TYPE_1_1,
74 HDMI_AUD_CHAN_TYPE_2_0,
75 HDMI_AUD_CHAN_TYPE_2_1,
76 HDMI_AUD_CHAN_TYPE_3_0,
77 HDMI_AUD_CHAN_TYPE_3_1,
78 HDMI_AUD_CHAN_TYPE_4_0,
79 HDMI_AUD_CHAN_TYPE_4_1,
80 HDMI_AUD_CHAN_TYPE_5_0,
81 HDMI_AUD_CHAN_TYPE_5_1,
82 HDMI_AUD_CHAN_TYPE_6_0,
83 HDMI_AUD_CHAN_TYPE_6_1,
84 HDMI_AUD_CHAN_TYPE_7_0,
85 HDMI_AUD_CHAN_TYPE_7_1,
86 HDMI_AUD_CHAN_TYPE_3_0_LRS,
87 HDMI_AUD_CHAN_TYPE_3_1_LRS,
88 HDMI_AUD_CHAN_TYPE_4_0_CLRS,
89 HDMI_AUD_CHAN_TYPE_4_1_CLRS,
90 HDMI_AUD_CHAN_TYPE_6_1_CS,
91 HDMI_AUD_CHAN_TYPE_6_1_CH,
92 HDMI_AUD_CHAN_TYPE_6_1_OH,
93 HDMI_AUD_CHAN_TYPE_6_1_CHR,
94 HDMI_AUD_CHAN_TYPE_7_1_LH_RH,
95 HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR,
96 HDMI_AUD_CHAN_TYPE_7_1_LC_RC,
97 HDMI_AUD_CHAN_TYPE_7_1_LW_RW,
98 HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD,
99 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS,
100 HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS,
101 HDMI_AUD_CHAN_TYPE_7_1_CS_CH,
102 HDMI_AUD_CHAN_TYPE_7_1_CS_OH,
103 HDMI_AUD_CHAN_TYPE_7_1_CS_CHR,
104 HDMI_AUD_CHAN_TYPE_7_1_CH_OH,
105 HDMI_AUD_CHAN_TYPE_7_1_CH_CHR,
106 HDMI_AUD_CHAN_TYPE_7_1_OH_CHR,
107 HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR,
108 HDMI_AUD_CHAN_TYPE_6_0_CS,
109 HDMI_AUD_CHAN_TYPE_6_0_CH,
110 HDMI_AUD_CHAN_TYPE_6_0_OH,
111 HDMI_AUD_CHAN_TYPE_6_0_CHR,
112 HDMI_AUD_CHAN_TYPE_7_0_LH_RH,
113 HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR,
114 HDMI_AUD_CHAN_TYPE_7_0_LC_RC,
115 HDMI_AUD_CHAN_TYPE_7_0_LW_RW,
116 HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD,
117 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS,
118 HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS,
119 HDMI_AUD_CHAN_TYPE_7_0_CS_CH,
120 HDMI_AUD_CHAN_TYPE_7_0_CS_OH,
121 HDMI_AUD_CHAN_TYPE_7_0_CS_CHR,
122 HDMI_AUD_CHAN_TYPE_7_0_CH_OH,
123 HDMI_AUD_CHAN_TYPE_7_0_CH_CHR,
124 HDMI_AUD_CHAN_TYPE_7_0_OH_CHR,
125 HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR,
126 HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS,
127 HDMI_AUD_CHAN_TYPE_UNKNOWN = 0xFF
128};
129
130enum hdmi_aud_channel_swap_type {
131 HDMI_AUD_SWAP_LR,
132 HDMI_AUD_SWAP_LFE_CC,
133 HDMI_AUD_SWAP_LSRS,
134 HDMI_AUD_SWAP_RLS_RRS,
135 HDMI_AUD_SWAP_LR_STATUS,
136};
137
138struct hdmi_audio_param {
139 enum hdmi_audio_coding_type aud_codec;
140 enum hdmi_audio_sample_size aud_sampe_size;
141 enum hdmi_aud_input_type aud_input_type;
142 enum hdmi_aud_i2s_fmt aud_i2s_fmt;
143 enum hdmi_aud_mclk aud_mclk;
144 enum hdmi_aud_channel_type aud_input_chan_type;
145 struct hdmi_codec_params codec_params;
146};
147
148struct mtk_hdmi_conf {
149 bool tz_disabled;
150 bool cea_modes_only;
151 unsigned long max_mode_clock;
152};
153
154struct mtk_hdmi {
155 struct drm_bridge bridge;
156 struct drm_bridge *next_bridge;
157 struct drm_connector *curr_conn;/* current connector (only valid when 'enabled') */
158 struct device *dev;
159 const struct mtk_hdmi_conf *conf;
160 struct phy *phy;
161 struct device *cec_dev;
162 struct i2c_adapter *ddc_adpt;
163 struct clk *clk[MTK_HDMI_CLK_COUNT];
164 struct drm_display_mode mode;
165 bool dvi_mode;
166 u32 min_clock;
167 u32 max_clock;
168 u32 max_hdisplay;
169 u32 max_vdisplay;
170 u32 ibias;
171 u32 ibias_up;
172 struct regmap *sys_regmap;
173 unsigned int sys_offset;
174 void __iomem *regs;
175 enum hdmi_colorspace csp;
176 struct hdmi_audio_param aud_param;
177 bool audio_enable;
178 bool powered;
179 bool enabled;
180 hdmi_codec_plugged_cb plugged_cb;
181 struct device *codec_dev;
182 struct mutex update_plugged_status_lock;
183};
184
185static inline struct mtk_hdmi *hdmi_ctx_from_bridge(struct drm_bridge *b)
186{
187 return container_of(b, struct mtk_hdmi, bridge);
188}
189
190static u32 mtk_hdmi_read(struct mtk_hdmi *hdmi, u32 offset)
191{
192 return readl(hdmi->regs + offset);
193}
194
195static void mtk_hdmi_write(struct mtk_hdmi *hdmi, u32 offset, u32 val)
196{
197 writel(val, hdmi->regs + offset);
198}
199
200static void mtk_hdmi_clear_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
201{
202 void __iomem *reg = hdmi->regs + offset;
203 u32 tmp;
204
205 tmp = readl(reg);
206 tmp &= ~bits;
207 writel(tmp, reg);
208}
209
210static void mtk_hdmi_set_bits(struct mtk_hdmi *hdmi, u32 offset, u32 bits)
211{
212 void __iomem *reg = hdmi->regs + offset;
213 u32 tmp;
214
215 tmp = readl(reg);
216 tmp |= bits;
217 writel(tmp, reg);
218}
219
220static void mtk_hdmi_mask(struct mtk_hdmi *hdmi, u32 offset, u32 val, u32 mask)
221{
222 void __iomem *reg = hdmi->regs + offset;
223 u32 tmp;
224
225 tmp = readl(reg);
226 tmp = (tmp & ~mask) | (val & mask);
227 writel(tmp, reg);
228}
229
230static void mtk_hdmi_hw_vid_black(struct mtk_hdmi *hdmi, bool black)
231{
232 mtk_hdmi_mask(hdmi, VIDEO_CFG_4, black ? GEN_RGB : NORMAL_PATH,
233 VIDEO_SOURCE_SEL);
234}
235
236static void mtk_hdmi_hw_make_reg_writable(struct mtk_hdmi *hdmi, bool enable)
237{
238 struct arm_smccc_res res;
239
240 /*
241 * MT8173 HDMI hardware has an output control bit to enable/disable HDMI
242 * output. This bit can only be controlled in ARM supervisor mode.
243 * The ARM trusted firmware provides an API for the HDMI driver to set
244 * this control bit to enable HDMI output in supervisor mode.
245 */
246 if (hdmi->conf && hdmi->conf->tz_disabled)
247 regmap_update_bits(hdmi->sys_regmap,
248 hdmi->sys_offset + HDMI_SYS_CFG20,
249 0x80008005, enable ? 0x80000005 : 0x8000);
250 else
251 arm_smccc_smc(MTK_SIP_SET_AUTHORIZED_SECURE_REG, 0x14000904,
252 0x80000000, 0, 0, 0, 0, 0, &res);
253
254 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
255 HDMI_PCLK_FREE_RUN, enable ? HDMI_PCLK_FREE_RUN : 0);
256 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
257 HDMI_ON | ANLG_ON, enable ? (HDMI_ON | ANLG_ON) : 0);
258}
259
260static void mtk_hdmi_hw_1p4_version_enable(struct mtk_hdmi *hdmi, bool enable)
261{
262 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
263 HDMI2P0_EN, enable ? 0 : HDMI2P0_EN);
264}
265
266static void mtk_hdmi_hw_aud_mute(struct mtk_hdmi *hdmi)
267{
268 mtk_hdmi_set_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
269}
270
271static void mtk_hdmi_hw_aud_unmute(struct mtk_hdmi *hdmi)
272{
273 mtk_hdmi_clear_bits(hdmi, GRL_AUDIO_CFG, AUDIO_ZERO);
274}
275
276static void mtk_hdmi_hw_reset(struct mtk_hdmi *hdmi)
277{
278 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
279 HDMI_RST, HDMI_RST);
280 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
281 HDMI_RST, 0);
282 mtk_hdmi_clear_bits(hdmi, GRL_CFG3, CFG3_CONTROL_PACKET_DELAY);
283 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG1C,
284 ANLG_ON, ANLG_ON);
285}
286
287static void mtk_hdmi_hw_enable_notice(struct mtk_hdmi *hdmi, bool enable_notice)
288{
289 mtk_hdmi_mask(hdmi, GRL_CFG2, enable_notice ? CFG2_NOTICE_EN : 0,
290 CFG2_NOTICE_EN);
291}
292
293static void mtk_hdmi_hw_write_int_mask(struct mtk_hdmi *hdmi, u32 int_mask)
294{
295 mtk_hdmi_write(hdmi, GRL_INT_MASK, int_mask);
296}
297
298static void mtk_hdmi_hw_enable_dvi_mode(struct mtk_hdmi *hdmi, bool enable)
299{
300 mtk_hdmi_mask(hdmi, GRL_CFG1, enable ? CFG1_DVI : 0, CFG1_DVI);
301}
302
303static void mtk_hdmi_hw_send_info_frame(struct mtk_hdmi *hdmi, u8 *buffer,
304 u8 len)
305{
306 u32 ctrl_reg = GRL_CTRL;
307 int i;
308 u8 *frame_data;
309 enum hdmi_infoframe_type frame_type;
310 u8 frame_ver;
311 u8 frame_len;
312 u8 checksum;
313 int ctrl_frame_en = 0;
314
315 frame_type = *buffer++;
316 frame_ver = *buffer++;
317 frame_len = *buffer++;
318 checksum = *buffer++;
319 frame_data = buffer;
320
321 dev_dbg(hdmi->dev,
322 "frame_type:0x%x,frame_ver:0x%x,frame_len:0x%x,checksum:0x%x\n",
323 frame_type, frame_ver, frame_len, checksum);
324
325 switch (frame_type) {
326 case HDMI_INFOFRAME_TYPE_AVI:
327 ctrl_frame_en = CTRL_AVI_EN;
328 ctrl_reg = GRL_CTRL;
329 break;
330 case HDMI_INFOFRAME_TYPE_SPD:
331 ctrl_frame_en = CTRL_SPD_EN;
332 ctrl_reg = GRL_CTRL;
333 break;
334 case HDMI_INFOFRAME_TYPE_AUDIO:
335 ctrl_frame_en = CTRL_AUDIO_EN;
336 ctrl_reg = GRL_CTRL;
337 break;
338 case HDMI_INFOFRAME_TYPE_VENDOR:
339 ctrl_frame_en = VS_EN;
340 ctrl_reg = GRL_ACP_ISRC_CTRL;
341 break;
342 default:
343 dev_err(hdmi->dev, "Unknown infoframe type %d\n", frame_type);
344 return;
345 }
346 mtk_hdmi_clear_bits(hdmi, ctrl_reg, ctrl_frame_en);
347 mtk_hdmi_write(hdmi, GRL_INFOFRM_TYPE, frame_type);
348 mtk_hdmi_write(hdmi, GRL_INFOFRM_VER, frame_ver);
349 mtk_hdmi_write(hdmi, GRL_INFOFRM_LNG, frame_len);
350
351 mtk_hdmi_write(hdmi, GRL_IFM_PORT, checksum);
352 for (i = 0; i < frame_len; i++)
353 mtk_hdmi_write(hdmi, GRL_IFM_PORT, frame_data[i]);
354
355 mtk_hdmi_set_bits(hdmi, ctrl_reg, ctrl_frame_en);
356}
357
358static void mtk_hdmi_hw_send_aud_packet(struct mtk_hdmi *hdmi, bool enable)
359{
360 mtk_hdmi_mask(hdmi, GRL_SHIFT_R2, enable ? 0 : AUDIO_PACKET_OFF,
361 AUDIO_PACKET_OFF);
362}
363
364static void mtk_hdmi_hw_config_sys(struct mtk_hdmi *hdmi)
365{
366 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
367 HDMI_OUT_FIFO_EN | MHL_MODE_ON, 0);
368 usleep_range(2000, 4000);
369 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
370 HDMI_OUT_FIFO_EN | MHL_MODE_ON, HDMI_OUT_FIFO_EN);
371}
372
373static void mtk_hdmi_hw_set_deep_color_mode(struct mtk_hdmi *hdmi)
374{
375 regmap_update_bits(hdmi->sys_regmap, hdmi->sys_offset + HDMI_SYS_CFG20,
376 DEEP_COLOR_MODE_MASK | DEEP_COLOR_EN,
377 COLOR_8BIT_MODE);
378}
379
380static void mtk_hdmi_hw_send_av_mute(struct mtk_hdmi *hdmi)
381{
382 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
383 usleep_range(2000, 4000);
384 mtk_hdmi_set_bits(hdmi, GRL_CFG4, CTRL_AVMUTE);
385}
386
387static void mtk_hdmi_hw_send_av_unmute(struct mtk_hdmi *hdmi)
388{
389 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_EN,
390 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
391 usleep_range(2000, 4000);
392 mtk_hdmi_mask(hdmi, GRL_CFG4, CFG4_AV_UNMUTE_SET,
393 CFG4_AV_UNMUTE_EN | CFG4_AV_UNMUTE_SET);
394}
395
396static void mtk_hdmi_hw_ncts_enable(struct mtk_hdmi *hdmi, bool on)
397{
398 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, on ? 0 : CTS_CTRL_SOFT,
399 CTS_CTRL_SOFT);
400}
401
402static void mtk_hdmi_hw_ncts_auto_write_enable(struct mtk_hdmi *hdmi,
403 bool enable)
404{
405 mtk_hdmi_mask(hdmi, GRL_CTS_CTRL, enable ? NCTS_WRI_ANYTIME : 0,
406 NCTS_WRI_ANYTIME);
407}
408
409static void mtk_hdmi_hw_msic_setting(struct mtk_hdmi *hdmi,
410 struct drm_display_mode *mode)
411{
412 mtk_hdmi_clear_bits(hdmi, GRL_CFG4, CFG4_MHL_MODE);
413
414 if (mode->flags & DRM_MODE_FLAG_INTERLACE &&
415 mode->clock == 74250 &&
416 mode->vdisplay == 1080)
417 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
418 else
419 mtk_hdmi_set_bits(hdmi, GRL_CFG2, CFG2_MHL_DE_SEL);
420}
421
422static void mtk_hdmi_hw_aud_set_channel_swap(struct mtk_hdmi *hdmi,
423 enum hdmi_aud_channel_swap_type swap)
424{
425 u8 swap_bit;
426
427 switch (swap) {
428 case HDMI_AUD_SWAP_LR:
429 swap_bit = LR_SWAP;
430 break;
431 case HDMI_AUD_SWAP_LFE_CC:
432 swap_bit = LFE_CC_SWAP;
433 break;
434 case HDMI_AUD_SWAP_LSRS:
435 swap_bit = LSRS_SWAP;
436 break;
437 case HDMI_AUD_SWAP_RLS_RRS:
438 swap_bit = RLS_RRS_SWAP;
439 break;
440 case HDMI_AUD_SWAP_LR_STATUS:
441 swap_bit = LR_STATUS_SWAP;
442 break;
443 default:
444 swap_bit = LFE_CC_SWAP;
445 break;
446 }
447 mtk_hdmi_mask(hdmi, GRL_CH_SWAP, swap_bit, 0xff);
448}
449
450static void mtk_hdmi_hw_aud_set_bit_num(struct mtk_hdmi *hdmi,
451 enum hdmi_audio_sample_size bit_num)
452{
453 u32 val;
454
455 switch (bit_num) {
456 case HDMI_AUDIO_SAMPLE_SIZE_16:
457 val = AOUT_16BIT;
458 break;
459 case HDMI_AUDIO_SAMPLE_SIZE_20:
460 val = AOUT_20BIT;
461 break;
462 case HDMI_AUDIO_SAMPLE_SIZE_24:
463 case HDMI_AUDIO_SAMPLE_SIZE_STREAM:
464 val = AOUT_24BIT;
465 break;
466 }
467
468 mtk_hdmi_mask(hdmi, GRL_AOUT_CFG, val, AOUT_BNUM_SEL_MASK);
469}
470
471static void mtk_hdmi_hw_aud_set_i2s_fmt(struct mtk_hdmi *hdmi,
472 enum hdmi_aud_i2s_fmt i2s_fmt)
473{
474 u32 val;
475
476 val = mtk_hdmi_read(hdmi, GRL_CFG0);
477 val &= ~(CFG0_W_LENGTH_MASK | CFG0_I2S_MODE_MASK);
478
479 switch (i2s_fmt) {
480 case HDMI_I2S_MODE_RJT_24BIT:
481 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_24BIT;
482 break;
483 case HDMI_I2S_MODE_RJT_16BIT:
484 val |= CFG0_I2S_MODE_RTJ | CFG0_W_LENGTH_16BIT;
485 break;
486 case HDMI_I2S_MODE_LJT_24BIT:
487 default:
488 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_24BIT;
489 break;
490 case HDMI_I2S_MODE_LJT_16BIT:
491 val |= CFG0_I2S_MODE_LTJ | CFG0_W_LENGTH_16BIT;
492 break;
493 case HDMI_I2S_MODE_I2S_24BIT:
494 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_24BIT;
495 break;
496 case HDMI_I2S_MODE_I2S_16BIT:
497 val |= CFG0_I2S_MODE_I2S | CFG0_W_LENGTH_16BIT;
498 break;
499 }
500 mtk_hdmi_write(hdmi, GRL_CFG0, val);
501}
502
503static void mtk_hdmi_hw_audio_config(struct mtk_hdmi *hdmi, bool dst)
504{
505 const u8 mask = HIGH_BIT_RATE | DST_NORMAL_DOUBLE | SACD_DST | DSD_SEL;
506 u8 val;
507
508 /* Disable high bitrate, set DST packet normal/double */
509 mtk_hdmi_clear_bits(hdmi, GRL_AOUT_CFG, HIGH_BIT_RATE_PACKET_ALIGN);
510
511 if (dst)
512 val = DST_NORMAL_DOUBLE | SACD_DST;
513 else
514 val = 0;
515
516 mtk_hdmi_mask(hdmi, GRL_AUDIO_CFG, val, mask);
517}
518
519static void mtk_hdmi_hw_aud_set_i2s_chan_num(struct mtk_hdmi *hdmi,
520 enum hdmi_aud_channel_type channel_type,
521 u8 channel_count)
522{
523 unsigned int ch_switch;
524 u8 i2s_uv;
525
526 ch_switch = CH_SWITCH(7, 7) | CH_SWITCH(6, 6) |
527 CH_SWITCH(5, 5) | CH_SWITCH(4, 4) |
528 CH_SWITCH(3, 3) | CH_SWITCH(1, 2) |
529 CH_SWITCH(2, 1) | CH_SWITCH(0, 0);
530
531 if (channel_count == 2) {
532 i2s_uv = I2S_UV_CH_EN(0);
533 } else if (channel_count == 3 || channel_count == 4) {
534 if (channel_count == 4 &&
535 (channel_type == HDMI_AUD_CHAN_TYPE_3_0_LRS ||
536 channel_type == HDMI_AUD_CHAN_TYPE_4_0))
537 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(0);
538 else
539 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2);
540 } else if (channel_count == 6 || channel_count == 5) {
541 if (channel_count == 6 &&
542 channel_type != HDMI_AUD_CHAN_TYPE_5_1 &&
543 channel_type != HDMI_AUD_CHAN_TYPE_4_1_CLRS) {
544 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
545 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
546 } else {
547 i2s_uv = I2S_UV_CH_EN(2) | I2S_UV_CH_EN(1) |
548 I2S_UV_CH_EN(0);
549 }
550 } else if (channel_count == 8 || channel_count == 7) {
551 i2s_uv = I2S_UV_CH_EN(3) | I2S_UV_CH_EN(2) |
552 I2S_UV_CH_EN(1) | I2S_UV_CH_EN(0);
553 } else {
554 i2s_uv = I2S_UV_CH_EN(0);
555 }
556
557 mtk_hdmi_write(hdmi, GRL_CH_SW0, ch_switch & 0xff);
558 mtk_hdmi_write(hdmi, GRL_CH_SW1, (ch_switch >> 8) & 0xff);
559 mtk_hdmi_write(hdmi, GRL_CH_SW2, (ch_switch >> 16) & 0xff);
560 mtk_hdmi_write(hdmi, GRL_I2S_UV, i2s_uv);
561}
562
563static void mtk_hdmi_hw_aud_set_input_type(struct mtk_hdmi *hdmi,
564 enum hdmi_aud_input_type input_type)
565{
566 u32 val;
567
568 val = mtk_hdmi_read(hdmi, GRL_CFG1);
569 if (input_type == HDMI_AUD_INPUT_I2S &&
570 (val & CFG1_SPDIF) == CFG1_SPDIF) {
571 val &= ~CFG1_SPDIF;
572 } else if (input_type == HDMI_AUD_INPUT_SPDIF &&
573 (val & CFG1_SPDIF) == 0) {
574 val |= CFG1_SPDIF;
575 }
576 mtk_hdmi_write(hdmi, GRL_CFG1, val);
577}
578
579static void mtk_hdmi_hw_aud_set_channel_status(struct mtk_hdmi *hdmi,
580 u8 *channel_status)
581{
582 int i;
583
584 for (i = 0; i < 5; i++) {
585 mtk_hdmi_write(hdmi, GRL_I2S_C_STA0 + i * 4, channel_status[i]);
586 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, channel_status[i]);
587 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, channel_status[i]);
588 }
589 for (; i < 24; i++) {
590 mtk_hdmi_write(hdmi, GRL_L_STATUS_0 + i * 4, 0);
591 mtk_hdmi_write(hdmi, GRL_R_STATUS_0 + i * 4, 0);
592 }
593}
594
595static void mtk_hdmi_hw_aud_src_reenable(struct mtk_hdmi *hdmi)
596{
597 u32 val;
598
599 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
600 if (val & MIX_CTRL_SRC_EN) {
601 val &= ~MIX_CTRL_SRC_EN;
602 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
603 usleep_range(255, 512);
604 val |= MIX_CTRL_SRC_EN;
605 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
606 }
607}
608
609static void mtk_hdmi_hw_aud_src_disable(struct mtk_hdmi *hdmi)
610{
611 u32 val;
612
613 val = mtk_hdmi_read(hdmi, GRL_MIX_CTRL);
614 val &= ~MIX_CTRL_SRC_EN;
615 mtk_hdmi_write(hdmi, GRL_MIX_CTRL, val);
616 mtk_hdmi_write(hdmi, GRL_SHIFT_L1, 0x00);
617}
618
619static void mtk_hdmi_hw_aud_set_mclk(struct mtk_hdmi *hdmi,
620 enum hdmi_aud_mclk mclk)
621{
622 u32 val;
623
624 val = mtk_hdmi_read(hdmi, GRL_CFG5);
625 val &= CFG5_CD_RATIO_MASK;
626
627 switch (mclk) {
628 case HDMI_AUD_MCLK_128FS:
629 val |= CFG5_FS128;
630 break;
631 case HDMI_AUD_MCLK_256FS:
632 val |= CFG5_FS256;
633 break;
634 case HDMI_AUD_MCLK_384FS:
635 val |= CFG5_FS384;
636 break;
637 case HDMI_AUD_MCLK_512FS:
638 val |= CFG5_FS512;
639 break;
640 case HDMI_AUD_MCLK_768FS:
641 val |= CFG5_FS768;
642 break;
643 default:
644 val |= CFG5_FS256;
645 break;
646 }
647 mtk_hdmi_write(hdmi, GRL_CFG5, val);
648}
649
650struct hdmi_acr_n {
651 unsigned int clock;
652 unsigned int n[3];
653};
654
655/* Recommended N values from HDMI specification, tables 7-1 to 7-3 */
656static const struct hdmi_acr_n hdmi_rec_n_table[] = {
657 /* Clock, N: 32kHz 44.1kHz 48kHz */
658 { 25175, { 4576, 7007, 6864 } },
659 { 74176, { 11648, 17836, 11648 } },
660 { 148352, { 11648, 8918, 5824 } },
661 { 296703, { 5824, 4459, 5824 } },
662 { 297000, { 3072, 4704, 5120 } },
663 { 0, { 4096, 6272, 6144 } }, /* all other TMDS clocks */
664};
665
666/**
667 * hdmi_recommended_n() - Return N value recommended by HDMI specification
668 * @freq: audio sample rate in Hz
669 * @clock: rounded TMDS clock in kHz
670 */
671static unsigned int hdmi_recommended_n(unsigned int freq, unsigned int clock)
672{
673 const struct hdmi_acr_n *recommended;
674 unsigned int i;
675
676 for (i = 0; i < ARRAY_SIZE(hdmi_rec_n_table) - 1; i++) {
677 if (clock == hdmi_rec_n_table[i].clock)
678 break;
679 }
680 recommended = hdmi_rec_n_table + i;
681
682 switch (freq) {
683 case 32000:
684 return recommended->n[0];
685 case 44100:
686 return recommended->n[1];
687 case 48000:
688 return recommended->n[2];
689 case 88200:
690 return recommended->n[1] * 2;
691 case 96000:
692 return recommended->n[2] * 2;
693 case 176400:
694 return recommended->n[1] * 4;
695 case 192000:
696 return recommended->n[2] * 4;
697 default:
698 return (128 * freq) / 1000;
699 }
700}
701
702static unsigned int hdmi_mode_clock_to_hz(unsigned int clock)
703{
704 switch (clock) {
705 case 25175:
706 return 25174825; /* 25.2/1.001 MHz */
707 case 74176:
708 return 74175824; /* 74.25/1.001 MHz */
709 case 148352:
710 return 148351648; /* 148.5/1.001 MHz */
711 case 296703:
712 return 296703297; /* 297/1.001 MHz */
713 default:
714 return clock * 1000;
715 }
716}
717
718static unsigned int hdmi_expected_cts(unsigned int audio_sample_rate,
719 unsigned int tmds_clock, unsigned int n)
720{
721 return DIV_ROUND_CLOSEST_ULL((u64)hdmi_mode_clock_to_hz(tmds_clock) * n,
722 128 * audio_sample_rate);
723}
724
725static void do_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi, unsigned int n,
726 unsigned int cts)
727{
728 unsigned char val[NCTS_BYTES];
729 int i;
730
731 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
732 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
733 mtk_hdmi_write(hdmi, GRL_NCTS, 0);
734 memset(val, 0, sizeof(val));
735
736 val[0] = (cts >> 24) & 0xff;
737 val[1] = (cts >> 16) & 0xff;
738 val[2] = (cts >> 8) & 0xff;
739 val[3] = cts & 0xff;
740
741 val[4] = (n >> 16) & 0xff;
742 val[5] = (n >> 8) & 0xff;
743 val[6] = n & 0xff;
744
745 for (i = 0; i < NCTS_BYTES; i++)
746 mtk_hdmi_write(hdmi, GRL_NCTS, val[i]);
747}
748
749static void mtk_hdmi_hw_aud_set_ncts(struct mtk_hdmi *hdmi,
750 unsigned int sample_rate,
751 unsigned int clock)
752{
753 unsigned int n, cts;
754
755 n = hdmi_recommended_n(sample_rate, clock);
756 cts = hdmi_expected_cts(sample_rate, clock, n);
757
758 dev_dbg(hdmi->dev, "%s: sample_rate=%u, clock=%d, cts=%u, n=%u\n",
759 __func__, sample_rate, clock, n, cts);
760
761 mtk_hdmi_mask(hdmi, DUMMY_304, AUDIO_I2S_NCTS_SEL_64,
762 AUDIO_I2S_NCTS_SEL);
763 do_hdmi_hw_aud_set_ncts(hdmi, n, cts);
764}
765
766static u8 mtk_hdmi_aud_get_chnl_count(enum hdmi_aud_channel_type channel_type)
767{
768 switch (channel_type) {
769 case HDMI_AUD_CHAN_TYPE_1_0:
770 case HDMI_AUD_CHAN_TYPE_1_1:
771 case HDMI_AUD_CHAN_TYPE_2_0:
772 return 2;
773 case HDMI_AUD_CHAN_TYPE_2_1:
774 case HDMI_AUD_CHAN_TYPE_3_0:
775 return 3;
776 case HDMI_AUD_CHAN_TYPE_3_1:
777 case HDMI_AUD_CHAN_TYPE_4_0:
778 case HDMI_AUD_CHAN_TYPE_3_0_LRS:
779 return 4;
780 case HDMI_AUD_CHAN_TYPE_4_1:
781 case HDMI_AUD_CHAN_TYPE_5_0:
782 case HDMI_AUD_CHAN_TYPE_3_1_LRS:
783 case HDMI_AUD_CHAN_TYPE_4_0_CLRS:
784 return 5;
785 case HDMI_AUD_CHAN_TYPE_5_1:
786 case HDMI_AUD_CHAN_TYPE_6_0:
787 case HDMI_AUD_CHAN_TYPE_4_1_CLRS:
788 case HDMI_AUD_CHAN_TYPE_6_0_CS:
789 case HDMI_AUD_CHAN_TYPE_6_0_CH:
790 case HDMI_AUD_CHAN_TYPE_6_0_OH:
791 case HDMI_AUD_CHAN_TYPE_6_0_CHR:
792 return 6;
793 case HDMI_AUD_CHAN_TYPE_6_1:
794 case HDMI_AUD_CHAN_TYPE_6_1_CS:
795 case HDMI_AUD_CHAN_TYPE_6_1_CH:
796 case HDMI_AUD_CHAN_TYPE_6_1_OH:
797 case HDMI_AUD_CHAN_TYPE_6_1_CHR:
798 case HDMI_AUD_CHAN_TYPE_7_0:
799 case HDMI_AUD_CHAN_TYPE_7_0_LH_RH:
800 case HDMI_AUD_CHAN_TYPE_7_0_LSR_RSR:
801 case HDMI_AUD_CHAN_TYPE_7_0_LC_RC:
802 case HDMI_AUD_CHAN_TYPE_7_0_LW_RW:
803 case HDMI_AUD_CHAN_TYPE_7_0_LSD_RSD:
804 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS:
805 case HDMI_AUD_CHAN_TYPE_7_0_LHS_RHS:
806 case HDMI_AUD_CHAN_TYPE_7_0_CS_CH:
807 case HDMI_AUD_CHAN_TYPE_7_0_CS_OH:
808 case HDMI_AUD_CHAN_TYPE_7_0_CS_CHR:
809 case HDMI_AUD_CHAN_TYPE_7_0_CH_OH:
810 case HDMI_AUD_CHAN_TYPE_7_0_CH_CHR:
811 case HDMI_AUD_CHAN_TYPE_7_0_OH_CHR:
812 case HDMI_AUD_CHAN_TYPE_7_0_LSS_RSS_LSR_RSR:
813 case HDMI_AUD_CHAN_TYPE_8_0_LH_RH_CS:
814 return 7;
815 case HDMI_AUD_CHAN_TYPE_7_1:
816 case HDMI_AUD_CHAN_TYPE_7_1_LH_RH:
817 case HDMI_AUD_CHAN_TYPE_7_1_LSR_RSR:
818 case HDMI_AUD_CHAN_TYPE_7_1_LC_RC:
819 case HDMI_AUD_CHAN_TYPE_7_1_LW_RW:
820 case HDMI_AUD_CHAN_TYPE_7_1_LSD_RSD:
821 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS:
822 case HDMI_AUD_CHAN_TYPE_7_1_LHS_RHS:
823 case HDMI_AUD_CHAN_TYPE_7_1_CS_CH:
824 case HDMI_AUD_CHAN_TYPE_7_1_CS_OH:
825 case HDMI_AUD_CHAN_TYPE_7_1_CS_CHR:
826 case HDMI_AUD_CHAN_TYPE_7_1_CH_OH:
827 case HDMI_AUD_CHAN_TYPE_7_1_CH_CHR:
828 case HDMI_AUD_CHAN_TYPE_7_1_OH_CHR:
829 case HDMI_AUD_CHAN_TYPE_7_1_LSS_RSS_LSR_RSR:
830 return 8;
831 default:
832 return 2;
833 }
834}
835
836static int mtk_hdmi_video_change_vpll(struct mtk_hdmi *hdmi, u32 clock)
837{
838 unsigned long rate;
839 int ret;
840
841 /* The DPI driver already should have set TVDPLL to the correct rate */
842 ret = clk_set_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL], clock);
843 if (ret) {
844 dev_err(hdmi->dev, "Failed to set PLL to %u Hz: %d\n", clock,
845 ret);
846 return ret;
847 }
848
849 rate = clk_get_rate(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
850
851 if (DIV_ROUND_CLOSEST(rate, 1000) != DIV_ROUND_CLOSEST(clock, 1000))
852 dev_warn(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock,
853 rate);
854 else
855 dev_dbg(hdmi->dev, "Want PLL %u Hz, got %lu Hz\n", clock, rate);
856
857 mtk_hdmi_hw_config_sys(hdmi);
858 mtk_hdmi_hw_set_deep_color_mode(hdmi);
859 return 0;
860}
861
862static void mtk_hdmi_video_set_display_mode(struct mtk_hdmi *hdmi,
863 struct drm_display_mode *mode)
864{
865 mtk_hdmi_hw_reset(hdmi);
866 mtk_hdmi_hw_enable_notice(hdmi, true);
867 mtk_hdmi_hw_write_int_mask(hdmi, 0xff);
868 mtk_hdmi_hw_enable_dvi_mode(hdmi, hdmi->dvi_mode);
869 mtk_hdmi_hw_ncts_auto_write_enable(hdmi, true);
870
871 mtk_hdmi_hw_msic_setting(hdmi, mode);
872}
873
874
875static void mtk_hdmi_aud_set_input(struct mtk_hdmi *hdmi)
876{
877 enum hdmi_aud_channel_type chan_type;
878 u8 chan_count;
879 bool dst;
880
881 mtk_hdmi_hw_aud_set_channel_swap(hdmi, HDMI_AUD_SWAP_LFE_CC);
882 mtk_hdmi_set_bits(hdmi, GRL_MIX_CTRL, MIX_CTRL_FLAT);
883
884 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF &&
885 hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST) {
886 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
887 } else if (hdmi->aud_param.aud_i2s_fmt == HDMI_I2S_MODE_LJT_24BIT) {
888 hdmi->aud_param.aud_i2s_fmt = HDMI_I2S_MODE_LJT_16BIT;
889 }
890
891 mtk_hdmi_hw_aud_set_i2s_fmt(hdmi, hdmi->aud_param.aud_i2s_fmt);
892 mtk_hdmi_hw_aud_set_bit_num(hdmi, HDMI_AUDIO_SAMPLE_SIZE_24);
893
894 dst = ((hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF) &&
895 (hdmi->aud_param.aud_codec == HDMI_AUDIO_CODING_TYPE_DST));
896 mtk_hdmi_hw_audio_config(hdmi, dst);
897
898 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_SPDIF)
899 chan_type = HDMI_AUD_CHAN_TYPE_2_0;
900 else
901 chan_type = hdmi->aud_param.aud_input_chan_type;
902 chan_count = mtk_hdmi_aud_get_chnl_count(chan_type);
903 mtk_hdmi_hw_aud_set_i2s_chan_num(hdmi, chan_type, chan_count);
904 mtk_hdmi_hw_aud_set_input_type(hdmi, hdmi->aud_param.aud_input_type);
905}
906
907static int mtk_hdmi_aud_set_src(struct mtk_hdmi *hdmi,
908 struct drm_display_mode *display_mode)
909{
910 unsigned int sample_rate = hdmi->aud_param.codec_params.sample_rate;
911
912 mtk_hdmi_hw_ncts_enable(hdmi, false);
913 mtk_hdmi_hw_aud_src_disable(hdmi);
914 mtk_hdmi_clear_bits(hdmi, GRL_CFG2, CFG2_ACLK_INV);
915
916 if (hdmi->aud_param.aud_input_type == HDMI_AUD_INPUT_I2S) {
917 switch (sample_rate) {
918 case 32000:
919 case 44100:
920 case 48000:
921 case 88200:
922 case 96000:
923 break;
924 default:
925 return -EINVAL;
926 }
927 mtk_hdmi_hw_aud_set_mclk(hdmi, hdmi->aud_param.aud_mclk);
928 } else {
929 switch (sample_rate) {
930 case 32000:
931 case 44100:
932 case 48000:
933 break;
934 default:
935 return -EINVAL;
936 }
937 mtk_hdmi_hw_aud_set_mclk(hdmi, HDMI_AUD_MCLK_128FS);
938 }
939
940 mtk_hdmi_hw_aud_set_ncts(hdmi, sample_rate, display_mode->clock);
941
942 mtk_hdmi_hw_aud_src_reenable(hdmi);
943 return 0;
944}
945
946static int mtk_hdmi_aud_output_config(struct mtk_hdmi *hdmi,
947 struct drm_display_mode *display_mode)
948{
949 mtk_hdmi_hw_aud_mute(hdmi);
950 mtk_hdmi_hw_send_aud_packet(hdmi, false);
951
952 mtk_hdmi_aud_set_input(hdmi);
953 mtk_hdmi_aud_set_src(hdmi, display_mode);
954 mtk_hdmi_hw_aud_set_channel_status(hdmi,
955 hdmi->aud_param.codec_params.iec.status);
956
957 usleep_range(50, 100);
958
959 mtk_hdmi_hw_ncts_enable(hdmi, true);
960 mtk_hdmi_hw_send_aud_packet(hdmi, true);
961 mtk_hdmi_hw_aud_unmute(hdmi);
962 return 0;
963}
964
965static int mtk_hdmi_setup_avi_infoframe(struct mtk_hdmi *hdmi,
966 struct drm_display_mode *mode)
967{
968 struct hdmi_avi_infoframe frame;
969 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
970 ssize_t err;
971
972 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
973 hdmi->curr_conn, mode);
974 if (err < 0) {
975 dev_err(hdmi->dev,
976 "Failed to get AVI infoframe from mode: %zd\n", err);
977 return err;
978 }
979
980 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
981 if (err < 0) {
982 dev_err(hdmi->dev, "Failed to pack AVI infoframe: %zd\n", err);
983 return err;
984 }
985
986 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
987 return 0;
988}
989
990static int mtk_hdmi_setup_spd_infoframe(struct mtk_hdmi *hdmi,
991 const char *vendor,
992 const char *product)
993{
994 struct hdmi_spd_infoframe frame;
995 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_SPD_INFOFRAME_SIZE];
996 ssize_t err;
997
998 err = hdmi_spd_infoframe_init(&frame, vendor, product);
999 if (err < 0) {
1000 dev_err(hdmi->dev, "Failed to initialize SPD infoframe: %zd\n",
1001 err);
1002 return err;
1003 }
1004
1005 err = hdmi_spd_infoframe_pack(&frame, buffer, sizeof(buffer));
1006 if (err < 0) {
1007 dev_err(hdmi->dev, "Failed to pack SDP infoframe: %zd\n", err);
1008 return err;
1009 }
1010
1011 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1012 return 0;
1013}
1014
1015static int mtk_hdmi_setup_audio_infoframe(struct mtk_hdmi *hdmi)
1016{
1017 struct hdmi_audio_infoframe frame;
1018 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AUDIO_INFOFRAME_SIZE];
1019 ssize_t err;
1020
1021 err = hdmi_audio_infoframe_init(&frame);
1022 if (err < 0) {
1023 dev_err(hdmi->dev, "Failed to setup audio infoframe: %zd\n",
1024 err);
1025 return err;
1026 }
1027
1028 frame.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
1029 frame.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
1030 frame.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
1031 frame.channels = mtk_hdmi_aud_get_chnl_count(
1032 hdmi->aud_param.aud_input_chan_type);
1033
1034 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
1035 if (err < 0) {
1036 dev_err(hdmi->dev, "Failed to pack audio infoframe: %zd\n",
1037 err);
1038 return err;
1039 }
1040
1041 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1042 return 0;
1043}
1044
1045static int mtk_hdmi_setup_vendor_specific_infoframe(struct mtk_hdmi *hdmi,
1046 struct drm_display_mode *mode)
1047{
1048 struct hdmi_vendor_infoframe frame;
1049 u8 buffer[10];
1050 ssize_t err;
1051
1052 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame,
1053 hdmi->curr_conn, mode);
1054 if (err) {
1055 dev_err(hdmi->dev,
1056 "Failed to get vendor infoframe from mode: %zd\n", err);
1057 return err;
1058 }
1059
1060 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
1061 if (err < 0) {
1062 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n",
1063 err);
1064 return err;
1065 }
1066
1067 mtk_hdmi_hw_send_info_frame(hdmi, buffer, sizeof(buffer));
1068 return 0;
1069}
1070
1071static int mtk_hdmi_output_init(struct mtk_hdmi *hdmi)
1072{
1073 struct hdmi_audio_param *aud_param = &hdmi->aud_param;
1074
1075 hdmi->csp = HDMI_COLORSPACE_RGB;
1076 aud_param->aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1077 aud_param->aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1078 aud_param->aud_input_type = HDMI_AUD_INPUT_I2S;
1079 aud_param->aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1080 aud_param->aud_mclk = HDMI_AUD_MCLK_128FS;
1081 aud_param->aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1082
1083 return 0;
1084}
1085
1086static void mtk_hdmi_audio_enable(struct mtk_hdmi *hdmi)
1087{
1088 mtk_hdmi_hw_send_aud_packet(hdmi, true);
1089 hdmi->audio_enable = true;
1090}
1091
1092static void mtk_hdmi_audio_disable(struct mtk_hdmi *hdmi)
1093{
1094 mtk_hdmi_hw_send_aud_packet(hdmi, false);
1095 hdmi->audio_enable = false;
1096}
1097
1098static int mtk_hdmi_audio_set_param(struct mtk_hdmi *hdmi,
1099 struct hdmi_audio_param *param)
1100{
1101 if (!hdmi->audio_enable) {
1102 dev_err(hdmi->dev, "hdmi audio is in disable state!\n");
1103 return -EINVAL;
1104 }
1105 dev_dbg(hdmi->dev, "codec:%d, input:%d, channel:%d, fs:%d\n",
1106 param->aud_codec, param->aud_input_type,
1107 param->aud_input_chan_type, param->codec_params.sample_rate);
1108 memcpy(&hdmi->aud_param, param, sizeof(*param));
1109 return mtk_hdmi_aud_output_config(hdmi, &hdmi->mode);
1110}
1111
1112static int mtk_hdmi_output_set_display_mode(struct mtk_hdmi *hdmi,
1113 struct drm_display_mode *mode)
1114{
1115 int ret;
1116
1117 mtk_hdmi_hw_vid_black(hdmi, true);
1118 mtk_hdmi_hw_aud_mute(hdmi);
1119 mtk_hdmi_hw_send_av_mute(hdmi);
1120 phy_power_off(hdmi->phy);
1121
1122 ret = mtk_hdmi_video_change_vpll(hdmi,
1123 mode->clock * 1000);
1124 if (ret) {
1125 dev_err(hdmi->dev, "Failed to set vpll: %d\n", ret);
1126 return ret;
1127 }
1128 mtk_hdmi_video_set_display_mode(hdmi, mode);
1129
1130 phy_power_on(hdmi->phy);
1131 mtk_hdmi_aud_output_config(hdmi, mode);
1132
1133 mtk_hdmi_hw_vid_black(hdmi, false);
1134 mtk_hdmi_hw_aud_unmute(hdmi);
1135 mtk_hdmi_hw_send_av_unmute(hdmi);
1136
1137 return 0;
1138}
1139
1140static const char * const mtk_hdmi_clk_names[MTK_HDMI_CLK_COUNT] = {
1141 [MTK_HDMI_CLK_HDMI_PIXEL] = "pixel",
1142 [MTK_HDMI_CLK_HDMI_PLL] = "pll",
1143 [MTK_HDMI_CLK_AUD_BCLK] = "bclk",
1144 [MTK_HDMI_CLK_AUD_SPDIF] = "spdif",
1145};
1146
1147static int mtk_hdmi_get_all_clk(struct mtk_hdmi *hdmi,
1148 struct device_node *np)
1149{
1150 int i;
1151
1152 for (i = 0; i < ARRAY_SIZE(mtk_hdmi_clk_names); i++) {
1153 hdmi->clk[i] = of_clk_get_by_name(np,
1154 mtk_hdmi_clk_names[i]);
1155 if (IS_ERR(hdmi->clk[i]))
1156 return PTR_ERR(hdmi->clk[i]);
1157 }
1158 return 0;
1159}
1160
1161static int mtk_hdmi_clk_enable_audio(struct mtk_hdmi *hdmi)
1162{
1163 int ret;
1164
1165 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1166 if (ret)
1167 return ret;
1168
1169 ret = clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1170 if (ret)
1171 goto err;
1172
1173 return 0;
1174err:
1175 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1176 return ret;
1177}
1178
1179static void mtk_hdmi_clk_disable_audio(struct mtk_hdmi *hdmi)
1180{
1181 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_BCLK]);
1182 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_AUD_SPDIF]);
1183}
1184
1185static enum drm_connector_status
1186mtk_hdmi_update_plugged_status(struct mtk_hdmi *hdmi)
1187{
1188 bool connected;
1189
1190 mutex_lock(&hdmi->update_plugged_status_lock);
1191 connected = mtk_cec_hpd_high(hdmi->cec_dev);
1192 if (hdmi->plugged_cb && hdmi->codec_dev)
1193 hdmi->plugged_cb(hdmi->codec_dev, connected);
1194 mutex_unlock(&hdmi->update_plugged_status_lock);
1195
1196 return connected ?
1197 connector_status_connected : connector_status_disconnected;
1198}
1199
1200static enum drm_connector_status mtk_hdmi_detect(struct mtk_hdmi *hdmi)
1201{
1202 return mtk_hdmi_update_plugged_status(hdmi);
1203}
1204
1205static enum drm_mode_status
1206mtk_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
1207 const struct drm_display_info *info,
1208 const struct drm_display_mode *mode)
1209{
1210 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1211 struct drm_bridge *next_bridge;
1212
1213 dev_dbg(hdmi->dev, "xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1214 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1215 !!(mode->flags & DRM_MODE_FLAG_INTERLACE), mode->clock * 1000);
1216
1217 next_bridge = drm_bridge_get_next_bridge(&hdmi->bridge);
1218 if (next_bridge) {
1219 struct drm_display_mode adjusted_mode;
1220
1221 drm_mode_init(&adjusted_mode, mode);
1222 if (!drm_bridge_chain_mode_fixup(next_bridge, mode,
1223 &adjusted_mode))
1224 return MODE_BAD;
1225 }
1226
1227 if (hdmi->conf) {
1228 if (hdmi->conf->cea_modes_only && !drm_match_cea_mode(mode))
1229 return MODE_BAD;
1230
1231 if (hdmi->conf->max_mode_clock &&
1232 mode->clock > hdmi->conf->max_mode_clock)
1233 return MODE_CLOCK_HIGH;
1234 }
1235
1236 if (mode->clock < 27000)
1237 return MODE_CLOCK_LOW;
1238 if (mode->clock > 297000)
1239 return MODE_CLOCK_HIGH;
1240
1241 return drm_mode_validate_size(mode, 0x1fff, 0x1fff);
1242}
1243
1244static void mtk_hdmi_hpd_event(bool hpd, struct device *dev)
1245{
1246 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1247
1248 if (hdmi && hdmi->bridge.encoder && hdmi->bridge.encoder->dev) {
1249 static enum drm_connector_status status;
1250
1251 status = mtk_hdmi_detect(hdmi);
1252 drm_helper_hpd_irq_event(hdmi->bridge.encoder->dev);
1253 drm_bridge_hpd_notify(&hdmi->bridge, status);
1254 }
1255}
1256
1257/*
1258 * Bridge callbacks
1259 */
1260
1261static enum drm_connector_status mtk_hdmi_bridge_detect(struct drm_bridge *bridge)
1262{
1263 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1264
1265 return mtk_hdmi_detect(hdmi);
1266}
1267
1268static struct edid *mtk_hdmi_bridge_get_edid(struct drm_bridge *bridge,
1269 struct drm_connector *connector)
1270{
1271 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1272 struct edid *edid;
1273
1274 if (!hdmi->ddc_adpt)
1275 return NULL;
1276 edid = drm_get_edid(connector, hdmi->ddc_adpt);
1277 if (!edid)
1278 return NULL;
1279 hdmi->dvi_mode = !drm_detect_monitor_audio(edid);
1280 return edid;
1281}
1282
1283static int mtk_hdmi_bridge_attach(struct drm_bridge *bridge,
1284 enum drm_bridge_attach_flags flags)
1285{
1286 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1287 int ret;
1288
1289 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
1290 DRM_ERROR("%s: The flag DRM_BRIDGE_ATTACH_NO_CONNECTOR must be supplied\n",
1291 __func__);
1292 return -EINVAL;
1293 }
1294
1295 if (hdmi->next_bridge) {
1296 ret = drm_bridge_attach(bridge->encoder, hdmi->next_bridge,
1297 bridge, flags);
1298 if (ret)
1299 return ret;
1300 }
1301
1302 mtk_cec_set_hpd_event(hdmi->cec_dev, mtk_hdmi_hpd_event, hdmi->dev);
1303
1304 return 0;
1305}
1306
1307static bool mtk_hdmi_bridge_mode_fixup(struct drm_bridge *bridge,
1308 const struct drm_display_mode *mode,
1309 struct drm_display_mode *adjusted_mode)
1310{
1311 return true;
1312}
1313
1314static void mtk_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
1315 struct drm_bridge_state *old_bridge_state)
1316{
1317 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1318
1319 if (!hdmi->enabled)
1320 return;
1321
1322 phy_power_off(hdmi->phy);
1323 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1324 clk_disable_unprepare(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1325
1326 hdmi->curr_conn = NULL;
1327
1328 hdmi->enabled = false;
1329}
1330
1331static void mtk_hdmi_bridge_atomic_post_disable(struct drm_bridge *bridge,
1332 struct drm_bridge_state *old_state)
1333{
1334 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1335
1336 if (!hdmi->powered)
1337 return;
1338
1339 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1340 mtk_hdmi_hw_make_reg_writable(hdmi, false);
1341
1342 hdmi->powered = false;
1343}
1344
1345static void mtk_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1346 const struct drm_display_mode *mode,
1347 const struct drm_display_mode *adjusted_mode)
1348{
1349 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1350
1351 dev_dbg(hdmi->dev, "cur info: name:%s, hdisplay:%d\n",
1352 adjusted_mode->name, adjusted_mode->hdisplay);
1353 dev_dbg(hdmi->dev, "hsync_start:%d,hsync_end:%d, htotal:%d",
1354 adjusted_mode->hsync_start, adjusted_mode->hsync_end,
1355 adjusted_mode->htotal);
1356 dev_dbg(hdmi->dev, "hskew:%d, vdisplay:%d\n",
1357 adjusted_mode->hskew, adjusted_mode->vdisplay);
1358 dev_dbg(hdmi->dev, "vsync_start:%d, vsync_end:%d, vtotal:%d",
1359 adjusted_mode->vsync_start, adjusted_mode->vsync_end,
1360 adjusted_mode->vtotal);
1361 dev_dbg(hdmi->dev, "vscan:%d, flag:%d\n",
1362 adjusted_mode->vscan, adjusted_mode->flags);
1363
1364 drm_mode_copy(&hdmi->mode, adjusted_mode);
1365}
1366
1367static void mtk_hdmi_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1368 struct drm_bridge_state *old_state)
1369{
1370 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1371
1372 mtk_hdmi_hw_make_reg_writable(hdmi, true);
1373 mtk_hdmi_hw_1p4_version_enable(hdmi, true);
1374
1375 hdmi->powered = true;
1376}
1377
1378static void mtk_hdmi_send_infoframe(struct mtk_hdmi *hdmi,
1379 struct drm_display_mode *mode)
1380{
1381 mtk_hdmi_setup_audio_infoframe(hdmi);
1382 mtk_hdmi_setup_avi_infoframe(hdmi, mode);
1383 mtk_hdmi_setup_spd_infoframe(hdmi, "mediatek", "On-chip HDMI");
1384 if (mode->flags & DRM_MODE_FLAG_3D_MASK)
1385 mtk_hdmi_setup_vendor_specific_infoframe(hdmi, mode);
1386}
1387
1388static void mtk_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
1389 struct drm_bridge_state *old_state)
1390{
1391 struct drm_atomic_state *state = old_state->base.state;
1392 struct mtk_hdmi *hdmi = hdmi_ctx_from_bridge(bridge);
1393
1394 /* Retrieve the connector through the atomic state. */
1395 hdmi->curr_conn = drm_atomic_get_new_connector_for_encoder(state,
1396 bridge->encoder);
1397
1398 mtk_hdmi_output_set_display_mode(hdmi, &hdmi->mode);
1399 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PLL]);
1400 clk_prepare_enable(hdmi->clk[MTK_HDMI_CLK_HDMI_PIXEL]);
1401 phy_power_on(hdmi->phy);
1402 mtk_hdmi_send_infoframe(hdmi, &hdmi->mode);
1403
1404 hdmi->enabled = true;
1405}
1406
1407static const struct drm_bridge_funcs mtk_hdmi_bridge_funcs = {
1408 .mode_valid = mtk_hdmi_bridge_mode_valid,
1409 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1410 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1411 .atomic_reset = drm_atomic_helper_bridge_reset,
1412 .attach = mtk_hdmi_bridge_attach,
1413 .mode_fixup = mtk_hdmi_bridge_mode_fixup,
1414 .atomic_disable = mtk_hdmi_bridge_atomic_disable,
1415 .atomic_post_disable = mtk_hdmi_bridge_atomic_post_disable,
1416 .mode_set = mtk_hdmi_bridge_mode_set,
1417 .atomic_pre_enable = mtk_hdmi_bridge_atomic_pre_enable,
1418 .atomic_enable = mtk_hdmi_bridge_atomic_enable,
1419 .detect = mtk_hdmi_bridge_detect,
1420 .get_edid = mtk_hdmi_bridge_get_edid,
1421};
1422
1423static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
1424 struct platform_device *pdev)
1425{
1426 struct device *dev = &pdev->dev;
1427 struct device_node *np = dev->of_node;
1428 struct device_node *cec_np, *remote, *i2c_np;
1429 struct platform_device *cec_pdev;
1430 struct regmap *regmap;
1431 struct resource *mem;
1432 int ret;
1433
1434 ret = mtk_hdmi_get_all_clk(hdmi, np);
1435 if (ret) {
1436 if (ret != -EPROBE_DEFER)
1437 dev_err(dev, "Failed to get clocks: %d\n", ret);
1438
1439 return ret;
1440 }
1441
1442 /* The CEC module handles HDMI hotplug detection */
1443 cec_np = of_get_compatible_child(np->parent, "mediatek,mt8173-cec");
1444 if (!cec_np) {
1445 dev_err(dev, "Failed to find CEC node\n");
1446 return -EINVAL;
1447 }
1448
1449 cec_pdev = of_find_device_by_node(cec_np);
1450 if (!cec_pdev) {
1451 dev_err(hdmi->dev, "Waiting for CEC device %pOF\n",
1452 cec_np);
1453 of_node_put(cec_np);
1454 return -EPROBE_DEFER;
1455 }
1456 of_node_put(cec_np);
1457 hdmi->cec_dev = &cec_pdev->dev;
1458
1459 /*
1460 * The mediatek,syscon-hdmi property contains a phandle link to the
1461 * MMSYS_CONFIG device and the register offset of the HDMI_SYS_CFG
1462 * registers it contains.
1463 */
1464 regmap = syscon_regmap_lookup_by_phandle(np, "mediatek,syscon-hdmi");
1465 ret = of_property_read_u32_index(np, "mediatek,syscon-hdmi", 1,
1466 &hdmi->sys_offset);
1467 if (IS_ERR(regmap))
1468 ret = PTR_ERR(regmap);
1469 if (ret) {
1470 dev_err(dev,
1471 "Failed to get system configuration registers: %d\n",
1472 ret);
1473 goto put_device;
1474 }
1475 hdmi->sys_regmap = regmap;
1476
1477 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1478 hdmi->regs = devm_ioremap_resource(dev, mem);
1479 if (IS_ERR(hdmi->regs)) {
1480 ret = PTR_ERR(hdmi->regs);
1481 goto put_device;
1482 }
1483
1484 remote = of_graph_get_remote_node(np, 1, 0);
1485 if (!remote) {
1486 ret = -EINVAL;
1487 goto put_device;
1488 }
1489
1490 if (!of_device_is_compatible(remote, "hdmi-connector")) {
1491 hdmi->next_bridge = of_drm_find_bridge(remote);
1492 if (!hdmi->next_bridge) {
1493 dev_err(dev, "Waiting for external bridge\n");
1494 of_node_put(remote);
1495 ret = -EPROBE_DEFER;
1496 goto put_device;
1497 }
1498 }
1499
1500 i2c_np = of_parse_phandle(remote, "ddc-i2c-bus", 0);
1501 if (!i2c_np) {
1502 dev_err(dev, "Failed to find ddc-i2c-bus node in %pOF\n",
1503 remote);
1504 of_node_put(remote);
1505 ret = -EINVAL;
1506 goto put_device;
1507 }
1508 of_node_put(remote);
1509
1510 hdmi->ddc_adpt = of_find_i2c_adapter_by_node(i2c_np);
1511 of_node_put(i2c_np);
1512 if (!hdmi->ddc_adpt) {
1513 dev_err(dev, "Failed to get ddc i2c adapter by node\n");
1514 ret = -EINVAL;
1515 goto put_device;
1516 }
1517
1518 return 0;
1519put_device:
1520 put_device(hdmi->cec_dev);
1521 return ret;
1522}
1523
1524/*
1525 * HDMI audio codec callbacks
1526 */
1527
1528static int mtk_hdmi_audio_hw_params(struct device *dev, void *data,
1529 struct hdmi_codec_daifmt *daifmt,
1530 struct hdmi_codec_params *params)
1531{
1532 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1533 struct hdmi_audio_param hdmi_params;
1534 unsigned int chan = params->cea.channels;
1535
1536 dev_dbg(hdmi->dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1537 params->sample_rate, params->sample_width, chan);
1538
1539 if (!hdmi->bridge.encoder)
1540 return -ENODEV;
1541
1542 switch (chan) {
1543 case 2:
1544 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_2_0;
1545 break;
1546 case 4:
1547 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_4_0;
1548 break;
1549 case 6:
1550 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_5_1;
1551 break;
1552 case 8:
1553 hdmi_params.aud_input_chan_type = HDMI_AUD_CHAN_TYPE_7_1;
1554 break;
1555 default:
1556 dev_err(hdmi->dev, "channel[%d] not supported!\n", chan);
1557 return -EINVAL;
1558 }
1559
1560 switch (params->sample_rate) {
1561 case 32000:
1562 case 44100:
1563 case 48000:
1564 case 88200:
1565 case 96000:
1566 case 176400:
1567 case 192000:
1568 break;
1569 default:
1570 dev_err(hdmi->dev, "rate[%d] not supported!\n",
1571 params->sample_rate);
1572 return -EINVAL;
1573 }
1574
1575 switch (daifmt->fmt) {
1576 case HDMI_I2S:
1577 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1578 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1579 hdmi_params.aud_input_type = HDMI_AUD_INPUT_I2S;
1580 hdmi_params.aud_i2s_fmt = HDMI_I2S_MODE_I2S_24BIT;
1581 hdmi_params.aud_mclk = HDMI_AUD_MCLK_128FS;
1582 break;
1583 case HDMI_SPDIF:
1584 hdmi_params.aud_codec = HDMI_AUDIO_CODING_TYPE_PCM;
1585 hdmi_params.aud_sampe_size = HDMI_AUDIO_SAMPLE_SIZE_16;
1586 hdmi_params.aud_input_type = HDMI_AUD_INPUT_SPDIF;
1587 break;
1588 default:
1589 dev_err(hdmi->dev, "%s: Invalid DAI format %d\n", __func__,
1590 daifmt->fmt);
1591 return -EINVAL;
1592 }
1593
1594 memcpy(&hdmi_params.codec_params, params,
1595 sizeof(hdmi_params.codec_params));
1596
1597 mtk_hdmi_audio_set_param(hdmi, &hdmi_params);
1598
1599 return 0;
1600}
1601
1602static int mtk_hdmi_audio_startup(struct device *dev, void *data)
1603{
1604 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1605
1606 mtk_hdmi_audio_enable(hdmi);
1607
1608 return 0;
1609}
1610
1611static void mtk_hdmi_audio_shutdown(struct device *dev, void *data)
1612{
1613 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1614
1615 mtk_hdmi_audio_disable(hdmi);
1616}
1617
1618static int
1619mtk_hdmi_audio_mute(struct device *dev, void *data,
1620 bool enable, int direction)
1621{
1622 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1623
1624 if (enable)
1625 mtk_hdmi_hw_aud_mute(hdmi);
1626 else
1627 mtk_hdmi_hw_aud_unmute(hdmi);
1628
1629 return 0;
1630}
1631
1632static int mtk_hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1633{
1634 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1635
1636 if (hdmi->enabled)
1637 memcpy(buf, hdmi->curr_conn->eld, min(sizeof(hdmi->curr_conn->eld), len));
1638 else
1639 memset(buf, 0, len);
1640 return 0;
1641}
1642
1643static int mtk_hdmi_audio_hook_plugged_cb(struct device *dev, void *data,
1644 hdmi_codec_plugged_cb fn,
1645 struct device *codec_dev)
1646{
1647 struct mtk_hdmi *hdmi = data;
1648
1649 mutex_lock(&hdmi->update_plugged_status_lock);
1650 hdmi->plugged_cb = fn;
1651 hdmi->codec_dev = codec_dev;
1652 mutex_unlock(&hdmi->update_plugged_status_lock);
1653
1654 mtk_hdmi_update_plugged_status(hdmi);
1655
1656 return 0;
1657}
1658
1659static const struct hdmi_codec_ops mtk_hdmi_audio_codec_ops = {
1660 .hw_params = mtk_hdmi_audio_hw_params,
1661 .audio_startup = mtk_hdmi_audio_startup,
1662 .audio_shutdown = mtk_hdmi_audio_shutdown,
1663 .mute_stream = mtk_hdmi_audio_mute,
1664 .get_eld = mtk_hdmi_audio_get_eld,
1665 .hook_plugged_cb = mtk_hdmi_audio_hook_plugged_cb,
1666 .no_capture_mute = 1,
1667};
1668
1669static int mtk_hdmi_register_audio_driver(struct device *dev)
1670{
1671 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1672 struct hdmi_codec_pdata codec_data = {
1673 .ops = &mtk_hdmi_audio_codec_ops,
1674 .max_i2s_channels = 2,
1675 .i2s = 1,
1676 .data = hdmi,
1677 };
1678 struct platform_device *pdev;
1679
1680 pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
1681 PLATFORM_DEVID_AUTO, &codec_data,
1682 sizeof(codec_data));
1683 if (IS_ERR(pdev))
1684 return PTR_ERR(pdev);
1685
1686 DRM_INFO("%s driver bound to HDMI\n", HDMI_CODEC_DRV_NAME);
1687 return 0;
1688}
1689
1690static int mtk_drm_hdmi_probe(struct platform_device *pdev)
1691{
1692 struct mtk_hdmi *hdmi;
1693 struct device *dev = &pdev->dev;
1694 int ret;
1695
1696 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1697 if (!hdmi)
1698 return -ENOMEM;
1699
1700 hdmi->dev = dev;
1701 hdmi->conf = of_device_get_match_data(dev);
1702
1703 ret = mtk_hdmi_dt_parse_pdata(hdmi, pdev);
1704 if (ret)
1705 return ret;
1706
1707 hdmi->phy = devm_phy_get(dev, "hdmi");
1708 if (IS_ERR(hdmi->phy)) {
1709 ret = PTR_ERR(hdmi->phy);
1710 dev_err(dev, "Failed to get HDMI PHY: %d\n", ret);
1711 return ret;
1712 }
1713
1714 mutex_init(&hdmi->update_plugged_status_lock);
1715 platform_set_drvdata(pdev, hdmi);
1716
1717 ret = mtk_hdmi_output_init(hdmi);
1718 if (ret) {
1719 dev_err(dev, "Failed to initialize hdmi output\n");
1720 return ret;
1721 }
1722
1723 ret = mtk_hdmi_register_audio_driver(dev);
1724 if (ret) {
1725 dev_err(dev, "Failed to register audio driver: %d\n", ret);
1726 return ret;
1727 }
1728
1729 hdmi->bridge.funcs = &mtk_hdmi_bridge_funcs;
1730 hdmi->bridge.of_node = pdev->dev.of_node;
1731 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
1732 | DRM_BRIDGE_OP_HPD;
1733 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1734 drm_bridge_add(&hdmi->bridge);
1735
1736 ret = mtk_hdmi_clk_enable_audio(hdmi);
1737 if (ret) {
1738 dev_err(dev, "Failed to enable audio clocks: %d\n", ret);
1739 goto err_bridge_remove;
1740 }
1741
1742 return 0;
1743
1744err_bridge_remove:
1745 drm_bridge_remove(&hdmi->bridge);
1746 return ret;
1747}
1748
1749static void mtk_drm_hdmi_remove(struct platform_device *pdev)
1750{
1751 struct mtk_hdmi *hdmi = platform_get_drvdata(pdev);
1752
1753 drm_bridge_remove(&hdmi->bridge);
1754 mtk_hdmi_clk_disable_audio(hdmi);
1755}
1756
1757#ifdef CONFIG_PM_SLEEP
1758static int mtk_hdmi_suspend(struct device *dev)
1759{
1760 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1761
1762 mtk_hdmi_clk_disable_audio(hdmi);
1763
1764 return 0;
1765}
1766
1767static int mtk_hdmi_resume(struct device *dev)
1768{
1769 struct mtk_hdmi *hdmi = dev_get_drvdata(dev);
1770 int ret = 0;
1771
1772 ret = mtk_hdmi_clk_enable_audio(hdmi);
1773 if (ret) {
1774 dev_err(dev, "hdmi resume failed!\n");
1775 return ret;
1776 }
1777
1778 return 0;
1779}
1780#endif
1781static SIMPLE_DEV_PM_OPS(mtk_hdmi_pm_ops,
1782 mtk_hdmi_suspend, mtk_hdmi_resume);
1783
1784static const struct mtk_hdmi_conf mtk_hdmi_conf_mt2701 = {
1785 .tz_disabled = true,
1786};
1787
1788static const struct mtk_hdmi_conf mtk_hdmi_conf_mt8167 = {
1789 .max_mode_clock = 148500,
1790 .cea_modes_only = true,
1791};
1792
1793static const struct of_device_id mtk_drm_hdmi_of_ids[] = {
1794 { .compatible = "mediatek,mt2701-hdmi",
1795 .data = &mtk_hdmi_conf_mt2701,
1796 },
1797 { .compatible = "mediatek,mt8167-hdmi",
1798 .data = &mtk_hdmi_conf_mt8167,
1799 },
1800 { .compatible = "mediatek,mt8173-hdmi",
1801 },
1802 {}
1803};
1804MODULE_DEVICE_TABLE(of, mtk_drm_hdmi_of_ids);
1805
1806static struct platform_driver mtk_hdmi_driver = {
1807 .probe = mtk_drm_hdmi_probe,
1808 .remove_new = mtk_drm_hdmi_remove,
1809 .driver = {
1810 .name = "mediatek-drm-hdmi",
1811 .of_match_table = mtk_drm_hdmi_of_ids,
1812 .pm = &mtk_hdmi_pm_ops,
1813 },
1814};
1815
1816static struct platform_driver * const mtk_hdmi_drivers[] = {
1817 &mtk_hdmi_ddc_driver,
1818 &mtk_cec_driver,
1819 &mtk_hdmi_driver,
1820};
1821
1822static int __init mtk_hdmitx_init(void)
1823{
1824 return platform_register_drivers(mtk_hdmi_drivers,
1825 ARRAY_SIZE(mtk_hdmi_drivers));
1826}
1827
1828static void __exit mtk_hdmitx_exit(void)
1829{
1830 platform_unregister_drivers(mtk_hdmi_drivers,
1831 ARRAY_SIZE(mtk_hdmi_drivers));
1832}
1833
1834module_init(mtk_hdmitx_init);
1835module_exit(mtk_hdmitx_exit);
1836
1837MODULE_AUTHOR("Jie Qiu <jie.qiu@mediatek.com>");
1838MODULE_DESCRIPTION("MediaTek HDMI Driver");
1839MODULE_LICENSE("GPL v2");