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1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Zhi Wang <zhi.a.wang@intel.com>
26 *
27 * Contributors:
28 * Min he <min.he@intel.com>
29 *
30 */
31
32#include <linux/eventfd.h>
33
34#include "i915_drv.h"
35#include "i915_reg.h"
36#include "gvt.h"
37#include "trace.h"
38
39struct intel_gvt_irq_info {
40 char *name;
41 i915_reg_t reg_base;
42 enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH];
43 unsigned long warned;
44 int group;
45 DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH);
46 bool has_upstream_irq;
47};
48
49struct intel_gvt_irq_map {
50 int up_irq_group;
51 int up_irq_bit;
52 int down_irq_group;
53 u32 down_irq_bitmask;
54};
55
56/* common offset among interrupt control registers */
57#define regbase_to_isr(base) (base)
58#define regbase_to_imr(base) (base + 0x4)
59#define regbase_to_iir(base) (base + 0x8)
60#define regbase_to_ier(base) (base + 0xC)
61
62#define iir_to_regbase(iir) (iir - 0x8)
63#define ier_to_regbase(ier) (ier - 0xC)
64
65#define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
66#define get_irq_info(irq, e) (irq->events[e].info)
67
68#define irq_to_gvt(irq) \
69 container_of(irq, struct intel_gvt, irq)
70
71static void update_upstream_irq(struct intel_vgpu *vgpu,
72 struct intel_gvt_irq_info *info);
73
74static const char * const irq_name[INTEL_GVT_EVENT_MAX] = {
75 [RCS_MI_USER_INTERRUPT] = "Render CS MI USER INTERRUPT",
76 [RCS_DEBUG] = "Render EU debug from SVG",
77 [RCS_MMIO_SYNC_FLUSH] = "Render MMIO sync flush status",
78 [RCS_CMD_STREAMER_ERR] = "Render CS error interrupt",
79 [RCS_PIPE_CONTROL] = "Render PIPE CONTROL notify",
80 [RCS_WATCHDOG_EXCEEDED] = "Render CS Watchdog counter exceeded",
81 [RCS_PAGE_DIRECTORY_FAULT] = "Render page directory faults",
82 [RCS_AS_CONTEXT_SWITCH] = "Render AS Context Switch Interrupt",
83
84 [VCS_MI_USER_INTERRUPT] = "Video CS MI USER INTERRUPT",
85 [VCS_MMIO_SYNC_FLUSH] = "Video MMIO sync flush status",
86 [VCS_CMD_STREAMER_ERR] = "Video CS error interrupt",
87 [VCS_MI_FLUSH_DW] = "Video MI FLUSH DW notify",
88 [VCS_WATCHDOG_EXCEEDED] = "Video CS Watchdog counter exceeded",
89 [VCS_PAGE_DIRECTORY_FAULT] = "Video page directory faults",
90 [VCS_AS_CONTEXT_SWITCH] = "Video AS Context Switch Interrupt",
91 [VCS2_MI_USER_INTERRUPT] = "VCS2 Video CS MI USER INTERRUPT",
92 [VCS2_MI_FLUSH_DW] = "VCS2 Video MI FLUSH DW notify",
93 [VCS2_AS_CONTEXT_SWITCH] = "VCS2 Context Switch Interrupt",
94
95 [BCS_MI_USER_INTERRUPT] = "Blitter CS MI USER INTERRUPT",
96 [BCS_MMIO_SYNC_FLUSH] = "Billter MMIO sync flush status",
97 [BCS_CMD_STREAMER_ERR] = "Blitter CS error interrupt",
98 [BCS_MI_FLUSH_DW] = "Blitter MI FLUSH DW notify",
99 [BCS_PAGE_DIRECTORY_FAULT] = "Blitter page directory faults",
100 [BCS_AS_CONTEXT_SWITCH] = "Blitter AS Context Switch Interrupt",
101
102 [VECS_MI_FLUSH_DW] = "Video Enhanced Streamer MI FLUSH DW notify",
103 [VECS_AS_CONTEXT_SWITCH] = "VECS Context Switch Interrupt",
104
105 [PIPE_A_FIFO_UNDERRUN] = "Pipe A FIFO underrun",
106 [PIPE_A_CRC_ERR] = "Pipe A CRC error",
107 [PIPE_A_CRC_DONE] = "Pipe A CRC done",
108 [PIPE_A_VSYNC] = "Pipe A vsync",
109 [PIPE_A_LINE_COMPARE] = "Pipe A line compare",
110 [PIPE_A_ODD_FIELD] = "Pipe A odd field",
111 [PIPE_A_EVEN_FIELD] = "Pipe A even field",
112 [PIPE_A_VBLANK] = "Pipe A vblank",
113 [PIPE_B_FIFO_UNDERRUN] = "Pipe B FIFO underrun",
114 [PIPE_B_CRC_ERR] = "Pipe B CRC error",
115 [PIPE_B_CRC_DONE] = "Pipe B CRC done",
116 [PIPE_B_VSYNC] = "Pipe B vsync",
117 [PIPE_B_LINE_COMPARE] = "Pipe B line compare",
118 [PIPE_B_ODD_FIELD] = "Pipe B odd field",
119 [PIPE_B_EVEN_FIELD] = "Pipe B even field",
120 [PIPE_B_VBLANK] = "Pipe B vblank",
121 [PIPE_C_VBLANK] = "Pipe C vblank",
122 [DPST_PHASE_IN] = "DPST phase in event",
123 [DPST_HISTOGRAM] = "DPST histogram event",
124 [GSE] = "GSE",
125 [DP_A_HOTPLUG] = "DP A Hotplug",
126 [AUX_CHANNEL_A] = "AUX Channel A",
127 [PERF_COUNTER] = "Performance counter",
128 [POISON] = "Poison",
129 [GTT_FAULT] = "GTT fault",
130 [PRIMARY_A_FLIP_DONE] = "Primary Plane A flip done",
131 [PRIMARY_B_FLIP_DONE] = "Primary Plane B flip done",
132 [PRIMARY_C_FLIP_DONE] = "Primary Plane C flip done",
133 [SPRITE_A_FLIP_DONE] = "Sprite Plane A flip done",
134 [SPRITE_B_FLIP_DONE] = "Sprite Plane B flip done",
135 [SPRITE_C_FLIP_DONE] = "Sprite Plane C flip done",
136
137 [PCU_THERMAL] = "PCU Thermal Event",
138 [PCU_PCODE2DRIVER_MAILBOX] = "PCU pcode2driver mailbox event",
139
140 [FDI_RX_INTERRUPTS_TRANSCODER_A] = "FDI RX Interrupts Combined A",
141 [AUDIO_CP_CHANGE_TRANSCODER_A] = "Audio CP Change Transcoder A",
142 [AUDIO_CP_REQUEST_TRANSCODER_A] = "Audio CP Request Transcoder A",
143 [FDI_RX_INTERRUPTS_TRANSCODER_B] = "FDI RX Interrupts Combined B",
144 [AUDIO_CP_CHANGE_TRANSCODER_B] = "Audio CP Change Transcoder B",
145 [AUDIO_CP_REQUEST_TRANSCODER_B] = "Audio CP Request Transcoder B",
146 [FDI_RX_INTERRUPTS_TRANSCODER_C] = "FDI RX Interrupts Combined C",
147 [AUDIO_CP_CHANGE_TRANSCODER_C] = "Audio CP Change Transcoder C",
148 [AUDIO_CP_REQUEST_TRANSCODER_C] = "Audio CP Request Transcoder C",
149 [ERR_AND_DBG] = "South Error and Debug Interrupts Combined",
150 [GMBUS] = "Gmbus",
151 [SDVO_B_HOTPLUG] = "SDVO B hotplug",
152 [CRT_HOTPLUG] = "CRT Hotplug",
153 [DP_B_HOTPLUG] = "DisplayPort/HDMI/DVI B Hotplug",
154 [DP_C_HOTPLUG] = "DisplayPort/HDMI/DVI C Hotplug",
155 [DP_D_HOTPLUG] = "DisplayPort/HDMI/DVI D Hotplug",
156 [AUX_CHANNEL_B] = "AUX Channel B",
157 [AUX_CHANNEL_C] = "AUX Channel C",
158 [AUX_CHANNEL_D] = "AUX Channel D",
159 [AUDIO_POWER_STATE_CHANGE_B] = "Audio Power State change Port B",
160 [AUDIO_POWER_STATE_CHANGE_C] = "Audio Power State change Port C",
161 [AUDIO_POWER_STATE_CHANGE_D] = "Audio Power State change Port D",
162
163 [INTEL_GVT_EVENT_RESERVED] = "RESERVED EVENTS!!!",
164};
165
166static inline struct intel_gvt_irq_info *regbase_to_irq_info(
167 struct intel_gvt *gvt,
168 unsigned int reg)
169{
170 struct intel_gvt_irq *irq = &gvt->irq;
171 int i;
172
173 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
174 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
175 return irq->info[i];
176 }
177
178 return NULL;
179}
180
181/**
182 * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
183 * @vgpu: a vGPU
184 * @reg: register offset written by guest
185 * @p_data: register data written by guest
186 * @bytes: register data length
187 *
188 * This function is used to emulate the generic IMR register bit change
189 * behavior.
190 *
191 * Returns:
192 * Zero on success, negative error code if failed.
193 *
194 */
195int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
196 unsigned int reg, void *p_data, unsigned int bytes)
197{
198 struct intel_gvt *gvt = vgpu->gvt;
199 const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
200 u32 imr = *(u32 *)p_data;
201
202 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
203 (vgpu_vreg(vgpu, reg) ^ imr));
204
205 vgpu_vreg(vgpu, reg) = imr;
206
207 ops->check_pending_irq(vgpu);
208
209 return 0;
210}
211
212/**
213 * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
214 * @vgpu: a vGPU
215 * @reg: register offset written by guest
216 * @p_data: register data written by guest
217 * @bytes: register data length
218 *
219 * This function is used to emulate the master IRQ register on gen8+.
220 *
221 * Returns:
222 * Zero on success, negative error code if failed.
223 *
224 */
225int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
226 unsigned int reg, void *p_data, unsigned int bytes)
227{
228 struct intel_gvt *gvt = vgpu->gvt;
229 const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
230 u32 ier = *(u32 *)p_data;
231 u32 virtual_ier = vgpu_vreg(vgpu, reg);
232
233 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
234 (virtual_ier ^ ier));
235
236 /*
237 * GEN8_MASTER_IRQ is a special irq register,
238 * only bit 31 is allowed to be modified
239 * and treated as an IER bit.
240 */
241 ier &= GEN8_MASTER_IRQ_CONTROL;
242 virtual_ier &= GEN8_MASTER_IRQ_CONTROL;
243 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
244 vgpu_vreg(vgpu, reg) |= ier;
245
246 ops->check_pending_irq(vgpu);
247
248 return 0;
249}
250
251/**
252 * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
253 * @vgpu: a vGPU
254 * @reg: register offset written by guest
255 * @p_data: register data written by guest
256 * @bytes: register data length
257 *
258 * This function is used to emulate the generic IER register behavior.
259 *
260 * Returns:
261 * Zero on success, negative error code if failed.
262 *
263 */
264int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
265 unsigned int reg, void *p_data, unsigned int bytes)
266{
267 struct intel_gvt *gvt = vgpu->gvt;
268 struct drm_i915_private *i915 = gvt->gt->i915;
269 const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
270 struct intel_gvt_irq_info *info;
271 u32 ier = *(u32 *)p_data;
272
273 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
274 (vgpu_vreg(vgpu, reg) ^ ier));
275
276 vgpu_vreg(vgpu, reg) = ier;
277
278 info = regbase_to_irq_info(gvt, ier_to_regbase(reg));
279 if (drm_WARN_ON(&i915->drm, !info))
280 return -EINVAL;
281
282 if (info->has_upstream_irq)
283 update_upstream_irq(vgpu, info);
284
285 ops->check_pending_irq(vgpu);
286
287 return 0;
288}
289
290/**
291 * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
292 * @vgpu: a vGPU
293 * @reg: register offset written by guest
294 * @p_data: register data written by guest
295 * @bytes: register data length
296 *
297 * This function is used to emulate the generic IIR register behavior.
298 *
299 * Returns:
300 * Zero on success, negative error code if failed.
301 *
302 */
303int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
304 void *p_data, unsigned int bytes)
305{
306 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
307 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
308 iir_to_regbase(reg));
309 u32 iir = *(u32 *)p_data;
310
311 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
312 (vgpu_vreg(vgpu, reg) ^ iir));
313
314 if (drm_WARN_ON(&i915->drm, !info))
315 return -EINVAL;
316
317 vgpu_vreg(vgpu, reg) &= ~iir;
318
319 if (info->has_upstream_irq)
320 update_upstream_irq(vgpu, info);
321 return 0;
322}
323
324static struct intel_gvt_irq_map gen8_irq_map[] = {
325 { INTEL_GVT_IRQ_INFO_MASTER, 0, INTEL_GVT_IRQ_INFO_GT0, 0xffff },
326 { INTEL_GVT_IRQ_INFO_MASTER, 1, INTEL_GVT_IRQ_INFO_GT0, 0xffff0000 },
327 { INTEL_GVT_IRQ_INFO_MASTER, 2, INTEL_GVT_IRQ_INFO_GT1, 0xffff },
328 { INTEL_GVT_IRQ_INFO_MASTER, 3, INTEL_GVT_IRQ_INFO_GT1, 0xffff0000 },
329 { INTEL_GVT_IRQ_INFO_MASTER, 4, INTEL_GVT_IRQ_INFO_GT2, 0xffff },
330 { INTEL_GVT_IRQ_INFO_MASTER, 6, INTEL_GVT_IRQ_INFO_GT3, 0xffff },
331 { INTEL_GVT_IRQ_INFO_MASTER, 16, INTEL_GVT_IRQ_INFO_DE_PIPE_A, ~0 },
332 { INTEL_GVT_IRQ_INFO_MASTER, 17, INTEL_GVT_IRQ_INFO_DE_PIPE_B, ~0 },
333 { INTEL_GVT_IRQ_INFO_MASTER, 18, INTEL_GVT_IRQ_INFO_DE_PIPE_C, ~0 },
334 { INTEL_GVT_IRQ_INFO_MASTER, 20, INTEL_GVT_IRQ_INFO_DE_PORT, ~0 },
335 { INTEL_GVT_IRQ_INFO_MASTER, 22, INTEL_GVT_IRQ_INFO_DE_MISC, ~0 },
336 { INTEL_GVT_IRQ_INFO_MASTER, 23, INTEL_GVT_IRQ_INFO_PCH, ~0 },
337 { INTEL_GVT_IRQ_INFO_MASTER, 30, INTEL_GVT_IRQ_INFO_PCU, ~0 },
338 { -1, -1, ~0 },
339};
340
341static void update_upstream_irq(struct intel_vgpu *vgpu,
342 struct intel_gvt_irq_info *info)
343{
344 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
345 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
346 struct intel_gvt_irq_map *map = irq->irq_map;
347 struct intel_gvt_irq_info *up_irq_info = NULL;
348 u32 set_bits = 0;
349 u32 clear_bits = 0;
350 int bit;
351 u32 val = vgpu_vreg(vgpu,
352 regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))
353 & vgpu_vreg(vgpu,
354 regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));
355
356 if (!info->has_upstream_irq)
357 return;
358
359 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
360 if (info->group != map->down_irq_group)
361 continue;
362
363 if (!up_irq_info)
364 up_irq_info = irq->info[map->up_irq_group];
365 else
366 drm_WARN_ON(&i915->drm, up_irq_info !=
367 irq->info[map->up_irq_group]);
368
369 bit = map->up_irq_bit;
370
371 if (val & map->down_irq_bitmask)
372 set_bits |= (1 << bit);
373 else
374 clear_bits |= (1 << bit);
375 }
376
377 if (drm_WARN_ON(&i915->drm, !up_irq_info))
378 return;
379
380 if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {
381 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);
382
383 vgpu_vreg(vgpu, isr) &= ~clear_bits;
384 vgpu_vreg(vgpu, isr) |= set_bits;
385 } else {
386 u32 iir = regbase_to_iir(
387 i915_mmio_reg_offset(up_irq_info->reg_base));
388 u32 imr = regbase_to_imr(
389 i915_mmio_reg_offset(up_irq_info->reg_base));
390
391 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
392 }
393
394 if (up_irq_info->has_upstream_irq)
395 update_upstream_irq(vgpu, up_irq_info);
396}
397
398static void init_irq_map(struct intel_gvt_irq *irq)
399{
400 struct intel_gvt_irq_map *map;
401 struct intel_gvt_irq_info *up_info, *down_info;
402 int up_bit;
403
404 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
405 up_info = irq->info[map->up_irq_group];
406 up_bit = map->up_irq_bit;
407 down_info = irq->info[map->down_irq_group];
408
409 set_bit(up_bit, up_info->downstream_irq_bitmap);
410 down_info->has_upstream_irq = true;
411
412 gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n",
413 up_info->group, up_bit,
414 down_info->group, map->down_irq_bitmask);
415 }
416}
417
418/* =======================vEvent injection===================== */
419
420#define MSI_CAP_CONTROL(offset) (offset + 2)
421#define MSI_CAP_ADDRESS(offset) (offset + 4)
422#define MSI_CAP_DATA(offset) (offset + 8)
423#define MSI_CAP_EN 0x1
424
425static void inject_virtual_interrupt(struct intel_vgpu *vgpu)
426{
427 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset;
428 u16 control, data;
429 u32 addr;
430
431 control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset));
432 addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));
433 data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset));
434
435 /* Do not generate MSI if MSIEN is disabled */
436 if (!(control & MSI_CAP_EN))
437 return;
438
439 if (WARN(control & GENMASK(15, 1), "only support one MSI format\n"))
440 return;
441
442 trace_inject_msi(vgpu->id, addr, data);
443
444 /*
445 * When guest is powered off, msi_trigger is set to NULL, but vgpu's
446 * config and mmio register isn't restored to default during guest
447 * poweroff. If this vgpu is still used in next vm, this vgpu's pipe
448 * may be enabled, then once this vgpu is active, it will get inject
449 * vblank interrupt request. But msi_trigger is null until msi is
450 * enabled by guest. so if msi_trigger is null, success is still
451 * returned and don't inject interrupt into guest.
452 */
453 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
454 return;
455 if (vgpu->msi_trigger)
456 eventfd_signal(vgpu->msi_trigger);
457}
458
459static void propagate_event(struct intel_gvt_irq *irq,
460 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
461{
462 struct intel_gvt_irq_info *info;
463 unsigned int reg_base;
464 int bit;
465
466 info = get_irq_info(irq, event);
467 if (WARN_ON(!info))
468 return;
469
470 reg_base = i915_mmio_reg_offset(info->reg_base);
471 bit = irq->events[event].bit;
472
473 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
474 regbase_to_imr(reg_base)))) {
475 trace_propagate_event(vgpu->id, irq_name[event], bit);
476 set_bit(bit, (void *)&vgpu_vreg(vgpu,
477 regbase_to_iir(reg_base)));
478 }
479}
480
481/* =======================vEvent Handlers===================== */
482static void handle_default_event_virt(struct intel_gvt_irq *irq,
483 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
484{
485 if (!vgpu->irq.irq_warn_once[event]) {
486 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
487 vgpu->id, event, irq_name[event]);
488 vgpu->irq.irq_warn_once[event] = true;
489 }
490 propagate_event(irq, event, vgpu);
491}
492
493/* =====================GEN specific logic======================= */
494/* GEN8 interrupt routines. */
495
496#define DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(regname, regbase) \
497static struct intel_gvt_irq_info gen8_##regname##_info = { \
498 .name = #regname"-IRQ", \
499 .reg_base = (regbase), \
500 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
501 INTEL_GVT_EVENT_RESERVED}, \
502}
503
504DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt0, GEN8_GT_ISR(0));
505DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt1, GEN8_GT_ISR(1));
506DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt2, GEN8_GT_ISR(2));
507DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(gt3, GEN8_GT_ISR(3));
508DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_a, GEN8_DE_PIPE_ISR(PIPE_A));
509DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
510DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
511DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_port, GEN8_DE_PORT_ISR);
512DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_misc, GEN8_DE_MISC_ISR);
513DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(pcu, GEN8_PCU_ISR);
514DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
515
516static struct intel_gvt_irq_info gvt_base_pch_info = {
517 .name = "PCH-IRQ",
518 .reg_base = SDEISR,
519 .bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
520 INTEL_GVT_EVENT_RESERVED},
521};
522
523static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
524{
525 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
526 int i;
527
528 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
529 GEN8_MASTER_IRQ_CONTROL))
530 return;
531
532 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
533 struct intel_gvt_irq_info *info = irq->info[i];
534 u32 reg_base;
535
536 if (!info->has_upstream_irq)
537 continue;
538
539 reg_base = i915_mmio_reg_offset(info->reg_base);
540 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
541 & vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
542 update_upstream_irq(vgpu, info);
543 }
544
545 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
546 & ~GEN8_MASTER_IRQ_CONTROL)
547 inject_virtual_interrupt(vgpu);
548}
549
550static void gen8_init_irq(
551 struct intel_gvt_irq *irq)
552{
553 struct intel_gvt *gvt = irq_to_gvt(irq);
554
555#define SET_BIT_INFO(s, b, e, i) \
556 do { \
557 s->events[e].bit = b; \
558 s->events[e].info = s->info[i]; \
559 s->info[i]->bit_to_event[b] = e;\
560 } while (0)
561
562#define SET_IRQ_GROUP(s, g, i) \
563 do { \
564 s->info[g] = i; \
565 (i)->group = g; \
566 set_bit(g, s->irq_info_bitmap); \
567 } while (0)
568
569 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);
570 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
571 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);
572 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);
573 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);
574 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
575 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
576 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);
577 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);
578 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);
579 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);
580 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);
581
582 /* GEN8 level 2 interrupts. */
583
584 /* GEN8 interrupt GT0 events */
585 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
586 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
587 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
588
589 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
590 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
591 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
592
593 /* GEN8 interrupt GT1 events */
594 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
595 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
596 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
597
598 if (HAS_ENGINE(gvt->gt, VCS1)) {
599 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
600 INTEL_GVT_IRQ_INFO_GT1);
601 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
602 INTEL_GVT_IRQ_INFO_GT1);
603 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
604 INTEL_GVT_IRQ_INFO_GT1);
605 }
606
607 /* GEN8 interrupt GT3 events */
608 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
609 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
610 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
611
612 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
613 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
614 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
615
616 /* GEN8 interrupt DE PORT events */
617 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
618 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
619
620 /* GEN8 interrupt DE MISC events */
621 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
622
623 /* PCH events */
624 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
625 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
626 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
627 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
628 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
629
630 if (IS_BROADWELL(gvt->gt->i915)) {
631 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
632 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
633 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
634
635 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
636 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
637
638 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
639 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
640
641 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
642 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
643 } else if (GRAPHICS_VER(gvt->gt->i915) >= 9) {
644 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
645 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
646 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
647
648 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
649 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
650 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
651
652 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
653 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
654 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
655 }
656
657 /* GEN8 interrupt PCU events */
658 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
659 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
660}
661
662static const struct intel_gvt_irq_ops gen8_irq_ops = {
663 .init_irq = gen8_init_irq,
664 .check_pending_irq = gen8_check_pending_irq,
665};
666
667/**
668 * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
669 * @vgpu: a vGPU
670 * @event: interrupt event
671 *
672 * This function is used to trigger a virtual interrupt event for vGPU.
673 * The caller provides the event to be triggered, the framework itself
674 * will emulate the IRQ register bit change.
675 *
676 */
677void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
678 enum intel_gvt_event_type event)
679{
680 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
681 struct intel_gvt *gvt = vgpu->gvt;
682 struct intel_gvt_irq *irq = &gvt->irq;
683 gvt_event_virt_handler_t handler;
684 const struct intel_gvt_irq_ops *ops = gvt->irq.ops;
685
686 handler = get_event_virt_handler(irq, event);
687 drm_WARN_ON(&i915->drm, !handler);
688
689 handler(irq, event, vgpu);
690
691 ops->check_pending_irq(vgpu);
692}
693
694static void init_events(
695 struct intel_gvt_irq *irq)
696{
697 int i;
698
699 for (i = 0; i < INTEL_GVT_EVENT_MAX; i++) {
700 irq->events[i].info = NULL;
701 irq->events[i].v_handler = handle_default_event_virt;
702 }
703}
704
705/**
706 * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
707 * @gvt: a GVT device
708 *
709 * This function is called at driver loading stage, to initialize the GVT-g IRQ
710 * emulation subsystem.
711 *
712 * Returns:
713 * Zero on success, negative error code if failed.
714 */
715int intel_gvt_init_irq(struct intel_gvt *gvt)
716{
717 struct intel_gvt_irq *irq = &gvt->irq;
718
719 gvt_dbg_core("init irq framework\n");
720
721 irq->ops = &gen8_irq_ops;
722 irq->irq_map = gen8_irq_map;
723
724 /* common event initialization */
725 init_events(irq);
726
727 /* gen specific initialization */
728 irq->ops->init_irq(irq);
729
730 init_irq_map(irq);
731
732 return 0;
733}