1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2023 Intel Corporation
  4 */
  5
  6#ifndef __INTEL_DISPLAY_DEVICE_H__
  7#define __INTEL_DISPLAY_DEVICE_H__
  8
  9#include <linux/types.h>
 10
 11#include "intel_display_limits.h"
 12
 13struct drm_i915_private;
 14struct drm_printer;
 15
 16#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
 17	/* Keep in alphabetical order */ \
 18	func(cursor_needs_physical); \
 19	func(has_cdclk_crawl); \
 20	func(has_cdclk_squash); \
 21	func(has_ddi); \
 22	func(has_dp_mst); \
 23	func(has_dsb); \
 24	func(has_fpga_dbg); \
 25	func(has_gmch); \
 26	func(has_hotplug); \
 27	func(has_hti); \
 28	func(has_ipc); \
 29	func(has_overlay); \
 30	func(has_psr); \
 31	func(has_psr_hw_tracking); \
 32	func(overlay_needs_physical); \
 33	func(supports_tv);
 34
 35#define HAS_4TILE(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
 36#define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)
 37#define HAS_CDCLK_CRAWL(i915)		(DISPLAY_INFO(i915)->has_cdclk_crawl)
 38#define HAS_CDCLK_SQUASH(i915)		(DISPLAY_INFO(i915)->has_cdclk_squash)
 39#define HAS_CUR_FBC(i915)		(!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13))
 40#define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))
 41#define HAS_DDI(i915)			(DISPLAY_INFO(i915)->has_ddi)
 42#define HAS_DISPLAY(i915)		(DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)
 43#define HAS_DMC(i915)			(DISPLAY_RUNTIME_INFO(i915)->has_dmc)
 44#define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))
 45#define HAS_DP_MST(i915)		(DISPLAY_INFO(i915)->has_dp_mst)
 46#define HAS_DP20(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
 47#define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)
 48#define HAS_DSB(i915)			(DISPLAY_INFO(i915)->has_dsb)
 49#define HAS_DSC(__i915)			(DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
 50#define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
 51#define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)->has_fpga_dbg)
 52#define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) >= 3)
 53#define HAS_GMBUS_IRQ(i915)		(DISPLAY_VER(i915) >= 4)
 54#define HAS_GMBUS_BURST_READ(i915)	(DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))
 55#define HAS_GMCH(i915)			(DISPLAY_INFO(i915)->has_gmch)
 56#define HAS_HW_SAGV_WM(i915)		(DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
 57#define HAS_IPC(i915)			(DISPLAY_INFO(i915)->has_ipc)
 58#define HAS_IPS(i915)			(IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))
 59#define HAS_LRR(i915)			(DISPLAY_VER(i915) >= 12)
 60#define HAS_LSPCON(i915)		(IS_DISPLAY_VER(i915, 9, 10))
 61#define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)
 62#define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)
 63#define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)
 64#define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)
 65#define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)
 66#define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)
 67#define HAS_SAGV(i915)			(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))
 68#define HAS_TRANSCODER(i915, trans)	((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \
 69					  BIT(trans)) != 0)
 70#define HAS_VRR(i915)			(DISPLAY_VER(i915) >= 11)
 71#define INTEL_NUM_PIPES(i915)		(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))
 72#define I915_HAS_HOTPLUG(i915)		(DISPLAY_INFO(i915)->has_hotplug)
 73#define OVERLAY_NEEDS_PHYSICAL(i915)	(DISPLAY_INFO(i915)->overlay_needs_physical)
 74#define SUPPORTS_TV(i915)		(DISPLAY_INFO(i915)->supports_tv)
 75
 76/* Check that device has a display IP version within the specific range. */
 77#define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \
 78	BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
 79	(DISPLAY_VER_FULL(__i915) >= (from) && \
 80	 DISPLAY_VER_FULL(__i915) <= (until)))
 81
 82/*
 83 * Check if a device has a specific IP version as well as a stepping within the
 84 * specified range [from, until).  The lower bound is inclusive, the upper
 85 * bound is exclusive.  The most common use-case of this macro is for checking
 86 * bounds for workarounds, which usually have a stepping ("from") at which the
 87 * hardware issue is first present and another stepping ("until") at which a
 88 * hardware fix is present and the software workaround is no longer necessary.
 89 * E.g.,
 90 *
 91 *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2)
 92 *    IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER)
 93 *
 94 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
 95 * stepping bound for the specified IP version.
 96 */
 97#define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \
 98	(IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \
 99	 IS_DISPLAY_STEP((__i915), (from), (until)))
100
101#define DISPLAY_INFO(i915)		((i915)->display.info.__device_info)
102#define DISPLAY_RUNTIME_INFO(i915)	(&(i915)->display.info.__runtime_info)
103
104#define DISPLAY_VER(i915)	(DISPLAY_RUNTIME_INFO(i915)->ip.ver)
105#define DISPLAY_VER_FULL(i915)	IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \
106				       DISPLAY_RUNTIME_INFO(i915)->ip.rel)
107#define IS_DISPLAY_VER(i915, from, until) \
108	(DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
109
110struct intel_display_runtime_info {
111	struct {
112		u16 ver;
113		u16 rel;
114		u16 step;
115	} ip;
116
117	u8 pipe_mask;
118	u8 cpu_transcoder_mask;
119	u16 port_mask;
120
121	u8 num_sprites[I915_MAX_PIPES];
122	u8 num_scalers[I915_MAX_PIPES];
123
124	u8 fbc_mask;
125
126	bool has_hdcp;
127	bool has_dmc;
128	bool has_dsc;
129};
130
131struct intel_display_device_info {
132	/* Initial runtime info. */
133	const struct intel_display_runtime_info __runtime_defaults;
134
135	u8 abox_mask;
136
137	struct {
138		u16 size; /* in blocks */
139		u8 slice_mask;
140	} dbuf;
141
142#define DEFINE_FLAG(name) u8 name:1
143	DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
144#undef DEFINE_FLAG
145
146	/* Global register offset for the display engine */
147	u32 mmio_offset;
148
149	/* Register offsets for the various display pipes and transcoders */
150	u32 pipe_offsets[I915_MAX_TRANSCODERS];
151	u32 trans_offsets[I915_MAX_TRANSCODERS];
152	u32 cursor_offsets[I915_MAX_PIPES];
153
154	struct {
155		u32 degamma_lut_size;
156		u32 gamma_lut_size;
157		u32 degamma_lut_tests;
158		u32 gamma_lut_tests;
159	} color;
160};
161
162bool intel_display_device_enabled(struct drm_i915_private *i915);
163void intel_display_device_probe(struct drm_i915_private *i915);
164void intel_display_device_remove(struct drm_i915_private *i915);
165void intel_display_device_info_runtime_init(struct drm_i915_private *i915);
166
167void intel_display_device_info_print(const struct intel_display_device_info *info,
168				     const struct intel_display_runtime_info *runtime,
169				     struct drm_printer *p);
170
171#endif