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1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include <linux/component.h>
19#include <linux/hdmi.h>
20#include <linux/module.h>
21#include <linux/irq.h>
22#include <sound/asoundef.h>
23
24#include <drm/drmP.h>
25#include <drm/drm_atomic_helper.h>
26#include <drm/drm_crtc_helper.h>
27#include <drm/drm_edid.h>
28#include <drm/drm_of.h>
29#include <drm/i2c/tda998x.h>
30
31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
32
33struct tda998x_priv {
34 struct i2c_client *cec;
35 struct i2c_client *hdmi;
36 struct mutex mutex;
37 u16 rev;
38 u8 current_page;
39 int dpms;
40 bool is_hdmi_sink;
41 u8 vip_cntrl_0;
42 u8 vip_cntrl_1;
43 u8 vip_cntrl_2;
44 struct tda998x_encoder_params params;
45
46 wait_queue_head_t wq_edid;
47 volatile int wq_edid_wait;
48
49 struct work_struct detect_work;
50 struct timer_list edid_delay_timer;
51 wait_queue_head_t edid_delay_waitq;
52 bool edid_delay_active;
53
54 struct drm_encoder encoder;
55 struct drm_connector connector;
56};
57
58#define conn_to_tda998x_priv(x) \
59 container_of(x, struct tda998x_priv, connector)
60
61#define enc_to_tda998x_priv(x) \
62 container_of(x, struct tda998x_priv, encoder)
63
64/* The TDA9988 series of devices use a paged register scheme.. to simplify
65 * things we encode the page # in upper bits of the register #. To read/
66 * write a given register, we need to make sure CURPAGE register is set
67 * appropriately. Which implies reads/writes are not atomic. Fun!
68 */
69
70#define REG(page, addr) (((page) << 8) | (addr))
71#define REG2ADDR(reg) ((reg) & 0xff)
72#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
73
74#define REG_CURPAGE 0xff /* write */
75
76
77/* Page 00h: General Control */
78#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
79#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
80# define MAIN_CNTRL0_SR (1 << 0)
81# define MAIN_CNTRL0_DECS (1 << 1)
82# define MAIN_CNTRL0_DEHS (1 << 2)
83# define MAIN_CNTRL0_CECS (1 << 3)
84# define MAIN_CNTRL0_CEHS (1 << 4)
85# define MAIN_CNTRL0_SCALER (1 << 7)
86#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
87#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
88# define SOFTRESET_AUDIO (1 << 0)
89# define SOFTRESET_I2C_MASTER (1 << 1)
90#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
91#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
92#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
93# define I2C_MASTER_DIS_MM (1 << 0)
94# define I2C_MASTER_DIS_FILT (1 << 1)
95# define I2C_MASTER_APP_STRT_LAT (1 << 2)
96#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
97# define FEAT_POWERDOWN_SPDIF (1 << 3)
98#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
99#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
100#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
101# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
102#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
103#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
104#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
105#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
106#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
107#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
108# define VIP_CNTRL_0_MIRR_A (1 << 7)
109# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
110# define VIP_CNTRL_0_MIRR_B (1 << 3)
111# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
112#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
113# define VIP_CNTRL_1_MIRR_C (1 << 7)
114# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
115# define VIP_CNTRL_1_MIRR_D (1 << 3)
116# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
117#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
118# define VIP_CNTRL_2_MIRR_E (1 << 7)
119# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
120# define VIP_CNTRL_2_MIRR_F (1 << 3)
121# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
122#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
123# define VIP_CNTRL_3_X_TGL (1 << 0)
124# define VIP_CNTRL_3_H_TGL (1 << 1)
125# define VIP_CNTRL_3_V_TGL (1 << 2)
126# define VIP_CNTRL_3_EMB (1 << 3)
127# define VIP_CNTRL_3_SYNC_DE (1 << 4)
128# define VIP_CNTRL_3_SYNC_HS (1 << 5)
129# define VIP_CNTRL_3_DE_INT (1 << 6)
130# define VIP_CNTRL_3_EDGE (1 << 7)
131#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
132# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
133# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
134# define VIP_CNTRL_4_CCIR656 (1 << 4)
135# define VIP_CNTRL_4_656_ALT (1 << 5)
136# define VIP_CNTRL_4_TST_656 (1 << 6)
137# define VIP_CNTRL_4_TST_PAT (1 << 7)
138#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
139# define VIP_CNTRL_5_CKCASE (1 << 0)
140# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
141#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
142# define MUX_AP_SELECT_I2S 0x64
143# define MUX_AP_SELECT_SPDIF 0x40
144#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
145#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
146# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
147# define MAT_CONTRL_MAT_BP (1 << 2)
148#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
149#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
150#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
151#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
152#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
153#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
154#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
155#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
156#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
157#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
158#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
159#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
160#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
161#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
162#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
163#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
164#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
165#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
166#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
167#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
168#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
169#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
170#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
171#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
172#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
173#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
174#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
175#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
176#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
177#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
178#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
179#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
180#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
181#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
182#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
183#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
184#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
185#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
186#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
187#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
188#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
189#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
190# define TBG_CNTRL_0_TOP_TGL (1 << 0)
191# define TBG_CNTRL_0_TOP_SEL (1 << 1)
192# define TBG_CNTRL_0_DE_EXT (1 << 2)
193# define TBG_CNTRL_0_TOP_EXT (1 << 3)
194# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
195# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
196# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
197#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
198# define TBG_CNTRL_1_H_TGL (1 << 0)
199# define TBG_CNTRL_1_V_TGL (1 << 1)
200# define TBG_CNTRL_1_TGL_EN (1 << 2)
201# define TBG_CNTRL_1_X_EXT (1 << 3)
202# define TBG_CNTRL_1_H_EXT (1 << 4)
203# define TBG_CNTRL_1_V_EXT (1 << 5)
204# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
205#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
206#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
207# define HVF_CNTRL_0_SM (1 << 7)
208# define HVF_CNTRL_0_RWB (1 << 6)
209# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
210# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
211#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
212# define HVF_CNTRL_1_FOR (1 << 0)
213# define HVF_CNTRL_1_YUVBLK (1 << 1)
214# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
215# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
216# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
217#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
218#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
219# define I2S_FORMAT(x) (((x) & 3) << 0)
220#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
221# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
222# define AIP_CLKSEL_AIP_I2S (1 << 3)
223# define AIP_CLKSEL_FS_ACLK (0 << 0)
224# define AIP_CLKSEL_FS_MCLK (1 << 0)
225# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
226
227/* Page 02h: PLL settings */
228#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
229# define PLL_SERIAL_1_SRL_FDN (1 << 0)
230# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
231# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
232#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
233# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
234# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
235#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
236# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
237# define PLL_SERIAL_3_SRL_DE (1 << 2)
238# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
239#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
240#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
241#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
242#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
243#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
244#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
245#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
246#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
247#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
248# define AUDIO_DIV_SERCLK_1 0
249# define AUDIO_DIV_SERCLK_2 1
250# define AUDIO_DIV_SERCLK_4 2
251# define AUDIO_DIV_SERCLK_8 3
252# define AUDIO_DIV_SERCLK_16 4
253# define AUDIO_DIV_SERCLK_32 5
254#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
255# define SEL_CLK_SEL_CLK1 (1 << 0)
256# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
257# define SEL_CLK_ENA_SC_CLK (1 << 3)
258#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
259
260
261/* Page 09h: EDID Control */
262#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
263/* next 127 successive registers are the EDID block */
264#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
265#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
266#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
267#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
268#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
269
270
271/* Page 10h: information frames and packets */
272#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
273#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
274#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
275#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
276#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
277
278
279/* Page 11h: audio settings and content info packets */
280#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
281# define AIP_CNTRL_0_RST_FIFO (1 << 0)
282# define AIP_CNTRL_0_SWAP (1 << 1)
283# define AIP_CNTRL_0_LAYOUT (1 << 2)
284# define AIP_CNTRL_0_ACR_MAN (1 << 5)
285# define AIP_CNTRL_0_RST_CTS (1 << 6)
286#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
287# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
288# define CA_I2S_HBR_CHSTAT (1 << 6)
289#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
290#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
291#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
292#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
293#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
294#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
295#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
296#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
297# define CTS_N_K(x) (((x) & 7) << 0)
298# define CTS_N_M(x) (((x) & 3) << 4)
299#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
300# define ENC_CNTRL_RST_ENC (1 << 0)
301# define ENC_CNTRL_RST_SEL (1 << 1)
302# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
303#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
304# define DIP_FLAGS_ACR (1 << 0)
305# define DIP_FLAGS_GC (1 << 1)
306#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
307# define DIP_IF_FLAGS_IF1 (1 << 1)
308# define DIP_IF_FLAGS_IF2 (1 << 2)
309# define DIP_IF_FLAGS_IF3 (1 << 3)
310# define DIP_IF_FLAGS_IF4 (1 << 4)
311# define DIP_IF_FLAGS_IF5 (1 << 5)
312#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
313
314
315/* Page 12h: HDCP and OTP */
316#define REG_TX3 REG(0x12, 0x9a) /* read/write */
317#define REG_TX4 REG(0x12, 0x9b) /* read/write */
318# define TX4_PD_RAM (1 << 1)
319#define REG_TX33 REG(0x12, 0xb8) /* read/write */
320# define TX33_HDMI (1 << 1)
321
322
323/* Page 13h: Gamut related metadata packets */
324
325
326
327/* CEC registers: (not paged)
328 */
329#define REG_CEC_INTSTATUS 0xee /* read */
330# define CEC_INTSTATUS_CEC (1 << 0)
331# define CEC_INTSTATUS_HDMI (1 << 1)
332#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
333# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
334# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
335# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
336# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
337#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
338#define REG_CEC_RXSHPDINT 0xfd /* read */
339# define CEC_RXSHPDINT_RXSENS BIT(0)
340# define CEC_RXSHPDINT_HPD BIT(1)
341#define REG_CEC_RXSHPDLEV 0xfe /* read */
342# define CEC_RXSHPDLEV_RXSENS (1 << 0)
343# define CEC_RXSHPDLEV_HPD (1 << 1)
344
345#define REG_CEC_ENAMODS 0xff /* read/write */
346# define CEC_ENAMODS_DIS_FRO (1 << 6)
347# define CEC_ENAMODS_DIS_CCLK (1 << 5)
348# define CEC_ENAMODS_EN_RXSENS (1 << 2)
349# define CEC_ENAMODS_EN_HDMI (1 << 1)
350# define CEC_ENAMODS_EN_CEC (1 << 0)
351
352
353/* Device versions: */
354#define TDA9989N2 0x0101
355#define TDA19989 0x0201
356#define TDA19989N2 0x0202
357#define TDA19988 0x0301
358
359static void
360cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
361{
362 struct i2c_client *client = priv->cec;
363 u8 buf[] = {addr, val};
364 int ret;
365
366 ret = i2c_master_send(client, buf, sizeof(buf));
367 if (ret < 0)
368 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
369}
370
371static u8
372cec_read(struct tda998x_priv *priv, u8 addr)
373{
374 struct i2c_client *client = priv->cec;
375 u8 val;
376 int ret;
377
378 ret = i2c_master_send(client, &addr, sizeof(addr));
379 if (ret < 0)
380 goto fail;
381
382 ret = i2c_master_recv(client, &val, sizeof(val));
383 if (ret < 0)
384 goto fail;
385
386 return val;
387
388fail:
389 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
390 return 0;
391}
392
393static int
394set_page(struct tda998x_priv *priv, u16 reg)
395{
396 if (REG2PAGE(reg) != priv->current_page) {
397 struct i2c_client *client = priv->hdmi;
398 u8 buf[] = {
399 REG_CURPAGE, REG2PAGE(reg)
400 };
401 int ret = i2c_master_send(client, buf, sizeof(buf));
402 if (ret < 0) {
403 dev_err(&client->dev, "%s %04x err %d\n", __func__,
404 reg, ret);
405 return ret;
406 }
407
408 priv->current_page = REG2PAGE(reg);
409 }
410 return 0;
411}
412
413static int
414reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
415{
416 struct i2c_client *client = priv->hdmi;
417 u8 addr = REG2ADDR(reg);
418 int ret;
419
420 mutex_lock(&priv->mutex);
421 ret = set_page(priv, reg);
422 if (ret < 0)
423 goto out;
424
425 ret = i2c_master_send(client, &addr, sizeof(addr));
426 if (ret < 0)
427 goto fail;
428
429 ret = i2c_master_recv(client, buf, cnt);
430 if (ret < 0)
431 goto fail;
432
433 goto out;
434
435fail:
436 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
437out:
438 mutex_unlock(&priv->mutex);
439 return ret;
440}
441
442static void
443reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
444{
445 struct i2c_client *client = priv->hdmi;
446 u8 buf[cnt+1];
447 int ret;
448
449 buf[0] = REG2ADDR(reg);
450 memcpy(&buf[1], p, cnt);
451
452 mutex_lock(&priv->mutex);
453 ret = set_page(priv, reg);
454 if (ret < 0)
455 goto out;
456
457 ret = i2c_master_send(client, buf, cnt + 1);
458 if (ret < 0)
459 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
460out:
461 mutex_unlock(&priv->mutex);
462}
463
464static int
465reg_read(struct tda998x_priv *priv, u16 reg)
466{
467 u8 val = 0;
468 int ret;
469
470 ret = reg_read_range(priv, reg, &val, sizeof(val));
471 if (ret < 0)
472 return ret;
473 return val;
474}
475
476static void
477reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
478{
479 struct i2c_client *client = priv->hdmi;
480 u8 buf[] = {REG2ADDR(reg), val};
481 int ret;
482
483 mutex_lock(&priv->mutex);
484 ret = set_page(priv, reg);
485 if (ret < 0)
486 goto out;
487
488 ret = i2c_master_send(client, buf, sizeof(buf));
489 if (ret < 0)
490 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
491out:
492 mutex_unlock(&priv->mutex);
493}
494
495static void
496reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
497{
498 struct i2c_client *client = priv->hdmi;
499 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
500 int ret;
501
502 mutex_lock(&priv->mutex);
503 ret = set_page(priv, reg);
504 if (ret < 0)
505 goto out;
506
507 ret = i2c_master_send(client, buf, sizeof(buf));
508 if (ret < 0)
509 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
510out:
511 mutex_unlock(&priv->mutex);
512}
513
514static void
515reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
516{
517 int old_val;
518
519 old_val = reg_read(priv, reg);
520 if (old_val >= 0)
521 reg_write(priv, reg, old_val | val);
522}
523
524static void
525reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
526{
527 int old_val;
528
529 old_val = reg_read(priv, reg);
530 if (old_val >= 0)
531 reg_write(priv, reg, old_val & ~val);
532}
533
534static void
535tda998x_reset(struct tda998x_priv *priv)
536{
537 /* reset audio and i2c master: */
538 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
539 msleep(50);
540 reg_write(priv, REG_SOFTRESET, 0);
541 msleep(50);
542
543 /* reset transmitter: */
544 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
545 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
546
547 /* PLL registers common configuration */
548 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
549 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
550 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
551 reg_write(priv, REG_SERIALIZER, 0x00);
552 reg_write(priv, REG_BUFFER_OUT, 0x00);
553 reg_write(priv, REG_PLL_SCG1, 0x00);
554 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
555 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
556 reg_write(priv, REG_PLL_SCGN1, 0xfa);
557 reg_write(priv, REG_PLL_SCGN2, 0x00);
558 reg_write(priv, REG_PLL_SCGR1, 0x5b);
559 reg_write(priv, REG_PLL_SCGR2, 0x00);
560 reg_write(priv, REG_PLL_SCG2, 0x10);
561
562 /* Write the default value MUX register */
563 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
564}
565
566/*
567 * The TDA998x has a problem when trying to read the EDID close to a
568 * HPD assertion: it needs a delay of 100ms to avoid timing out while
569 * trying to read EDID data.
570 *
571 * However, tda998x_encoder_get_modes() may be called at any moment
572 * after tda998x_connector_detect() indicates that we are connected, so
573 * we need to delay probing modes in tda998x_encoder_get_modes() after
574 * we have seen a HPD inactive->active transition. This code implements
575 * that delay.
576 */
577static void tda998x_edid_delay_done(unsigned long data)
578{
579 struct tda998x_priv *priv = (struct tda998x_priv *)data;
580
581 priv->edid_delay_active = false;
582 wake_up(&priv->edid_delay_waitq);
583 schedule_work(&priv->detect_work);
584}
585
586static void tda998x_edid_delay_start(struct tda998x_priv *priv)
587{
588 priv->edid_delay_active = true;
589 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
590}
591
592static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
593{
594 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
595}
596
597/*
598 * We need to run the KMS hotplug event helper outside of our threaded
599 * interrupt routine as this can call back into our get_modes method,
600 * which will want to make use of interrupts.
601 */
602static void tda998x_detect_work(struct work_struct *work)
603{
604 struct tda998x_priv *priv =
605 container_of(work, struct tda998x_priv, detect_work);
606 struct drm_device *dev = priv->encoder.dev;
607
608 if (dev)
609 drm_kms_helper_hotplug_event(dev);
610}
611
612/*
613 * only 2 interrupts may occur: screen plug/unplug and EDID read
614 */
615static irqreturn_t tda998x_irq_thread(int irq, void *data)
616{
617 struct tda998x_priv *priv = data;
618 u8 sta, cec, lvl, flag0, flag1, flag2;
619 bool handled = false;
620
621 sta = cec_read(priv, REG_CEC_INTSTATUS);
622 cec = cec_read(priv, REG_CEC_RXSHPDINT);
623 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
624 flag0 = reg_read(priv, REG_INT_FLAGS_0);
625 flag1 = reg_read(priv, REG_INT_FLAGS_1);
626 flag2 = reg_read(priv, REG_INT_FLAGS_2);
627 DRM_DEBUG_DRIVER(
628 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
629 sta, cec, lvl, flag0, flag1, flag2);
630
631 if (cec & CEC_RXSHPDINT_HPD) {
632 if (lvl & CEC_RXSHPDLEV_HPD)
633 tda998x_edid_delay_start(priv);
634 else
635 schedule_work(&priv->detect_work);
636
637 handled = true;
638 }
639
640 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
641 priv->wq_edid_wait = 0;
642 wake_up(&priv->wq_edid);
643 handled = true;
644 }
645
646 return IRQ_RETVAL(handled);
647}
648
649static void
650tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
651 union hdmi_infoframe *frame)
652{
653 u8 buf[32];
654 ssize_t len;
655
656 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
657 if (len < 0) {
658 dev_err(&priv->hdmi->dev,
659 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
660 frame->any.type, len);
661 return;
662 }
663
664 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
665 reg_write_range(priv, addr, buf, len);
666 reg_set(priv, REG_DIP_IF_FLAGS, bit);
667}
668
669static void
670tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
671{
672 union hdmi_infoframe frame;
673
674 hdmi_audio_infoframe_init(&frame.audio);
675
676 frame.audio.channels = p->audio_frame[1] & 0x07;
677 frame.audio.channel_allocation = p->audio_frame[4];
678 frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3;
679 frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7;
680
681 /*
682 * L-PCM and IEC61937 compressed audio shall always set sample
683 * frequency to "refer to stream". For others, see the HDMI
684 * specification.
685 */
686 frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2;
687
688 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
689}
690
691static void
692tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
693{
694 union hdmi_infoframe frame;
695
696 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
697 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
698
699 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
700}
701
702static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
703{
704 if (on) {
705 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
706 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
707 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
708 } else {
709 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
710 }
711}
712
713static void
714tda998x_configure_audio(struct tda998x_priv *priv,
715 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
716{
717 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
718 u32 n;
719
720 /* Enable audio ports */
721 reg_write(priv, REG_ENA_AP, p->audio_cfg);
722 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
723
724 /* Set audio input source */
725 switch (p->audio_format) {
726 case AFMT_SPDIF:
727 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
728 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
729 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
730 cts_n = CTS_N_M(3) | CTS_N_K(3);
731 break;
732
733 case AFMT_I2S:
734 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
735 clksel_aip = AIP_CLKSEL_AIP_I2S;
736 clksel_fs = AIP_CLKSEL_FS_ACLK;
737 cts_n = CTS_N_M(3) | CTS_N_K(3);
738 break;
739
740 default:
741 BUG();
742 return;
743 }
744
745 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
746 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
747 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
748 reg_write(priv, REG_CTS_N, cts_n);
749
750 /*
751 * Audio input somehow depends on HDMI line rate which is
752 * related to pixclk. Testing showed that modes with pixclk
753 * >100MHz need a larger divider while <40MHz need the default.
754 * There is no detailed info in the datasheet, so we just
755 * assume 100MHz requires larger divider.
756 */
757 adiv = AUDIO_DIV_SERCLK_8;
758 if (mode->clock > 100000)
759 adiv++; /* AUDIO_DIV_SERCLK_16 */
760
761 /* S/PDIF asks for a larger divider */
762 if (p->audio_format == AFMT_SPDIF)
763 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
764
765 reg_write(priv, REG_AUDIO_DIV, adiv);
766
767 /*
768 * This is the approximate value of N, which happens to be
769 * the recommended values for non-coherent clocks.
770 */
771 n = 128 * p->audio_sample_rate / 1000;
772
773 /* Write the CTS and N values */
774 buf[0] = 0x44;
775 buf[1] = 0x42;
776 buf[2] = 0x01;
777 buf[3] = n;
778 buf[4] = n >> 8;
779 buf[5] = n >> 16;
780 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
781
782 /* Set CTS clock reference */
783 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
784
785 /* Reset CTS generator */
786 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
787 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
788
789 /* Write the channel status */
790 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
791 buf[1] = 0x00;
792 buf[2] = IEC958_AES3_CON_FS_NOTID;
793 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
794 IEC958_AES4_CON_MAX_WORDLEN_24;
795 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
796
797 tda998x_audio_mute(priv, true);
798 msleep(20);
799 tda998x_audio_mute(priv, false);
800
801 /* Write the audio information packet */
802 tda998x_write_aif(priv, p);
803}
804
805/* DRM encoder functions */
806
807static void tda998x_encoder_set_config(struct tda998x_priv *priv,
808 const struct tda998x_encoder_params *p)
809{
810 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
811 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
812 VIP_CNTRL_0_SWAP_B(p->swap_b) |
813 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
814 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
815 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
816 VIP_CNTRL_1_SWAP_D(p->swap_d) |
817 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
818 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
819 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
820 VIP_CNTRL_2_SWAP_F(p->swap_f) |
821 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
822
823 priv->params = *p;
824}
825
826static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
827{
828 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
829
830 /* we only care about on or off: */
831 if (mode != DRM_MODE_DPMS_ON)
832 mode = DRM_MODE_DPMS_OFF;
833
834 if (mode == priv->dpms)
835 return;
836
837 switch (mode) {
838 case DRM_MODE_DPMS_ON:
839 /* enable video ports, audio will be enabled later */
840 reg_write(priv, REG_ENA_VP_0, 0xff);
841 reg_write(priv, REG_ENA_VP_1, 0xff);
842 reg_write(priv, REG_ENA_VP_2, 0xff);
843 /* set muxing after enabling ports: */
844 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
845 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
846 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
847 break;
848 case DRM_MODE_DPMS_OFF:
849 /* disable video ports */
850 reg_write(priv, REG_ENA_VP_0, 0x00);
851 reg_write(priv, REG_ENA_VP_1, 0x00);
852 reg_write(priv, REG_ENA_VP_2, 0x00);
853 break;
854 }
855
856 priv->dpms = mode;
857}
858
859static int tda998x_connector_mode_valid(struct drm_connector *connector,
860 struct drm_display_mode *mode)
861{
862 /* TDA19988 dotclock can go up to 165MHz */
863 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
864
865 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
866 return MODE_CLOCK_HIGH;
867 if (mode->htotal >= BIT(13))
868 return MODE_BAD_HVALUE;
869 if (mode->vtotal >= BIT(11))
870 return MODE_BAD_VVALUE;
871 return MODE_OK;
872}
873
874static void
875tda998x_encoder_mode_set(struct drm_encoder *encoder,
876 struct drm_display_mode *mode,
877 struct drm_display_mode *adjusted_mode)
878{
879 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
880 u16 ref_pix, ref_line, n_pix, n_line;
881 u16 hs_pix_s, hs_pix_e;
882 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
883 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
884 u16 vwin1_line_s, vwin1_line_e;
885 u16 vwin2_line_s, vwin2_line_e;
886 u16 de_pix_s, de_pix_e;
887 u8 reg, div, rep;
888
889 /*
890 * Internally TDA998x is using ITU-R BT.656 style sync but
891 * we get VESA style sync. TDA998x is using a reference pixel
892 * relative to ITU to sync to the input frame and for output
893 * sync generation. Currently, we are using reference detection
894 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
895 * which is position of rising VS with coincident rising HS.
896 *
897 * Now there is some issues to take care of:
898 * - HDMI data islands require sync-before-active
899 * - TDA998x register values must be > 0 to be enabled
900 * - REFLINE needs an additional offset of +1
901 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
902 *
903 * So we add +1 to all horizontal and vertical register values,
904 * plus an additional +3 for REFPIX as we are using RGB input only.
905 */
906 n_pix = mode->htotal;
907 n_line = mode->vtotal;
908
909 hs_pix_e = mode->hsync_end - mode->hdisplay;
910 hs_pix_s = mode->hsync_start - mode->hdisplay;
911 de_pix_e = mode->htotal;
912 de_pix_s = mode->htotal - mode->hdisplay;
913 ref_pix = 3 + hs_pix_s;
914
915 /*
916 * Attached LCD controllers may generate broken sync. Allow
917 * those to adjust the position of the rising VS edge by adding
918 * HSKEW to ref_pix.
919 */
920 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
921 ref_pix += adjusted_mode->hskew;
922
923 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
924 ref_line = 1 + mode->vsync_start - mode->vdisplay;
925 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
926 vwin1_line_e = vwin1_line_s + mode->vdisplay;
927 vs1_pix_s = vs1_pix_e = hs_pix_s;
928 vs1_line_s = mode->vsync_start - mode->vdisplay;
929 vs1_line_e = vs1_line_s +
930 mode->vsync_end - mode->vsync_start;
931 vwin2_line_s = vwin2_line_e = 0;
932 vs2_pix_s = vs2_pix_e = 0;
933 vs2_line_s = vs2_line_e = 0;
934 } else {
935 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
936 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
937 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
938 vs1_pix_s = vs1_pix_e = hs_pix_s;
939 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
940 vs1_line_e = vs1_line_s +
941 (mode->vsync_end - mode->vsync_start)/2;
942 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
943 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
944 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
945 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
946 vs2_line_e = vs2_line_s +
947 (mode->vsync_end - mode->vsync_start)/2;
948 }
949
950 div = 148500 / mode->clock;
951 if (div != 0) {
952 div--;
953 if (div > 3)
954 div = 3;
955 }
956
957 /* mute the audio FIFO: */
958 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
959
960 /* set HDMI HDCP mode off: */
961 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
962 reg_clear(priv, REG_TX33, TX33_HDMI);
963 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
964
965 /* no pre-filter or interpolator: */
966 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
967 HVF_CNTRL_0_INTPOL(0));
968 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
969 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
970 VIP_CNTRL_4_BLC(0));
971
972 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
973 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
974 PLL_SERIAL_3_SRL_DE);
975 reg_write(priv, REG_SERIALIZER, 0);
976 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
977
978 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
979 rep = 0;
980 reg_write(priv, REG_RPT_CNTRL, 0);
981 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
982 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
983
984 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
985 PLL_SERIAL_2_SRL_PR(rep));
986
987 /* set color matrix bypass flag: */
988 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
989 MAT_CONTRL_MAT_SC(1));
990
991 /* set BIAS tmds value: */
992 reg_write(priv, REG_ANA_GENERAL, 0x09);
993
994 /*
995 * Sync on rising HSYNC/VSYNC
996 */
997 reg = VIP_CNTRL_3_SYNC_HS;
998
999 /*
1000 * TDA19988 requires high-active sync at input stage,
1001 * so invert low-active sync provided by master encoder here
1002 */
1003 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1004 reg |= VIP_CNTRL_3_H_TGL;
1005 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1006 reg |= VIP_CNTRL_3_V_TGL;
1007 reg_write(priv, REG_VIP_CNTRL_3, reg);
1008
1009 reg_write(priv, REG_VIDFORMAT, 0x00);
1010 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1011 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1012 reg_write16(priv, REG_NPIX_MSB, n_pix);
1013 reg_write16(priv, REG_NLINE_MSB, n_line);
1014 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1015 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1016 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1017 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1018 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1019 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1020 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1021 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1022 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1023 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1024 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1025 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1026 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1027 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1028 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1029 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1030
1031 if (priv->rev == TDA19988) {
1032 /* let incoming pixels fill the active space (if any) */
1033 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1034 }
1035
1036 /*
1037 * Always generate sync polarity relative to input sync and
1038 * revert input stage toggled sync at output stage
1039 */
1040 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1041 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1042 reg |= TBG_CNTRL_1_H_TGL;
1043 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1044 reg |= TBG_CNTRL_1_V_TGL;
1045 reg_write(priv, REG_TBG_CNTRL_1, reg);
1046
1047 /* must be last register set: */
1048 reg_write(priv, REG_TBG_CNTRL_0, 0);
1049
1050 /* Only setup the info frames if the sink is HDMI */
1051 if (priv->is_hdmi_sink) {
1052 /* We need to turn HDMI HDCP stuff on to get audio through */
1053 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1054 reg_write(priv, REG_TBG_CNTRL_1, reg);
1055 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1056 reg_set(priv, REG_TX33, TX33_HDMI);
1057
1058 tda998x_write_avi(priv, adjusted_mode);
1059
1060 if (priv->params.audio_cfg)
1061 tda998x_configure_audio(priv, adjusted_mode,
1062 &priv->params);
1063 }
1064}
1065
1066static enum drm_connector_status
1067tda998x_connector_detect(struct drm_connector *connector, bool force)
1068{
1069 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1070 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1071
1072 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1073 connector_status_disconnected;
1074}
1075
1076static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1077{
1078 struct tda998x_priv *priv = data;
1079 u8 offset, segptr;
1080 int ret, i;
1081
1082 offset = (blk & 1) ? 128 : 0;
1083 segptr = blk / 2;
1084
1085 reg_write(priv, REG_DDC_ADDR, 0xa0);
1086 reg_write(priv, REG_DDC_OFFS, offset);
1087 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1088 reg_write(priv, REG_DDC_SEGM, segptr);
1089
1090 /* enable reading EDID: */
1091 priv->wq_edid_wait = 1;
1092 reg_write(priv, REG_EDID_CTRL, 0x1);
1093
1094 /* flag must be cleared by sw: */
1095 reg_write(priv, REG_EDID_CTRL, 0x0);
1096
1097 /* wait for block read to complete: */
1098 if (priv->hdmi->irq) {
1099 i = wait_event_timeout(priv->wq_edid,
1100 !priv->wq_edid_wait,
1101 msecs_to_jiffies(100));
1102 if (i < 0) {
1103 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1104 return i;
1105 }
1106 } else {
1107 for (i = 100; i > 0; i--) {
1108 msleep(1);
1109 ret = reg_read(priv, REG_INT_FLAGS_2);
1110 if (ret < 0)
1111 return ret;
1112 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1113 break;
1114 }
1115 }
1116
1117 if (i == 0) {
1118 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1119 return -ETIMEDOUT;
1120 }
1121
1122 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1123 if (ret != length) {
1124 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1125 blk, ret);
1126 return ret;
1127 }
1128
1129 return 0;
1130}
1131
1132static int tda998x_connector_get_modes(struct drm_connector *connector)
1133{
1134 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1135 struct edid *edid;
1136 int n;
1137
1138 /*
1139 * If we get killed while waiting for the HPD timeout, return
1140 * no modes found: we are not in a restartable path, so we
1141 * can't handle signals gracefully.
1142 */
1143 if (tda998x_edid_delay_wait(priv))
1144 return 0;
1145
1146 if (priv->rev == TDA19988)
1147 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1148
1149 edid = drm_do_get_edid(connector, read_edid_block, priv);
1150
1151 if (priv->rev == TDA19988)
1152 reg_set(priv, REG_TX4, TX4_PD_RAM);
1153
1154 if (!edid) {
1155 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1156 return 0;
1157 }
1158
1159 drm_mode_connector_update_edid_property(connector, edid);
1160 n = drm_add_edid_modes(connector, edid);
1161 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1162 kfree(edid);
1163
1164 return n;
1165}
1166
1167static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1168 struct drm_connector *connector)
1169{
1170 if (priv->hdmi->irq)
1171 connector->polled = DRM_CONNECTOR_POLL_HPD;
1172 else
1173 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1174 DRM_CONNECTOR_POLL_DISCONNECT;
1175}
1176
1177static void tda998x_destroy(struct tda998x_priv *priv)
1178{
1179 /* disable all IRQs and free the IRQ handler */
1180 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1181 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1182
1183 if (priv->hdmi->irq)
1184 free_irq(priv->hdmi->irq, priv);
1185
1186 del_timer_sync(&priv->edid_delay_timer);
1187 cancel_work_sync(&priv->detect_work);
1188
1189 i2c_unregister_device(priv->cec);
1190}
1191
1192/* I2C driver functions */
1193
1194static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
1195{
1196 struct device_node *np = client->dev.of_node;
1197 u32 video;
1198 int rev_lo, rev_hi, ret;
1199 unsigned short cec_addr;
1200
1201 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1202 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1203 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1204
1205 priv->current_page = 0xff;
1206 priv->hdmi = client;
1207 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1208 cec_addr = 0x34 + (client->addr & 0x03);
1209 priv->cec = i2c_new_dummy(client->adapter, cec_addr);
1210 if (!priv->cec)
1211 return -ENODEV;
1212
1213 priv->dpms = DRM_MODE_DPMS_OFF;
1214
1215 mutex_init(&priv->mutex); /* protect the page access */
1216 init_waitqueue_head(&priv->edid_delay_waitq);
1217 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1218 (unsigned long)priv);
1219 INIT_WORK(&priv->detect_work, tda998x_detect_work);
1220
1221 /* wake up the device: */
1222 cec_write(priv, REG_CEC_ENAMODS,
1223 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1224
1225 tda998x_reset(priv);
1226
1227 /* read version: */
1228 rev_lo = reg_read(priv, REG_VERSION_LSB);
1229 rev_hi = reg_read(priv, REG_VERSION_MSB);
1230 if (rev_lo < 0 || rev_hi < 0) {
1231 ret = rev_lo < 0 ? rev_lo : rev_hi;
1232 goto fail;
1233 }
1234
1235 priv->rev = rev_lo | rev_hi << 8;
1236
1237 /* mask off feature bits: */
1238 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1239
1240 switch (priv->rev) {
1241 case TDA9989N2:
1242 dev_info(&client->dev, "found TDA9989 n2");
1243 break;
1244 case TDA19989:
1245 dev_info(&client->dev, "found TDA19989");
1246 break;
1247 case TDA19989N2:
1248 dev_info(&client->dev, "found TDA19989 n2");
1249 break;
1250 case TDA19988:
1251 dev_info(&client->dev, "found TDA19988");
1252 break;
1253 default:
1254 dev_err(&client->dev, "found unsupported device: %04x\n",
1255 priv->rev);
1256 goto fail;
1257 }
1258
1259 /* after reset, enable DDC: */
1260 reg_write(priv, REG_DDC_DISABLE, 0x00);
1261
1262 /* set clock on DDC channel: */
1263 reg_write(priv, REG_TX3, 39);
1264
1265 /* if necessary, disable multi-master: */
1266 if (priv->rev == TDA19989)
1267 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1268
1269 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1270 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1271
1272 /* initialize the optional IRQ */
1273 if (client->irq) {
1274 int irqf_trigger;
1275
1276 /* init read EDID waitqueue and HDP work */
1277 init_waitqueue_head(&priv->wq_edid);
1278
1279 /* clear pending interrupts */
1280 reg_read(priv, REG_INT_FLAGS_0);
1281 reg_read(priv, REG_INT_FLAGS_1);
1282 reg_read(priv, REG_INT_FLAGS_2);
1283
1284 irqf_trigger =
1285 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1286 ret = request_threaded_irq(client->irq, NULL,
1287 tda998x_irq_thread,
1288 irqf_trigger | IRQF_ONESHOT,
1289 "tda998x", priv);
1290 if (ret) {
1291 dev_err(&client->dev,
1292 "failed to request IRQ#%u: %d\n",
1293 client->irq, ret);
1294 goto fail;
1295 }
1296
1297 /* enable HPD irq */
1298 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1299 }
1300
1301 /* enable EDID read irq: */
1302 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1303
1304 if (!np)
1305 return 0; /* non-DT */
1306
1307 /* get the optional video properties */
1308 ret = of_property_read_u32(np, "video-ports", &video);
1309 if (ret == 0) {
1310 priv->vip_cntrl_0 = video >> 16;
1311 priv->vip_cntrl_1 = video >> 8;
1312 priv->vip_cntrl_2 = video;
1313 }
1314
1315 return 0;
1316
1317fail:
1318 /* if encoder_init fails, the encoder slave is never registered,
1319 * so cleanup here:
1320 */
1321 if (priv->cec)
1322 i2c_unregister_device(priv->cec);
1323 return -ENXIO;
1324}
1325
1326static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1327{
1328 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1329}
1330
1331static void tda998x_encoder_commit(struct drm_encoder *encoder)
1332{
1333 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1334}
1335
1336static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
1337 .dpms = tda998x_encoder_dpms,
1338 .prepare = tda998x_encoder_prepare,
1339 .commit = tda998x_encoder_commit,
1340 .mode_set = tda998x_encoder_mode_set,
1341};
1342
1343static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1344{
1345 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
1346
1347 tda998x_destroy(priv);
1348 drm_encoder_cleanup(encoder);
1349}
1350
1351static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1352 .destroy = tda998x_encoder_destroy,
1353};
1354
1355static struct drm_encoder *
1356tda998x_connector_best_encoder(struct drm_connector *connector)
1357{
1358 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1359
1360 return &priv->encoder;
1361}
1362
1363static
1364const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1365 .get_modes = tda998x_connector_get_modes,
1366 .mode_valid = tda998x_connector_mode_valid,
1367 .best_encoder = tda998x_connector_best_encoder,
1368};
1369
1370static void tda998x_connector_destroy(struct drm_connector *connector)
1371{
1372 drm_connector_unregister(connector);
1373 drm_connector_cleanup(connector);
1374}
1375
1376static int tda998x_connector_dpms(struct drm_connector *connector, int mode)
1377{
1378 if (drm_core_check_feature(connector->dev, DRIVER_ATOMIC))
1379 return drm_atomic_helper_connector_dpms(connector, mode);
1380 else
1381 return drm_helper_connector_dpms(connector, mode);
1382}
1383
1384static const struct drm_connector_funcs tda998x_connector_funcs = {
1385 .dpms = tda998x_connector_dpms,
1386 .reset = drm_atomic_helper_connector_reset,
1387 .fill_modes = drm_helper_probe_single_connector_modes,
1388 .detect = tda998x_connector_detect,
1389 .destroy = tda998x_connector_destroy,
1390 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1391 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1392};
1393
1394static int tda998x_bind(struct device *dev, struct device *master, void *data)
1395{
1396 struct tda998x_encoder_params *params = dev->platform_data;
1397 struct i2c_client *client = to_i2c_client(dev);
1398 struct drm_device *drm = data;
1399 struct tda998x_priv *priv;
1400 u32 crtcs = 0;
1401 int ret;
1402
1403 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1404 if (!priv)
1405 return -ENOMEM;
1406
1407 dev_set_drvdata(dev, priv);
1408
1409 if (dev->of_node)
1410 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1411
1412 /* If no CRTCs were found, fall back to our old behaviour */
1413 if (crtcs == 0) {
1414 dev_warn(dev, "Falling back to first CRTC\n");
1415 crtcs = 1 << 0;
1416 }
1417
1418 priv->connector.interlace_allowed = 1;
1419 priv->encoder.possible_crtcs = crtcs;
1420
1421 ret = tda998x_create(client, priv);
1422 if (ret)
1423 return ret;
1424
1425 if (!dev->of_node && params)
1426 tda998x_encoder_set_config(priv, params);
1427
1428 tda998x_encoder_set_polling(priv, &priv->connector);
1429
1430 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1431 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
1432 DRM_MODE_ENCODER_TMDS, NULL);
1433 if (ret)
1434 goto err_encoder;
1435
1436 drm_connector_helper_add(&priv->connector,
1437 &tda998x_connector_helper_funcs);
1438 ret = drm_connector_init(drm, &priv->connector,
1439 &tda998x_connector_funcs,
1440 DRM_MODE_CONNECTOR_HDMIA);
1441 if (ret)
1442 goto err_connector;
1443
1444 ret = drm_connector_register(&priv->connector);
1445 if (ret)
1446 goto err_sysfs;
1447
1448 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
1449
1450 return 0;
1451
1452err_sysfs:
1453 drm_connector_cleanup(&priv->connector);
1454err_connector:
1455 drm_encoder_cleanup(&priv->encoder);
1456err_encoder:
1457 tda998x_destroy(priv);
1458 return ret;
1459}
1460
1461static void tda998x_unbind(struct device *dev, struct device *master,
1462 void *data)
1463{
1464 struct tda998x_priv *priv = dev_get_drvdata(dev);
1465
1466 drm_connector_unregister(&priv->connector);
1467 drm_connector_cleanup(&priv->connector);
1468 drm_encoder_cleanup(&priv->encoder);
1469 tda998x_destroy(priv);
1470}
1471
1472static const struct component_ops tda998x_ops = {
1473 .bind = tda998x_bind,
1474 .unbind = tda998x_unbind,
1475};
1476
1477static int
1478tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1479{
1480 return component_add(&client->dev, &tda998x_ops);
1481}
1482
1483static int tda998x_remove(struct i2c_client *client)
1484{
1485 component_del(&client->dev, &tda998x_ops);
1486 return 0;
1487}
1488
1489#ifdef CONFIG_OF
1490static const struct of_device_id tda998x_dt_ids[] = {
1491 { .compatible = "nxp,tda998x", },
1492 { }
1493};
1494MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1495#endif
1496
1497static struct i2c_device_id tda998x_ids[] = {
1498 { "tda998x", 0 },
1499 { }
1500};
1501MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1502
1503static struct i2c_driver tda998x_driver = {
1504 .probe = tda998x_probe,
1505 .remove = tda998x_remove,
1506 .driver = {
1507 .name = "tda998x",
1508 .of_match_table = of_match_ptr(tda998x_dt_ids),
1509 },
1510 .id_table = tda998x_ids,
1511};
1512
1513module_i2c_driver(tda998x_driver);
1514
1515MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1516MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1517MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7#include <linux/component.h>
8#include <linux/gpio/consumer.h>
9#include <linux/hdmi.h>
10#include <linux/i2c.h>
11#include <linux/module.h>
12#include <linux/platform_data/tda9950.h>
13#include <linux/irq.h>
14#include <sound/asoundef.h>
15#include <sound/hdmi-codec.h>
16
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_bridge.h>
19#include <drm/drm_edid.h>
20#include <drm/drm_of.h>
21#include <drm/drm_print.h>
22#include <drm/drm_probe_helper.h>
23#include <drm/drm_simple_kms_helper.h>
24#include <drm/i2c/tda998x.h>
25
26#include <media/cec-notifier.h>
27
28#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
29
30enum {
31 AUDIO_ROUTE_I2S,
32 AUDIO_ROUTE_SPDIF,
33 AUDIO_ROUTE_NUM
34};
35
36struct tda998x_audio_route {
37 u8 ena_aclk;
38 u8 mux_ap;
39 u8 aip_clksel;
40};
41
42struct tda998x_audio_settings {
43 const struct tda998x_audio_route *route;
44 struct hdmi_audio_infoframe cea;
45 unsigned int sample_rate;
46 u8 status[5];
47 u8 ena_ap;
48 u8 i2s_format;
49 u8 cts_n;
50};
51
52struct tda998x_priv {
53 struct i2c_client *cec;
54 struct i2c_client *hdmi;
55 struct mutex mutex;
56 u16 rev;
57 u8 cec_addr;
58 u8 current_page;
59 bool is_on;
60 bool supports_infoframes;
61 bool sink_has_audio;
62 enum hdmi_quantization_range rgb_quant_range;
63 u8 vip_cntrl_0;
64 u8 vip_cntrl_1;
65 u8 vip_cntrl_2;
66 unsigned long tmds_clock;
67 struct tda998x_audio_settings audio;
68
69 struct platform_device *audio_pdev;
70 struct mutex audio_mutex;
71
72 struct mutex edid_mutex;
73 wait_queue_head_t wq_edid;
74 volatile int wq_edid_wait;
75
76 struct work_struct detect_work;
77 struct timer_list edid_delay_timer;
78 wait_queue_head_t edid_delay_waitq;
79 bool edid_delay_active;
80
81 struct drm_encoder encoder;
82 struct drm_bridge bridge;
83 struct drm_connector connector;
84
85 u8 audio_port_enable[AUDIO_ROUTE_NUM];
86 struct tda9950_glue cec_glue;
87 struct gpio_desc *calib;
88 struct cec_notifier *cec_notify;
89};
90
91#define conn_to_tda998x_priv(x) \
92 container_of(x, struct tda998x_priv, connector)
93#define enc_to_tda998x_priv(x) \
94 container_of(x, struct tda998x_priv, encoder)
95#define bridge_to_tda998x_priv(x) \
96 container_of(x, struct tda998x_priv, bridge)
97
98/* The TDA9988 series of devices use a paged register scheme.. to simplify
99 * things we encode the page # in upper bits of the register #. To read/
100 * write a given register, we need to make sure CURPAGE register is set
101 * appropriately. Which implies reads/writes are not atomic. Fun!
102 */
103
104#define REG(page, addr) (((page) << 8) | (addr))
105#define REG2ADDR(reg) ((reg) & 0xff)
106#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
107
108#define REG_CURPAGE 0xff /* write */
109
110
111/* Page 00h: General Control */
112#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
113#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
114# define MAIN_CNTRL0_SR (1 << 0)
115# define MAIN_CNTRL0_DECS (1 << 1)
116# define MAIN_CNTRL0_DEHS (1 << 2)
117# define MAIN_CNTRL0_CECS (1 << 3)
118# define MAIN_CNTRL0_CEHS (1 << 4)
119# define MAIN_CNTRL0_SCALER (1 << 7)
120#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
121#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
122# define SOFTRESET_AUDIO (1 << 0)
123# define SOFTRESET_I2C_MASTER (1 << 1)
124#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
125#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
126#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
127# define I2C_MASTER_DIS_MM (1 << 0)
128# define I2C_MASTER_DIS_FILT (1 << 1)
129# define I2C_MASTER_APP_STRT_LAT (1 << 2)
130#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
131# define FEAT_POWERDOWN_PREFILT BIT(0)
132# define FEAT_POWERDOWN_CSC BIT(1)
133# define FEAT_POWERDOWN_SPDIF (1 << 3)
134#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
135#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
136#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
137# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
138#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
139#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
140#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
141#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
142#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
143#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
144# define VIP_CNTRL_0_MIRR_A (1 << 7)
145# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
146# define VIP_CNTRL_0_MIRR_B (1 << 3)
147# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
148#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
149# define VIP_CNTRL_1_MIRR_C (1 << 7)
150# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
151# define VIP_CNTRL_1_MIRR_D (1 << 3)
152# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
153#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
154# define VIP_CNTRL_2_MIRR_E (1 << 7)
155# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
156# define VIP_CNTRL_2_MIRR_F (1 << 3)
157# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
158#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
159# define VIP_CNTRL_3_X_TGL (1 << 0)
160# define VIP_CNTRL_3_H_TGL (1 << 1)
161# define VIP_CNTRL_3_V_TGL (1 << 2)
162# define VIP_CNTRL_3_EMB (1 << 3)
163# define VIP_CNTRL_3_SYNC_DE (1 << 4)
164# define VIP_CNTRL_3_SYNC_HS (1 << 5)
165# define VIP_CNTRL_3_DE_INT (1 << 6)
166# define VIP_CNTRL_3_EDGE (1 << 7)
167#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
168# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
169# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
170# define VIP_CNTRL_4_CCIR656 (1 << 4)
171# define VIP_CNTRL_4_656_ALT (1 << 5)
172# define VIP_CNTRL_4_TST_656 (1 << 6)
173# define VIP_CNTRL_4_TST_PAT (1 << 7)
174#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
175# define VIP_CNTRL_5_CKCASE (1 << 0)
176# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
177#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
178# define MUX_AP_SELECT_I2S 0x64
179# define MUX_AP_SELECT_SPDIF 0x40
180#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
181#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
182# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
183# define MAT_CONTRL_MAT_BP (1 << 2)
184#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
185#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
186#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
187#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
188#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
189#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
190#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
191#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
192#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
193#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
194#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
195#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
196#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
197#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
198#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
199#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
200#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
201#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
202#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
203#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
204#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
205#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
206#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
207#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
208#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
209#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
210#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
211#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
212#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
213#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
214#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
215#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
216#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
217#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
218#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
219#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
220#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
221#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
222#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
223#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
224#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
225#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
226# define TBG_CNTRL_0_TOP_TGL (1 << 0)
227# define TBG_CNTRL_0_TOP_SEL (1 << 1)
228# define TBG_CNTRL_0_DE_EXT (1 << 2)
229# define TBG_CNTRL_0_TOP_EXT (1 << 3)
230# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
231# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
232# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
233#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
234# define TBG_CNTRL_1_H_TGL (1 << 0)
235# define TBG_CNTRL_1_V_TGL (1 << 1)
236# define TBG_CNTRL_1_TGL_EN (1 << 2)
237# define TBG_CNTRL_1_X_EXT (1 << 3)
238# define TBG_CNTRL_1_H_EXT (1 << 4)
239# define TBG_CNTRL_1_V_EXT (1 << 5)
240# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
241#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
242#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
243# define HVF_CNTRL_0_SM (1 << 7)
244# define HVF_CNTRL_0_RWB (1 << 6)
245# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
246# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
247#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
248# define HVF_CNTRL_1_FOR (1 << 0)
249# define HVF_CNTRL_1_YUVBLK (1 << 1)
250# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
251# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
252# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
253#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
254# define RPT_CNTRL_REPEAT(x) ((x) & 15)
255#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
256# define I2S_FORMAT_PHILIPS (0 << 0)
257# define I2S_FORMAT_LEFT_J (2 << 0)
258# define I2S_FORMAT_RIGHT_J (3 << 0)
259#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
260# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
261# define AIP_CLKSEL_AIP_I2S (1 << 3)
262# define AIP_CLKSEL_FS_ACLK (0 << 0)
263# define AIP_CLKSEL_FS_MCLK (1 << 0)
264# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
265
266/* Page 02h: PLL settings */
267#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
268# define PLL_SERIAL_1_SRL_FDN (1 << 0)
269# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
270# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
271#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
272# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
273# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
274#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
275# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
276# define PLL_SERIAL_3_SRL_DE (1 << 2)
277# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
278#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
279#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
280#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
281#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
282#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
283#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
284#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
285#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
286#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
287# define AUDIO_DIV_SERCLK_1 0
288# define AUDIO_DIV_SERCLK_2 1
289# define AUDIO_DIV_SERCLK_4 2
290# define AUDIO_DIV_SERCLK_8 3
291# define AUDIO_DIV_SERCLK_16 4
292# define AUDIO_DIV_SERCLK_32 5
293#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
294# define SEL_CLK_SEL_CLK1 (1 << 0)
295# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
296# define SEL_CLK_ENA_SC_CLK (1 << 3)
297#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
298
299
300/* Page 09h: EDID Control */
301#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
302/* next 127 successive registers are the EDID block */
303#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
304#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
305#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
306#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
307#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
308
309
310/* Page 10h: information frames and packets */
311#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
312#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
313#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
314#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
315#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
316
317
318/* Page 11h: audio settings and content info packets */
319#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
320# define AIP_CNTRL_0_RST_FIFO (1 << 0)
321# define AIP_CNTRL_0_SWAP (1 << 1)
322# define AIP_CNTRL_0_LAYOUT (1 << 2)
323# define AIP_CNTRL_0_ACR_MAN (1 << 5)
324# define AIP_CNTRL_0_RST_CTS (1 << 6)
325#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
326# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
327# define CA_I2S_HBR_CHSTAT (1 << 6)
328#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
329#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
330#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
331#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
332#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
333#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
334#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
335#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
336# define CTS_N_K(x) (((x) & 7) << 0)
337# define CTS_N_M(x) (((x) & 3) << 4)
338#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
339# define ENC_CNTRL_RST_ENC (1 << 0)
340# define ENC_CNTRL_RST_SEL (1 << 1)
341# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
342#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
343# define DIP_FLAGS_ACR (1 << 0)
344# define DIP_FLAGS_GC (1 << 1)
345#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
346# define DIP_IF_FLAGS_IF1 (1 << 1)
347# define DIP_IF_FLAGS_IF2 (1 << 2)
348# define DIP_IF_FLAGS_IF3 (1 << 3)
349# define DIP_IF_FLAGS_IF4 (1 << 4)
350# define DIP_IF_FLAGS_IF5 (1 << 5)
351#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
352
353
354/* Page 12h: HDCP and OTP */
355#define REG_TX3 REG(0x12, 0x9a) /* read/write */
356#define REG_TX4 REG(0x12, 0x9b) /* read/write */
357# define TX4_PD_RAM (1 << 1)
358#define REG_TX33 REG(0x12, 0xb8) /* read/write */
359# define TX33_HDMI (1 << 1)
360
361
362/* Page 13h: Gamut related metadata packets */
363
364
365
366/* CEC registers: (not paged)
367 */
368#define REG_CEC_INTSTATUS 0xee /* read */
369# define CEC_INTSTATUS_CEC (1 << 0)
370# define CEC_INTSTATUS_HDMI (1 << 1)
371#define REG_CEC_CAL_XOSC_CTRL1 0xf2
372# define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0)
373#define REG_CEC_DES_FREQ2 0xf5
374# define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
375#define REG_CEC_CLK 0xf6
376# define CEC_CLK_FRO 0x11
377#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
378# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
379# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
380# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
381# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
382#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
383#define REG_CEC_RXSHPDINT 0xfd /* read */
384# define CEC_RXSHPDINT_RXSENS BIT(0)
385# define CEC_RXSHPDINT_HPD BIT(1)
386#define REG_CEC_RXSHPDLEV 0xfe /* read */
387# define CEC_RXSHPDLEV_RXSENS (1 << 0)
388# define CEC_RXSHPDLEV_HPD (1 << 1)
389
390#define REG_CEC_ENAMODS 0xff /* read/write */
391# define CEC_ENAMODS_EN_CEC_CLK (1 << 7)
392# define CEC_ENAMODS_DIS_FRO (1 << 6)
393# define CEC_ENAMODS_DIS_CCLK (1 << 5)
394# define CEC_ENAMODS_EN_RXSENS (1 << 2)
395# define CEC_ENAMODS_EN_HDMI (1 << 1)
396# define CEC_ENAMODS_EN_CEC (1 << 0)
397
398
399/* Device versions: */
400#define TDA9989N2 0x0101
401#define TDA19989 0x0201
402#define TDA19989N2 0x0202
403#define TDA19988 0x0301
404
405static void
406cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
407{
408 u8 buf[] = {addr, val};
409 struct i2c_msg msg = {
410 .addr = priv->cec_addr,
411 .len = 2,
412 .buf = buf,
413 };
414 int ret;
415
416 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
417 if (ret < 0)
418 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
419 ret, addr);
420}
421
422static u8
423cec_read(struct tda998x_priv *priv, u8 addr)
424{
425 u8 val;
426 struct i2c_msg msg[2] = {
427 {
428 .addr = priv->cec_addr,
429 .len = 1,
430 .buf = &addr,
431 }, {
432 .addr = priv->cec_addr,
433 .flags = I2C_M_RD,
434 .len = 1,
435 .buf = &val,
436 },
437 };
438 int ret;
439
440 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
441 if (ret < 0) {
442 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
443 ret, addr);
444 val = 0;
445 }
446
447 return val;
448}
449
450static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
451{
452 int val = cec_read(priv, REG_CEC_ENAMODS);
453
454 if (val < 0)
455 return;
456
457 if (enable)
458 val |= mods;
459 else
460 val &= ~mods;
461
462 cec_write(priv, REG_CEC_ENAMODS, val);
463}
464
465static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
466{
467 if (enable) {
468 u8 val;
469
470 cec_write(priv, 0xf3, 0xc0);
471 cec_write(priv, 0xf4, 0xd4);
472
473 /* Enable automatic calibration mode */
474 val = cec_read(priv, REG_CEC_DES_FREQ2);
475 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
476 cec_write(priv, REG_CEC_DES_FREQ2, val);
477
478 /* Enable free running oscillator */
479 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
480 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
481
482 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
483 CEC_CAL_XOSC_CTRL1_ENA_CAL);
484 } else {
485 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
486 }
487}
488
489/*
490 * Calibration for the internal oscillator: we need to set calibration mode,
491 * and then pulse the IRQ line low for a 10ms ± 1% period.
492 */
493static void tda998x_cec_calibration(struct tda998x_priv *priv)
494{
495 struct gpio_desc *calib = priv->calib;
496
497 mutex_lock(&priv->edid_mutex);
498 if (priv->hdmi->irq > 0)
499 disable_irq(priv->hdmi->irq);
500 gpiod_direction_output(calib, 1);
501 tda998x_cec_set_calibration(priv, true);
502
503 local_irq_disable();
504 gpiod_set_value(calib, 0);
505 mdelay(10);
506 gpiod_set_value(calib, 1);
507 local_irq_enable();
508
509 tda998x_cec_set_calibration(priv, false);
510 gpiod_direction_input(calib);
511 if (priv->hdmi->irq > 0)
512 enable_irq(priv->hdmi->irq);
513 mutex_unlock(&priv->edid_mutex);
514}
515
516static int tda998x_cec_hook_init(void *data)
517{
518 struct tda998x_priv *priv = data;
519 struct gpio_desc *calib;
520
521 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
522 if (IS_ERR(calib)) {
523 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
524 PTR_ERR(calib));
525 return PTR_ERR(calib);
526 }
527
528 priv->calib = calib;
529
530 return 0;
531}
532
533static void tda998x_cec_hook_exit(void *data)
534{
535 struct tda998x_priv *priv = data;
536
537 gpiod_put(priv->calib);
538 priv->calib = NULL;
539}
540
541static int tda998x_cec_hook_open(void *data)
542{
543 struct tda998x_priv *priv = data;
544
545 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
546 tda998x_cec_calibration(priv);
547
548 return 0;
549}
550
551static void tda998x_cec_hook_release(void *data)
552{
553 struct tda998x_priv *priv = data;
554
555 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
556}
557
558static int
559set_page(struct tda998x_priv *priv, u16 reg)
560{
561 if (REG2PAGE(reg) != priv->current_page) {
562 struct i2c_client *client = priv->hdmi;
563 u8 buf[] = {
564 REG_CURPAGE, REG2PAGE(reg)
565 };
566 int ret = i2c_master_send(client, buf, sizeof(buf));
567 if (ret < 0) {
568 dev_err(&client->dev, "%s %04x err %d\n", __func__,
569 reg, ret);
570 return ret;
571 }
572
573 priv->current_page = REG2PAGE(reg);
574 }
575 return 0;
576}
577
578static int
579reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
580{
581 struct i2c_client *client = priv->hdmi;
582 u8 addr = REG2ADDR(reg);
583 int ret;
584
585 mutex_lock(&priv->mutex);
586 ret = set_page(priv, reg);
587 if (ret < 0)
588 goto out;
589
590 ret = i2c_master_send(client, &addr, sizeof(addr));
591 if (ret < 0)
592 goto fail;
593
594 ret = i2c_master_recv(client, buf, cnt);
595 if (ret < 0)
596 goto fail;
597
598 goto out;
599
600fail:
601 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
602out:
603 mutex_unlock(&priv->mutex);
604 return ret;
605}
606
607#define MAX_WRITE_RANGE_BUF 32
608
609static void
610reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
611{
612 struct i2c_client *client = priv->hdmi;
613 /* This is the maximum size of the buffer passed in */
614 u8 buf[MAX_WRITE_RANGE_BUF + 1];
615 int ret;
616
617 if (cnt > MAX_WRITE_RANGE_BUF) {
618 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
619 MAX_WRITE_RANGE_BUF);
620 return;
621 }
622
623 buf[0] = REG2ADDR(reg);
624 memcpy(&buf[1], p, cnt);
625
626 mutex_lock(&priv->mutex);
627 ret = set_page(priv, reg);
628 if (ret < 0)
629 goto out;
630
631 ret = i2c_master_send(client, buf, cnt + 1);
632 if (ret < 0)
633 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
634out:
635 mutex_unlock(&priv->mutex);
636}
637
638static int
639reg_read(struct tda998x_priv *priv, u16 reg)
640{
641 u8 val = 0;
642 int ret;
643
644 ret = reg_read_range(priv, reg, &val, sizeof(val));
645 if (ret < 0)
646 return ret;
647 return val;
648}
649
650static void
651reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
652{
653 struct i2c_client *client = priv->hdmi;
654 u8 buf[] = {REG2ADDR(reg), val};
655 int ret;
656
657 mutex_lock(&priv->mutex);
658 ret = set_page(priv, reg);
659 if (ret < 0)
660 goto out;
661
662 ret = i2c_master_send(client, buf, sizeof(buf));
663 if (ret < 0)
664 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
665out:
666 mutex_unlock(&priv->mutex);
667}
668
669static void
670reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
671{
672 struct i2c_client *client = priv->hdmi;
673 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
674 int ret;
675
676 mutex_lock(&priv->mutex);
677 ret = set_page(priv, reg);
678 if (ret < 0)
679 goto out;
680
681 ret = i2c_master_send(client, buf, sizeof(buf));
682 if (ret < 0)
683 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
684out:
685 mutex_unlock(&priv->mutex);
686}
687
688static void
689reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
690{
691 int old_val;
692
693 old_val = reg_read(priv, reg);
694 if (old_val >= 0)
695 reg_write(priv, reg, old_val | val);
696}
697
698static void
699reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
700{
701 int old_val;
702
703 old_val = reg_read(priv, reg);
704 if (old_val >= 0)
705 reg_write(priv, reg, old_val & ~val);
706}
707
708static void
709tda998x_reset(struct tda998x_priv *priv)
710{
711 /* reset audio and i2c master: */
712 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
713 msleep(50);
714 reg_write(priv, REG_SOFTRESET, 0);
715 msleep(50);
716
717 /* reset transmitter: */
718 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
719 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
720
721 /* PLL registers common configuration */
722 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
723 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
724 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
725 reg_write(priv, REG_SERIALIZER, 0x00);
726 reg_write(priv, REG_BUFFER_OUT, 0x00);
727 reg_write(priv, REG_PLL_SCG1, 0x00);
728 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
729 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
730 reg_write(priv, REG_PLL_SCGN1, 0xfa);
731 reg_write(priv, REG_PLL_SCGN2, 0x00);
732 reg_write(priv, REG_PLL_SCGR1, 0x5b);
733 reg_write(priv, REG_PLL_SCGR2, 0x00);
734 reg_write(priv, REG_PLL_SCG2, 0x10);
735
736 /* Write the default value MUX register */
737 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
738}
739
740/*
741 * The TDA998x has a problem when trying to read the EDID close to a
742 * HPD assertion: it needs a delay of 100ms to avoid timing out while
743 * trying to read EDID data.
744 *
745 * However, tda998x_connector_get_modes() may be called at any moment
746 * after tda998x_connector_detect() indicates that we are connected, so
747 * we need to delay probing modes in tda998x_connector_get_modes() after
748 * we have seen a HPD inactive->active transition. This code implements
749 * that delay.
750 */
751static void tda998x_edid_delay_done(struct timer_list *t)
752{
753 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
754
755 priv->edid_delay_active = false;
756 wake_up(&priv->edid_delay_waitq);
757 schedule_work(&priv->detect_work);
758}
759
760static void tda998x_edid_delay_start(struct tda998x_priv *priv)
761{
762 priv->edid_delay_active = true;
763 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
764}
765
766static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
767{
768 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
769}
770
771/*
772 * We need to run the KMS hotplug event helper outside of our threaded
773 * interrupt routine as this can call back into our get_modes method,
774 * which will want to make use of interrupts.
775 */
776static void tda998x_detect_work(struct work_struct *work)
777{
778 struct tda998x_priv *priv =
779 container_of(work, struct tda998x_priv, detect_work);
780 struct drm_device *dev = priv->connector.dev;
781
782 if (dev)
783 drm_kms_helper_hotplug_event(dev);
784}
785
786/*
787 * only 2 interrupts may occur: screen plug/unplug and EDID read
788 */
789static irqreturn_t tda998x_irq_thread(int irq, void *data)
790{
791 struct tda998x_priv *priv = data;
792 u8 sta, cec, lvl, flag0, flag1, flag2;
793 bool handled = false;
794
795 sta = cec_read(priv, REG_CEC_INTSTATUS);
796 if (sta & CEC_INTSTATUS_HDMI) {
797 cec = cec_read(priv, REG_CEC_RXSHPDINT);
798 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
799 flag0 = reg_read(priv, REG_INT_FLAGS_0);
800 flag1 = reg_read(priv, REG_INT_FLAGS_1);
801 flag2 = reg_read(priv, REG_INT_FLAGS_2);
802 DRM_DEBUG_DRIVER(
803 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
804 sta, cec, lvl, flag0, flag1, flag2);
805
806 if (cec & CEC_RXSHPDINT_HPD) {
807 if (lvl & CEC_RXSHPDLEV_HPD) {
808 tda998x_edid_delay_start(priv);
809 } else {
810 schedule_work(&priv->detect_work);
811 cec_notifier_phys_addr_invalidate(
812 priv->cec_notify);
813 }
814
815 handled = true;
816 }
817
818 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
819 priv->wq_edid_wait = 0;
820 wake_up(&priv->wq_edid);
821 handled = true;
822 }
823 }
824
825 return IRQ_RETVAL(handled);
826}
827
828static void
829tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
830 union hdmi_infoframe *frame)
831{
832 u8 buf[MAX_WRITE_RANGE_BUF];
833 ssize_t len;
834
835 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
836 if (len < 0) {
837 dev_err(&priv->hdmi->dev,
838 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
839 frame->any.type, len);
840 return;
841 }
842
843 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
844 reg_write_range(priv, addr, buf, len);
845 reg_set(priv, REG_DIP_IF_FLAGS, bit);
846}
847
848static void tda998x_write_aif(struct tda998x_priv *priv,
849 const struct hdmi_audio_infoframe *cea)
850{
851 union hdmi_infoframe frame;
852
853 frame.audio = *cea;
854
855 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
856}
857
858static void
859tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
860{
861 union hdmi_infoframe frame;
862
863 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
864 &priv->connector, mode);
865 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
866 drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode,
867 priv->rgb_quant_range);
868
869 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
870}
871
872static void tda998x_write_vsi(struct tda998x_priv *priv,
873 const struct drm_display_mode *mode)
874{
875 union hdmi_infoframe frame;
876
877 if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
878 &priv->connector,
879 mode))
880 reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1);
881 else
882 tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame);
883}
884
885/* Audio support */
886
887static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = {
888 [AUDIO_ROUTE_I2S] = {
889 .ena_aclk = 1,
890 .mux_ap = MUX_AP_SELECT_I2S,
891 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK,
892 },
893 [AUDIO_ROUTE_SPDIF] = {
894 .ena_aclk = 0,
895 .mux_ap = MUX_AP_SELECT_SPDIF,
896 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF,
897 },
898};
899
900/* Configure the TDA998x audio data and clock routing. */
901static int tda998x_derive_routing(struct tda998x_priv *priv,
902 struct tda998x_audio_settings *s,
903 unsigned int route)
904{
905 s->route = &tda998x_audio_route[route];
906 s->ena_ap = priv->audio_port_enable[route];
907 if (s->ena_ap == 0) {
908 dev_err(&priv->hdmi->dev, "no audio configuration found\n");
909 return -EINVAL;
910 }
911
912 return 0;
913}
914
915/*
916 * The audio clock divisor register controls a divider producing Audio_Clk_Out
917 * from SERclk by dividing it by 2^n where 0 <= n <= 5. We don't know what
918 * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock.
919 *
920 * It seems that Audio_Clk_Out must be the smallest value that is greater
921 * than 128*fs, otherwise audio does not function. There is some suggestion
922 * that 126*fs is a better value.
923 */
924static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs)
925{
926 unsigned long min_audio_clk = fs * 128;
927 unsigned long ser_clk = priv->tmds_clock * 1000;
928 u8 adiv;
929
930 for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--)
931 if (ser_clk > min_audio_clk << adiv)
932 break;
933
934 dev_dbg(&priv->hdmi->dev,
935 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n",
936 ser_clk, fs, min_audio_clk, adiv);
937
938 return adiv;
939}
940
941/*
942 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
943 * generate the CTS value. It appears that the "measured time stamp" is
944 * the number of TDMS clock cycles within a number of audio input clock
945 * cycles defined by the k and N parameters defined below, in a similar
946 * way to that which is set out in the CTS generation in the HDMI spec.
947 *
948 * tmdsclk ----> mts -> /m ---> CTS
949 * ^
950 * sclk -> /k -> /N
951 *
952 * CTS = mts / m, where m is 2^M.
953 * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
954 * /N is a divider based on the HDMI specified N value.
955 *
956 * This produces the following equation:
957 * CTS = tmds_clock * k * N / (sclk * m)
958 *
959 * When combined with the sink-side equation, and realising that sclk is
960 * bclk_ratio * fs, we end up with:
961 * k = m * bclk_ratio / 128.
962 *
963 * Note: S/PDIF always uses a bclk_ratio of 64.
964 */
965static int tda998x_derive_cts_n(struct tda998x_priv *priv,
966 struct tda998x_audio_settings *settings,
967 unsigned int ratio)
968{
969 switch (ratio) {
970 case 16:
971 settings->cts_n = CTS_N_M(3) | CTS_N_K(0);
972 break;
973 case 32:
974 settings->cts_n = CTS_N_M(3) | CTS_N_K(1);
975 break;
976 case 48:
977 settings->cts_n = CTS_N_M(3) | CTS_N_K(2);
978 break;
979 case 64:
980 settings->cts_n = CTS_N_M(3) | CTS_N_K(3);
981 break;
982 case 128:
983 settings->cts_n = CTS_N_M(0) | CTS_N_K(0);
984 break;
985 default:
986 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n",
987 ratio);
988 return -EINVAL;
989 }
990 return 0;
991}
992
993static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
994{
995 if (on) {
996 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
997 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
998 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
999 } else {
1000 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1001 }
1002}
1003
1004static void tda998x_configure_audio(struct tda998x_priv *priv)
1005{
1006 const struct tda998x_audio_settings *settings = &priv->audio;
1007 u8 buf[6], adiv;
1008 u32 n;
1009
1010 /* If audio is not configured, there is nothing to do. */
1011 if (settings->ena_ap == 0)
1012 return;
1013
1014 adiv = tda998x_get_adiv(priv, settings->sample_rate);
1015
1016 /* Enable audio ports */
1017 reg_write(priv, REG_ENA_AP, settings->ena_ap);
1018 reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1019 reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1020 reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1021 reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1022 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
1023 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
1024 reg_write(priv, REG_CTS_N, settings->cts_n);
1025 reg_write(priv, REG_AUDIO_DIV, adiv);
1026
1027 /*
1028 * This is the approximate value of N, which happens to be
1029 * the recommended values for non-coherent clocks.
1030 */
1031 n = 128 * settings->sample_rate / 1000;
1032
1033 /* Write the CTS and N values */
1034 buf[0] = 0x44;
1035 buf[1] = 0x42;
1036 buf[2] = 0x01;
1037 buf[3] = n;
1038 buf[4] = n >> 8;
1039 buf[5] = n >> 16;
1040 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
1041
1042 /* Reset CTS generator */
1043 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1044 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1045
1046 /* Write the channel status
1047 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
1048 * there is a separate register for each I2S wire.
1049 */
1050 buf[0] = settings->status[0];
1051 buf[1] = settings->status[1];
1052 buf[2] = settings->status[3];
1053 buf[3] = settings->status[4];
1054 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
1055
1056 tda998x_audio_mute(priv, true);
1057 msleep(20);
1058 tda998x_audio_mute(priv, false);
1059
1060 tda998x_write_aif(priv, &settings->cea);
1061}
1062
1063static int tda998x_audio_hw_params(struct device *dev, void *data,
1064 struct hdmi_codec_daifmt *daifmt,
1065 struct hdmi_codec_params *params)
1066{
1067 struct tda998x_priv *priv = dev_get_drvdata(dev);
1068 unsigned int bclk_ratio;
1069 bool spdif = daifmt->fmt == HDMI_SPDIF;
1070 int ret;
1071 struct tda998x_audio_settings audio = {
1072 .sample_rate = params->sample_rate,
1073 .cea = params->cea,
1074 };
1075
1076 memcpy(audio.status, params->iec.status,
1077 min(sizeof(audio.status), sizeof(params->iec.status)));
1078
1079 switch (daifmt->fmt) {
1080 case HDMI_I2S:
1081 audio.i2s_format = I2S_FORMAT_PHILIPS;
1082 break;
1083 case HDMI_LEFT_J:
1084 audio.i2s_format = I2S_FORMAT_LEFT_J;
1085 break;
1086 case HDMI_RIGHT_J:
1087 audio.i2s_format = I2S_FORMAT_RIGHT_J;
1088 break;
1089 case HDMI_SPDIF:
1090 audio.i2s_format = 0;
1091 break;
1092 default:
1093 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1094 return -EINVAL;
1095 }
1096
1097 if (!spdif &&
1098 (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1099 daifmt->bit_clk_provider || daifmt->frame_clk_provider)) {
1100 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1101 daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1102 daifmt->bit_clk_provider,
1103 daifmt->frame_clk_provider);
1104 return -EINVAL;
1105 }
1106
1107 ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif);
1108 if (ret < 0)
1109 return ret;
1110
1111 bclk_ratio = spdif ? 64 : params->sample_width * 2;
1112 ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio);
1113 if (ret < 0)
1114 return ret;
1115
1116 mutex_lock(&priv->audio_mutex);
1117 priv->audio = audio;
1118 if (priv->supports_infoframes && priv->sink_has_audio)
1119 tda998x_configure_audio(priv);
1120 mutex_unlock(&priv->audio_mutex);
1121
1122 return 0;
1123}
1124
1125static void tda998x_audio_shutdown(struct device *dev, void *data)
1126{
1127 struct tda998x_priv *priv = dev_get_drvdata(dev);
1128
1129 mutex_lock(&priv->audio_mutex);
1130
1131 reg_write(priv, REG_ENA_AP, 0);
1132 priv->audio.ena_ap = 0;
1133
1134 mutex_unlock(&priv->audio_mutex);
1135}
1136
1137static int tda998x_audio_mute_stream(struct device *dev, void *data,
1138 bool enable, int direction)
1139{
1140 struct tda998x_priv *priv = dev_get_drvdata(dev);
1141
1142 mutex_lock(&priv->audio_mutex);
1143
1144 tda998x_audio_mute(priv, enable);
1145
1146 mutex_unlock(&priv->audio_mutex);
1147 return 0;
1148}
1149
1150static int tda998x_audio_get_eld(struct device *dev, void *data,
1151 uint8_t *buf, size_t len)
1152{
1153 struct tda998x_priv *priv = dev_get_drvdata(dev);
1154
1155 mutex_lock(&priv->audio_mutex);
1156 memcpy(buf, priv->connector.eld,
1157 min(sizeof(priv->connector.eld), len));
1158 mutex_unlock(&priv->audio_mutex);
1159
1160 return 0;
1161}
1162
1163static const struct hdmi_codec_ops audio_codec_ops = {
1164 .hw_params = tda998x_audio_hw_params,
1165 .audio_shutdown = tda998x_audio_shutdown,
1166 .mute_stream = tda998x_audio_mute_stream,
1167 .get_eld = tda998x_audio_get_eld,
1168 .no_capture_mute = 1,
1169};
1170
1171static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1172 struct device *dev)
1173{
1174 struct hdmi_codec_pdata codec_data = {
1175 .ops = &audio_codec_ops,
1176 .max_i2s_channels = 2,
1177 .no_i2s_capture = 1,
1178 .no_spdif_capture = 1,
1179 };
1180
1181 if (priv->audio_port_enable[AUDIO_ROUTE_I2S])
1182 codec_data.i2s = 1;
1183 if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1184 codec_data.spdif = 1;
1185
1186 priv->audio_pdev = platform_device_register_data(
1187 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1188 &codec_data, sizeof(codec_data));
1189
1190 return PTR_ERR_OR_ZERO(priv->audio_pdev);
1191}
1192
1193/* DRM connector functions */
1194
1195static enum drm_connector_status
1196tda998x_connector_detect(struct drm_connector *connector, bool force)
1197{
1198 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1199 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1200
1201 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1202 connector_status_disconnected;
1203}
1204
1205static void tda998x_connector_destroy(struct drm_connector *connector)
1206{
1207 drm_connector_cleanup(connector);
1208}
1209
1210static const struct drm_connector_funcs tda998x_connector_funcs = {
1211 .reset = drm_atomic_helper_connector_reset,
1212 .fill_modes = drm_helper_probe_single_connector_modes,
1213 .detect = tda998x_connector_detect,
1214 .destroy = tda998x_connector_destroy,
1215 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1216 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1217};
1218
1219static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1220{
1221 struct tda998x_priv *priv = data;
1222 u8 offset, segptr;
1223 int ret, i;
1224
1225 offset = (blk & 1) ? 128 : 0;
1226 segptr = blk / 2;
1227
1228 mutex_lock(&priv->edid_mutex);
1229
1230 reg_write(priv, REG_DDC_ADDR, 0xa0);
1231 reg_write(priv, REG_DDC_OFFS, offset);
1232 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1233 reg_write(priv, REG_DDC_SEGM, segptr);
1234
1235 /* enable reading EDID: */
1236 priv->wq_edid_wait = 1;
1237 reg_write(priv, REG_EDID_CTRL, 0x1);
1238
1239 /* flag must be cleared by sw: */
1240 reg_write(priv, REG_EDID_CTRL, 0x0);
1241
1242 /* wait for block read to complete: */
1243 if (priv->hdmi->irq) {
1244 i = wait_event_timeout(priv->wq_edid,
1245 !priv->wq_edid_wait,
1246 msecs_to_jiffies(100));
1247 if (i < 0) {
1248 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1249 ret = i;
1250 goto failed;
1251 }
1252 } else {
1253 for (i = 100; i > 0; i--) {
1254 msleep(1);
1255 ret = reg_read(priv, REG_INT_FLAGS_2);
1256 if (ret < 0)
1257 goto failed;
1258 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1259 break;
1260 }
1261 }
1262
1263 if (i == 0) {
1264 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1265 ret = -ETIMEDOUT;
1266 goto failed;
1267 }
1268
1269 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1270 if (ret != length) {
1271 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1272 blk, ret);
1273 goto failed;
1274 }
1275
1276 ret = 0;
1277
1278 failed:
1279 mutex_unlock(&priv->edid_mutex);
1280 return ret;
1281}
1282
1283static int tda998x_connector_get_modes(struct drm_connector *connector)
1284{
1285 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1286 struct edid *edid;
1287 int n;
1288
1289 /*
1290 * If we get killed while waiting for the HPD timeout, return
1291 * no modes found: we are not in a restartable path, so we
1292 * can't handle signals gracefully.
1293 */
1294 if (tda998x_edid_delay_wait(priv))
1295 return 0;
1296
1297 if (priv->rev == TDA19988)
1298 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1299
1300 edid = drm_do_get_edid(connector, read_edid_block, priv);
1301
1302 if (priv->rev == TDA19988)
1303 reg_set(priv, REG_TX4, TX4_PD_RAM);
1304
1305 if (!edid) {
1306 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1307 return 0;
1308 }
1309
1310 drm_connector_update_edid_property(connector, edid);
1311 cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1312
1313 mutex_lock(&priv->audio_mutex);
1314 n = drm_add_edid_modes(connector, edid);
1315 priv->sink_has_audio = drm_detect_monitor_audio(edid);
1316 mutex_unlock(&priv->audio_mutex);
1317
1318 kfree(edid);
1319
1320 return n;
1321}
1322
1323static struct drm_encoder *
1324tda998x_connector_best_encoder(struct drm_connector *connector)
1325{
1326 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1327
1328 return priv->bridge.encoder;
1329}
1330
1331static
1332const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1333 .get_modes = tda998x_connector_get_modes,
1334 .best_encoder = tda998x_connector_best_encoder,
1335};
1336
1337static int tda998x_connector_init(struct tda998x_priv *priv,
1338 struct drm_device *drm)
1339{
1340 struct drm_connector *connector = &priv->connector;
1341 int ret;
1342
1343 connector->interlace_allowed = 1;
1344
1345 if (priv->hdmi->irq)
1346 connector->polled = DRM_CONNECTOR_POLL_HPD;
1347 else
1348 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1349 DRM_CONNECTOR_POLL_DISCONNECT;
1350
1351 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1352 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1353 DRM_MODE_CONNECTOR_HDMIA);
1354 if (ret)
1355 return ret;
1356
1357 drm_connector_attach_encoder(&priv->connector,
1358 priv->bridge.encoder);
1359
1360 return 0;
1361}
1362
1363/* DRM bridge functions */
1364
1365static int tda998x_bridge_attach(struct drm_bridge *bridge,
1366 enum drm_bridge_attach_flags flags)
1367{
1368 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1369
1370 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1371 DRM_ERROR("Fix bridge driver to make connector optional!");
1372 return -EINVAL;
1373 }
1374
1375 return tda998x_connector_init(priv, bridge->dev);
1376}
1377
1378static void tda998x_bridge_detach(struct drm_bridge *bridge)
1379{
1380 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1381
1382 drm_connector_cleanup(&priv->connector);
1383}
1384
1385static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1386 const struct drm_display_info *info,
1387 const struct drm_display_mode *mode)
1388{
1389 /* TDA19988 dotclock can go up to 165MHz */
1390 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1391
1392 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1393 return MODE_CLOCK_HIGH;
1394 if (mode->htotal >= BIT(13))
1395 return MODE_BAD_HVALUE;
1396 if (mode->vtotal >= BIT(11))
1397 return MODE_BAD_VVALUE;
1398 return MODE_OK;
1399}
1400
1401static void tda998x_bridge_enable(struct drm_bridge *bridge)
1402{
1403 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1404
1405 if (!priv->is_on) {
1406 /* enable video ports, audio will be enabled later */
1407 reg_write(priv, REG_ENA_VP_0, 0xff);
1408 reg_write(priv, REG_ENA_VP_1, 0xff);
1409 reg_write(priv, REG_ENA_VP_2, 0xff);
1410 /* set muxing after enabling ports: */
1411 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1412 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1413 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1414
1415 priv->is_on = true;
1416 }
1417}
1418
1419static void tda998x_bridge_disable(struct drm_bridge *bridge)
1420{
1421 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1422
1423 if (priv->is_on) {
1424 /* disable video ports */
1425 reg_write(priv, REG_ENA_VP_0, 0x00);
1426 reg_write(priv, REG_ENA_VP_1, 0x00);
1427 reg_write(priv, REG_ENA_VP_2, 0x00);
1428
1429 priv->is_on = false;
1430 }
1431}
1432
1433static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1434 const struct drm_display_mode *mode,
1435 const struct drm_display_mode *adjusted_mode)
1436{
1437 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1438 unsigned long tmds_clock;
1439 u16 ref_pix, ref_line, n_pix, n_line;
1440 u16 hs_pix_s, hs_pix_e;
1441 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1442 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1443 u16 vwin1_line_s, vwin1_line_e;
1444 u16 vwin2_line_s, vwin2_line_e;
1445 u16 de_pix_s, de_pix_e;
1446 u8 reg, div, rep, sel_clk;
1447
1448 /*
1449 * Since we are "computer" like, our source invariably produces
1450 * full-range RGB. If the monitor supports full-range, then use
1451 * it, otherwise reduce to limited-range.
1452 */
1453 priv->rgb_quant_range =
1454 priv->connector.display_info.rgb_quant_range_selectable ?
1455 HDMI_QUANTIZATION_RANGE_FULL :
1456 drm_default_rgb_quant_range(adjusted_mode);
1457
1458 /*
1459 * Internally TDA998x is using ITU-R BT.656 style sync but
1460 * we get VESA style sync. TDA998x is using a reference pixel
1461 * relative to ITU to sync to the input frame and for output
1462 * sync generation. Currently, we are using reference detection
1463 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1464 * which is position of rising VS with coincident rising HS.
1465 *
1466 * Now there is some issues to take care of:
1467 * - HDMI data islands require sync-before-active
1468 * - TDA998x register values must be > 0 to be enabled
1469 * - REFLINE needs an additional offset of +1
1470 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1471 *
1472 * So we add +1 to all horizontal and vertical register values,
1473 * plus an additional +3 for REFPIX as we are using RGB input only.
1474 */
1475 n_pix = mode->htotal;
1476 n_line = mode->vtotal;
1477
1478 hs_pix_e = mode->hsync_end - mode->hdisplay;
1479 hs_pix_s = mode->hsync_start - mode->hdisplay;
1480 de_pix_e = mode->htotal;
1481 de_pix_s = mode->htotal - mode->hdisplay;
1482 ref_pix = 3 + hs_pix_s;
1483
1484 /*
1485 * Attached LCD controllers may generate broken sync. Allow
1486 * those to adjust the position of the rising VS edge by adding
1487 * HSKEW to ref_pix.
1488 */
1489 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1490 ref_pix += adjusted_mode->hskew;
1491
1492 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1493 ref_line = 1 + mode->vsync_start - mode->vdisplay;
1494 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1495 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1496 vs1_pix_s = vs1_pix_e = hs_pix_s;
1497 vs1_line_s = mode->vsync_start - mode->vdisplay;
1498 vs1_line_e = vs1_line_s +
1499 mode->vsync_end - mode->vsync_start;
1500 vwin2_line_s = vwin2_line_e = 0;
1501 vs2_pix_s = vs2_pix_e = 0;
1502 vs2_line_s = vs2_line_e = 0;
1503 } else {
1504 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
1505 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1506 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1507 vs1_pix_s = vs1_pix_e = hs_pix_s;
1508 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
1509 vs1_line_e = vs1_line_s +
1510 (mode->vsync_end - mode->vsync_start)/2;
1511 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1512 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1513 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
1514 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
1515 vs2_line_e = vs2_line_s +
1516 (mode->vsync_end - mode->vsync_start)/2;
1517 }
1518
1519 /*
1520 * Select pixel repeat depending on the double-clock flag
1521 * (which means we have to repeat each pixel once.)
1522 */
1523 rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0;
1524 sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 |
1525 SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0);
1526
1527 /* the TMDS clock is scaled up by the pixel repeat */
1528 tmds_clock = mode->clock * (1 + rep);
1529
1530 /*
1531 * The divisor is power-of-2. The TDA9983B datasheet gives
1532 * this as ranges of Msample/s, which is 10x the TMDS clock:
1533 * 0 - 800 to 1500 Msample/s
1534 * 1 - 400 to 800 Msample/s
1535 * 2 - 200 to 400 Msample/s
1536 * 3 - as 2 above
1537 */
1538 for (div = 0; div < 3; div++)
1539 if (80000 >> div <= tmds_clock)
1540 break;
1541
1542 mutex_lock(&priv->audio_mutex);
1543
1544 priv->tmds_clock = tmds_clock;
1545
1546 /* mute the audio FIFO: */
1547 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1548
1549 /* set HDMI HDCP mode off: */
1550 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1551 reg_clear(priv, REG_TX33, TX33_HDMI);
1552 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1553
1554 /* no pre-filter or interpolator: */
1555 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1556 HVF_CNTRL_0_INTPOL(0));
1557 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1558 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1559 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1560 VIP_CNTRL_4_BLC(0));
1561
1562 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1563 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1564 PLL_SERIAL_3_SRL_DE);
1565 reg_write(priv, REG_SERIALIZER, 0);
1566 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1567
1568 reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));
1569 reg_write(priv, REG_SEL_CLK, sel_clk);
1570 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1571 PLL_SERIAL_2_SRL_PR(rep));
1572
1573 /* set color matrix according to output rgb quant range */
1574 if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
1575 static u8 tda998x_full_to_limited_range[] = {
1576 MAT_CONTRL_MAT_SC(2),
1577 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1578 0x03, 0x6f, 0x00, 0x00, 0x00, 0x00,
1579 0x00, 0x00, 0x03, 0x6f, 0x00, 0x00,
1580 0x00, 0x00, 0x00, 0x00, 0x03, 0x6f,
1581 0x00, 0x40, 0x00, 0x40, 0x00, 0x40
1582 };
1583 reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1584 reg_write_range(priv, REG_MAT_CONTRL,
1585 tda998x_full_to_limited_range,
1586 sizeof(tda998x_full_to_limited_range));
1587 } else {
1588 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1589 MAT_CONTRL_MAT_SC(1));
1590 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1591 }
1592
1593 /* set BIAS tmds value: */
1594 reg_write(priv, REG_ANA_GENERAL, 0x09);
1595
1596 /*
1597 * Sync on rising HSYNC/VSYNC
1598 */
1599 reg = VIP_CNTRL_3_SYNC_HS;
1600
1601 /*
1602 * TDA19988 requires high-active sync at input stage,
1603 * so invert low-active sync provided by master encoder here
1604 */
1605 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1606 reg |= VIP_CNTRL_3_H_TGL;
1607 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1608 reg |= VIP_CNTRL_3_V_TGL;
1609 reg_write(priv, REG_VIP_CNTRL_3, reg);
1610
1611 reg_write(priv, REG_VIDFORMAT, 0x00);
1612 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1613 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1614 reg_write16(priv, REG_NPIX_MSB, n_pix);
1615 reg_write16(priv, REG_NLINE_MSB, n_line);
1616 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1617 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1618 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1619 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1620 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1621 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1622 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1623 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1624 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1625 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1626 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1627 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1628 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1629 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1630 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1631 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1632
1633 if (priv->rev == TDA19988) {
1634 /* let incoming pixels fill the active space (if any) */
1635 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1636 }
1637
1638 /*
1639 * Always generate sync polarity relative to input sync and
1640 * revert input stage toggled sync at output stage
1641 */
1642 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1643 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1644 reg |= TBG_CNTRL_1_H_TGL;
1645 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1646 reg |= TBG_CNTRL_1_V_TGL;
1647 reg_write(priv, REG_TBG_CNTRL_1, reg);
1648
1649 /* must be last register set: */
1650 reg_write(priv, REG_TBG_CNTRL_0, 0);
1651
1652 /* CEA-861B section 6 says that:
1653 * CEA version 1 (CEA-861) has no support for infoframes.
1654 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1655 * and optional basic audio.
1656 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1657 * and optional digital audio, with audio infoframes.
1658 *
1659 * Since we only support generation of version 2 AVI infoframes,
1660 * ignore CEA version 2 and below (iow, behave as if we're a
1661 * CEA-861 source.)
1662 */
1663 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1664
1665 if (priv->supports_infoframes) {
1666 /* We need to turn HDMI HDCP stuff on to get audio through */
1667 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1668 reg_write(priv, REG_TBG_CNTRL_1, reg);
1669 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1670 reg_set(priv, REG_TX33, TX33_HDMI);
1671
1672 tda998x_write_avi(priv, adjusted_mode);
1673 tda998x_write_vsi(priv, adjusted_mode);
1674
1675 if (priv->sink_has_audio)
1676 tda998x_configure_audio(priv);
1677 }
1678
1679 mutex_unlock(&priv->audio_mutex);
1680}
1681
1682static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1683 .attach = tda998x_bridge_attach,
1684 .detach = tda998x_bridge_detach,
1685 .mode_valid = tda998x_bridge_mode_valid,
1686 .disable = tda998x_bridge_disable,
1687 .mode_set = tda998x_bridge_mode_set,
1688 .enable = tda998x_bridge_enable,
1689};
1690
1691/* I2C driver functions */
1692
1693static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1694 struct device_node *np)
1695{
1696 const u32 *port_data;
1697 u32 size;
1698 int i;
1699
1700 port_data = of_get_property(np, "audio-ports", &size);
1701 if (!port_data)
1702 return 0;
1703
1704 size /= sizeof(u32);
1705 if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) {
1706 dev_err(&priv->hdmi->dev,
1707 "Bad number of elements in audio-ports dt-property\n");
1708 return -EINVAL;
1709 }
1710
1711 size /= 2;
1712
1713 for (i = 0; i < size; i++) {
1714 unsigned int route;
1715 u8 afmt = be32_to_cpup(&port_data[2*i]);
1716 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1717
1718 switch (afmt) {
1719 case AFMT_I2S:
1720 route = AUDIO_ROUTE_I2S;
1721 break;
1722 case AFMT_SPDIF:
1723 route = AUDIO_ROUTE_SPDIF;
1724 break;
1725 default:
1726 dev_err(&priv->hdmi->dev,
1727 "Bad audio format %u\n", afmt);
1728 return -EINVAL;
1729 }
1730
1731 if (!ena_ap) {
1732 dev_err(&priv->hdmi->dev, "invalid zero port config\n");
1733 continue;
1734 }
1735
1736 if (priv->audio_port_enable[route]) {
1737 dev_err(&priv->hdmi->dev,
1738 "%s format already configured\n",
1739 route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S");
1740 return -EINVAL;
1741 }
1742
1743 priv->audio_port_enable[route] = ena_ap;
1744 }
1745 return 0;
1746}
1747
1748static int tda998x_set_config(struct tda998x_priv *priv,
1749 const struct tda998x_encoder_params *p)
1750{
1751 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1752 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1753 VIP_CNTRL_0_SWAP_B(p->swap_b) |
1754 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1755 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1756 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1757 VIP_CNTRL_1_SWAP_D(p->swap_d) |
1758 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1759 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1760 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1761 VIP_CNTRL_2_SWAP_F(p->swap_f) |
1762 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1763
1764 if (p->audio_params.format != AFMT_UNUSED) {
1765 unsigned int ratio, route;
1766 bool spdif = p->audio_params.format == AFMT_SPDIF;
1767
1768 route = AUDIO_ROUTE_I2S + spdif;
1769
1770 priv->audio.route = &tda998x_audio_route[route];
1771 priv->audio.cea = p->audio_params.cea;
1772 priv->audio.sample_rate = p->audio_params.sample_rate;
1773 memcpy(priv->audio.status, p->audio_params.status,
1774 min(sizeof(priv->audio.status),
1775 sizeof(p->audio_params.status)));
1776 priv->audio.ena_ap = p->audio_params.config;
1777 priv->audio.i2s_format = I2S_FORMAT_PHILIPS;
1778
1779 ratio = spdif ? 64 : p->audio_params.sample_width * 2;
1780 return tda998x_derive_cts_n(priv, &priv->audio, ratio);
1781 }
1782
1783 return 0;
1784}
1785
1786static void tda998x_destroy(struct device *dev)
1787{
1788 struct tda998x_priv *priv = dev_get_drvdata(dev);
1789
1790 drm_bridge_remove(&priv->bridge);
1791
1792 /* disable all IRQs and free the IRQ handler */
1793 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1794 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1795
1796 if (priv->audio_pdev)
1797 platform_device_unregister(priv->audio_pdev);
1798
1799 if (priv->hdmi->irq)
1800 free_irq(priv->hdmi->irq, priv);
1801
1802 del_timer_sync(&priv->edid_delay_timer);
1803 cancel_work_sync(&priv->detect_work);
1804
1805 i2c_unregister_device(priv->cec);
1806
1807 cec_notifier_conn_unregister(priv->cec_notify);
1808}
1809
1810static int tda998x_create(struct device *dev)
1811{
1812 struct i2c_client *client = to_i2c_client(dev);
1813 struct device_node *np = client->dev.of_node;
1814 struct i2c_board_info cec_info;
1815 struct tda998x_priv *priv;
1816 u32 video;
1817 int rev_lo, rev_hi, ret;
1818
1819 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1820 if (!priv)
1821 return -ENOMEM;
1822
1823 dev_set_drvdata(dev, priv);
1824
1825 mutex_init(&priv->mutex); /* protect the page access */
1826 mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1827 mutex_init(&priv->edid_mutex);
1828 INIT_LIST_HEAD(&priv->bridge.list);
1829 init_waitqueue_head(&priv->edid_delay_waitq);
1830 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1831 INIT_WORK(&priv->detect_work, tda998x_detect_work);
1832
1833 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1834 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1835 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1836
1837 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1838 priv->cec_addr = 0x34 + (client->addr & 0x03);
1839 priv->current_page = 0xff;
1840 priv->hdmi = client;
1841
1842 /* wake up the device: */
1843 cec_write(priv, REG_CEC_ENAMODS,
1844 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1845
1846 tda998x_reset(priv);
1847
1848 /* read version: */
1849 rev_lo = reg_read(priv, REG_VERSION_LSB);
1850 if (rev_lo < 0) {
1851 dev_err(dev, "failed to read version: %d\n", rev_lo);
1852 return rev_lo;
1853 }
1854
1855 rev_hi = reg_read(priv, REG_VERSION_MSB);
1856 if (rev_hi < 0) {
1857 dev_err(dev, "failed to read version: %d\n", rev_hi);
1858 return rev_hi;
1859 }
1860
1861 priv->rev = rev_lo | rev_hi << 8;
1862
1863 /* mask off feature bits: */
1864 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1865
1866 switch (priv->rev) {
1867 case TDA9989N2:
1868 dev_info(dev, "found TDA9989 n2");
1869 break;
1870 case TDA19989:
1871 dev_info(dev, "found TDA19989");
1872 break;
1873 case TDA19989N2:
1874 dev_info(dev, "found TDA19989 n2");
1875 break;
1876 case TDA19988:
1877 dev_info(dev, "found TDA19988");
1878 break;
1879 default:
1880 dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1881 return -ENXIO;
1882 }
1883
1884 /* after reset, enable DDC: */
1885 reg_write(priv, REG_DDC_DISABLE, 0x00);
1886
1887 /* set clock on DDC channel: */
1888 reg_write(priv, REG_TX3, 39);
1889
1890 /* if necessary, disable multi-master: */
1891 if (priv->rev == TDA19989)
1892 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1893
1894 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1895 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1896
1897 /* ensure interrupts are disabled */
1898 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1899
1900 /* clear pending interrupts */
1901 cec_read(priv, REG_CEC_RXSHPDINT);
1902 reg_read(priv, REG_INT_FLAGS_0);
1903 reg_read(priv, REG_INT_FLAGS_1);
1904 reg_read(priv, REG_INT_FLAGS_2);
1905
1906 /* initialize the optional IRQ */
1907 if (client->irq) {
1908 unsigned long irq_flags;
1909
1910 /* init read EDID waitqueue and HDP work */
1911 init_waitqueue_head(&priv->wq_edid);
1912
1913 irq_flags =
1914 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1915
1916 priv->cec_glue.irq_flags = irq_flags;
1917
1918 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1919 ret = request_threaded_irq(client->irq, NULL,
1920 tda998x_irq_thread, irq_flags,
1921 "tda998x", priv);
1922 if (ret) {
1923 dev_err(dev, "failed to request IRQ#%u: %d\n",
1924 client->irq, ret);
1925 goto err_irq;
1926 }
1927
1928 /* enable HPD irq */
1929 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1930 }
1931
1932 priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL);
1933 if (!priv->cec_notify) {
1934 ret = -ENOMEM;
1935 goto fail;
1936 }
1937
1938 priv->cec_glue.parent = dev;
1939 priv->cec_glue.data = priv;
1940 priv->cec_glue.init = tda998x_cec_hook_init;
1941 priv->cec_glue.exit = tda998x_cec_hook_exit;
1942 priv->cec_glue.open = tda998x_cec_hook_open;
1943 priv->cec_glue.release = tda998x_cec_hook_release;
1944
1945 /*
1946 * Some TDA998x are actually two I2C devices merged onto one piece
1947 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1948 * with a slightly modified TDA9950 CEC device. The CEC device
1949 * is at the TDA9950 address, with the address pins strapped across
1950 * to the TDA998x address pins. Hence, it always has the same
1951 * offset.
1952 */
1953 memset(&cec_info, 0, sizeof(cec_info));
1954 strscpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1955 cec_info.addr = priv->cec_addr;
1956 cec_info.platform_data = &priv->cec_glue;
1957 cec_info.irq = client->irq;
1958
1959 priv->cec = i2c_new_client_device(client->adapter, &cec_info);
1960 if (IS_ERR(priv->cec)) {
1961 ret = PTR_ERR(priv->cec);
1962 goto fail;
1963 }
1964
1965 /* enable EDID read irq: */
1966 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1967
1968 if (np) {
1969 /* get the device tree parameters */
1970 ret = of_property_read_u32(np, "video-ports", &video);
1971 if (ret == 0) {
1972 priv->vip_cntrl_0 = video >> 16;
1973 priv->vip_cntrl_1 = video >> 8;
1974 priv->vip_cntrl_2 = video;
1975 }
1976
1977 ret = tda998x_get_audio_ports(priv, np);
1978 if (ret)
1979 goto fail;
1980
1981 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] ||
1982 priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1983 tda998x_audio_codec_init(priv, &client->dev);
1984 } else if (dev->platform_data) {
1985 ret = tda998x_set_config(priv, dev->platform_data);
1986 if (ret)
1987 goto fail;
1988 }
1989
1990 priv->bridge.funcs = &tda998x_bridge_funcs;
1991#ifdef CONFIG_OF
1992 priv->bridge.of_node = dev->of_node;
1993#endif
1994
1995 drm_bridge_add(&priv->bridge);
1996
1997 return 0;
1998
1999fail:
2000 tda998x_destroy(dev);
2001err_irq:
2002 return ret;
2003}
2004
2005/* DRM encoder functions */
2006
2007static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
2008{
2009 struct tda998x_priv *priv = dev_get_drvdata(dev);
2010 u32 crtcs = 0;
2011 int ret;
2012
2013 if (dev->of_node)
2014 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
2015
2016 /* If no CRTCs were found, fall back to our old behaviour */
2017 if (crtcs == 0) {
2018 dev_warn(dev, "Falling back to first CRTC\n");
2019 crtcs = 1 << 0;
2020 }
2021
2022 priv->encoder.possible_crtcs = crtcs;
2023
2024 ret = drm_simple_encoder_init(drm, &priv->encoder,
2025 DRM_MODE_ENCODER_TMDS);
2026 if (ret)
2027 goto err_encoder;
2028
2029 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL, 0);
2030 if (ret)
2031 goto err_bridge;
2032
2033 return 0;
2034
2035err_bridge:
2036 drm_encoder_cleanup(&priv->encoder);
2037err_encoder:
2038 return ret;
2039}
2040
2041static int tda998x_bind(struct device *dev, struct device *master, void *data)
2042{
2043 struct drm_device *drm = data;
2044
2045 return tda998x_encoder_init(dev, drm);
2046}
2047
2048static void tda998x_unbind(struct device *dev, struct device *master,
2049 void *data)
2050{
2051 struct tda998x_priv *priv = dev_get_drvdata(dev);
2052
2053 drm_encoder_cleanup(&priv->encoder);
2054}
2055
2056static const struct component_ops tda998x_ops = {
2057 .bind = tda998x_bind,
2058 .unbind = tda998x_unbind,
2059};
2060
2061static int
2062tda998x_probe(struct i2c_client *client)
2063{
2064 int ret;
2065
2066 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2067 dev_warn(&client->dev, "adapter does not support I2C\n");
2068 return -EIO;
2069 }
2070
2071 ret = tda998x_create(&client->dev);
2072 if (ret)
2073 return ret;
2074
2075 ret = component_add(&client->dev, &tda998x_ops);
2076 if (ret)
2077 tda998x_destroy(&client->dev);
2078 return ret;
2079}
2080
2081static void tda998x_remove(struct i2c_client *client)
2082{
2083 component_del(&client->dev, &tda998x_ops);
2084 tda998x_destroy(&client->dev);
2085}
2086
2087#ifdef CONFIG_OF
2088static const struct of_device_id tda998x_dt_ids[] = {
2089 { .compatible = "nxp,tda998x", },
2090 { }
2091};
2092MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
2093#endif
2094
2095static const struct i2c_device_id tda998x_ids[] = {
2096 { "tda998x", 0 },
2097 { }
2098};
2099MODULE_DEVICE_TABLE(i2c, tda998x_ids);
2100
2101static struct i2c_driver tda998x_driver = {
2102 .probe = tda998x_probe,
2103 .remove = tda998x_remove,
2104 .driver = {
2105 .name = "tda998x",
2106 .of_match_table = of_match_ptr(tda998x_dt_ids),
2107 },
2108 .id_table = tda998x_ids,
2109};
2110
2111module_i2c_driver(tda998x_driver);
2112
2113MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
2114MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
2115MODULE_LICENSE("GPL");