1/*
  2 * Copyright 2014 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 */
 22
 23#ifndef KFD_DBGDEV_H_
 24#define KFD_DBGDEV_H_
 25
 26enum {
 27	SQ_CMD_VMID_OFFSET = 28,
 28	ADDRESS_WATCH_CNTL_OFFSET = 24
 29};
 30
 31enum {
 32	PRIV_QUEUE_SYNC_TIME_MS = 200
 33};
 34
 35/* CONTEXT reg space definition */
 36enum {
 37	CONTEXT_REG_BASE = 0xA000,
 38	CONTEXT_REG_END = 0xA400,
 39	CONTEXT_REG_SIZE = CONTEXT_REG_END - CONTEXT_REG_BASE
 40};
 41
 42/* USER CONFIG reg space definition */
 43enum {
 44	USERCONFIG_REG_BASE = 0xC000,
 45	USERCONFIG_REG_END = 0x10000,
 46	USERCONFIG_REG_SIZE = USERCONFIG_REG_END - USERCONFIG_REG_BASE
 47};
 48
 49/* CONFIG reg space definition */
 50enum {
 51	AMD_CONFIG_REG_BASE = 0x2000,	/* in dwords */
 52	AMD_CONFIG_REG_END = 0x2B00,
 53	AMD_CONFIG_REG_SIZE = AMD_CONFIG_REG_END - AMD_CONFIG_REG_BASE
 54};
 55
 56/* SH reg space definition */
 57enum {
 58	SH_REG_BASE = 0x2C00,
 59	SH_REG_END = 0x3000,
 60	SH_REG_SIZE = SH_REG_END - SH_REG_BASE
 61};
 62
 63enum SQ_IND_CMD_CMD {
 64	SQ_IND_CMD_CMD_NULL = 0x00000000,
 65	SQ_IND_CMD_CMD_HALT = 0x00000001,
 66	SQ_IND_CMD_CMD_RESUME = 0x00000002,
 67	SQ_IND_CMD_CMD_KILL = 0x00000003,
 68	SQ_IND_CMD_CMD_DEBUG = 0x00000004,
 69	SQ_IND_CMD_CMD_TRAP = 0x00000005,
 70};
 71
 72enum SQ_IND_CMD_MODE {
 73	SQ_IND_CMD_MODE_SINGLE = 0x00000000,
 74	SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
 75	SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
 76	SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
 77	SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
 78};
 79
 80union SQ_IND_INDEX_BITS {
 81	struct {
 82		uint32_t wave_id:4;
 83		uint32_t simd_id:2;
 84		uint32_t thread_id:6;
 85		 uint32_t:1;
 86		uint32_t force_read:1;
 87		uint32_t read_timeout:1;
 88		uint32_t unindexed:1;
 89		uint32_t index:16;
 90
 91	} bitfields, bits;
 92	uint32_t u32All;
 93	signed int i32All;
 94	float f32All;
 95};
 96
 97union SQ_IND_CMD_BITS {
 98	struct {
 99		uint32_t data:32;
100	} bitfields, bits;
101	uint32_t u32All;
102	signed int i32All;
103	float f32All;
104};
105
106union SQ_CMD_BITS {
107	struct {
108		uint32_t cmd:3;
109		 uint32_t:1;
110		uint32_t mode:3;
111		uint32_t check_vmid:1;
112		uint32_t trap_id:3;
113		 uint32_t:5;
114		uint32_t wave_id:4;
115		uint32_t simd_id:2;
116		 uint32_t:2;
117		uint32_t queue_id:3;
118		 uint32_t:1;
119		uint32_t vm_id:4;
120	} bitfields, bits;
121	uint32_t u32All;
122	signed int i32All;
123	float f32All;
124};
125
126union SQ_IND_DATA_BITS {
127	struct {
128		uint32_t data:32;
129	} bitfields, bits;
130	uint32_t u32All;
131	signed int i32All;
132	float f32All;
133};
134
135union GRBM_GFX_INDEX_BITS {
136	struct {
137		uint32_t instance_index:8;
138		uint32_t sh_index:8;
139		uint32_t se_index:8;
140		 uint32_t:5;
141		uint32_t sh_broadcast_writes:1;
142		uint32_t instance_broadcast_writes:1;
143		uint32_t se_broadcast_writes:1;
144	} bitfields, bits;
145	uint32_t u32All;
146	signed int i32All;
147	float f32All;
148};
149
150union TCP_WATCH_ADDR_H_BITS {
151	struct {
152		uint32_t addr:16;
153		 uint32_t:16;
154
155	} bitfields, bits;
156	uint32_t u32All;
157	signed int i32All;
158	float f32All;
159};
160
161union TCP_WATCH_ADDR_L_BITS {
162	struct {
163		uint32_t:6;
164		uint32_t addr:26;
165	} bitfields, bits;
166	uint32_t u32All;
167	signed int i32All;
168	float f32All;
169};
170
171enum {
172	QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */
173	QUEUESTATE__ACTIVE_COMPLETION_PENDING,
174	QUEUESTATE__ACTIVE
175};
176
177union ULARGE_INTEGER {
178	struct {
179		uint32_t low_part;
180		uint32_t high_part;
181	} u;
182	unsigned long long quad_part;
183};
184
185
186#define KFD_CIK_VMID_START_OFFSET (8)
187#define KFD_CIK_VMID_END_OFFSET (KFD_CIK_VMID_START_OFFSET + (8))
188
189
190void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
191			enum DBGDEV_TYPE type);
192
193#endif	/* KFD_DBGDEV_H_ */