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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/device.h>
24#include <linux/export.h>
25#include <linux/err.h>
26#include <linux/fs.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/uaccess.h>
30#include <linux/compat.h>
31#include <uapi/linux/kfd_ioctl.h>
32#include <linux/time.h>
33#include <linux/mm.h>
34#include <linux/mman.h>
35#include <asm/processor.h>
36#include "kfd_priv.h"
37#include "kfd_device_queue_manager.h"
38#include "kfd_dbgmgr.h"
39
40static long kfd_ioctl(struct file *, unsigned int, unsigned long);
41static int kfd_open(struct inode *, struct file *);
42static int kfd_mmap(struct file *, struct vm_area_struct *);
43
44static const char kfd_dev_name[] = "kfd";
45
46static const struct file_operations kfd_fops = {
47 .owner = THIS_MODULE,
48 .unlocked_ioctl = kfd_ioctl,
49 .compat_ioctl = kfd_ioctl,
50 .open = kfd_open,
51 .mmap = kfd_mmap,
52};
53
54static int kfd_char_dev_major = -1;
55static struct class *kfd_class;
56struct device *kfd_device;
57
58int kfd_chardev_init(void)
59{
60 int err = 0;
61
62 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
63 err = kfd_char_dev_major;
64 if (err < 0)
65 goto err_register_chrdev;
66
67 kfd_class = class_create(THIS_MODULE, kfd_dev_name);
68 err = PTR_ERR(kfd_class);
69 if (IS_ERR(kfd_class))
70 goto err_class_create;
71
72 kfd_device = device_create(kfd_class, NULL,
73 MKDEV(kfd_char_dev_major, 0),
74 NULL, kfd_dev_name);
75 err = PTR_ERR(kfd_device);
76 if (IS_ERR(kfd_device))
77 goto err_device_create;
78
79 return 0;
80
81err_device_create:
82 class_destroy(kfd_class);
83err_class_create:
84 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
85err_register_chrdev:
86 return err;
87}
88
89void kfd_chardev_exit(void)
90{
91 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
92 class_destroy(kfd_class);
93 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
94}
95
96struct device *kfd_chardev(void)
97{
98 return kfd_device;
99}
100
101
102static int kfd_open(struct inode *inode, struct file *filep)
103{
104 struct kfd_process *process;
105 bool is_32bit_user_mode;
106
107 if (iminor(inode) != 0)
108 return -ENODEV;
109
110 is_32bit_user_mode = in_compat_syscall();
111
112 if (is_32bit_user_mode == true) {
113 dev_warn(kfd_device,
114 "Process %d (32-bit) failed to open /dev/kfd\n"
115 "32-bit processes are not supported by amdkfd\n",
116 current->pid);
117 return -EPERM;
118 }
119
120 process = kfd_create_process(current);
121 if (IS_ERR(process))
122 return PTR_ERR(process);
123
124 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
125 process->pasid, process->is_32bit_user_mode);
126
127 return 0;
128}
129
130static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
131 void *data)
132{
133 struct kfd_ioctl_get_version_args *args = data;
134 int err = 0;
135
136 args->major_version = KFD_IOCTL_MAJOR_VERSION;
137 args->minor_version = KFD_IOCTL_MINOR_VERSION;
138
139 return err;
140}
141
142static int set_queue_properties_from_user(struct queue_properties *q_properties,
143 struct kfd_ioctl_create_queue_args *args)
144{
145 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
146 pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
147 return -EINVAL;
148 }
149
150 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
151 pr_err("kfd: queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
152 return -EINVAL;
153 }
154
155 if ((args->ring_base_address) &&
156 (!access_ok(VERIFY_WRITE,
157 (const void __user *) args->ring_base_address,
158 sizeof(uint64_t)))) {
159 pr_err("kfd: can't access ring base address\n");
160 return -EFAULT;
161 }
162
163 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
164 pr_err("kfd: ring size must be a power of 2 or 0\n");
165 return -EINVAL;
166 }
167
168 if (!access_ok(VERIFY_WRITE,
169 (const void __user *) args->read_pointer_address,
170 sizeof(uint32_t))) {
171 pr_err("kfd: can't access read pointer\n");
172 return -EFAULT;
173 }
174
175 if (!access_ok(VERIFY_WRITE,
176 (const void __user *) args->write_pointer_address,
177 sizeof(uint32_t))) {
178 pr_err("kfd: can't access write pointer\n");
179 return -EFAULT;
180 }
181
182 if (args->eop_buffer_address &&
183 !access_ok(VERIFY_WRITE,
184 (const void __user *) args->eop_buffer_address,
185 sizeof(uint32_t))) {
186 pr_debug("kfd: can't access eop buffer");
187 return -EFAULT;
188 }
189
190 if (args->ctx_save_restore_address &&
191 !access_ok(VERIFY_WRITE,
192 (const void __user *) args->ctx_save_restore_address,
193 sizeof(uint32_t))) {
194 pr_debug("kfd: can't access ctx save restore buffer");
195 return -EFAULT;
196 }
197
198 q_properties->is_interop = false;
199 q_properties->queue_percent = args->queue_percentage;
200 q_properties->priority = args->queue_priority;
201 q_properties->queue_address = args->ring_base_address;
202 q_properties->queue_size = args->ring_size;
203 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
204 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
205 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
206 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
207 q_properties->ctx_save_restore_area_address =
208 args->ctx_save_restore_address;
209 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
210 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
211 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
212 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
213 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
214 q_properties->type = KFD_QUEUE_TYPE_SDMA;
215 else
216 return -ENOTSUPP;
217
218 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
219 q_properties->format = KFD_QUEUE_FORMAT_AQL;
220 else
221 q_properties->format = KFD_QUEUE_FORMAT_PM4;
222
223 pr_debug("Queue Percentage (%d, %d)\n",
224 q_properties->queue_percent, args->queue_percentage);
225
226 pr_debug("Queue Priority (%d, %d)\n",
227 q_properties->priority, args->queue_priority);
228
229 pr_debug("Queue Address (0x%llX, 0x%llX)\n",
230 q_properties->queue_address, args->ring_base_address);
231
232 pr_debug("Queue Size (0x%llX, %u)\n",
233 q_properties->queue_size, args->ring_size);
234
235 pr_debug("Queue r/w Pointers (0x%llX, 0x%llX)\n",
236 (uint64_t) q_properties->read_ptr,
237 (uint64_t) q_properties->write_ptr);
238
239 pr_debug("Queue Format (%d)\n", q_properties->format);
240
241 pr_debug("Queue EOP (0x%llX)\n", q_properties->eop_ring_buffer_address);
242
243 pr_debug("Queue CTX save arex (0x%llX)\n",
244 q_properties->ctx_save_restore_area_address);
245
246 return 0;
247}
248
249static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
250 void *data)
251{
252 struct kfd_ioctl_create_queue_args *args = data;
253 struct kfd_dev *dev;
254 int err = 0;
255 unsigned int queue_id;
256 struct kfd_process_device *pdd;
257 struct queue_properties q_properties;
258
259 memset(&q_properties, 0, sizeof(struct queue_properties));
260
261 pr_debug("kfd: creating queue ioctl\n");
262
263 err = set_queue_properties_from_user(&q_properties, args);
264 if (err)
265 return err;
266
267 pr_debug("kfd: looking for gpu id 0x%x\n", args->gpu_id);
268 dev = kfd_device_by_id(args->gpu_id);
269 if (dev == NULL) {
270 pr_debug("kfd: gpu id 0x%x was not found\n", args->gpu_id);
271 return -EINVAL;
272 }
273
274 mutex_lock(&p->mutex);
275
276 pdd = kfd_bind_process_to_device(dev, p);
277 if (IS_ERR(pdd)) {
278 err = -ESRCH;
279 goto err_bind_process;
280 }
281
282 pr_debug("kfd: creating queue for PASID %d on GPU 0x%x\n",
283 p->pasid,
284 dev->id);
285
286 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties,
287 0, q_properties.type, &queue_id);
288 if (err != 0)
289 goto err_create_queue;
290
291 args->queue_id = queue_id;
292
293
294 /* Return gpu_id as doorbell offset for mmap usage */
295 args->doorbell_offset = (KFD_MMAP_DOORBELL_MASK | args->gpu_id);
296 args->doorbell_offset <<= PAGE_SHIFT;
297
298 mutex_unlock(&p->mutex);
299
300 pr_debug("kfd: queue id %d was created successfully\n", args->queue_id);
301
302 pr_debug("ring buffer address == 0x%016llX\n",
303 args->ring_base_address);
304
305 pr_debug("read ptr address == 0x%016llX\n",
306 args->read_pointer_address);
307
308 pr_debug("write ptr address == 0x%016llX\n",
309 args->write_pointer_address);
310
311 return 0;
312
313err_create_queue:
314err_bind_process:
315 mutex_unlock(&p->mutex);
316 return err;
317}
318
319static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
320 void *data)
321{
322 int retval;
323 struct kfd_ioctl_destroy_queue_args *args = data;
324
325 pr_debug("kfd: destroying queue id %d for PASID %d\n",
326 args->queue_id,
327 p->pasid);
328
329 mutex_lock(&p->mutex);
330
331 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
332
333 mutex_unlock(&p->mutex);
334 return retval;
335}
336
337static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
338 void *data)
339{
340 int retval;
341 struct kfd_ioctl_update_queue_args *args = data;
342 struct queue_properties properties;
343
344 if (args->queue_percentage > KFD_MAX_QUEUE_PERCENTAGE) {
345 pr_err("kfd: queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
346 return -EINVAL;
347 }
348
349 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
350 pr_err("kfd: queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
351 return -EINVAL;
352 }
353
354 if ((args->ring_base_address) &&
355 (!access_ok(VERIFY_WRITE,
356 (const void __user *) args->ring_base_address,
357 sizeof(uint64_t)))) {
358 pr_err("kfd: can't access ring base address\n");
359 return -EFAULT;
360 }
361
362 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
363 pr_err("kfd: ring size must be a power of 2 or 0\n");
364 return -EINVAL;
365 }
366
367 properties.queue_address = args->ring_base_address;
368 properties.queue_size = args->ring_size;
369 properties.queue_percent = args->queue_percentage;
370 properties.priority = args->queue_priority;
371
372 pr_debug("kfd: updating queue id %d for PASID %d\n",
373 args->queue_id, p->pasid);
374
375 mutex_lock(&p->mutex);
376
377 retval = pqm_update_queue(&p->pqm, args->queue_id, &properties);
378
379 mutex_unlock(&p->mutex);
380
381 return retval;
382}
383
384static int kfd_ioctl_set_memory_policy(struct file *filep,
385 struct kfd_process *p, void *data)
386{
387 struct kfd_ioctl_set_memory_policy_args *args = data;
388 struct kfd_dev *dev;
389 int err = 0;
390 struct kfd_process_device *pdd;
391 enum cache_policy default_policy, alternate_policy;
392
393 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
394 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
395 return -EINVAL;
396 }
397
398 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
399 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
400 return -EINVAL;
401 }
402
403 dev = kfd_device_by_id(args->gpu_id);
404 if (dev == NULL)
405 return -EINVAL;
406
407 mutex_lock(&p->mutex);
408
409 pdd = kfd_bind_process_to_device(dev, p);
410 if (IS_ERR(pdd)) {
411 err = -ESRCH;
412 goto out;
413 }
414
415 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
416 ? cache_policy_coherent : cache_policy_noncoherent;
417
418 alternate_policy =
419 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
420 ? cache_policy_coherent : cache_policy_noncoherent;
421
422 if (!dev->dqm->ops.set_cache_memory_policy(dev->dqm,
423 &pdd->qpd,
424 default_policy,
425 alternate_policy,
426 (void __user *)args->alternate_aperture_base,
427 args->alternate_aperture_size))
428 err = -EINVAL;
429
430out:
431 mutex_unlock(&p->mutex);
432
433 return err;
434}
435
436static int kfd_ioctl_dbg_register(struct file *filep,
437 struct kfd_process *p, void *data)
438{
439 struct kfd_ioctl_dbg_register_args *args = data;
440 struct kfd_dev *dev;
441 struct kfd_dbgmgr *dbgmgr_ptr;
442 struct kfd_process_device *pdd;
443 bool create_ok;
444 long status = 0;
445
446 dev = kfd_device_by_id(args->gpu_id);
447 if (dev == NULL)
448 return -EINVAL;
449
450 if (dev->device_info->asic_family == CHIP_CARRIZO) {
451 pr_debug("kfd_ioctl_dbg_register not supported on CZ\n");
452 return -EINVAL;
453 }
454
455 mutex_lock(kfd_get_dbgmgr_mutex());
456 mutex_lock(&p->mutex);
457
458 /*
459 * make sure that we have pdd, if this the first queue created for
460 * this process
461 */
462 pdd = kfd_bind_process_to_device(dev, p);
463 if (IS_ERR(pdd)) {
464 mutex_unlock(&p->mutex);
465 mutex_unlock(kfd_get_dbgmgr_mutex());
466 return PTR_ERR(pdd);
467 }
468
469 if (dev->dbgmgr == NULL) {
470 /* In case of a legal call, we have no dbgmgr yet */
471 create_ok = kfd_dbgmgr_create(&dbgmgr_ptr, dev);
472 if (create_ok) {
473 status = kfd_dbgmgr_register(dbgmgr_ptr, p);
474 if (status != 0)
475 kfd_dbgmgr_destroy(dbgmgr_ptr);
476 else
477 dev->dbgmgr = dbgmgr_ptr;
478 }
479 } else {
480 pr_debug("debugger already registered\n");
481 status = -EINVAL;
482 }
483
484 mutex_unlock(&p->mutex);
485 mutex_unlock(kfd_get_dbgmgr_mutex());
486
487 return status;
488}
489
490static int kfd_ioctl_dbg_unrgesiter(struct file *filep,
491 struct kfd_process *p, void *data)
492{
493 struct kfd_ioctl_dbg_unregister_args *args = data;
494 struct kfd_dev *dev;
495 long status;
496
497 dev = kfd_device_by_id(args->gpu_id);
498 if (dev == NULL)
499 return -EINVAL;
500
501 if (dev->device_info->asic_family == CHIP_CARRIZO) {
502 pr_debug("kfd_ioctl_dbg_unrgesiter not supported on CZ\n");
503 return -EINVAL;
504 }
505
506 mutex_lock(kfd_get_dbgmgr_mutex());
507
508 status = kfd_dbgmgr_unregister(dev->dbgmgr, p);
509 if (status == 0) {
510 kfd_dbgmgr_destroy(dev->dbgmgr);
511 dev->dbgmgr = NULL;
512 }
513
514 mutex_unlock(kfd_get_dbgmgr_mutex());
515
516 return status;
517}
518
519/*
520 * Parse and generate variable size data structure for address watch.
521 * Total size of the buffer and # watch points is limited in order
522 * to prevent kernel abuse. (no bearing to the much smaller HW limitation
523 * which is enforced by dbgdev module)
524 * please also note that the watch address itself are not "copied from user",
525 * since it be set into the HW in user mode values.
526 *
527 */
528static int kfd_ioctl_dbg_address_watch(struct file *filep,
529 struct kfd_process *p, void *data)
530{
531 struct kfd_ioctl_dbg_address_watch_args *args = data;
532 struct kfd_dev *dev;
533 struct dbg_address_watch_info aw_info;
534 unsigned char *args_buff;
535 long status;
536 void __user *cmd_from_user;
537 uint64_t watch_mask_value = 0;
538 unsigned int args_idx = 0;
539
540 memset((void *) &aw_info, 0, sizeof(struct dbg_address_watch_info));
541
542 dev = kfd_device_by_id(args->gpu_id);
543 if (dev == NULL)
544 return -EINVAL;
545
546 if (dev->device_info->asic_family == CHIP_CARRIZO) {
547 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
548 return -EINVAL;
549 }
550
551 cmd_from_user = (void __user *) args->content_ptr;
552
553 /* Validate arguments */
554
555 if ((args->buf_size_in_bytes > MAX_ALLOWED_AW_BUFF_SIZE) ||
556 (args->buf_size_in_bytes <= sizeof(*args) + sizeof(int) * 2) ||
557 (cmd_from_user == NULL))
558 return -EINVAL;
559
560 /* this is the actual buffer to work with */
561 args_buff = memdup_user(cmd_from_user,
562 args->buf_size_in_bytes - sizeof(*args));
563 if (IS_ERR(args_buff))
564 return PTR_ERR(args_buff);
565
566 aw_info.process = p;
567
568 aw_info.num_watch_points = *((uint32_t *)(&args_buff[args_idx]));
569 args_idx += sizeof(aw_info.num_watch_points);
570
571 aw_info.watch_mode = (enum HSA_DBG_WATCH_MODE *) &args_buff[args_idx];
572 args_idx += sizeof(enum HSA_DBG_WATCH_MODE) * aw_info.num_watch_points;
573
574 /*
575 * set watch address base pointer to point on the array base
576 * within args_buff
577 */
578 aw_info.watch_address = (uint64_t *) &args_buff[args_idx];
579
580 /* skip over the addresses buffer */
581 args_idx += sizeof(aw_info.watch_address) * aw_info.num_watch_points;
582
583 if (args_idx >= args->buf_size_in_bytes - sizeof(*args)) {
584 kfree(args_buff);
585 return -EINVAL;
586 }
587
588 watch_mask_value = (uint64_t) args_buff[args_idx];
589
590 if (watch_mask_value > 0) {
591 /*
592 * There is an array of masks.
593 * set watch mask base pointer to point on the array base
594 * within args_buff
595 */
596 aw_info.watch_mask = (uint64_t *) &args_buff[args_idx];
597
598 /* skip over the masks buffer */
599 args_idx += sizeof(aw_info.watch_mask) *
600 aw_info.num_watch_points;
601 } else {
602 /* just the NULL mask, set to NULL and skip over it */
603 aw_info.watch_mask = NULL;
604 args_idx += sizeof(aw_info.watch_mask);
605 }
606
607 if (args_idx >= args->buf_size_in_bytes - sizeof(args)) {
608 kfree(args_buff);
609 return -EINVAL;
610 }
611
612 /* Currently HSA Event is not supported for DBG */
613 aw_info.watch_event = NULL;
614
615 mutex_lock(kfd_get_dbgmgr_mutex());
616
617 status = kfd_dbgmgr_address_watch(dev->dbgmgr, &aw_info);
618
619 mutex_unlock(kfd_get_dbgmgr_mutex());
620
621 kfree(args_buff);
622
623 return status;
624}
625
626/* Parse and generate fixed size data structure for wave control */
627static int kfd_ioctl_dbg_wave_control(struct file *filep,
628 struct kfd_process *p, void *data)
629{
630 struct kfd_ioctl_dbg_wave_control_args *args = data;
631 struct kfd_dev *dev;
632 struct dbg_wave_control_info wac_info;
633 unsigned char *args_buff;
634 uint32_t computed_buff_size;
635 long status;
636 void __user *cmd_from_user;
637 unsigned int args_idx = 0;
638
639 memset((void *) &wac_info, 0, sizeof(struct dbg_wave_control_info));
640
641 /* we use compact form, independent of the packing attribute value */
642 computed_buff_size = sizeof(*args) +
643 sizeof(wac_info.mode) +
644 sizeof(wac_info.operand) +
645 sizeof(wac_info.dbgWave_msg.DbgWaveMsg) +
646 sizeof(wac_info.dbgWave_msg.MemoryVA) +
647 sizeof(wac_info.trapId);
648
649 dev = kfd_device_by_id(args->gpu_id);
650 if (dev == NULL)
651 return -EINVAL;
652
653 if (dev->device_info->asic_family == CHIP_CARRIZO) {
654 pr_debug("kfd_ioctl_dbg_wave_control not supported on CZ\n");
655 return -EINVAL;
656 }
657
658 /* input size must match the computed "compact" size */
659 if (args->buf_size_in_bytes != computed_buff_size) {
660 pr_debug("size mismatch, computed : actual %u : %u\n",
661 args->buf_size_in_bytes, computed_buff_size);
662 return -EINVAL;
663 }
664
665 cmd_from_user = (void __user *) args->content_ptr;
666
667 if (cmd_from_user == NULL)
668 return -EINVAL;
669
670 /* copy the entire buffer from user */
671
672 args_buff = memdup_user(cmd_from_user,
673 args->buf_size_in_bytes - sizeof(*args));
674 if (IS_ERR(args_buff))
675 return PTR_ERR(args_buff);
676
677 /* move ptr to the start of the "pay-load" area */
678 wac_info.process = p;
679
680 wac_info.operand = *((enum HSA_DBG_WAVEOP *)(&args_buff[args_idx]));
681 args_idx += sizeof(wac_info.operand);
682
683 wac_info.mode = *((enum HSA_DBG_WAVEMODE *)(&args_buff[args_idx]));
684 args_idx += sizeof(wac_info.mode);
685
686 wac_info.trapId = *((uint32_t *)(&args_buff[args_idx]));
687 args_idx += sizeof(wac_info.trapId);
688
689 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value =
690 *((uint32_t *)(&args_buff[args_idx]));
691 wac_info.dbgWave_msg.MemoryVA = NULL;
692
693 mutex_lock(kfd_get_dbgmgr_mutex());
694
695 pr_debug("Calling dbg manager process %p, operand %u, mode %u, trapId %u, message %u\n",
696 wac_info.process, wac_info.operand,
697 wac_info.mode, wac_info.trapId,
698 wac_info.dbgWave_msg.DbgWaveMsg.WaveMsgInfoGen2.Value);
699
700 status = kfd_dbgmgr_wave_control(dev->dbgmgr, &wac_info);
701
702 pr_debug("Returned status of dbg manager is %ld\n", status);
703
704 mutex_unlock(kfd_get_dbgmgr_mutex());
705
706 kfree(args_buff);
707
708 return status;
709}
710
711static int kfd_ioctl_get_clock_counters(struct file *filep,
712 struct kfd_process *p, void *data)
713{
714 struct kfd_ioctl_get_clock_counters_args *args = data;
715 struct kfd_dev *dev;
716 struct timespec64 time;
717
718 dev = kfd_device_by_id(args->gpu_id);
719 if (dev == NULL)
720 return -EINVAL;
721
722 /* Reading GPU clock counter from KGD */
723 args->gpu_clock_counter =
724 dev->kfd2kgd->get_gpu_clock_counter(dev->kgd);
725
726 /* No access to rdtsc. Using raw monotonic time */
727 getrawmonotonic64(&time);
728 args->cpu_clock_counter = (uint64_t)timespec64_to_ns(&time);
729
730 get_monotonic_boottime64(&time);
731 args->system_clock_counter = (uint64_t)timespec64_to_ns(&time);
732
733 /* Since the counter is in nano-seconds we use 1GHz frequency */
734 args->system_clock_freq = 1000000000;
735
736 return 0;
737}
738
739
740static int kfd_ioctl_get_process_apertures(struct file *filp,
741 struct kfd_process *p, void *data)
742{
743 struct kfd_ioctl_get_process_apertures_args *args = data;
744 struct kfd_process_device_apertures *pAperture;
745 struct kfd_process_device *pdd;
746
747 dev_dbg(kfd_device, "get apertures for PASID %d", p->pasid);
748
749 args->num_of_nodes = 0;
750
751 mutex_lock(&p->mutex);
752
753 /*if the process-device list isn't empty*/
754 if (kfd_has_process_device_data(p)) {
755 /* Run over all pdd of the process */
756 pdd = kfd_get_first_process_device_data(p);
757 do {
758 pAperture =
759 &args->process_apertures[args->num_of_nodes];
760 pAperture->gpu_id = pdd->dev->id;
761 pAperture->lds_base = pdd->lds_base;
762 pAperture->lds_limit = pdd->lds_limit;
763 pAperture->gpuvm_base = pdd->gpuvm_base;
764 pAperture->gpuvm_limit = pdd->gpuvm_limit;
765 pAperture->scratch_base = pdd->scratch_base;
766 pAperture->scratch_limit = pdd->scratch_limit;
767
768 dev_dbg(kfd_device,
769 "node id %u\n", args->num_of_nodes);
770 dev_dbg(kfd_device,
771 "gpu id %u\n", pdd->dev->id);
772 dev_dbg(kfd_device,
773 "lds_base %llX\n", pdd->lds_base);
774 dev_dbg(kfd_device,
775 "lds_limit %llX\n", pdd->lds_limit);
776 dev_dbg(kfd_device,
777 "gpuvm_base %llX\n", pdd->gpuvm_base);
778 dev_dbg(kfd_device,
779 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
780 dev_dbg(kfd_device,
781 "scratch_base %llX\n", pdd->scratch_base);
782 dev_dbg(kfd_device,
783 "scratch_limit %llX\n", pdd->scratch_limit);
784
785 args->num_of_nodes++;
786 } while ((pdd = kfd_get_next_process_device_data(p, pdd)) != NULL &&
787 (args->num_of_nodes < NUM_OF_SUPPORTED_GPUS));
788 }
789
790 mutex_unlock(&p->mutex);
791
792 return 0;
793}
794
795static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
796 void *data)
797{
798 struct kfd_ioctl_create_event_args *args = data;
799 int err;
800
801 err = kfd_event_create(filp, p, args->event_type,
802 args->auto_reset != 0, args->node_id,
803 &args->event_id, &args->event_trigger_data,
804 &args->event_page_offset,
805 &args->event_slot_index);
806
807 return err;
808}
809
810static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
811 void *data)
812{
813 struct kfd_ioctl_destroy_event_args *args = data;
814
815 return kfd_event_destroy(p, args->event_id);
816}
817
818static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
819 void *data)
820{
821 struct kfd_ioctl_set_event_args *args = data;
822
823 return kfd_set_event(p, args->event_id);
824}
825
826static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
827 void *data)
828{
829 struct kfd_ioctl_reset_event_args *args = data;
830
831 return kfd_reset_event(p, args->event_id);
832}
833
834static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
835 void *data)
836{
837 struct kfd_ioctl_wait_events_args *args = data;
838 enum kfd_event_wait_result wait_result;
839 int err;
840
841 err = kfd_wait_on_events(p, args->num_events,
842 (void __user *)args->events_ptr,
843 (args->wait_for_all != 0),
844 args->timeout, &wait_result);
845
846 args->wait_result = wait_result;
847
848 return err;
849}
850
851#define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
852 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, .cmd_drv = 0, .name = #ioctl}
853
854/** Ioctl table */
855static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
856 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
857 kfd_ioctl_get_version, 0),
858
859 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
860 kfd_ioctl_create_queue, 0),
861
862 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
863 kfd_ioctl_destroy_queue, 0),
864
865 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
866 kfd_ioctl_set_memory_policy, 0),
867
868 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
869 kfd_ioctl_get_clock_counters, 0),
870
871 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
872 kfd_ioctl_get_process_apertures, 0),
873
874 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
875 kfd_ioctl_update_queue, 0),
876
877 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
878 kfd_ioctl_create_event, 0),
879
880 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
881 kfd_ioctl_destroy_event, 0),
882
883 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
884 kfd_ioctl_set_event, 0),
885
886 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
887 kfd_ioctl_reset_event, 0),
888
889 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
890 kfd_ioctl_wait_events, 0),
891
892 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER,
893 kfd_ioctl_dbg_register, 0),
894
895 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER,
896 kfd_ioctl_dbg_unrgesiter, 0),
897
898 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH,
899 kfd_ioctl_dbg_address_watch, 0),
900
901 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL,
902 kfd_ioctl_dbg_wave_control, 0),
903};
904
905#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
906
907static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
908{
909 struct kfd_process *process;
910 amdkfd_ioctl_t *func;
911 const struct amdkfd_ioctl_desc *ioctl = NULL;
912 unsigned int nr = _IOC_NR(cmd);
913 char stack_kdata[128];
914 char *kdata = NULL;
915 unsigned int usize, asize;
916 int retcode = -EINVAL;
917
918 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
919 goto err_i1;
920
921 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
922 u32 amdkfd_size;
923
924 ioctl = &amdkfd_ioctls[nr];
925
926 amdkfd_size = _IOC_SIZE(ioctl->cmd);
927 usize = asize = _IOC_SIZE(cmd);
928 if (amdkfd_size > asize)
929 asize = amdkfd_size;
930
931 cmd = ioctl->cmd;
932 } else
933 goto err_i1;
934
935 dev_dbg(kfd_device, "ioctl cmd 0x%x (#%d), arg 0x%lx\n", cmd, nr, arg);
936
937 process = kfd_get_process(current);
938 if (IS_ERR(process)) {
939 dev_dbg(kfd_device, "no process\n");
940 goto err_i1;
941 }
942
943 /* Do not trust userspace, use our own definition */
944 func = ioctl->func;
945
946 if (unlikely(!func)) {
947 dev_dbg(kfd_device, "no function\n");
948 retcode = -EINVAL;
949 goto err_i1;
950 }
951
952 if (cmd & (IOC_IN | IOC_OUT)) {
953 if (asize <= sizeof(stack_kdata)) {
954 kdata = stack_kdata;
955 } else {
956 kdata = kmalloc(asize, GFP_KERNEL);
957 if (!kdata) {
958 retcode = -ENOMEM;
959 goto err_i1;
960 }
961 }
962 if (asize > usize)
963 memset(kdata + usize, 0, asize - usize);
964 }
965
966 if (cmd & IOC_IN) {
967 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
968 retcode = -EFAULT;
969 goto err_i1;
970 }
971 } else if (cmd & IOC_OUT) {
972 memset(kdata, 0, usize);
973 }
974
975 retcode = func(filep, process, kdata);
976
977 if (cmd & IOC_OUT)
978 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
979 retcode = -EFAULT;
980
981err_i1:
982 if (!ioctl)
983 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
984 task_pid_nr(current), cmd, nr);
985
986 if (kdata != stack_kdata)
987 kfree(kdata);
988
989 if (retcode)
990 dev_dbg(kfd_device, "ret = %d\n", retcode);
991
992 return retcode;
993}
994
995static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
996{
997 struct kfd_process *process;
998
999 process = kfd_get_process(current);
1000 if (IS_ERR(process))
1001 return PTR_ERR(process);
1002
1003 if ((vma->vm_pgoff & KFD_MMAP_DOORBELL_MASK) ==
1004 KFD_MMAP_DOORBELL_MASK) {
1005 vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_DOORBELL_MASK;
1006 return kfd_doorbell_mmap(process, vma);
1007 } else if ((vma->vm_pgoff & KFD_MMAP_EVENTS_MASK) ==
1008 KFD_MMAP_EVENTS_MASK) {
1009 vma->vm_pgoff = vma->vm_pgoff ^ KFD_MMAP_EVENTS_MASK;
1010 return kfd_event_mmap(process, vma);
1011 }
1012
1013 return -EFAULT;
1014}
1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24#include <linux/device.h>
25#include <linux/export.h>
26#include <linux/err.h>
27#include <linux/fs.h>
28#include <linux/file.h>
29#include <linux/sched.h>
30#include <linux/slab.h>
31#include <linux/uaccess.h>
32#include <linux/compat.h>
33#include <uapi/linux/kfd_ioctl.h>
34#include <linux/time.h>
35#include <linux/mm.h>
36#include <linux/mman.h>
37#include <linux/ptrace.h>
38#include <linux/dma-buf.h>
39#include <linux/fdtable.h>
40#include <linux/processor.h>
41#include "kfd_priv.h"
42#include "kfd_device_queue_manager.h"
43#include "kfd_svm.h"
44#include "amdgpu_amdkfd.h"
45#include "kfd_smi_events.h"
46#include "amdgpu_dma_buf.h"
47#include "kfd_debug.h"
48
49static long kfd_ioctl(struct file *, unsigned int, unsigned long);
50static int kfd_open(struct inode *, struct file *);
51static int kfd_release(struct inode *, struct file *);
52static int kfd_mmap(struct file *, struct vm_area_struct *);
53
54static const char kfd_dev_name[] = "kfd";
55
56static const struct file_operations kfd_fops = {
57 .owner = THIS_MODULE,
58 .unlocked_ioctl = kfd_ioctl,
59 .compat_ioctl = compat_ptr_ioctl,
60 .open = kfd_open,
61 .release = kfd_release,
62 .mmap = kfd_mmap,
63};
64
65static int kfd_char_dev_major = -1;
66static struct class *kfd_class;
67struct device *kfd_device;
68
69static inline struct kfd_process_device *kfd_lock_pdd_by_id(struct kfd_process *p, __u32 gpu_id)
70{
71 struct kfd_process_device *pdd;
72
73 mutex_lock(&p->mutex);
74 pdd = kfd_process_device_data_by_id(p, gpu_id);
75
76 if (pdd)
77 return pdd;
78
79 mutex_unlock(&p->mutex);
80 return NULL;
81}
82
83static inline void kfd_unlock_pdd(struct kfd_process_device *pdd)
84{
85 mutex_unlock(&pdd->process->mutex);
86}
87
88int kfd_chardev_init(void)
89{
90 int err = 0;
91
92 kfd_char_dev_major = register_chrdev(0, kfd_dev_name, &kfd_fops);
93 err = kfd_char_dev_major;
94 if (err < 0)
95 goto err_register_chrdev;
96
97 kfd_class = class_create(kfd_dev_name);
98 err = PTR_ERR(kfd_class);
99 if (IS_ERR(kfd_class))
100 goto err_class_create;
101
102 kfd_device = device_create(kfd_class, NULL,
103 MKDEV(kfd_char_dev_major, 0),
104 NULL, kfd_dev_name);
105 err = PTR_ERR(kfd_device);
106 if (IS_ERR(kfd_device))
107 goto err_device_create;
108
109 return 0;
110
111err_device_create:
112 class_destroy(kfd_class);
113err_class_create:
114 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
115err_register_chrdev:
116 return err;
117}
118
119void kfd_chardev_exit(void)
120{
121 device_destroy(kfd_class, MKDEV(kfd_char_dev_major, 0));
122 class_destroy(kfd_class);
123 unregister_chrdev(kfd_char_dev_major, kfd_dev_name);
124 kfd_device = NULL;
125}
126
127
128static int kfd_open(struct inode *inode, struct file *filep)
129{
130 struct kfd_process *process;
131 bool is_32bit_user_mode;
132
133 if (iminor(inode) != 0)
134 return -ENODEV;
135
136 is_32bit_user_mode = in_compat_syscall();
137
138 if (is_32bit_user_mode) {
139 dev_warn(kfd_device,
140 "Process %d (32-bit) failed to open /dev/kfd\n"
141 "32-bit processes are not supported by amdkfd\n",
142 current->pid);
143 return -EPERM;
144 }
145
146 process = kfd_create_process(current);
147 if (IS_ERR(process))
148 return PTR_ERR(process);
149
150 if (kfd_process_init_cwsr_apu(process, filep)) {
151 kfd_unref_process(process);
152 return -EFAULT;
153 }
154
155 /* filep now owns the reference returned by kfd_create_process */
156 filep->private_data = process;
157
158 dev_dbg(kfd_device, "process %d opened, compat mode (32 bit) - %d\n",
159 process->pasid, process->is_32bit_user_mode);
160
161 return 0;
162}
163
164static int kfd_release(struct inode *inode, struct file *filep)
165{
166 struct kfd_process *process = filep->private_data;
167
168 if (process)
169 kfd_unref_process(process);
170
171 return 0;
172}
173
174static int kfd_ioctl_get_version(struct file *filep, struct kfd_process *p,
175 void *data)
176{
177 struct kfd_ioctl_get_version_args *args = data;
178
179 args->major_version = KFD_IOCTL_MAJOR_VERSION;
180 args->minor_version = KFD_IOCTL_MINOR_VERSION;
181
182 return 0;
183}
184
185static int set_queue_properties_from_user(struct queue_properties *q_properties,
186 struct kfd_ioctl_create_queue_args *args)
187{
188 /*
189 * Repurpose queue percentage to accommodate new features:
190 * bit 0-7: queue percentage
191 * bit 8-15: pm4_target_xcc
192 */
193 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
194 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
195 return -EINVAL;
196 }
197
198 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
199 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
200 return -EINVAL;
201 }
202
203 if ((args->ring_base_address) &&
204 (!access_ok((const void __user *) args->ring_base_address,
205 sizeof(uint64_t)))) {
206 pr_err("Can't access ring base address\n");
207 return -EFAULT;
208 }
209
210 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
211 pr_err("Ring size must be a power of 2 or 0\n");
212 return -EINVAL;
213 }
214
215 if (!access_ok((const void __user *) args->read_pointer_address,
216 sizeof(uint32_t))) {
217 pr_err("Can't access read pointer\n");
218 return -EFAULT;
219 }
220
221 if (!access_ok((const void __user *) args->write_pointer_address,
222 sizeof(uint32_t))) {
223 pr_err("Can't access write pointer\n");
224 return -EFAULT;
225 }
226
227 if (args->eop_buffer_address &&
228 !access_ok((const void __user *) args->eop_buffer_address,
229 sizeof(uint32_t))) {
230 pr_debug("Can't access eop buffer");
231 return -EFAULT;
232 }
233
234 if (args->ctx_save_restore_address &&
235 !access_ok((const void __user *) args->ctx_save_restore_address,
236 sizeof(uint32_t))) {
237 pr_debug("Can't access ctx save restore buffer");
238 return -EFAULT;
239 }
240
241 q_properties->is_interop = false;
242 q_properties->is_gws = false;
243 q_properties->queue_percent = args->queue_percentage & 0xFF;
244 /* bit 8-15 are repurposed to be PM4 target XCC */
245 q_properties->pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
246 q_properties->priority = args->queue_priority;
247 q_properties->queue_address = args->ring_base_address;
248 q_properties->queue_size = args->ring_size;
249 q_properties->read_ptr = (uint32_t *) args->read_pointer_address;
250 q_properties->write_ptr = (uint32_t *) args->write_pointer_address;
251 q_properties->eop_ring_buffer_address = args->eop_buffer_address;
252 q_properties->eop_ring_buffer_size = args->eop_buffer_size;
253 q_properties->ctx_save_restore_area_address =
254 args->ctx_save_restore_address;
255 q_properties->ctx_save_restore_area_size = args->ctx_save_restore_size;
256 q_properties->ctl_stack_size = args->ctl_stack_size;
257 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE ||
258 args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
259 q_properties->type = KFD_QUEUE_TYPE_COMPUTE;
260 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA)
261 q_properties->type = KFD_QUEUE_TYPE_SDMA;
262 else if (args->queue_type == KFD_IOC_QUEUE_TYPE_SDMA_XGMI)
263 q_properties->type = KFD_QUEUE_TYPE_SDMA_XGMI;
264 else
265 return -ENOTSUPP;
266
267 if (args->queue_type == KFD_IOC_QUEUE_TYPE_COMPUTE_AQL)
268 q_properties->format = KFD_QUEUE_FORMAT_AQL;
269 else
270 q_properties->format = KFD_QUEUE_FORMAT_PM4;
271
272 pr_debug("Queue Percentage: %d, %d\n",
273 q_properties->queue_percent, args->queue_percentage);
274
275 pr_debug("Queue Priority: %d, %d\n",
276 q_properties->priority, args->queue_priority);
277
278 pr_debug("Queue Address: 0x%llX, 0x%llX\n",
279 q_properties->queue_address, args->ring_base_address);
280
281 pr_debug("Queue Size: 0x%llX, %u\n",
282 q_properties->queue_size, args->ring_size);
283
284 pr_debug("Queue r/w Pointers: %px, %px\n",
285 q_properties->read_ptr,
286 q_properties->write_ptr);
287
288 pr_debug("Queue Format: %d\n", q_properties->format);
289
290 pr_debug("Queue EOP: 0x%llX\n", q_properties->eop_ring_buffer_address);
291
292 pr_debug("Queue CTX save area: 0x%llX\n",
293 q_properties->ctx_save_restore_area_address);
294
295 return 0;
296}
297
298static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p,
299 void *data)
300{
301 struct kfd_ioctl_create_queue_args *args = data;
302 struct kfd_node *dev;
303 int err = 0;
304 unsigned int queue_id;
305 struct kfd_process_device *pdd;
306 struct queue_properties q_properties;
307 uint32_t doorbell_offset_in_process = 0;
308 struct amdgpu_bo *wptr_bo = NULL;
309
310 memset(&q_properties, 0, sizeof(struct queue_properties));
311
312 pr_debug("Creating queue ioctl\n");
313
314 err = set_queue_properties_from_user(&q_properties, args);
315 if (err)
316 return err;
317
318 pr_debug("Looking for gpu id 0x%x\n", args->gpu_id);
319
320 mutex_lock(&p->mutex);
321
322 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
323 if (!pdd) {
324 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
325 err = -EINVAL;
326 goto err_pdd;
327 }
328 dev = pdd->dev;
329
330 pdd = kfd_bind_process_to_device(dev, p);
331 if (IS_ERR(pdd)) {
332 err = -ESRCH;
333 goto err_bind_process;
334 }
335
336 if (!pdd->qpd.proc_doorbells) {
337 err = kfd_alloc_process_doorbells(dev->kfd, pdd);
338 if (err) {
339 pr_debug("failed to allocate process doorbells\n");
340 goto err_bind_process;
341 }
342 }
343
344 /* Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
345 * on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
346 */
347 if (dev->kfd->shared_resources.enable_mes &&
348 ((dev->adev->mes.sched_version & AMDGPU_MES_API_VERSION_MASK)
349 >> AMDGPU_MES_API_VERSION_SHIFT) >= 2) {
350 struct amdgpu_bo_va_mapping *wptr_mapping;
351 struct amdgpu_vm *wptr_vm;
352
353 wptr_vm = drm_priv_to_vm(pdd->drm_priv);
354 err = amdgpu_bo_reserve(wptr_vm->root.bo, false);
355 if (err)
356 goto err_wptr_map_gart;
357
358 wptr_mapping = amdgpu_vm_bo_lookup_mapping(
359 wptr_vm, args->write_pointer_address >> PAGE_SHIFT);
360 amdgpu_bo_unreserve(wptr_vm->root.bo);
361 if (!wptr_mapping) {
362 pr_err("Failed to lookup wptr bo\n");
363 err = -EINVAL;
364 goto err_wptr_map_gart;
365 }
366
367 wptr_bo = wptr_mapping->bo_va->base.bo;
368 if (wptr_bo->tbo.base.size > PAGE_SIZE) {
369 pr_err("Requested GART mapping for wptr bo larger than one page\n");
370 err = -EINVAL;
371 goto err_wptr_map_gart;
372 }
373
374 err = amdgpu_amdkfd_map_gtt_bo_to_gart(dev->adev, wptr_bo);
375 if (err) {
376 pr_err("Failed to map wptr bo to GART\n");
377 goto err_wptr_map_gart;
378 }
379 }
380
381 pr_debug("Creating queue for PASID 0x%x on gpu 0x%x\n",
382 p->pasid,
383 dev->id);
384
385 err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, wptr_bo,
386 NULL, NULL, NULL, &doorbell_offset_in_process);
387 if (err != 0)
388 goto err_create_queue;
389
390 args->queue_id = queue_id;
391
392
393 /* Return gpu_id as doorbell offset for mmap usage */
394 args->doorbell_offset = KFD_MMAP_TYPE_DOORBELL;
395 args->doorbell_offset |= KFD_MMAP_GPU_ID(args->gpu_id);
396 if (KFD_IS_SOC15(dev))
397 /* On SOC15 ASICs, include the doorbell offset within the
398 * process doorbell frame, which is 2 pages.
399 */
400 args->doorbell_offset |= doorbell_offset_in_process;
401
402 mutex_unlock(&p->mutex);
403
404 pr_debug("Queue id %d was created successfully\n", args->queue_id);
405
406 pr_debug("Ring buffer address == 0x%016llX\n",
407 args->ring_base_address);
408
409 pr_debug("Read ptr address == 0x%016llX\n",
410 args->read_pointer_address);
411
412 pr_debug("Write ptr address == 0x%016llX\n",
413 args->write_pointer_address);
414
415 kfd_dbg_ev_raise(KFD_EC_MASK(EC_QUEUE_NEW), p, dev, queue_id, false, NULL, 0);
416 return 0;
417
418err_create_queue:
419 if (wptr_bo)
420 amdgpu_amdkfd_free_gtt_mem(dev->adev, wptr_bo);
421err_wptr_map_gart:
422err_bind_process:
423err_pdd:
424 mutex_unlock(&p->mutex);
425 return err;
426}
427
428static int kfd_ioctl_destroy_queue(struct file *filp, struct kfd_process *p,
429 void *data)
430{
431 int retval;
432 struct kfd_ioctl_destroy_queue_args *args = data;
433
434 pr_debug("Destroying queue id %d for pasid 0x%x\n",
435 args->queue_id,
436 p->pasid);
437
438 mutex_lock(&p->mutex);
439
440 retval = pqm_destroy_queue(&p->pqm, args->queue_id);
441
442 mutex_unlock(&p->mutex);
443 return retval;
444}
445
446static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p,
447 void *data)
448{
449 int retval;
450 struct kfd_ioctl_update_queue_args *args = data;
451 struct queue_properties properties;
452
453 /*
454 * Repurpose queue percentage to accommodate new features:
455 * bit 0-7: queue percentage
456 * bit 8-15: pm4_target_xcc
457 */
458 if ((args->queue_percentage & 0xFF) > KFD_MAX_QUEUE_PERCENTAGE) {
459 pr_err("Queue percentage must be between 0 to KFD_MAX_QUEUE_PERCENTAGE\n");
460 return -EINVAL;
461 }
462
463 if (args->queue_priority > KFD_MAX_QUEUE_PRIORITY) {
464 pr_err("Queue priority must be between 0 to KFD_MAX_QUEUE_PRIORITY\n");
465 return -EINVAL;
466 }
467
468 if ((args->ring_base_address) &&
469 (!access_ok((const void __user *) args->ring_base_address,
470 sizeof(uint64_t)))) {
471 pr_err("Can't access ring base address\n");
472 return -EFAULT;
473 }
474
475 if (!is_power_of_2(args->ring_size) && (args->ring_size != 0)) {
476 pr_err("Ring size must be a power of 2 or 0\n");
477 return -EINVAL;
478 }
479
480 properties.queue_address = args->ring_base_address;
481 properties.queue_size = args->ring_size;
482 properties.queue_percent = args->queue_percentage & 0xFF;
483 /* bit 8-15 are repurposed to be PM4 target XCC */
484 properties.pm4_target_xcc = (args->queue_percentage >> 8) & 0xFF;
485 properties.priority = args->queue_priority;
486
487 pr_debug("Updating queue id %d for pasid 0x%x\n",
488 args->queue_id, p->pasid);
489
490 mutex_lock(&p->mutex);
491
492 retval = pqm_update_queue_properties(&p->pqm, args->queue_id, &properties);
493
494 mutex_unlock(&p->mutex);
495
496 return retval;
497}
498
499static int kfd_ioctl_set_cu_mask(struct file *filp, struct kfd_process *p,
500 void *data)
501{
502 int retval;
503 const int max_num_cus = 1024;
504 struct kfd_ioctl_set_cu_mask_args *args = data;
505 struct mqd_update_info minfo = {0};
506 uint32_t __user *cu_mask_ptr = (uint32_t __user *)args->cu_mask_ptr;
507 size_t cu_mask_size = sizeof(uint32_t) * (args->num_cu_mask / 32);
508
509 if ((args->num_cu_mask % 32) != 0) {
510 pr_debug("num_cu_mask 0x%x must be a multiple of 32",
511 args->num_cu_mask);
512 return -EINVAL;
513 }
514
515 minfo.cu_mask.count = args->num_cu_mask;
516 if (minfo.cu_mask.count == 0) {
517 pr_debug("CU mask cannot be 0");
518 return -EINVAL;
519 }
520
521 /* To prevent an unreasonably large CU mask size, set an arbitrary
522 * limit of max_num_cus bits. We can then just drop any CU mask bits
523 * past max_num_cus bits and just use the first max_num_cus bits.
524 */
525 if (minfo.cu_mask.count > max_num_cus) {
526 pr_debug("CU mask cannot be greater than 1024 bits");
527 minfo.cu_mask.count = max_num_cus;
528 cu_mask_size = sizeof(uint32_t) * (max_num_cus/32);
529 }
530
531 minfo.cu_mask.ptr = kzalloc(cu_mask_size, GFP_KERNEL);
532 if (!minfo.cu_mask.ptr)
533 return -ENOMEM;
534
535 retval = copy_from_user(minfo.cu_mask.ptr, cu_mask_ptr, cu_mask_size);
536 if (retval) {
537 pr_debug("Could not copy CU mask from userspace");
538 retval = -EFAULT;
539 goto out;
540 }
541
542 mutex_lock(&p->mutex);
543
544 retval = pqm_update_mqd(&p->pqm, args->queue_id, &minfo);
545
546 mutex_unlock(&p->mutex);
547
548out:
549 kfree(minfo.cu_mask.ptr);
550 return retval;
551}
552
553static int kfd_ioctl_get_queue_wave_state(struct file *filep,
554 struct kfd_process *p, void *data)
555{
556 struct kfd_ioctl_get_queue_wave_state_args *args = data;
557 int r;
558
559 mutex_lock(&p->mutex);
560
561 r = pqm_get_wave_state(&p->pqm, args->queue_id,
562 (void __user *)args->ctl_stack_address,
563 &args->ctl_stack_used_size,
564 &args->save_area_used_size);
565
566 mutex_unlock(&p->mutex);
567
568 return r;
569}
570
571static int kfd_ioctl_set_memory_policy(struct file *filep,
572 struct kfd_process *p, void *data)
573{
574 struct kfd_ioctl_set_memory_policy_args *args = data;
575 int err = 0;
576 struct kfd_process_device *pdd;
577 enum cache_policy default_policy, alternate_policy;
578
579 if (args->default_policy != KFD_IOC_CACHE_POLICY_COHERENT
580 && args->default_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
581 return -EINVAL;
582 }
583
584 if (args->alternate_policy != KFD_IOC_CACHE_POLICY_COHERENT
585 && args->alternate_policy != KFD_IOC_CACHE_POLICY_NONCOHERENT) {
586 return -EINVAL;
587 }
588
589 mutex_lock(&p->mutex);
590 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
591 if (!pdd) {
592 pr_debug("Could not find gpu id 0x%x\n", args->gpu_id);
593 err = -EINVAL;
594 goto err_pdd;
595 }
596
597 pdd = kfd_bind_process_to_device(pdd->dev, p);
598 if (IS_ERR(pdd)) {
599 err = -ESRCH;
600 goto out;
601 }
602
603 default_policy = (args->default_policy == KFD_IOC_CACHE_POLICY_COHERENT)
604 ? cache_policy_coherent : cache_policy_noncoherent;
605
606 alternate_policy =
607 (args->alternate_policy == KFD_IOC_CACHE_POLICY_COHERENT)
608 ? cache_policy_coherent : cache_policy_noncoherent;
609
610 if (!pdd->dev->dqm->ops.set_cache_memory_policy(pdd->dev->dqm,
611 &pdd->qpd,
612 default_policy,
613 alternate_policy,
614 (void __user *)args->alternate_aperture_base,
615 args->alternate_aperture_size))
616 err = -EINVAL;
617
618out:
619err_pdd:
620 mutex_unlock(&p->mutex);
621
622 return err;
623}
624
625static int kfd_ioctl_set_trap_handler(struct file *filep,
626 struct kfd_process *p, void *data)
627{
628 struct kfd_ioctl_set_trap_handler_args *args = data;
629 int err = 0;
630 struct kfd_process_device *pdd;
631
632 mutex_lock(&p->mutex);
633
634 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
635 if (!pdd) {
636 err = -EINVAL;
637 goto err_pdd;
638 }
639
640 pdd = kfd_bind_process_to_device(pdd->dev, p);
641 if (IS_ERR(pdd)) {
642 err = -ESRCH;
643 goto out;
644 }
645
646 kfd_process_set_trap_handler(&pdd->qpd, args->tba_addr, args->tma_addr);
647
648out:
649err_pdd:
650 mutex_unlock(&p->mutex);
651
652 return err;
653}
654
655static int kfd_ioctl_dbg_register(struct file *filep,
656 struct kfd_process *p, void *data)
657{
658 return -EPERM;
659}
660
661static int kfd_ioctl_dbg_unregister(struct file *filep,
662 struct kfd_process *p, void *data)
663{
664 return -EPERM;
665}
666
667static int kfd_ioctl_dbg_address_watch(struct file *filep,
668 struct kfd_process *p, void *data)
669{
670 return -EPERM;
671}
672
673/* Parse and generate fixed size data structure for wave control */
674static int kfd_ioctl_dbg_wave_control(struct file *filep,
675 struct kfd_process *p, void *data)
676{
677 return -EPERM;
678}
679
680static int kfd_ioctl_get_clock_counters(struct file *filep,
681 struct kfd_process *p, void *data)
682{
683 struct kfd_ioctl_get_clock_counters_args *args = data;
684 struct kfd_process_device *pdd;
685
686 mutex_lock(&p->mutex);
687 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
688 mutex_unlock(&p->mutex);
689 if (pdd)
690 /* Reading GPU clock counter from KGD */
691 args->gpu_clock_counter = amdgpu_amdkfd_get_gpu_clock_counter(pdd->dev->adev);
692 else
693 /* Node without GPU resource */
694 args->gpu_clock_counter = 0;
695
696 /* No access to rdtsc. Using raw monotonic time */
697 args->cpu_clock_counter = ktime_get_raw_ns();
698 args->system_clock_counter = ktime_get_boottime_ns();
699
700 /* Since the counter is in nano-seconds we use 1GHz frequency */
701 args->system_clock_freq = 1000000000;
702
703 return 0;
704}
705
706
707static int kfd_ioctl_get_process_apertures(struct file *filp,
708 struct kfd_process *p, void *data)
709{
710 struct kfd_ioctl_get_process_apertures_args *args = data;
711 struct kfd_process_device_apertures *pAperture;
712 int i;
713
714 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
715
716 args->num_of_nodes = 0;
717
718 mutex_lock(&p->mutex);
719 /* Run over all pdd of the process */
720 for (i = 0; i < p->n_pdds; i++) {
721 struct kfd_process_device *pdd = p->pdds[i];
722
723 pAperture =
724 &args->process_apertures[args->num_of_nodes];
725 pAperture->gpu_id = pdd->dev->id;
726 pAperture->lds_base = pdd->lds_base;
727 pAperture->lds_limit = pdd->lds_limit;
728 pAperture->gpuvm_base = pdd->gpuvm_base;
729 pAperture->gpuvm_limit = pdd->gpuvm_limit;
730 pAperture->scratch_base = pdd->scratch_base;
731 pAperture->scratch_limit = pdd->scratch_limit;
732
733 dev_dbg(kfd_device,
734 "node id %u\n", args->num_of_nodes);
735 dev_dbg(kfd_device,
736 "gpu id %u\n", pdd->dev->id);
737 dev_dbg(kfd_device,
738 "lds_base %llX\n", pdd->lds_base);
739 dev_dbg(kfd_device,
740 "lds_limit %llX\n", pdd->lds_limit);
741 dev_dbg(kfd_device,
742 "gpuvm_base %llX\n", pdd->gpuvm_base);
743 dev_dbg(kfd_device,
744 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
745 dev_dbg(kfd_device,
746 "scratch_base %llX\n", pdd->scratch_base);
747 dev_dbg(kfd_device,
748 "scratch_limit %llX\n", pdd->scratch_limit);
749
750 if (++args->num_of_nodes >= NUM_OF_SUPPORTED_GPUS)
751 break;
752 }
753 mutex_unlock(&p->mutex);
754
755 return 0;
756}
757
758static int kfd_ioctl_get_process_apertures_new(struct file *filp,
759 struct kfd_process *p, void *data)
760{
761 struct kfd_ioctl_get_process_apertures_new_args *args = data;
762 struct kfd_process_device_apertures *pa;
763 int ret;
764 int i;
765
766 dev_dbg(kfd_device, "get apertures for PASID 0x%x", p->pasid);
767
768 if (args->num_of_nodes == 0) {
769 /* Return number of nodes, so that user space can alloacate
770 * sufficient memory
771 */
772 mutex_lock(&p->mutex);
773 args->num_of_nodes = p->n_pdds;
774 goto out_unlock;
775 }
776
777 /* Fill in process-aperture information for all available
778 * nodes, but not more than args->num_of_nodes as that is
779 * the amount of memory allocated by user
780 */
781 pa = kzalloc((sizeof(struct kfd_process_device_apertures) *
782 args->num_of_nodes), GFP_KERNEL);
783 if (!pa)
784 return -ENOMEM;
785
786 mutex_lock(&p->mutex);
787
788 if (!p->n_pdds) {
789 args->num_of_nodes = 0;
790 kfree(pa);
791 goto out_unlock;
792 }
793
794 /* Run over all pdd of the process */
795 for (i = 0; i < min(p->n_pdds, args->num_of_nodes); i++) {
796 struct kfd_process_device *pdd = p->pdds[i];
797
798 pa[i].gpu_id = pdd->dev->id;
799 pa[i].lds_base = pdd->lds_base;
800 pa[i].lds_limit = pdd->lds_limit;
801 pa[i].gpuvm_base = pdd->gpuvm_base;
802 pa[i].gpuvm_limit = pdd->gpuvm_limit;
803 pa[i].scratch_base = pdd->scratch_base;
804 pa[i].scratch_limit = pdd->scratch_limit;
805
806 dev_dbg(kfd_device,
807 "gpu id %u\n", pdd->dev->id);
808 dev_dbg(kfd_device,
809 "lds_base %llX\n", pdd->lds_base);
810 dev_dbg(kfd_device,
811 "lds_limit %llX\n", pdd->lds_limit);
812 dev_dbg(kfd_device,
813 "gpuvm_base %llX\n", pdd->gpuvm_base);
814 dev_dbg(kfd_device,
815 "gpuvm_limit %llX\n", pdd->gpuvm_limit);
816 dev_dbg(kfd_device,
817 "scratch_base %llX\n", pdd->scratch_base);
818 dev_dbg(kfd_device,
819 "scratch_limit %llX\n", pdd->scratch_limit);
820 }
821 mutex_unlock(&p->mutex);
822
823 args->num_of_nodes = i;
824 ret = copy_to_user(
825 (void __user *)args->kfd_process_device_apertures_ptr,
826 pa,
827 (i * sizeof(struct kfd_process_device_apertures)));
828 kfree(pa);
829 return ret ? -EFAULT : 0;
830
831out_unlock:
832 mutex_unlock(&p->mutex);
833 return 0;
834}
835
836static int kfd_ioctl_create_event(struct file *filp, struct kfd_process *p,
837 void *data)
838{
839 struct kfd_ioctl_create_event_args *args = data;
840 int err;
841
842 /* For dGPUs the event page is allocated in user mode. The
843 * handle is passed to KFD with the first call to this IOCTL
844 * through the event_page_offset field.
845 */
846 if (args->event_page_offset) {
847 mutex_lock(&p->mutex);
848 err = kfd_kmap_event_page(p, args->event_page_offset);
849 mutex_unlock(&p->mutex);
850 if (err)
851 return err;
852 }
853
854 err = kfd_event_create(filp, p, args->event_type,
855 args->auto_reset != 0, args->node_id,
856 &args->event_id, &args->event_trigger_data,
857 &args->event_page_offset,
858 &args->event_slot_index);
859
860 pr_debug("Created event (id:0x%08x) (%s)\n", args->event_id, __func__);
861 return err;
862}
863
864static int kfd_ioctl_destroy_event(struct file *filp, struct kfd_process *p,
865 void *data)
866{
867 struct kfd_ioctl_destroy_event_args *args = data;
868
869 return kfd_event_destroy(p, args->event_id);
870}
871
872static int kfd_ioctl_set_event(struct file *filp, struct kfd_process *p,
873 void *data)
874{
875 struct kfd_ioctl_set_event_args *args = data;
876
877 return kfd_set_event(p, args->event_id);
878}
879
880static int kfd_ioctl_reset_event(struct file *filp, struct kfd_process *p,
881 void *data)
882{
883 struct kfd_ioctl_reset_event_args *args = data;
884
885 return kfd_reset_event(p, args->event_id);
886}
887
888static int kfd_ioctl_wait_events(struct file *filp, struct kfd_process *p,
889 void *data)
890{
891 struct kfd_ioctl_wait_events_args *args = data;
892
893 return kfd_wait_on_events(p, args->num_events,
894 (void __user *)args->events_ptr,
895 (args->wait_for_all != 0),
896 &args->timeout, &args->wait_result);
897}
898static int kfd_ioctl_set_scratch_backing_va(struct file *filep,
899 struct kfd_process *p, void *data)
900{
901 struct kfd_ioctl_set_scratch_backing_va_args *args = data;
902 struct kfd_process_device *pdd;
903 struct kfd_node *dev;
904 long err;
905
906 mutex_lock(&p->mutex);
907 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
908 if (!pdd) {
909 err = -EINVAL;
910 goto err_pdd;
911 }
912 dev = pdd->dev;
913
914 pdd = kfd_bind_process_to_device(dev, p);
915 if (IS_ERR(pdd)) {
916 err = PTR_ERR(pdd);
917 goto bind_process_to_device_fail;
918 }
919
920 pdd->qpd.sh_hidden_private_base = args->va_addr;
921
922 mutex_unlock(&p->mutex);
923
924 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS &&
925 pdd->qpd.vmid != 0 && dev->kfd2kgd->set_scratch_backing_va)
926 dev->kfd2kgd->set_scratch_backing_va(
927 dev->adev, args->va_addr, pdd->qpd.vmid);
928
929 return 0;
930
931bind_process_to_device_fail:
932err_pdd:
933 mutex_unlock(&p->mutex);
934 return err;
935}
936
937static int kfd_ioctl_get_tile_config(struct file *filep,
938 struct kfd_process *p, void *data)
939{
940 struct kfd_ioctl_get_tile_config_args *args = data;
941 struct kfd_process_device *pdd;
942 struct tile_config config;
943 int err = 0;
944
945 mutex_lock(&p->mutex);
946 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
947 mutex_unlock(&p->mutex);
948 if (!pdd)
949 return -EINVAL;
950
951 amdgpu_amdkfd_get_tile_config(pdd->dev->adev, &config);
952
953 args->gb_addr_config = config.gb_addr_config;
954 args->num_banks = config.num_banks;
955 args->num_ranks = config.num_ranks;
956
957 if (args->num_tile_configs > config.num_tile_configs)
958 args->num_tile_configs = config.num_tile_configs;
959 err = copy_to_user((void __user *)args->tile_config_ptr,
960 config.tile_config_ptr,
961 args->num_tile_configs * sizeof(uint32_t));
962 if (err) {
963 args->num_tile_configs = 0;
964 return -EFAULT;
965 }
966
967 if (args->num_macro_tile_configs > config.num_macro_tile_configs)
968 args->num_macro_tile_configs =
969 config.num_macro_tile_configs;
970 err = copy_to_user((void __user *)args->macro_tile_config_ptr,
971 config.macro_tile_config_ptr,
972 args->num_macro_tile_configs * sizeof(uint32_t));
973 if (err) {
974 args->num_macro_tile_configs = 0;
975 return -EFAULT;
976 }
977
978 return 0;
979}
980
981static int kfd_ioctl_acquire_vm(struct file *filep, struct kfd_process *p,
982 void *data)
983{
984 struct kfd_ioctl_acquire_vm_args *args = data;
985 struct kfd_process_device *pdd;
986 struct file *drm_file;
987 int ret;
988
989 drm_file = fget(args->drm_fd);
990 if (!drm_file)
991 return -EINVAL;
992
993 mutex_lock(&p->mutex);
994 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
995 if (!pdd) {
996 ret = -EINVAL;
997 goto err_pdd;
998 }
999
1000 if (pdd->drm_file) {
1001 ret = pdd->drm_file == drm_file ? 0 : -EBUSY;
1002 goto err_drm_file;
1003 }
1004
1005 ret = kfd_process_device_init_vm(pdd, drm_file);
1006 if (ret)
1007 goto err_unlock;
1008
1009 /* On success, the PDD keeps the drm_file reference */
1010 mutex_unlock(&p->mutex);
1011
1012 return 0;
1013
1014err_unlock:
1015err_pdd:
1016err_drm_file:
1017 mutex_unlock(&p->mutex);
1018 fput(drm_file);
1019 return ret;
1020}
1021
1022bool kfd_dev_is_large_bar(struct kfd_node *dev)
1023{
1024 if (dev->kfd->adev->debug_largebar) {
1025 pr_debug("Simulate large-bar allocation on non large-bar machine\n");
1026 return true;
1027 }
1028
1029 if (dev->local_mem_info.local_mem_size_private == 0 &&
1030 dev->local_mem_info.local_mem_size_public > 0)
1031 return true;
1032
1033 if (dev->local_mem_info.local_mem_size_public == 0 &&
1034 dev->kfd->adev->gmc.is_app_apu) {
1035 pr_debug("APP APU, Consider like a large bar system\n");
1036 return true;
1037 }
1038
1039 return false;
1040}
1041
1042static int kfd_ioctl_get_available_memory(struct file *filep,
1043 struct kfd_process *p, void *data)
1044{
1045 struct kfd_ioctl_get_available_memory_args *args = data;
1046 struct kfd_process_device *pdd = kfd_lock_pdd_by_id(p, args->gpu_id);
1047
1048 if (!pdd)
1049 return -EINVAL;
1050 args->available = amdgpu_amdkfd_get_available_memory(pdd->dev->adev,
1051 pdd->dev->node_id);
1052 kfd_unlock_pdd(pdd);
1053 return 0;
1054}
1055
1056static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep,
1057 struct kfd_process *p, void *data)
1058{
1059 struct kfd_ioctl_alloc_memory_of_gpu_args *args = data;
1060 struct kfd_process_device *pdd;
1061 void *mem;
1062 struct kfd_node *dev;
1063 int idr_handle;
1064 long err;
1065 uint64_t offset = args->mmap_offset;
1066 uint32_t flags = args->flags;
1067
1068 if (args->size == 0)
1069 return -EINVAL;
1070
1071#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1072 /* Flush pending deferred work to avoid racing with deferred actions
1073 * from previous memory map changes (e.g. munmap).
1074 */
1075 svm_range_list_lock_and_flush_work(&p->svms, current->mm);
1076 mutex_lock(&p->svms.lock);
1077 mmap_write_unlock(current->mm);
1078 if (interval_tree_iter_first(&p->svms.objects,
1079 args->va_addr >> PAGE_SHIFT,
1080 (args->va_addr + args->size - 1) >> PAGE_SHIFT)) {
1081 pr_err("Address: 0x%llx already allocated by SVM\n",
1082 args->va_addr);
1083 mutex_unlock(&p->svms.lock);
1084 return -EADDRINUSE;
1085 }
1086
1087 /* When register user buffer check if it has been registered by svm by
1088 * buffer cpu virtual address.
1089 */
1090 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) &&
1091 interval_tree_iter_first(&p->svms.objects,
1092 args->mmap_offset >> PAGE_SHIFT,
1093 (args->mmap_offset + args->size - 1) >> PAGE_SHIFT)) {
1094 pr_err("User Buffer Address: 0x%llx already allocated by SVM\n",
1095 args->mmap_offset);
1096 mutex_unlock(&p->svms.lock);
1097 return -EADDRINUSE;
1098 }
1099
1100 mutex_unlock(&p->svms.lock);
1101#endif
1102 mutex_lock(&p->mutex);
1103 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1104 if (!pdd) {
1105 err = -EINVAL;
1106 goto err_pdd;
1107 }
1108
1109 dev = pdd->dev;
1110
1111 if ((flags & KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC) &&
1112 (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) &&
1113 !kfd_dev_is_large_bar(dev)) {
1114 pr_err("Alloc host visible vram on small bar is not allowed\n");
1115 err = -EINVAL;
1116 goto err_large_bar;
1117 }
1118
1119 pdd = kfd_bind_process_to_device(dev, p);
1120 if (IS_ERR(pdd)) {
1121 err = PTR_ERR(pdd);
1122 goto err_unlock;
1123 }
1124
1125 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
1126 if (args->size != kfd_doorbell_process_slice(dev->kfd)) {
1127 err = -EINVAL;
1128 goto err_unlock;
1129 }
1130 offset = kfd_get_process_doorbells(pdd);
1131 if (!offset) {
1132 err = -ENOMEM;
1133 goto err_unlock;
1134 }
1135 } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
1136 if (args->size != PAGE_SIZE) {
1137 err = -EINVAL;
1138 goto err_unlock;
1139 }
1140 offset = dev->adev->rmmio_remap.bus_addr;
1141 if (!offset) {
1142 err = -ENOMEM;
1143 goto err_unlock;
1144 }
1145 }
1146
1147 err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
1148 dev->adev, args->va_addr, args->size,
1149 pdd->drm_priv, (struct kgd_mem **) &mem, &offset,
1150 flags, false);
1151
1152 if (err)
1153 goto err_unlock;
1154
1155 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1156 if (idr_handle < 0) {
1157 err = -EFAULT;
1158 goto err_free;
1159 }
1160
1161 /* Update the VRAM usage count */
1162 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
1163 uint64_t size = args->size;
1164
1165 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM)
1166 size >>= 1;
1167 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + PAGE_ALIGN(size));
1168 }
1169
1170 mutex_unlock(&p->mutex);
1171
1172 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1173 args->mmap_offset = offset;
1174
1175 /* MMIO is mapped through kfd device
1176 * Generate a kfd mmap offset
1177 */
1178 if (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1179 args->mmap_offset = KFD_MMAP_TYPE_MMIO
1180 | KFD_MMAP_GPU_ID(args->gpu_id);
1181
1182 return 0;
1183
1184err_free:
1185 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem,
1186 pdd->drm_priv, NULL);
1187err_unlock:
1188err_pdd:
1189err_large_bar:
1190 mutex_unlock(&p->mutex);
1191 return err;
1192}
1193
1194static int kfd_ioctl_free_memory_of_gpu(struct file *filep,
1195 struct kfd_process *p, void *data)
1196{
1197 struct kfd_ioctl_free_memory_of_gpu_args *args = data;
1198 struct kfd_process_device *pdd;
1199 void *mem;
1200 int ret;
1201 uint64_t size = 0;
1202
1203 mutex_lock(&p->mutex);
1204 /*
1205 * Safeguard to prevent user space from freeing signal BO.
1206 * It will be freed at process termination.
1207 */
1208 if (p->signal_handle && (p->signal_handle == args->handle)) {
1209 pr_err("Free signal BO is not allowed\n");
1210 ret = -EPERM;
1211 goto err_unlock;
1212 }
1213
1214 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1215 if (!pdd) {
1216 pr_err("Process device data doesn't exist\n");
1217 ret = -EINVAL;
1218 goto err_pdd;
1219 }
1220
1221 mem = kfd_process_device_translate_handle(
1222 pdd, GET_IDR_HANDLE(args->handle));
1223 if (!mem) {
1224 ret = -EINVAL;
1225 goto err_unlock;
1226 }
1227
1228 ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev,
1229 (struct kgd_mem *)mem, pdd->drm_priv, &size);
1230
1231 /* If freeing the buffer failed, leave the handle in place for
1232 * clean-up during process tear-down.
1233 */
1234 if (!ret)
1235 kfd_process_device_remove_obj_handle(
1236 pdd, GET_IDR_HANDLE(args->handle));
1237
1238 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size);
1239
1240err_unlock:
1241err_pdd:
1242 mutex_unlock(&p->mutex);
1243 return ret;
1244}
1245
1246static int kfd_ioctl_map_memory_to_gpu(struct file *filep,
1247 struct kfd_process *p, void *data)
1248{
1249 struct kfd_ioctl_map_memory_to_gpu_args *args = data;
1250 struct kfd_process_device *pdd, *peer_pdd;
1251 void *mem;
1252 struct kfd_node *dev;
1253 long err = 0;
1254 int i;
1255 uint32_t *devices_arr = NULL;
1256
1257 if (!args->n_devices) {
1258 pr_debug("Device IDs array empty\n");
1259 return -EINVAL;
1260 }
1261 if (args->n_success > args->n_devices) {
1262 pr_debug("n_success exceeds n_devices\n");
1263 return -EINVAL;
1264 }
1265
1266 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1267 GFP_KERNEL);
1268 if (!devices_arr)
1269 return -ENOMEM;
1270
1271 err = copy_from_user(devices_arr,
1272 (void __user *)args->device_ids_array_ptr,
1273 args->n_devices * sizeof(*devices_arr));
1274 if (err != 0) {
1275 err = -EFAULT;
1276 goto copy_from_user_failed;
1277 }
1278
1279 mutex_lock(&p->mutex);
1280 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1281 if (!pdd) {
1282 err = -EINVAL;
1283 goto get_process_device_data_failed;
1284 }
1285 dev = pdd->dev;
1286
1287 pdd = kfd_bind_process_to_device(dev, p);
1288 if (IS_ERR(pdd)) {
1289 err = PTR_ERR(pdd);
1290 goto bind_process_to_device_failed;
1291 }
1292
1293 mem = kfd_process_device_translate_handle(pdd,
1294 GET_IDR_HANDLE(args->handle));
1295 if (!mem) {
1296 err = -ENOMEM;
1297 goto get_mem_obj_from_handle_failed;
1298 }
1299
1300 for (i = args->n_success; i < args->n_devices; i++) {
1301 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1302 if (!peer_pdd) {
1303 pr_debug("Getting device by id failed for 0x%x\n",
1304 devices_arr[i]);
1305 err = -EINVAL;
1306 goto get_mem_obj_from_handle_failed;
1307 }
1308
1309 peer_pdd = kfd_bind_process_to_device(peer_pdd->dev, p);
1310 if (IS_ERR(peer_pdd)) {
1311 err = PTR_ERR(peer_pdd);
1312 goto get_mem_obj_from_handle_failed;
1313 }
1314
1315 err = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
1316 peer_pdd->dev->adev, (struct kgd_mem *)mem,
1317 peer_pdd->drm_priv);
1318 if (err) {
1319 struct pci_dev *pdev = peer_pdd->dev->adev->pdev;
1320
1321 dev_err(dev->adev->dev,
1322 "Failed to map peer:%04x:%02x:%02x.%d mem_domain:%d\n",
1323 pci_domain_nr(pdev->bus),
1324 pdev->bus->number,
1325 PCI_SLOT(pdev->devfn),
1326 PCI_FUNC(pdev->devfn),
1327 ((struct kgd_mem *)mem)->domain);
1328 goto map_memory_to_gpu_failed;
1329 }
1330 args->n_success = i+1;
1331 }
1332
1333 err = amdgpu_amdkfd_gpuvm_sync_memory(dev->adev, (struct kgd_mem *) mem, true);
1334 if (err) {
1335 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1336 goto sync_memory_failed;
1337 }
1338
1339 mutex_unlock(&p->mutex);
1340
1341 /* Flush TLBs after waiting for the page table updates to complete */
1342 for (i = 0; i < args->n_devices; i++) {
1343 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1344 if (WARN_ON_ONCE(!peer_pdd))
1345 continue;
1346 kfd_flush_tlb(peer_pdd, TLB_FLUSH_LEGACY);
1347 }
1348 kfree(devices_arr);
1349
1350 return err;
1351
1352get_process_device_data_failed:
1353bind_process_to_device_failed:
1354get_mem_obj_from_handle_failed:
1355map_memory_to_gpu_failed:
1356sync_memory_failed:
1357 mutex_unlock(&p->mutex);
1358copy_from_user_failed:
1359 kfree(devices_arr);
1360
1361 return err;
1362}
1363
1364static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep,
1365 struct kfd_process *p, void *data)
1366{
1367 struct kfd_ioctl_unmap_memory_from_gpu_args *args = data;
1368 struct kfd_process_device *pdd, *peer_pdd;
1369 void *mem;
1370 long err = 0;
1371 uint32_t *devices_arr = NULL, i;
1372 bool flush_tlb;
1373
1374 if (!args->n_devices) {
1375 pr_debug("Device IDs array empty\n");
1376 return -EINVAL;
1377 }
1378 if (args->n_success > args->n_devices) {
1379 pr_debug("n_success exceeds n_devices\n");
1380 return -EINVAL;
1381 }
1382
1383 devices_arr = kmalloc_array(args->n_devices, sizeof(*devices_arr),
1384 GFP_KERNEL);
1385 if (!devices_arr)
1386 return -ENOMEM;
1387
1388 err = copy_from_user(devices_arr,
1389 (void __user *)args->device_ids_array_ptr,
1390 args->n_devices * sizeof(*devices_arr));
1391 if (err != 0) {
1392 err = -EFAULT;
1393 goto copy_from_user_failed;
1394 }
1395
1396 mutex_lock(&p->mutex);
1397 pdd = kfd_process_device_data_by_id(p, GET_GPU_ID(args->handle));
1398 if (!pdd) {
1399 err = -EINVAL;
1400 goto bind_process_to_device_failed;
1401 }
1402
1403 mem = kfd_process_device_translate_handle(pdd,
1404 GET_IDR_HANDLE(args->handle));
1405 if (!mem) {
1406 err = -ENOMEM;
1407 goto get_mem_obj_from_handle_failed;
1408 }
1409
1410 for (i = args->n_success; i < args->n_devices; i++) {
1411 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1412 if (!peer_pdd) {
1413 err = -EINVAL;
1414 goto get_mem_obj_from_handle_failed;
1415 }
1416 err = amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
1417 peer_pdd->dev->adev, (struct kgd_mem *)mem, peer_pdd->drm_priv);
1418 if (err) {
1419 pr_err("Failed to unmap from gpu %d/%d\n",
1420 i, args->n_devices);
1421 goto unmap_memory_from_gpu_failed;
1422 }
1423 args->n_success = i+1;
1424 }
1425
1426 flush_tlb = kfd_flush_tlb_after_unmap(pdd->dev->kfd);
1427 if (flush_tlb) {
1428 err = amdgpu_amdkfd_gpuvm_sync_memory(pdd->dev->adev,
1429 (struct kgd_mem *) mem, true);
1430 if (err) {
1431 pr_debug("Sync memory failed, wait interrupted by user signal\n");
1432 goto sync_memory_failed;
1433 }
1434 }
1435
1436 /* Flush TLBs after waiting for the page table updates to complete */
1437 for (i = 0; i < args->n_devices; i++) {
1438 peer_pdd = kfd_process_device_data_by_id(p, devices_arr[i]);
1439 if (WARN_ON_ONCE(!peer_pdd))
1440 continue;
1441 if (flush_tlb)
1442 kfd_flush_tlb(peer_pdd, TLB_FLUSH_HEAVYWEIGHT);
1443
1444 /* Remove dma mapping after tlb flush to avoid IO_PAGE_FAULT */
1445 err = amdgpu_amdkfd_gpuvm_dmaunmap_mem(mem, peer_pdd->drm_priv);
1446 if (err)
1447 goto sync_memory_failed;
1448 }
1449
1450 mutex_unlock(&p->mutex);
1451
1452 kfree(devices_arr);
1453
1454 return 0;
1455
1456bind_process_to_device_failed:
1457get_mem_obj_from_handle_failed:
1458unmap_memory_from_gpu_failed:
1459sync_memory_failed:
1460 mutex_unlock(&p->mutex);
1461copy_from_user_failed:
1462 kfree(devices_arr);
1463 return err;
1464}
1465
1466static int kfd_ioctl_alloc_queue_gws(struct file *filep,
1467 struct kfd_process *p, void *data)
1468{
1469 int retval;
1470 struct kfd_ioctl_alloc_queue_gws_args *args = data;
1471 struct queue *q;
1472 struct kfd_node *dev;
1473
1474 mutex_lock(&p->mutex);
1475 q = pqm_get_user_queue(&p->pqm, args->queue_id);
1476
1477 if (q) {
1478 dev = q->device;
1479 } else {
1480 retval = -EINVAL;
1481 goto out_unlock;
1482 }
1483
1484 if (!dev->gws) {
1485 retval = -ENODEV;
1486 goto out_unlock;
1487 }
1488
1489 if (dev->dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) {
1490 retval = -ENODEV;
1491 goto out_unlock;
1492 }
1493
1494 if (p->debug_trap_enabled && (!kfd_dbg_has_gws_support(dev) ||
1495 kfd_dbg_has_cwsr_workaround(dev))) {
1496 retval = -EBUSY;
1497 goto out_unlock;
1498 }
1499
1500 retval = pqm_set_gws(&p->pqm, args->queue_id, args->num_gws ? dev->gws : NULL);
1501 mutex_unlock(&p->mutex);
1502
1503 args->first_gws = 0;
1504 return retval;
1505
1506out_unlock:
1507 mutex_unlock(&p->mutex);
1508 return retval;
1509}
1510
1511static int kfd_ioctl_get_dmabuf_info(struct file *filep,
1512 struct kfd_process *p, void *data)
1513{
1514 struct kfd_ioctl_get_dmabuf_info_args *args = data;
1515 struct kfd_node *dev = NULL;
1516 struct amdgpu_device *dmabuf_adev;
1517 void *metadata_buffer = NULL;
1518 uint32_t flags;
1519 int8_t xcp_id;
1520 unsigned int i;
1521 int r;
1522
1523 /* Find a KFD GPU device that supports the get_dmabuf_info query */
1524 for (i = 0; kfd_topology_enum_kfd_devices(i, &dev) == 0; i++)
1525 if (dev)
1526 break;
1527 if (!dev)
1528 return -EINVAL;
1529
1530 if (args->metadata_ptr) {
1531 metadata_buffer = kzalloc(args->metadata_size, GFP_KERNEL);
1532 if (!metadata_buffer)
1533 return -ENOMEM;
1534 }
1535
1536 /* Get dmabuf info from KGD */
1537 r = amdgpu_amdkfd_get_dmabuf_info(dev->adev, args->dmabuf_fd,
1538 &dmabuf_adev, &args->size,
1539 metadata_buffer, args->metadata_size,
1540 &args->metadata_size, &flags, &xcp_id);
1541 if (r)
1542 goto exit;
1543
1544 if (xcp_id >= 0)
1545 args->gpu_id = dmabuf_adev->kfd.dev->nodes[xcp_id]->id;
1546 else
1547 args->gpu_id = dmabuf_adev->kfd.dev->nodes[0]->id;
1548 args->flags = flags;
1549
1550 /* Copy metadata buffer to user mode */
1551 if (metadata_buffer) {
1552 r = copy_to_user((void __user *)args->metadata_ptr,
1553 metadata_buffer, args->metadata_size);
1554 if (r != 0)
1555 r = -EFAULT;
1556 }
1557
1558exit:
1559 kfree(metadata_buffer);
1560
1561 return r;
1562}
1563
1564static int kfd_ioctl_import_dmabuf(struct file *filep,
1565 struct kfd_process *p, void *data)
1566{
1567 struct kfd_ioctl_import_dmabuf_args *args = data;
1568 struct kfd_process_device *pdd;
1569 int idr_handle;
1570 uint64_t size;
1571 void *mem;
1572 int r;
1573
1574 mutex_lock(&p->mutex);
1575 pdd = kfd_process_device_data_by_id(p, args->gpu_id);
1576 if (!pdd) {
1577 r = -EINVAL;
1578 goto err_unlock;
1579 }
1580
1581 pdd = kfd_bind_process_to_device(pdd->dev, p);
1582 if (IS_ERR(pdd)) {
1583 r = PTR_ERR(pdd);
1584 goto err_unlock;
1585 }
1586
1587 r = amdgpu_amdkfd_gpuvm_import_dmabuf_fd(pdd->dev->adev, args->dmabuf_fd,
1588 args->va_addr, pdd->drm_priv,
1589 (struct kgd_mem **)&mem, &size,
1590 NULL);
1591 if (r)
1592 goto err_unlock;
1593
1594 idr_handle = kfd_process_device_create_obj_handle(pdd, mem);
1595 if (idr_handle < 0) {
1596 r = -EFAULT;
1597 goto err_free;
1598 }
1599
1600 mutex_unlock(&p->mutex);
1601
1602 args->handle = MAKE_HANDLE(args->gpu_id, idr_handle);
1603
1604 return 0;
1605
1606err_free:
1607 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem,
1608 pdd->drm_priv, NULL);
1609err_unlock:
1610 mutex_unlock(&p->mutex);
1611 return r;
1612}
1613
1614static int kfd_ioctl_export_dmabuf(struct file *filep,
1615 struct kfd_process *p, void *data)
1616{
1617 struct kfd_ioctl_export_dmabuf_args *args = data;
1618 struct kfd_process_device *pdd;
1619 struct dma_buf *dmabuf;
1620 struct kfd_node *dev;
1621 void *mem;
1622 int ret = 0;
1623
1624 dev = kfd_device_by_id(GET_GPU_ID(args->handle));
1625 if (!dev)
1626 return -EINVAL;
1627
1628 mutex_lock(&p->mutex);
1629
1630 pdd = kfd_get_process_device_data(dev, p);
1631 if (!pdd) {
1632 ret = -EINVAL;
1633 goto err_unlock;
1634 }
1635
1636 mem = kfd_process_device_translate_handle(pdd,
1637 GET_IDR_HANDLE(args->handle));
1638 if (!mem) {
1639 ret = -EINVAL;
1640 goto err_unlock;
1641 }
1642
1643 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1644 mutex_unlock(&p->mutex);
1645 if (ret)
1646 goto err_out;
1647
1648 ret = dma_buf_fd(dmabuf, args->flags);
1649 if (ret < 0) {
1650 dma_buf_put(dmabuf);
1651 goto err_out;
1652 }
1653 /* dma_buf_fd assigns the reference count to the fd, no need to
1654 * put the reference here.
1655 */
1656 args->dmabuf_fd = ret;
1657
1658 return 0;
1659
1660err_unlock:
1661 mutex_unlock(&p->mutex);
1662err_out:
1663 return ret;
1664}
1665
1666/* Handle requests for watching SMI events */
1667static int kfd_ioctl_smi_events(struct file *filep,
1668 struct kfd_process *p, void *data)
1669{
1670 struct kfd_ioctl_smi_events_args *args = data;
1671 struct kfd_process_device *pdd;
1672
1673 mutex_lock(&p->mutex);
1674
1675 pdd = kfd_process_device_data_by_id(p, args->gpuid);
1676 mutex_unlock(&p->mutex);
1677 if (!pdd)
1678 return -EINVAL;
1679
1680 return kfd_smi_event_open(pdd->dev, &args->anon_fd);
1681}
1682
1683#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
1684
1685static int kfd_ioctl_set_xnack_mode(struct file *filep,
1686 struct kfd_process *p, void *data)
1687{
1688 struct kfd_ioctl_set_xnack_mode_args *args = data;
1689 int r = 0;
1690
1691 mutex_lock(&p->mutex);
1692 if (args->xnack_enabled >= 0) {
1693 if (!list_empty(&p->pqm.queues)) {
1694 pr_debug("Process has user queues running\n");
1695 r = -EBUSY;
1696 goto out_unlock;
1697 }
1698
1699 if (p->xnack_enabled == args->xnack_enabled)
1700 goto out_unlock;
1701
1702 if (args->xnack_enabled && !kfd_process_xnack_mode(p, true)) {
1703 r = -EPERM;
1704 goto out_unlock;
1705 }
1706
1707 r = svm_range_switch_xnack_reserve_mem(p, args->xnack_enabled);
1708 } else {
1709 args->xnack_enabled = p->xnack_enabled;
1710 }
1711
1712out_unlock:
1713 mutex_unlock(&p->mutex);
1714
1715 return r;
1716}
1717
1718static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1719{
1720 struct kfd_ioctl_svm_args *args = data;
1721 int r = 0;
1722
1723 pr_debug("start 0x%llx size 0x%llx op 0x%x nattr 0x%x\n",
1724 args->start_addr, args->size, args->op, args->nattr);
1725
1726 if ((args->start_addr & ~PAGE_MASK) || (args->size & ~PAGE_MASK))
1727 return -EINVAL;
1728 if (!args->start_addr || !args->size)
1729 return -EINVAL;
1730
1731 r = svm_ioctl(p, args->op, args->start_addr, args->size, args->nattr,
1732 args->attrs);
1733
1734 return r;
1735}
1736#else
1737static int kfd_ioctl_set_xnack_mode(struct file *filep,
1738 struct kfd_process *p, void *data)
1739{
1740 return -EPERM;
1741}
1742static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data)
1743{
1744 return -EPERM;
1745}
1746#endif
1747
1748static int criu_checkpoint_process(struct kfd_process *p,
1749 uint8_t __user *user_priv_data,
1750 uint64_t *priv_offset)
1751{
1752 struct kfd_criu_process_priv_data process_priv;
1753 int ret;
1754
1755 memset(&process_priv, 0, sizeof(process_priv));
1756
1757 process_priv.version = KFD_CRIU_PRIV_VERSION;
1758 /* For CR, we don't consider negative xnack mode which is used for
1759 * querying without changing it, here 0 simply means disabled and 1
1760 * means enabled so retry for finding a valid PTE.
1761 */
1762 process_priv.xnack_mode = p->xnack_enabled ? 1 : 0;
1763
1764 ret = copy_to_user(user_priv_data + *priv_offset,
1765 &process_priv, sizeof(process_priv));
1766
1767 if (ret) {
1768 pr_err("Failed to copy process information to user\n");
1769 ret = -EFAULT;
1770 }
1771
1772 *priv_offset += sizeof(process_priv);
1773 return ret;
1774}
1775
1776static int criu_checkpoint_devices(struct kfd_process *p,
1777 uint32_t num_devices,
1778 uint8_t __user *user_addr,
1779 uint8_t __user *user_priv_data,
1780 uint64_t *priv_offset)
1781{
1782 struct kfd_criu_device_priv_data *device_priv = NULL;
1783 struct kfd_criu_device_bucket *device_buckets = NULL;
1784 int ret = 0, i;
1785
1786 device_buckets = kvzalloc(num_devices * sizeof(*device_buckets), GFP_KERNEL);
1787 if (!device_buckets) {
1788 ret = -ENOMEM;
1789 goto exit;
1790 }
1791
1792 device_priv = kvzalloc(num_devices * sizeof(*device_priv), GFP_KERNEL);
1793 if (!device_priv) {
1794 ret = -ENOMEM;
1795 goto exit;
1796 }
1797
1798 for (i = 0; i < num_devices; i++) {
1799 struct kfd_process_device *pdd = p->pdds[i];
1800
1801 device_buckets[i].user_gpu_id = pdd->user_gpu_id;
1802 device_buckets[i].actual_gpu_id = pdd->dev->id;
1803
1804 /*
1805 * priv_data does not contain useful information for now and is reserved for
1806 * future use, so we do not set its contents.
1807 */
1808 }
1809
1810 ret = copy_to_user(user_addr, device_buckets, num_devices * sizeof(*device_buckets));
1811 if (ret) {
1812 pr_err("Failed to copy device information to user\n");
1813 ret = -EFAULT;
1814 goto exit;
1815 }
1816
1817 ret = copy_to_user(user_priv_data + *priv_offset,
1818 device_priv,
1819 num_devices * sizeof(*device_priv));
1820 if (ret) {
1821 pr_err("Failed to copy device information to user\n");
1822 ret = -EFAULT;
1823 }
1824 *priv_offset += num_devices * sizeof(*device_priv);
1825
1826exit:
1827 kvfree(device_buckets);
1828 kvfree(device_priv);
1829 return ret;
1830}
1831
1832static uint32_t get_process_num_bos(struct kfd_process *p)
1833{
1834 uint32_t num_of_bos = 0;
1835 int i;
1836
1837 /* Run over all PDDs of the process */
1838 for (i = 0; i < p->n_pdds; i++) {
1839 struct kfd_process_device *pdd = p->pdds[i];
1840 void *mem;
1841 int id;
1842
1843 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1844 struct kgd_mem *kgd_mem = (struct kgd_mem *)mem;
1845
1846 if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base)
1847 num_of_bos++;
1848 }
1849 }
1850 return num_of_bos;
1851}
1852
1853static int criu_get_prime_handle(struct kgd_mem *mem,
1854 int flags, u32 *shared_fd)
1855{
1856 struct dma_buf *dmabuf;
1857 int ret;
1858
1859 ret = amdgpu_amdkfd_gpuvm_export_dmabuf(mem, &dmabuf);
1860 if (ret) {
1861 pr_err("dmabuf export failed for the BO\n");
1862 return ret;
1863 }
1864
1865 ret = dma_buf_fd(dmabuf, flags);
1866 if (ret < 0) {
1867 pr_err("dmabuf create fd failed, ret:%d\n", ret);
1868 goto out_free_dmabuf;
1869 }
1870
1871 *shared_fd = ret;
1872 return 0;
1873
1874out_free_dmabuf:
1875 dma_buf_put(dmabuf);
1876 return ret;
1877}
1878
1879static int criu_checkpoint_bos(struct kfd_process *p,
1880 uint32_t num_bos,
1881 uint8_t __user *user_bos,
1882 uint8_t __user *user_priv_data,
1883 uint64_t *priv_offset)
1884{
1885 struct kfd_criu_bo_bucket *bo_buckets;
1886 struct kfd_criu_bo_priv_data *bo_privs;
1887 int ret = 0, pdd_index, bo_index = 0, id;
1888 void *mem;
1889
1890 bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL);
1891 if (!bo_buckets)
1892 return -ENOMEM;
1893
1894 bo_privs = kvzalloc(num_bos * sizeof(*bo_privs), GFP_KERNEL);
1895 if (!bo_privs) {
1896 ret = -ENOMEM;
1897 goto exit;
1898 }
1899
1900 for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) {
1901 struct kfd_process_device *pdd = p->pdds[pdd_index];
1902 struct amdgpu_bo *dumper_bo;
1903 struct kgd_mem *kgd_mem;
1904
1905 idr_for_each_entry(&pdd->alloc_idr, mem, id) {
1906 struct kfd_criu_bo_bucket *bo_bucket;
1907 struct kfd_criu_bo_priv_data *bo_priv;
1908 int i, dev_idx = 0;
1909
1910 if (!mem) {
1911 ret = -ENOMEM;
1912 goto exit;
1913 }
1914
1915 kgd_mem = (struct kgd_mem *)mem;
1916 dumper_bo = kgd_mem->bo;
1917
1918 /* Skip checkpointing BOs that are used for Trap handler
1919 * code and state. Currently, these BOs have a VA that
1920 * is less GPUVM Base
1921 */
1922 if (kgd_mem->va && kgd_mem->va <= pdd->gpuvm_base)
1923 continue;
1924
1925 bo_bucket = &bo_buckets[bo_index];
1926 bo_priv = &bo_privs[bo_index];
1927
1928 bo_bucket->gpu_id = pdd->user_gpu_id;
1929 bo_bucket->addr = (uint64_t)kgd_mem->va;
1930 bo_bucket->size = amdgpu_bo_size(dumper_bo);
1931 bo_bucket->alloc_flags = (uint32_t)kgd_mem->alloc_flags;
1932 bo_priv->idr_handle = id;
1933
1934 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
1935 ret = amdgpu_ttm_tt_get_userptr(&dumper_bo->tbo,
1936 &bo_priv->user_addr);
1937 if (ret) {
1938 pr_err("Failed to obtain user address for user-pointer bo\n");
1939 goto exit;
1940 }
1941 }
1942 if (bo_bucket->alloc_flags
1943 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
1944 ret = criu_get_prime_handle(kgd_mem,
1945 bo_bucket->alloc_flags &
1946 KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0,
1947 &bo_bucket->dmabuf_fd);
1948 if (ret)
1949 goto exit;
1950 } else {
1951 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
1952 }
1953
1954 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
1955 bo_bucket->offset = KFD_MMAP_TYPE_DOORBELL |
1956 KFD_MMAP_GPU_ID(pdd->dev->id);
1957 else if (bo_bucket->alloc_flags &
1958 KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)
1959 bo_bucket->offset = KFD_MMAP_TYPE_MMIO |
1960 KFD_MMAP_GPU_ID(pdd->dev->id);
1961 else
1962 bo_bucket->offset = amdgpu_bo_mmap_offset(dumper_bo);
1963
1964 for (i = 0; i < p->n_pdds; i++) {
1965 if (amdgpu_amdkfd_bo_mapped_to_dev(p->pdds[i]->dev->adev, kgd_mem))
1966 bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id;
1967 }
1968
1969 pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n"
1970 "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x",
1971 bo_bucket->size,
1972 bo_bucket->addr,
1973 bo_bucket->offset,
1974 bo_bucket->gpu_id,
1975 bo_bucket->alloc_flags,
1976 bo_priv->idr_handle);
1977 bo_index++;
1978 }
1979 }
1980
1981 ret = copy_to_user(user_bos, bo_buckets, num_bos * sizeof(*bo_buckets));
1982 if (ret) {
1983 pr_err("Failed to copy BO information to user\n");
1984 ret = -EFAULT;
1985 goto exit;
1986 }
1987
1988 ret = copy_to_user(user_priv_data + *priv_offset, bo_privs, num_bos * sizeof(*bo_privs));
1989 if (ret) {
1990 pr_err("Failed to copy BO priv information to user\n");
1991 ret = -EFAULT;
1992 goto exit;
1993 }
1994
1995 *priv_offset += num_bos * sizeof(*bo_privs);
1996
1997exit:
1998 while (ret && bo_index--) {
1999 if (bo_buckets[bo_index].alloc_flags
2000 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
2001 close_fd(bo_buckets[bo_index].dmabuf_fd);
2002 }
2003
2004 kvfree(bo_buckets);
2005 kvfree(bo_privs);
2006 return ret;
2007}
2008
2009static int criu_get_process_object_info(struct kfd_process *p,
2010 uint32_t *num_devices,
2011 uint32_t *num_bos,
2012 uint32_t *num_objects,
2013 uint64_t *objs_priv_size)
2014{
2015 uint64_t queues_priv_data_size, svm_priv_data_size, priv_size;
2016 uint32_t num_queues, num_events, num_svm_ranges;
2017 int ret;
2018
2019 *num_devices = p->n_pdds;
2020 *num_bos = get_process_num_bos(p);
2021
2022 ret = kfd_process_get_queue_info(p, &num_queues, &queues_priv_data_size);
2023 if (ret)
2024 return ret;
2025
2026 num_events = kfd_get_num_events(p);
2027
2028 ret = svm_range_get_info(p, &num_svm_ranges, &svm_priv_data_size);
2029 if (ret)
2030 return ret;
2031
2032 *num_objects = num_queues + num_events + num_svm_ranges;
2033
2034 if (objs_priv_size) {
2035 priv_size = sizeof(struct kfd_criu_process_priv_data);
2036 priv_size += *num_devices * sizeof(struct kfd_criu_device_priv_data);
2037 priv_size += *num_bos * sizeof(struct kfd_criu_bo_priv_data);
2038 priv_size += queues_priv_data_size;
2039 priv_size += num_events * sizeof(struct kfd_criu_event_priv_data);
2040 priv_size += svm_priv_data_size;
2041 *objs_priv_size = priv_size;
2042 }
2043 return 0;
2044}
2045
2046static int criu_checkpoint(struct file *filep,
2047 struct kfd_process *p,
2048 struct kfd_ioctl_criu_args *args)
2049{
2050 int ret;
2051 uint32_t num_devices, num_bos, num_objects;
2052 uint64_t priv_size, priv_offset = 0, bo_priv_offset;
2053
2054 if (!args->devices || !args->bos || !args->priv_data)
2055 return -EINVAL;
2056
2057 mutex_lock(&p->mutex);
2058
2059 if (!p->n_pdds) {
2060 pr_err("No pdd for given process\n");
2061 ret = -ENODEV;
2062 goto exit_unlock;
2063 }
2064
2065 /* Confirm all process queues are evicted */
2066 if (!p->queues_paused) {
2067 pr_err("Cannot dump process when queues are not in evicted state\n");
2068 /* CRIU plugin did not call op PROCESS_INFO before checkpointing */
2069 ret = -EINVAL;
2070 goto exit_unlock;
2071 }
2072
2073 ret = criu_get_process_object_info(p, &num_devices, &num_bos, &num_objects, &priv_size);
2074 if (ret)
2075 goto exit_unlock;
2076
2077 if (num_devices != args->num_devices ||
2078 num_bos != args->num_bos ||
2079 num_objects != args->num_objects ||
2080 priv_size != args->priv_data_size) {
2081
2082 ret = -EINVAL;
2083 goto exit_unlock;
2084 }
2085
2086 /* each function will store private data inside priv_data and adjust priv_offset */
2087 ret = criu_checkpoint_process(p, (uint8_t __user *)args->priv_data, &priv_offset);
2088 if (ret)
2089 goto exit_unlock;
2090
2091 ret = criu_checkpoint_devices(p, num_devices, (uint8_t __user *)args->devices,
2092 (uint8_t __user *)args->priv_data, &priv_offset);
2093 if (ret)
2094 goto exit_unlock;
2095
2096 /* Leave room for BOs in the private data. They need to be restored
2097 * before events, but we checkpoint them last to simplify the error
2098 * handling.
2099 */
2100 bo_priv_offset = priv_offset;
2101 priv_offset += num_bos * sizeof(struct kfd_criu_bo_priv_data);
2102
2103 if (num_objects) {
2104 ret = kfd_criu_checkpoint_queues(p, (uint8_t __user *)args->priv_data,
2105 &priv_offset);
2106 if (ret)
2107 goto exit_unlock;
2108
2109 ret = kfd_criu_checkpoint_events(p, (uint8_t __user *)args->priv_data,
2110 &priv_offset);
2111 if (ret)
2112 goto exit_unlock;
2113
2114 ret = kfd_criu_checkpoint_svm(p, (uint8_t __user *)args->priv_data, &priv_offset);
2115 if (ret)
2116 goto exit_unlock;
2117 }
2118
2119 /* This must be the last thing in this function that can fail.
2120 * Otherwise we leak dmabuf file descriptors.
2121 */
2122 ret = criu_checkpoint_bos(p, num_bos, (uint8_t __user *)args->bos,
2123 (uint8_t __user *)args->priv_data, &bo_priv_offset);
2124
2125exit_unlock:
2126 mutex_unlock(&p->mutex);
2127 if (ret)
2128 pr_err("Failed to dump CRIU ret:%d\n", ret);
2129 else
2130 pr_debug("CRIU dump ret:%d\n", ret);
2131
2132 return ret;
2133}
2134
2135static int criu_restore_process(struct kfd_process *p,
2136 struct kfd_ioctl_criu_args *args,
2137 uint64_t *priv_offset,
2138 uint64_t max_priv_data_size)
2139{
2140 int ret = 0;
2141 struct kfd_criu_process_priv_data process_priv;
2142
2143 if (*priv_offset + sizeof(process_priv) > max_priv_data_size)
2144 return -EINVAL;
2145
2146 ret = copy_from_user(&process_priv,
2147 (void __user *)(args->priv_data + *priv_offset),
2148 sizeof(process_priv));
2149 if (ret) {
2150 pr_err("Failed to copy process private information from user\n");
2151 ret = -EFAULT;
2152 goto exit;
2153 }
2154 *priv_offset += sizeof(process_priv);
2155
2156 if (process_priv.version != KFD_CRIU_PRIV_VERSION) {
2157 pr_err("Invalid CRIU API version (checkpointed:%d current:%d)\n",
2158 process_priv.version, KFD_CRIU_PRIV_VERSION);
2159 return -EINVAL;
2160 }
2161
2162 pr_debug("Setting XNACK mode\n");
2163 if (process_priv.xnack_mode && !kfd_process_xnack_mode(p, true)) {
2164 pr_err("xnack mode cannot be set\n");
2165 ret = -EPERM;
2166 goto exit;
2167 } else {
2168 pr_debug("set xnack mode: %d\n", process_priv.xnack_mode);
2169 p->xnack_enabled = process_priv.xnack_mode;
2170 }
2171
2172exit:
2173 return ret;
2174}
2175
2176static int criu_restore_devices(struct kfd_process *p,
2177 struct kfd_ioctl_criu_args *args,
2178 uint64_t *priv_offset,
2179 uint64_t max_priv_data_size)
2180{
2181 struct kfd_criu_device_bucket *device_buckets;
2182 struct kfd_criu_device_priv_data *device_privs;
2183 int ret = 0;
2184 uint32_t i;
2185
2186 if (args->num_devices != p->n_pdds)
2187 return -EINVAL;
2188
2189 if (*priv_offset + (args->num_devices * sizeof(*device_privs)) > max_priv_data_size)
2190 return -EINVAL;
2191
2192 device_buckets = kmalloc_array(args->num_devices, sizeof(*device_buckets), GFP_KERNEL);
2193 if (!device_buckets)
2194 return -ENOMEM;
2195
2196 ret = copy_from_user(device_buckets, (void __user *)args->devices,
2197 args->num_devices * sizeof(*device_buckets));
2198 if (ret) {
2199 pr_err("Failed to copy devices buckets from user\n");
2200 ret = -EFAULT;
2201 goto exit;
2202 }
2203
2204 for (i = 0; i < args->num_devices; i++) {
2205 struct kfd_node *dev;
2206 struct kfd_process_device *pdd;
2207 struct file *drm_file;
2208
2209 /* device private data is not currently used */
2210
2211 if (!device_buckets[i].user_gpu_id) {
2212 pr_err("Invalid user gpu_id\n");
2213 ret = -EINVAL;
2214 goto exit;
2215 }
2216
2217 dev = kfd_device_by_id(device_buckets[i].actual_gpu_id);
2218 if (!dev) {
2219 pr_err("Failed to find device with gpu_id = %x\n",
2220 device_buckets[i].actual_gpu_id);
2221 ret = -EINVAL;
2222 goto exit;
2223 }
2224
2225 pdd = kfd_get_process_device_data(dev, p);
2226 if (!pdd) {
2227 pr_err("Failed to get pdd for gpu_id = %x\n",
2228 device_buckets[i].actual_gpu_id);
2229 ret = -EINVAL;
2230 goto exit;
2231 }
2232 pdd->user_gpu_id = device_buckets[i].user_gpu_id;
2233
2234 drm_file = fget(device_buckets[i].drm_fd);
2235 if (!drm_file) {
2236 pr_err("Invalid render node file descriptor sent from plugin (%d)\n",
2237 device_buckets[i].drm_fd);
2238 ret = -EINVAL;
2239 goto exit;
2240 }
2241
2242 if (pdd->drm_file) {
2243 ret = -EINVAL;
2244 goto exit;
2245 }
2246
2247 /* create the vm using render nodes for kfd pdd */
2248 if (kfd_process_device_init_vm(pdd, drm_file)) {
2249 pr_err("could not init vm for given pdd\n");
2250 /* On success, the PDD keeps the drm_file reference */
2251 fput(drm_file);
2252 ret = -EINVAL;
2253 goto exit;
2254 }
2255 /*
2256 * pdd now already has the vm bound to render node so below api won't create a new
2257 * exclusive kfd mapping but use existing one with renderDXXX but is still needed
2258 * for iommu v2 binding and runtime pm.
2259 */
2260 pdd = kfd_bind_process_to_device(dev, p);
2261 if (IS_ERR(pdd)) {
2262 ret = PTR_ERR(pdd);
2263 goto exit;
2264 }
2265
2266 if (!pdd->qpd.proc_doorbells) {
2267 ret = kfd_alloc_process_doorbells(dev->kfd, pdd);
2268 if (ret)
2269 goto exit;
2270 }
2271 }
2272
2273 /*
2274 * We are not copying device private data from user as we are not using the data for now,
2275 * but we still adjust for its private data.
2276 */
2277 *priv_offset += args->num_devices * sizeof(*device_privs);
2278
2279exit:
2280 kfree(device_buckets);
2281 return ret;
2282}
2283
2284static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd,
2285 struct kfd_criu_bo_bucket *bo_bucket,
2286 struct kfd_criu_bo_priv_data *bo_priv,
2287 struct kgd_mem **kgd_mem)
2288{
2289 int idr_handle;
2290 int ret;
2291 const bool criu_resume = true;
2292 u64 offset;
2293
2294 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) {
2295 if (bo_bucket->size !=
2296 kfd_doorbell_process_slice(pdd->dev->kfd))
2297 return -EINVAL;
2298
2299 offset = kfd_get_process_doorbells(pdd);
2300 if (!offset)
2301 return -ENOMEM;
2302 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2303 /* MMIO BOs need remapped bus address */
2304 if (bo_bucket->size != PAGE_SIZE) {
2305 pr_err("Invalid page size\n");
2306 return -EINVAL;
2307 }
2308 offset = pdd->dev->adev->rmmio_remap.bus_addr;
2309 if (!offset) {
2310 pr_err("amdgpu_amdkfd_get_mmio_remap_phys_addr failed\n");
2311 return -ENOMEM;
2312 }
2313 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) {
2314 offset = bo_priv->user_addr;
2315 }
2316 /* Create the BO */
2317 ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr,
2318 bo_bucket->size, pdd->drm_priv, kgd_mem,
2319 &offset, bo_bucket->alloc_flags, criu_resume);
2320 if (ret) {
2321 pr_err("Could not create the BO\n");
2322 return ret;
2323 }
2324 pr_debug("New BO created: size:0x%llx addr:0x%llx offset:0x%llx\n",
2325 bo_bucket->size, bo_bucket->addr, offset);
2326
2327 /* Restore previous IDR handle */
2328 pr_debug("Restoring old IDR handle for the BO");
2329 idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle,
2330 bo_priv->idr_handle + 1, GFP_KERNEL);
2331
2332 if (idr_handle < 0) {
2333 pr_err("Could not allocate idr\n");
2334 amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv,
2335 NULL);
2336 return -ENOMEM;
2337 }
2338
2339 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL)
2340 bo_bucket->restored_offset = KFD_MMAP_TYPE_DOORBELL | KFD_MMAP_GPU_ID(pdd->dev->id);
2341 if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) {
2342 bo_bucket->restored_offset = KFD_MMAP_TYPE_MMIO | KFD_MMAP_GPU_ID(pdd->dev->id);
2343 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_GTT) {
2344 bo_bucket->restored_offset = offset;
2345 } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) {
2346 bo_bucket->restored_offset = offset;
2347 /* Update the VRAM usage count */
2348 WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size);
2349 }
2350 return 0;
2351}
2352
2353static int criu_restore_bo(struct kfd_process *p,
2354 struct kfd_criu_bo_bucket *bo_bucket,
2355 struct kfd_criu_bo_priv_data *bo_priv)
2356{
2357 struct kfd_process_device *pdd;
2358 struct kgd_mem *kgd_mem;
2359 int ret;
2360 int j;
2361
2362 pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n",
2363 bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags,
2364 bo_priv->idr_handle);
2365
2366 pdd = kfd_process_device_data_by_id(p, bo_bucket->gpu_id);
2367 if (!pdd) {
2368 pr_err("Failed to get pdd\n");
2369 return -ENODEV;
2370 }
2371
2372 ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem);
2373 if (ret)
2374 return ret;
2375
2376 /* now map these BOs to GPU/s */
2377 for (j = 0; j < p->n_pdds; j++) {
2378 struct kfd_node *peer;
2379 struct kfd_process_device *peer_pdd;
2380
2381 if (!bo_priv->mapped_gpuids[j])
2382 break;
2383
2384 peer_pdd = kfd_process_device_data_by_id(p, bo_priv->mapped_gpuids[j]);
2385 if (!peer_pdd)
2386 return -EINVAL;
2387
2388 peer = peer_pdd->dev;
2389
2390 peer_pdd = kfd_bind_process_to_device(peer, p);
2391 if (IS_ERR(peer_pdd))
2392 return PTR_ERR(peer_pdd);
2393
2394 ret = amdgpu_amdkfd_gpuvm_map_memory_to_gpu(peer->adev, kgd_mem,
2395 peer_pdd->drm_priv);
2396 if (ret) {
2397 pr_err("Failed to map to gpu %d/%d\n", j, p->n_pdds);
2398 return ret;
2399 }
2400 }
2401
2402 pr_debug("map memory was successful for the BO\n");
2403 /* create the dmabuf object and export the bo */
2404 if (bo_bucket->alloc_flags
2405 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) {
2406 ret = criu_get_prime_handle(kgd_mem, DRM_RDWR,
2407 &bo_bucket->dmabuf_fd);
2408 if (ret)
2409 return ret;
2410 } else {
2411 bo_bucket->dmabuf_fd = KFD_INVALID_FD;
2412 }
2413
2414 return 0;
2415}
2416
2417static int criu_restore_bos(struct kfd_process *p,
2418 struct kfd_ioctl_criu_args *args,
2419 uint64_t *priv_offset,
2420 uint64_t max_priv_data_size)
2421{
2422 struct kfd_criu_bo_bucket *bo_buckets = NULL;
2423 struct kfd_criu_bo_priv_data *bo_privs = NULL;
2424 int ret = 0;
2425 uint32_t i = 0;
2426
2427 if (*priv_offset + (args->num_bos * sizeof(*bo_privs)) > max_priv_data_size)
2428 return -EINVAL;
2429
2430 /* Prevent MMU notifications until stage-4 IOCTL (CRIU_RESUME) is received */
2431 amdgpu_amdkfd_block_mmu_notifications(p->kgd_process_info);
2432
2433 bo_buckets = kvmalloc_array(args->num_bos, sizeof(*bo_buckets), GFP_KERNEL);
2434 if (!bo_buckets)
2435 return -ENOMEM;
2436
2437 ret = copy_from_user(bo_buckets, (void __user *)args->bos,
2438 args->num_bos * sizeof(*bo_buckets));
2439 if (ret) {
2440 pr_err("Failed to copy BOs information from user\n");
2441 ret = -EFAULT;
2442 goto exit;
2443 }
2444
2445 bo_privs = kvmalloc_array(args->num_bos, sizeof(*bo_privs), GFP_KERNEL);
2446 if (!bo_privs) {
2447 ret = -ENOMEM;
2448 goto exit;
2449 }
2450
2451 ret = copy_from_user(bo_privs, (void __user *)args->priv_data + *priv_offset,
2452 args->num_bos * sizeof(*bo_privs));
2453 if (ret) {
2454 pr_err("Failed to copy BOs information from user\n");
2455 ret = -EFAULT;
2456 goto exit;
2457 }
2458 *priv_offset += args->num_bos * sizeof(*bo_privs);
2459
2460 /* Create and map new BOs */
2461 for (; i < args->num_bos; i++) {
2462 ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]);
2463 if (ret) {
2464 pr_debug("Failed to restore BO[%d] ret%d\n", i, ret);
2465 goto exit;
2466 }
2467 } /* done */
2468
2469 /* Copy only the buckets back so user can read bo_buckets[N].restored_offset */
2470 ret = copy_to_user((void __user *)args->bos,
2471 bo_buckets,
2472 (args->num_bos * sizeof(*bo_buckets)));
2473 if (ret)
2474 ret = -EFAULT;
2475
2476exit:
2477 while (ret && i--) {
2478 if (bo_buckets[i].alloc_flags
2479 & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT))
2480 close_fd(bo_buckets[i].dmabuf_fd);
2481 }
2482 kvfree(bo_buckets);
2483 kvfree(bo_privs);
2484 return ret;
2485}
2486
2487static int criu_restore_objects(struct file *filep,
2488 struct kfd_process *p,
2489 struct kfd_ioctl_criu_args *args,
2490 uint64_t *priv_offset,
2491 uint64_t max_priv_data_size)
2492{
2493 int ret = 0;
2494 uint32_t i;
2495
2496 BUILD_BUG_ON(offsetof(struct kfd_criu_queue_priv_data, object_type));
2497 BUILD_BUG_ON(offsetof(struct kfd_criu_event_priv_data, object_type));
2498 BUILD_BUG_ON(offsetof(struct kfd_criu_svm_range_priv_data, object_type));
2499
2500 for (i = 0; i < args->num_objects; i++) {
2501 uint32_t object_type;
2502
2503 if (*priv_offset + sizeof(object_type) > max_priv_data_size) {
2504 pr_err("Invalid private data size\n");
2505 return -EINVAL;
2506 }
2507
2508 ret = get_user(object_type, (uint32_t __user *)(args->priv_data + *priv_offset));
2509 if (ret) {
2510 pr_err("Failed to copy private information from user\n");
2511 goto exit;
2512 }
2513
2514 switch (object_type) {
2515 case KFD_CRIU_OBJECT_TYPE_QUEUE:
2516 ret = kfd_criu_restore_queue(p, (uint8_t __user *)args->priv_data,
2517 priv_offset, max_priv_data_size);
2518 if (ret)
2519 goto exit;
2520 break;
2521 case KFD_CRIU_OBJECT_TYPE_EVENT:
2522 ret = kfd_criu_restore_event(filep, p, (uint8_t __user *)args->priv_data,
2523 priv_offset, max_priv_data_size);
2524 if (ret)
2525 goto exit;
2526 break;
2527 case KFD_CRIU_OBJECT_TYPE_SVM_RANGE:
2528 ret = kfd_criu_restore_svm(p, (uint8_t __user *)args->priv_data,
2529 priv_offset, max_priv_data_size);
2530 if (ret)
2531 goto exit;
2532 break;
2533 default:
2534 pr_err("Invalid object type:%u at index:%d\n", object_type, i);
2535 ret = -EINVAL;
2536 goto exit;
2537 }
2538 }
2539exit:
2540 return ret;
2541}
2542
2543static int criu_restore(struct file *filep,
2544 struct kfd_process *p,
2545 struct kfd_ioctl_criu_args *args)
2546{
2547 uint64_t priv_offset = 0;
2548 int ret = 0;
2549
2550 pr_debug("CRIU restore (num_devices:%u num_bos:%u num_objects:%u priv_data_size:%llu)\n",
2551 args->num_devices, args->num_bos, args->num_objects, args->priv_data_size);
2552
2553 if (!args->bos || !args->devices || !args->priv_data || !args->priv_data_size ||
2554 !args->num_devices || !args->num_bos)
2555 return -EINVAL;
2556
2557 mutex_lock(&p->mutex);
2558
2559 /*
2560 * Set the process to evicted state to avoid running any new queues before all the memory
2561 * mappings are ready.
2562 */
2563 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE);
2564 if (ret)
2565 goto exit_unlock;
2566
2567 /* Each function will adjust priv_offset based on how many bytes they consumed */
2568 ret = criu_restore_process(p, args, &priv_offset, args->priv_data_size);
2569 if (ret)
2570 goto exit_unlock;
2571
2572 ret = criu_restore_devices(p, args, &priv_offset, args->priv_data_size);
2573 if (ret)
2574 goto exit_unlock;
2575
2576 ret = criu_restore_bos(p, args, &priv_offset, args->priv_data_size);
2577 if (ret)
2578 goto exit_unlock;
2579
2580 ret = criu_restore_objects(filep, p, args, &priv_offset, args->priv_data_size);
2581 if (ret)
2582 goto exit_unlock;
2583
2584 if (priv_offset != args->priv_data_size) {
2585 pr_err("Invalid private data size\n");
2586 ret = -EINVAL;
2587 }
2588
2589exit_unlock:
2590 mutex_unlock(&p->mutex);
2591 if (ret)
2592 pr_err("Failed to restore CRIU ret:%d\n", ret);
2593 else
2594 pr_debug("CRIU restore successful\n");
2595
2596 return ret;
2597}
2598
2599static int criu_unpause(struct file *filep,
2600 struct kfd_process *p,
2601 struct kfd_ioctl_criu_args *args)
2602{
2603 int ret;
2604
2605 mutex_lock(&p->mutex);
2606
2607 if (!p->queues_paused) {
2608 mutex_unlock(&p->mutex);
2609 return -EINVAL;
2610 }
2611
2612 ret = kfd_process_restore_queues(p);
2613 if (ret)
2614 pr_err("Failed to unpause queues ret:%d\n", ret);
2615 else
2616 p->queues_paused = false;
2617
2618 mutex_unlock(&p->mutex);
2619
2620 return ret;
2621}
2622
2623static int criu_resume(struct file *filep,
2624 struct kfd_process *p,
2625 struct kfd_ioctl_criu_args *args)
2626{
2627 struct kfd_process *target = NULL;
2628 struct pid *pid = NULL;
2629 int ret = 0;
2630
2631 pr_debug("Inside %s, target pid for criu restore: %d\n", __func__,
2632 args->pid);
2633
2634 pid = find_get_pid(args->pid);
2635 if (!pid) {
2636 pr_err("Cannot find pid info for %i\n", args->pid);
2637 return -ESRCH;
2638 }
2639
2640 pr_debug("calling kfd_lookup_process_by_pid\n");
2641 target = kfd_lookup_process_by_pid(pid);
2642
2643 put_pid(pid);
2644
2645 if (!target) {
2646 pr_debug("Cannot find process info for %i\n", args->pid);
2647 return -ESRCH;
2648 }
2649
2650 mutex_lock(&target->mutex);
2651 ret = kfd_criu_resume_svm(target);
2652 if (ret) {
2653 pr_err("kfd_criu_resume_svm failed for %i\n", args->pid);
2654 goto exit;
2655 }
2656
2657 ret = amdgpu_amdkfd_criu_resume(target->kgd_process_info);
2658 if (ret)
2659 pr_err("amdgpu_amdkfd_criu_resume failed for %i\n", args->pid);
2660
2661exit:
2662 mutex_unlock(&target->mutex);
2663
2664 kfd_unref_process(target);
2665 return ret;
2666}
2667
2668static int criu_process_info(struct file *filep,
2669 struct kfd_process *p,
2670 struct kfd_ioctl_criu_args *args)
2671{
2672 int ret = 0;
2673
2674 mutex_lock(&p->mutex);
2675
2676 if (!p->n_pdds) {
2677 pr_err("No pdd for given process\n");
2678 ret = -ENODEV;
2679 goto err_unlock;
2680 }
2681
2682 ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT);
2683 if (ret)
2684 goto err_unlock;
2685
2686 p->queues_paused = true;
2687
2688 args->pid = task_pid_nr_ns(p->lead_thread,
2689 task_active_pid_ns(p->lead_thread));
2690
2691 ret = criu_get_process_object_info(p, &args->num_devices, &args->num_bos,
2692 &args->num_objects, &args->priv_data_size);
2693 if (ret)
2694 goto err_unlock;
2695
2696 dev_dbg(kfd_device, "Num of devices:%u bos:%u objects:%u priv_data_size:%lld\n",
2697 args->num_devices, args->num_bos, args->num_objects,
2698 args->priv_data_size);
2699
2700err_unlock:
2701 if (ret) {
2702 kfd_process_restore_queues(p);
2703 p->queues_paused = false;
2704 }
2705 mutex_unlock(&p->mutex);
2706 return ret;
2707}
2708
2709static int kfd_ioctl_criu(struct file *filep, struct kfd_process *p, void *data)
2710{
2711 struct kfd_ioctl_criu_args *args = data;
2712 int ret;
2713
2714 dev_dbg(kfd_device, "CRIU operation: %d\n", args->op);
2715 switch (args->op) {
2716 case KFD_CRIU_OP_PROCESS_INFO:
2717 ret = criu_process_info(filep, p, args);
2718 break;
2719 case KFD_CRIU_OP_CHECKPOINT:
2720 ret = criu_checkpoint(filep, p, args);
2721 break;
2722 case KFD_CRIU_OP_UNPAUSE:
2723 ret = criu_unpause(filep, p, args);
2724 break;
2725 case KFD_CRIU_OP_RESTORE:
2726 ret = criu_restore(filep, p, args);
2727 break;
2728 case KFD_CRIU_OP_RESUME:
2729 ret = criu_resume(filep, p, args);
2730 break;
2731 default:
2732 dev_dbg(kfd_device, "Unsupported CRIU operation:%d\n", args->op);
2733 ret = -EINVAL;
2734 break;
2735 }
2736
2737 if (ret)
2738 dev_dbg(kfd_device, "CRIU operation:%d err:%d\n", args->op, ret);
2739
2740 return ret;
2741}
2742
2743static int runtime_enable(struct kfd_process *p, uint64_t r_debug,
2744 bool enable_ttmp_setup)
2745{
2746 int i = 0, ret = 0;
2747
2748 if (p->is_runtime_retry)
2749 goto retry;
2750
2751 if (p->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_DISABLED)
2752 return -EBUSY;
2753
2754 for (i = 0; i < p->n_pdds; i++) {
2755 struct kfd_process_device *pdd = p->pdds[i];
2756
2757 if (pdd->qpd.queue_count)
2758 return -EEXIST;
2759
2760 /*
2761 * Setup TTMPs by default.
2762 * Note that this call must remain here for MES ADD QUEUE to
2763 * skip_process_ctx_clear unconditionally as the first call to
2764 * SET_SHADER_DEBUGGER clears any stale process context data
2765 * saved in MES.
2766 */
2767 if (pdd->dev->kfd->shared_resources.enable_mes)
2768 kfd_dbg_set_mes_debug_mode(pdd, !kfd_dbg_has_cwsr_workaround(pdd->dev));
2769 }
2770
2771 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED;
2772 p->runtime_info.r_debug = r_debug;
2773 p->runtime_info.ttmp_setup = enable_ttmp_setup;
2774
2775 if (p->runtime_info.ttmp_setup) {
2776 for (i = 0; i < p->n_pdds; i++) {
2777 struct kfd_process_device *pdd = p->pdds[i];
2778
2779 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) {
2780 amdgpu_gfx_off_ctrl(pdd->dev->adev, false);
2781 pdd->dev->kfd2kgd->enable_debug_trap(
2782 pdd->dev->adev,
2783 true,
2784 pdd->dev->vm_info.last_vmid_kfd);
2785 } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2786 pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap(
2787 pdd->dev->adev,
2788 false,
2789 0);
2790 }
2791 }
2792 }
2793
2794retry:
2795 if (p->debug_trap_enabled) {
2796 if (!p->is_runtime_retry) {
2797 kfd_dbg_trap_activate(p);
2798 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2799 p, NULL, 0, false, NULL, 0);
2800 }
2801
2802 mutex_unlock(&p->mutex);
2803 ret = down_interruptible(&p->runtime_enable_sema);
2804 mutex_lock(&p->mutex);
2805
2806 p->is_runtime_retry = !!ret;
2807 }
2808
2809 return ret;
2810}
2811
2812static int runtime_disable(struct kfd_process *p)
2813{
2814 int i = 0, ret;
2815 bool was_enabled = p->runtime_info.runtime_state == DEBUG_RUNTIME_STATE_ENABLED;
2816
2817 p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_DISABLED;
2818 p->runtime_info.r_debug = 0;
2819
2820 if (p->debug_trap_enabled) {
2821 if (was_enabled)
2822 kfd_dbg_trap_deactivate(p, false, 0);
2823
2824 if (!p->is_runtime_retry)
2825 kfd_dbg_ev_raise(KFD_EC_MASK(EC_PROCESS_RUNTIME),
2826 p, NULL, 0, false, NULL, 0);
2827
2828 mutex_unlock(&p->mutex);
2829 ret = down_interruptible(&p->runtime_enable_sema);
2830 mutex_lock(&p->mutex);
2831
2832 p->is_runtime_retry = !!ret;
2833 if (ret)
2834 return ret;
2835 }
2836
2837 if (was_enabled && p->runtime_info.ttmp_setup) {
2838 for (i = 0; i < p->n_pdds; i++) {
2839 struct kfd_process_device *pdd = p->pdds[i];
2840
2841 if (!kfd_dbg_is_rlc_restore_supported(pdd->dev))
2842 amdgpu_gfx_off_ctrl(pdd->dev->adev, true);
2843 }
2844 }
2845
2846 p->runtime_info.ttmp_setup = false;
2847
2848 /* disable ttmp setup */
2849 for (i = 0; i < p->n_pdds; i++) {
2850 struct kfd_process_device *pdd = p->pdds[i];
2851
2852 if (kfd_dbg_is_per_vmid_supported(pdd->dev)) {
2853 pdd->spi_dbg_override =
2854 pdd->dev->kfd2kgd->disable_debug_trap(
2855 pdd->dev->adev,
2856 false,
2857 pdd->dev->vm_info.last_vmid_kfd);
2858
2859 if (!pdd->dev->kfd->shared_resources.enable_mes)
2860 debug_refresh_runlist(pdd->dev->dqm);
2861 else
2862 kfd_dbg_set_mes_debug_mode(pdd,
2863 !kfd_dbg_has_cwsr_workaround(pdd->dev));
2864 }
2865 }
2866
2867 return 0;
2868}
2869
2870static int kfd_ioctl_runtime_enable(struct file *filep, struct kfd_process *p, void *data)
2871{
2872 struct kfd_ioctl_runtime_enable_args *args = data;
2873 int r;
2874
2875 mutex_lock(&p->mutex);
2876
2877 if (args->mode_mask & KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK)
2878 r = runtime_enable(p, args->r_debug,
2879 !!(args->mode_mask & KFD_RUNTIME_ENABLE_MODE_TTMP_SAVE_MASK));
2880 else
2881 r = runtime_disable(p);
2882
2883 mutex_unlock(&p->mutex);
2884
2885 return r;
2886}
2887
2888static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, void *data)
2889{
2890 struct kfd_ioctl_dbg_trap_args *args = data;
2891 struct task_struct *thread = NULL;
2892 struct mm_struct *mm = NULL;
2893 struct pid *pid = NULL;
2894 struct kfd_process *target = NULL;
2895 struct kfd_process_device *pdd = NULL;
2896 int r = 0;
2897
2898 if (sched_policy == KFD_SCHED_POLICY_NO_HWS) {
2899 pr_err("Debugging does not support sched_policy %i", sched_policy);
2900 return -EINVAL;
2901 }
2902
2903 pid = find_get_pid(args->pid);
2904 if (!pid) {
2905 pr_debug("Cannot find pid info for %i\n", args->pid);
2906 r = -ESRCH;
2907 goto out;
2908 }
2909
2910 thread = get_pid_task(pid, PIDTYPE_PID);
2911 if (!thread) {
2912 r = -ESRCH;
2913 goto out;
2914 }
2915
2916 mm = get_task_mm(thread);
2917 if (!mm) {
2918 r = -ESRCH;
2919 goto out;
2920 }
2921
2922 if (args->op == KFD_IOC_DBG_TRAP_ENABLE) {
2923 bool create_process;
2924
2925 rcu_read_lock();
2926 create_process = thread && thread != current && ptrace_parent(thread) == current;
2927 rcu_read_unlock();
2928
2929 target = create_process ? kfd_create_process(thread) :
2930 kfd_lookup_process_by_pid(pid);
2931 } else {
2932 target = kfd_lookup_process_by_pid(pid);
2933 }
2934
2935 if (IS_ERR_OR_NULL(target)) {
2936 pr_debug("Cannot find process PID %i to debug\n", args->pid);
2937 r = target ? PTR_ERR(target) : -ESRCH;
2938 goto out;
2939 }
2940
2941 /* Check if target is still PTRACED. */
2942 rcu_read_lock();
2943 if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE
2944 && ptrace_parent(target->lead_thread) != current) {
2945 pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid);
2946 r = -EPERM;
2947 }
2948 rcu_read_unlock();
2949
2950 if (r)
2951 goto out;
2952
2953 mutex_lock(&target->mutex);
2954
2955 if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) {
2956 pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op);
2957 r = -EINVAL;
2958 goto unlock_out;
2959 }
2960
2961 if (target->runtime_info.runtime_state != DEBUG_RUNTIME_STATE_ENABLED &&
2962 (args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE ||
2963 args->op == KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE ||
2964 args->op == KFD_IOC_DBG_TRAP_SUSPEND_QUEUES ||
2965 args->op == KFD_IOC_DBG_TRAP_RESUME_QUEUES ||
2966 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2967 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH ||
2968 args->op == KFD_IOC_DBG_TRAP_SET_FLAGS)) {
2969 r = -EPERM;
2970 goto unlock_out;
2971 }
2972
2973 if (args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ||
2974 args->op == KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH) {
2975 int user_gpu_id = kfd_process_get_user_gpu_id(target,
2976 args->op == KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH ?
2977 args->set_node_address_watch.gpu_id :
2978 args->clear_node_address_watch.gpu_id);
2979
2980 pdd = kfd_process_device_data_by_id(target, user_gpu_id);
2981 if (user_gpu_id == -EINVAL || !pdd) {
2982 r = -ENODEV;
2983 goto unlock_out;
2984 }
2985 }
2986
2987 switch (args->op) {
2988 case KFD_IOC_DBG_TRAP_ENABLE:
2989 if (target != p)
2990 target->debugger_process = p;
2991
2992 r = kfd_dbg_trap_enable(target,
2993 args->enable.dbg_fd,
2994 (void __user *)args->enable.rinfo_ptr,
2995 &args->enable.rinfo_size);
2996 if (!r)
2997 target->exception_enable_mask = args->enable.exception_mask;
2998
2999 break;
3000 case KFD_IOC_DBG_TRAP_DISABLE:
3001 r = kfd_dbg_trap_disable(target);
3002 break;
3003 case KFD_IOC_DBG_TRAP_SEND_RUNTIME_EVENT:
3004 r = kfd_dbg_send_exception_to_runtime(target,
3005 args->send_runtime_event.gpu_id,
3006 args->send_runtime_event.queue_id,
3007 args->send_runtime_event.exception_mask);
3008 break;
3009 case KFD_IOC_DBG_TRAP_SET_EXCEPTIONS_ENABLED:
3010 kfd_dbg_set_enabled_debug_exception_mask(target,
3011 args->set_exceptions_enabled.exception_mask);
3012 break;
3013 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_OVERRIDE:
3014 r = kfd_dbg_trap_set_wave_launch_override(target,
3015 args->launch_override.override_mode,
3016 args->launch_override.enable_mask,
3017 args->launch_override.support_request_mask,
3018 &args->launch_override.enable_mask,
3019 &args->launch_override.support_request_mask);
3020 break;
3021 case KFD_IOC_DBG_TRAP_SET_WAVE_LAUNCH_MODE:
3022 r = kfd_dbg_trap_set_wave_launch_mode(target,
3023 args->launch_mode.launch_mode);
3024 break;
3025 case KFD_IOC_DBG_TRAP_SUSPEND_QUEUES:
3026 r = suspend_queues(target,
3027 args->suspend_queues.num_queues,
3028 args->suspend_queues.grace_period,
3029 args->suspend_queues.exception_mask,
3030 (uint32_t *)args->suspend_queues.queue_array_ptr);
3031
3032 break;
3033 case KFD_IOC_DBG_TRAP_RESUME_QUEUES:
3034 r = resume_queues(target, args->resume_queues.num_queues,
3035 (uint32_t *)args->resume_queues.queue_array_ptr);
3036 break;
3037 case KFD_IOC_DBG_TRAP_SET_NODE_ADDRESS_WATCH:
3038 r = kfd_dbg_trap_set_dev_address_watch(pdd,
3039 args->set_node_address_watch.address,
3040 args->set_node_address_watch.mask,
3041 &args->set_node_address_watch.id,
3042 args->set_node_address_watch.mode);
3043 break;
3044 case KFD_IOC_DBG_TRAP_CLEAR_NODE_ADDRESS_WATCH:
3045 r = kfd_dbg_trap_clear_dev_address_watch(pdd,
3046 args->clear_node_address_watch.id);
3047 break;
3048 case KFD_IOC_DBG_TRAP_SET_FLAGS:
3049 r = kfd_dbg_trap_set_flags(target, &args->set_flags.flags);
3050 break;
3051 case KFD_IOC_DBG_TRAP_QUERY_DEBUG_EVENT:
3052 r = kfd_dbg_ev_query_debug_event(target,
3053 &args->query_debug_event.queue_id,
3054 &args->query_debug_event.gpu_id,
3055 args->query_debug_event.exception_mask,
3056 &args->query_debug_event.exception_mask);
3057 break;
3058 case KFD_IOC_DBG_TRAP_QUERY_EXCEPTION_INFO:
3059 r = kfd_dbg_trap_query_exception_info(target,
3060 args->query_exception_info.source_id,
3061 args->query_exception_info.exception_code,
3062 args->query_exception_info.clear_exception,
3063 (void __user *)args->query_exception_info.info_ptr,
3064 &args->query_exception_info.info_size);
3065 break;
3066 case KFD_IOC_DBG_TRAP_GET_QUEUE_SNAPSHOT:
3067 r = pqm_get_queue_snapshot(&target->pqm,
3068 args->queue_snapshot.exception_mask,
3069 (void __user *)args->queue_snapshot.snapshot_buf_ptr,
3070 &args->queue_snapshot.num_queues,
3071 &args->queue_snapshot.entry_size);
3072 break;
3073 case KFD_IOC_DBG_TRAP_GET_DEVICE_SNAPSHOT:
3074 r = kfd_dbg_trap_device_snapshot(target,
3075 args->device_snapshot.exception_mask,
3076 (void __user *)args->device_snapshot.snapshot_buf_ptr,
3077 &args->device_snapshot.num_devices,
3078 &args->device_snapshot.entry_size);
3079 break;
3080 default:
3081 pr_err("Invalid option: %i\n", args->op);
3082 r = -EINVAL;
3083 }
3084
3085unlock_out:
3086 mutex_unlock(&target->mutex);
3087
3088out:
3089 if (thread)
3090 put_task_struct(thread);
3091
3092 if (mm)
3093 mmput(mm);
3094
3095 if (pid)
3096 put_pid(pid);
3097
3098 if (target)
3099 kfd_unref_process(target);
3100
3101 return r;
3102}
3103
3104#define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
3105 [_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
3106 .cmd_drv = 0, .name = #ioctl}
3107
3108/** Ioctl table */
3109static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
3110 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_VERSION,
3111 kfd_ioctl_get_version, 0),
3112
3113 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_QUEUE,
3114 kfd_ioctl_create_queue, 0),
3115
3116 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_QUEUE,
3117 kfd_ioctl_destroy_queue, 0),
3118
3119 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_MEMORY_POLICY,
3120 kfd_ioctl_set_memory_policy, 0),
3121
3122 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_CLOCK_COUNTERS,
3123 kfd_ioctl_get_clock_counters, 0),
3124
3125 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES,
3126 kfd_ioctl_get_process_apertures, 0),
3127
3128 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UPDATE_QUEUE,
3129 kfd_ioctl_update_queue, 0),
3130
3131 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CREATE_EVENT,
3132 kfd_ioctl_create_event, 0),
3133
3134 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DESTROY_EVENT,
3135 kfd_ioctl_destroy_event, 0),
3136
3137 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_EVENT,
3138 kfd_ioctl_set_event, 0),
3139
3140 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RESET_EVENT,
3141 kfd_ioctl_reset_event, 0),
3142
3143 AMDKFD_IOCTL_DEF(AMDKFD_IOC_WAIT_EVENTS,
3144 kfd_ioctl_wait_events, 0),
3145
3146 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_REGISTER_DEPRECATED,
3147 kfd_ioctl_dbg_register, 0),
3148
3149 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_UNREGISTER_DEPRECATED,
3150 kfd_ioctl_dbg_unregister, 0),
3151
3152 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_ADDRESS_WATCH_DEPRECATED,
3153 kfd_ioctl_dbg_address_watch, 0),
3154
3155 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_WAVE_CONTROL_DEPRECATED,
3156 kfd_ioctl_dbg_wave_control, 0),
3157
3158 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_SCRATCH_BACKING_VA,
3159 kfd_ioctl_set_scratch_backing_va, 0),
3160
3161 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_TILE_CONFIG,
3162 kfd_ioctl_get_tile_config, 0),
3163
3164 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_TRAP_HANDLER,
3165 kfd_ioctl_set_trap_handler, 0),
3166
3167 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_PROCESS_APERTURES_NEW,
3168 kfd_ioctl_get_process_apertures_new, 0),
3169
3170 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ACQUIRE_VM,
3171 kfd_ioctl_acquire_vm, 0),
3172
3173 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_MEMORY_OF_GPU,
3174 kfd_ioctl_alloc_memory_of_gpu, 0),
3175
3176 AMDKFD_IOCTL_DEF(AMDKFD_IOC_FREE_MEMORY_OF_GPU,
3177 kfd_ioctl_free_memory_of_gpu, 0),
3178
3179 AMDKFD_IOCTL_DEF(AMDKFD_IOC_MAP_MEMORY_TO_GPU,
3180 kfd_ioctl_map_memory_to_gpu, 0),
3181
3182 AMDKFD_IOCTL_DEF(AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU,
3183 kfd_ioctl_unmap_memory_from_gpu, 0),
3184
3185 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_CU_MASK,
3186 kfd_ioctl_set_cu_mask, 0),
3187
3188 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_QUEUE_WAVE_STATE,
3189 kfd_ioctl_get_queue_wave_state, 0),
3190
3191 AMDKFD_IOCTL_DEF(AMDKFD_IOC_GET_DMABUF_INFO,
3192 kfd_ioctl_get_dmabuf_info, 0),
3193
3194 AMDKFD_IOCTL_DEF(AMDKFD_IOC_IMPORT_DMABUF,
3195 kfd_ioctl_import_dmabuf, 0),
3196
3197 AMDKFD_IOCTL_DEF(AMDKFD_IOC_ALLOC_QUEUE_GWS,
3198 kfd_ioctl_alloc_queue_gws, 0),
3199
3200 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
3201 kfd_ioctl_smi_events, 0),
3202
3203 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0),
3204
3205 AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
3206 kfd_ioctl_set_xnack_mode, 0),
3207
3208 AMDKFD_IOCTL_DEF(AMDKFD_IOC_CRIU_OP,
3209 kfd_ioctl_criu, KFD_IOC_FLAG_CHECKPOINT_RESTORE),
3210
3211 AMDKFD_IOCTL_DEF(AMDKFD_IOC_AVAILABLE_MEMORY,
3212 kfd_ioctl_get_available_memory, 0),
3213
3214 AMDKFD_IOCTL_DEF(AMDKFD_IOC_EXPORT_DMABUF,
3215 kfd_ioctl_export_dmabuf, 0),
3216
3217 AMDKFD_IOCTL_DEF(AMDKFD_IOC_RUNTIME_ENABLE,
3218 kfd_ioctl_runtime_enable, 0),
3219
3220 AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP,
3221 kfd_ioctl_set_debug_trap, 0),
3222};
3223
3224#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls)
3225
3226static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
3227{
3228 struct kfd_process *process;
3229 amdkfd_ioctl_t *func;
3230 const struct amdkfd_ioctl_desc *ioctl = NULL;
3231 unsigned int nr = _IOC_NR(cmd);
3232 char stack_kdata[128];
3233 char *kdata = NULL;
3234 unsigned int usize, asize;
3235 int retcode = -EINVAL;
3236 bool ptrace_attached = false;
3237
3238 if (nr >= AMDKFD_CORE_IOCTL_COUNT)
3239 goto err_i1;
3240
3241 if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) {
3242 u32 amdkfd_size;
3243
3244 ioctl = &amdkfd_ioctls[nr];
3245
3246 amdkfd_size = _IOC_SIZE(ioctl->cmd);
3247 usize = asize = _IOC_SIZE(cmd);
3248 if (amdkfd_size > asize)
3249 asize = amdkfd_size;
3250
3251 cmd = ioctl->cmd;
3252 } else
3253 goto err_i1;
3254
3255 dev_dbg(kfd_device, "ioctl cmd 0x%x (#0x%x), arg 0x%lx\n", cmd, nr, arg);
3256
3257 /* Get the process struct from the filep. Only the process
3258 * that opened /dev/kfd can use the file descriptor. Child
3259 * processes need to create their own KFD device context.
3260 */
3261 process = filep->private_data;
3262
3263 rcu_read_lock();
3264 if ((ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE) &&
3265 ptrace_parent(process->lead_thread) == current)
3266 ptrace_attached = true;
3267 rcu_read_unlock();
3268
3269 if (process->lead_thread != current->group_leader
3270 && !ptrace_attached) {
3271 dev_dbg(kfd_device, "Using KFD FD in wrong process\n");
3272 retcode = -EBADF;
3273 goto err_i1;
3274 }
3275
3276 /* Do not trust userspace, use our own definition */
3277 func = ioctl->func;
3278
3279 if (unlikely(!func)) {
3280 dev_dbg(kfd_device, "no function\n");
3281 retcode = -EINVAL;
3282 goto err_i1;
3283 }
3284
3285 /*
3286 * Versions of docker shipped in Ubuntu 18.xx and 20.xx do not support
3287 * CAP_CHECKPOINT_RESTORE, so we also allow access if CAP_SYS_ADMIN as CAP_SYS_ADMIN is a
3288 * more priviledged access.
3289 */
3290 if (unlikely(ioctl->flags & KFD_IOC_FLAG_CHECKPOINT_RESTORE)) {
3291 if (!capable(CAP_CHECKPOINT_RESTORE) &&
3292 !capable(CAP_SYS_ADMIN)) {
3293 retcode = -EACCES;
3294 goto err_i1;
3295 }
3296 }
3297
3298 if (cmd & (IOC_IN | IOC_OUT)) {
3299 if (asize <= sizeof(stack_kdata)) {
3300 kdata = stack_kdata;
3301 } else {
3302 kdata = kmalloc(asize, GFP_KERNEL);
3303 if (!kdata) {
3304 retcode = -ENOMEM;
3305 goto err_i1;
3306 }
3307 }
3308 if (asize > usize)
3309 memset(kdata + usize, 0, asize - usize);
3310 }
3311
3312 if (cmd & IOC_IN) {
3313 if (copy_from_user(kdata, (void __user *)arg, usize) != 0) {
3314 retcode = -EFAULT;
3315 goto err_i1;
3316 }
3317 } else if (cmd & IOC_OUT) {
3318 memset(kdata, 0, usize);
3319 }
3320
3321 retcode = func(filep, process, kdata);
3322
3323 if (cmd & IOC_OUT)
3324 if (copy_to_user((void __user *)arg, kdata, usize) != 0)
3325 retcode = -EFAULT;
3326
3327err_i1:
3328 if (!ioctl)
3329 dev_dbg(kfd_device, "invalid ioctl: pid=%d, cmd=0x%02x, nr=0x%02x\n",
3330 task_pid_nr(current), cmd, nr);
3331
3332 if (kdata != stack_kdata)
3333 kfree(kdata);
3334
3335 if (retcode)
3336 dev_dbg(kfd_device, "ioctl cmd (#0x%x), arg 0x%lx, ret = %d\n",
3337 nr, arg, retcode);
3338
3339 return retcode;
3340}
3341
3342static int kfd_mmio_mmap(struct kfd_node *dev, struct kfd_process *process,
3343 struct vm_area_struct *vma)
3344{
3345 phys_addr_t address;
3346
3347 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
3348 return -EINVAL;
3349
3350 address = dev->adev->rmmio_remap.bus_addr;
3351
3352 vm_flags_set(vma, VM_IO | VM_DONTCOPY | VM_DONTEXPAND | VM_NORESERVE |
3353 VM_DONTDUMP | VM_PFNMAP);
3354
3355 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
3356
3357 pr_debug("pasid 0x%x mapping mmio page\n"
3358 " target user address == 0x%08llX\n"
3359 " physical address == 0x%08llX\n"
3360 " vm_flags == 0x%04lX\n"
3361 " size == 0x%04lX\n",
3362 process->pasid, (unsigned long long) vma->vm_start,
3363 address, vma->vm_flags, PAGE_SIZE);
3364
3365 return io_remap_pfn_range(vma,
3366 vma->vm_start,
3367 address >> PAGE_SHIFT,
3368 PAGE_SIZE,
3369 vma->vm_page_prot);
3370}
3371
3372
3373static int kfd_mmap(struct file *filp, struct vm_area_struct *vma)
3374{
3375 struct kfd_process *process;
3376 struct kfd_node *dev = NULL;
3377 unsigned long mmap_offset;
3378 unsigned int gpu_id;
3379
3380 process = kfd_get_process(current);
3381 if (IS_ERR(process))
3382 return PTR_ERR(process);
3383
3384 mmap_offset = vma->vm_pgoff << PAGE_SHIFT;
3385 gpu_id = KFD_MMAP_GET_GPU_ID(mmap_offset);
3386 if (gpu_id)
3387 dev = kfd_device_by_id(gpu_id);
3388
3389 switch (mmap_offset & KFD_MMAP_TYPE_MASK) {
3390 case KFD_MMAP_TYPE_DOORBELL:
3391 if (!dev)
3392 return -ENODEV;
3393 return kfd_doorbell_mmap(dev, process, vma);
3394
3395 case KFD_MMAP_TYPE_EVENTS:
3396 return kfd_event_mmap(process, vma);
3397
3398 case KFD_MMAP_TYPE_RESERVED_MEM:
3399 if (!dev)
3400 return -ENODEV;
3401 return kfd_reserved_mem_mmap(dev, process, vma);
3402 case KFD_MMAP_TYPE_MMIO:
3403 if (!dev)
3404 return -ENODEV;
3405 return kfd_mmio_mmap(dev, process, vma);
3406 }
3407
3408 return -EFAULT;
3409}