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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_9.h"
26#include "amdgpu_ras.h"
27
28#include "nbio/nbio_7_9_0_offset.h"
29#include "nbio/nbio_7_9_0_sh_mask.h"
30#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
31#include <uapi/linux/kfd_ioctl.h>
32
33#define NPS_MODE_MASK 0x000000FFL
34
35/* Core 0 Port 0 counter */
36#define smnPCIEP_NAK_COUNTER 0x1A340218
37
38#define smnPCIE_PERF_CNTL_TXCLK3 0x1A38021c
39#define smnPCIE_PERF_CNTL_TXCLK7 0x1A380888
40#define smnPCIE_PERF_COUNT_CNTL 0x1A380200
41#define smnPCIE_PERF_COUNT0_TXCLK3 0x1A380220
42#define smnPCIE_PERF_COUNT0_TXCLK7 0x1A38088C
43#define smnPCIE_PERF_COUNT0_UPVAL_TXCLK3 0x1A3808F8
44#define smnPCIE_PERF_COUNT0_UPVAL_TXCLK7 0x1A380918
45
46
47static void nbio_v7_9_remap_hdp_registers(struct amdgpu_device *adev)
48{
49 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
50 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
51 WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
52 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
53}
54
55static u32 nbio_v7_9_get_rev_id(struct amdgpu_device *adev)
56{
57 u32 tmp;
58
59 tmp = IP_VERSION_SUBREV(amdgpu_ip_version_full(adev, NBIO_HWIP, 0));
60 /* If it is VF or subrevision holds a non-zero value, that should be used */
61 if (tmp || amdgpu_sriov_vf(adev))
62 return tmp;
63
64 /* If discovery subrev is not updated, use register version */
65 tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
66 tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,
67 STRAP_ATI_REV_ID_DEV0_F0);
68
69 return tmp;
70}
71
72static void nbio_v7_9_mc_access_enable(struct amdgpu_device *adev, bool enable)
73{
74 if (enable)
75 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
76 BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
77 else
78 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
79}
80
81static u32 nbio_v7_9_get_memsize(struct amdgpu_device *adev)
82{
83 return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
84}
85
86static void nbio_v7_9_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
87 bool use_doorbell, int doorbell_index, int doorbell_size)
88{
89 u32 doorbell_range = 0, doorbell_ctrl = 0;
90 int aid_id, dev_inst;
91
92 dev_inst = GET_INST(SDMA0, instance);
93 aid_id = adev->sdma.instance[instance].aid_id;
94
95 if (use_doorbell == false)
96 return;
97
98 doorbell_range =
99 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
100 BIF_DOORBELL0_RANGE_OFFSET_ENTRY, doorbell_index);
101 doorbell_range =
102 REG_SET_FIELD(doorbell_range, DOORBELL0_CTRL_ENTRY_0,
103 BIF_DOORBELL0_RANGE_SIZE_ENTRY, doorbell_size);
104 doorbell_ctrl =
105 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
106 S2A_DOORBELL_PORT1_ENABLE, 1);
107 doorbell_ctrl =
108 REG_SET_FIELD(doorbell_ctrl, S2A_DOORBELL_ENTRY_1_CTRL,
109 S2A_DOORBELL_PORT1_RANGE_SIZE, doorbell_size);
110
111 switch (dev_inst % adev->sdma.num_inst_per_aid) {
112 case 0:
113 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_1,
114 4 * aid_id, doorbell_range);
115
116 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
117 S2A_DOORBELL_ENTRY_1_CTRL,
118 S2A_DOORBELL_PORT1_AWID, 0xe);
119 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
120 S2A_DOORBELL_ENTRY_1_CTRL,
121 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xe);
122 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
123 S2A_DOORBELL_ENTRY_1_CTRL,
124 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
125 0x1);
126 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_1_CTRL,
127 aid_id, doorbell_ctrl);
128 break;
129 case 1:
130 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_2,
131 4 * aid_id, doorbell_range);
132
133 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
134 S2A_DOORBELL_ENTRY_1_CTRL,
135 S2A_DOORBELL_PORT1_AWID, 0x8);
136 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
137 S2A_DOORBELL_ENTRY_1_CTRL,
138 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x8);
139 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
140 S2A_DOORBELL_ENTRY_1_CTRL,
141 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
142 0x2);
143 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_2_CTRL,
144 aid_id, doorbell_ctrl);
145 break;
146 case 2:
147 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_3,
148 4 * aid_id, doorbell_range);
149
150 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
151 S2A_DOORBELL_ENTRY_1_CTRL,
152 S2A_DOORBELL_PORT1_AWID, 0x9);
153 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
154 S2A_DOORBELL_ENTRY_1_CTRL,
155 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x9);
156 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
157 S2A_DOORBELL_ENTRY_1_CTRL,
158 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
159 0x8);
160 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_5_CTRL,
161 aid_id, doorbell_ctrl);
162 break;
163 case 3:
164 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_4,
165 4 * aid_id, doorbell_range);
166
167 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
168 S2A_DOORBELL_ENTRY_1_CTRL,
169 S2A_DOORBELL_PORT1_AWID, 0xa);
170 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
171 S2A_DOORBELL_ENTRY_1_CTRL,
172 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0xa);
173 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
174 S2A_DOORBELL_ENTRY_1_CTRL,
175 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
176 0x9);
177 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_6_CTRL,
178 aid_id, doorbell_ctrl);
179 break;
180 default:
181 break;
182 }
183}
184
185static void nbio_v7_9_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
186 int doorbell_index, int instance)
187{
188 u32 doorbell_range = 0, doorbell_ctrl = 0;
189 u32 aid_id = instance;
190
191 if (use_doorbell) {
192 doorbell_range = REG_SET_FIELD(doorbell_range,
193 DOORBELL0_CTRL_ENTRY_0,
194 BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
195 doorbell_index);
196 doorbell_range = REG_SET_FIELD(doorbell_range,
197 DOORBELL0_CTRL_ENTRY_0,
198 BIF_DOORBELL0_RANGE_SIZE_ENTRY,
199 0x9);
200 if (aid_id)
201 doorbell_range = REG_SET_FIELD(doorbell_range,
202 DOORBELL0_CTRL_ENTRY_0,
203 DOORBELL0_FENCE_ENABLE_ENTRY,
204 0x4);
205
206 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
207 S2A_DOORBELL_ENTRY_1_CTRL,
208 S2A_DOORBELL_PORT1_ENABLE, 1);
209 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
210 S2A_DOORBELL_ENTRY_1_CTRL,
211 S2A_DOORBELL_PORT1_AWID, 0x4);
212 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
213 S2A_DOORBELL_ENTRY_1_CTRL,
214 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0x4);
215 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
216 S2A_DOORBELL_ENTRY_1_CTRL,
217 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x9);
218 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
219 S2A_DOORBELL_ENTRY_1_CTRL,
220 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0x4);
221
222 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
223 aid_id, doorbell_range);
224 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
225 aid_id, doorbell_ctrl);
226 } else {
227 doorbell_range = REG_SET_FIELD(doorbell_range,
228 DOORBELL0_CTRL_ENTRY_0,
229 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
230 doorbell_ctrl = REG_SET_FIELD(doorbell_ctrl,
231 S2A_DOORBELL_ENTRY_1_CTRL,
232 S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
233
234 WREG32_SOC15_OFFSET(NBIO, 0, regDOORBELL0_CTRL_ENTRY_17,
235 aid_id, doorbell_range);
236 WREG32_SOC15_EXT(NBIO, aid_id, regS2A_DOORBELL_ENTRY_4_CTRL,
237 aid_id, doorbell_ctrl);
238 }
239}
240
241static void nbio_v7_9_enable_doorbell_aperture(struct amdgpu_device *adev,
242 bool enable)
243{
244 /* Enable to allow doorbell pass thru on pre-silicon bare-metal */
245 WREG32_SOC15(NBIO, 0, regBIFC_DOORBELL_ACCESS_EN_PF, 0xfffff);
246 WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
247 BIF_DOORBELL_APER_EN, enable ? 1 : 0);
248}
249
250static void nbio_v7_9_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
251 bool enable)
252{
253 u32 tmp = 0;
254
255 if (enable) {
256 tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
257 DOORBELL_SELFRING_GPA_APER_EN, 1) |
258 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
259 DOORBELL_SELFRING_GPA_APER_MODE, 1) |
260 REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
261 DOORBELL_SELFRING_GPA_APER_SIZE, 0);
262
263 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
264 lower_32_bits(adev->doorbell.base));
265 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
266 upper_32_bits(adev->doorbell.base));
267 }
268
269 WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
270}
271
272static void nbio_v7_9_ih_doorbell_range(struct amdgpu_device *adev,
273 bool use_doorbell, int doorbell_index)
274{
275 u32 ih_doorbell_range = 0, ih_doorbell_ctrl = 0;
276
277 if (use_doorbell) {
278 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
279 DOORBELL0_CTRL_ENTRY_0,
280 BIF_DOORBELL0_RANGE_OFFSET_ENTRY,
281 doorbell_index);
282 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
283 DOORBELL0_CTRL_ENTRY_0,
284 BIF_DOORBELL0_RANGE_SIZE_ENTRY,
285 0x8);
286
287 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
288 S2A_DOORBELL_ENTRY_1_CTRL,
289 S2A_DOORBELL_PORT1_ENABLE, 1);
290 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
291 S2A_DOORBELL_ENTRY_1_CTRL,
292 S2A_DOORBELL_PORT1_AWID, 0);
293 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
294 S2A_DOORBELL_ENTRY_1_CTRL,
295 S2A_DOORBELL_PORT1_RANGE_OFFSET, 0);
296 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
297 S2A_DOORBELL_ENTRY_1_CTRL,
298 S2A_DOORBELL_PORT1_RANGE_SIZE, 0x8);
299 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
300 S2A_DOORBELL_ENTRY_1_CTRL,
301 S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE, 0);
302 } else {
303 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
304 DOORBELL0_CTRL_ENTRY_0,
305 BIF_DOORBELL0_RANGE_SIZE_ENTRY, 0);
306 ih_doorbell_ctrl = REG_SET_FIELD(ih_doorbell_ctrl,
307 S2A_DOORBELL_ENTRY_1_CTRL,
308 S2A_DOORBELL_PORT1_RANGE_SIZE, 0);
309 }
310
311 WREG32_SOC15(NBIO, 0, regDOORBELL0_CTRL_ENTRY_0, ih_doorbell_range);
312 WREG32_SOC15(NBIO, 0, regS2A_DOORBELL_ENTRY_3_CTRL, ih_doorbell_ctrl);
313}
314
315
316static void nbio_v7_9_update_medium_grain_clock_gating(struct amdgpu_device *adev,
317 bool enable)
318{
319}
320
321static void nbio_v7_9_update_medium_grain_light_sleep(struct amdgpu_device *adev,
322 bool enable)
323{
324}
325
326static void nbio_v7_9_get_clockgating_state(struct amdgpu_device *adev,
327 u64 *flags)
328{
329}
330
331static void nbio_v7_9_ih_control(struct amdgpu_device *adev)
332{
333 u32 interrupt_cntl;
334
335 /* setup interrupt control */
336 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
337 interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
338 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
339 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
340 */
341 interrupt_cntl =
342 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
343 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
344 interrupt_cntl =
345 REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
346 WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
347}
348
349static u32 nbio_v7_9_get_hdp_flush_req_offset(struct amdgpu_device *adev)
350{
351 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_REQ);
352}
353
354static u32 nbio_v7_9_get_hdp_flush_done_offset(struct amdgpu_device *adev)
355{
356 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX_PF0_GPU_HDP_FLUSH_DONE);
357}
358
359static u32 nbio_v7_9_get_pcie_index_offset(struct amdgpu_device *adev)
360{
361 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
362}
363
364static u32 nbio_v7_9_get_pcie_data_offset(struct amdgpu_device *adev)
365{
366 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
367}
368
369static u32 nbio_v7_9_get_pcie_index_hi_offset(struct amdgpu_device *adev)
370{
371 return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI);
372}
373
374const struct nbio_hdp_flush_reg nbio_v7_9_hdp_flush_reg = {
375 .ref_and_mask_cp0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK,
376 .ref_and_mask_cp1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK,
377 .ref_and_mask_cp2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK,
378 .ref_and_mask_cp3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK,
379 .ref_and_mask_cp4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK,
380 .ref_and_mask_cp5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK,
381 .ref_and_mask_cp6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK,
382 .ref_and_mask_cp7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK,
383 .ref_and_mask_cp8 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK,
384 .ref_and_mask_cp9 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK,
385 .ref_and_mask_sdma0 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK,
386 .ref_and_mask_sdma1 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK,
387 .ref_and_mask_sdma2 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
388 .ref_and_mask_sdma3 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
389 .ref_and_mask_sdma4 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
390 .ref_and_mask_sdma5 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
391 .ref_and_mask_sdma6 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
392 .ref_and_mask_sdma7 = BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
393};
394
395static void nbio_v7_9_enable_doorbell_interrupt(struct amdgpu_device *adev,
396 bool enable)
397{
398 WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL,
399 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
400}
401
402static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev)
403{
404 u32 tmp, px;
405
406 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
407 px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
408 PARTITION_MODE);
409
410 return px;
411}
412
413static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev,
414 u32 *supp_modes)
415{
416 u32 tmp;
417
418 tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
419 tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
420
421 if (supp_modes) {
422 *supp_modes =
423 RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);
424 }
425
426 return ffs(tmp);
427}
428
429static void nbio_v7_9_init_registers(struct amdgpu_device *adev)
430{
431 u32 inst_mask;
432 int i;
433
434 if (amdgpu_sriov_vf(adev))
435 adev->rmmio_remap.reg_offset =
436 SOC15_REG_OFFSET(
437 NBIO, 0,
438 regBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
439 << 2;
440 WREG32_SOC15(NBIO, 0, regXCC_DOORBELL_FENCE,
441 0xff & ~(adev->gfx.xcc_mask));
442
443 WREG32_SOC15(NBIO, 0, regBIFC_GFX_INT_MONITOR_MASK, 0x7ff);
444
445 inst_mask = adev->aid_mask & ~1U;
446 for_each_inst(i, inst_mask) {
447 WREG32_SOC15_EXT(NBIO, i, regXCC_DOORBELL_FENCE, i,
448 XCC_DOORBELL_FENCE__SHUB_SLV_MODE_MASK);
449
450 }
451
452 if (!amdgpu_sriov_vf(adev)) {
453 u32 baco_cntl;
454 for_each_inst(i, adev->aid_mask) {
455 baco_cntl = RREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL);
456 if (baco_cntl & (BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
457 BIF_BX0_BACO_CNTL__BACO_EN_MASK)) {
458 baco_cntl &= ~(
459 BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK |
460 BIF_BX0_BACO_CNTL__BACO_EN_MASK);
461 dev_dbg(adev->dev,
462 "Unsetting baco dummy mode %x",
463 baco_cntl);
464 WREG32_SOC15(NBIO, i, regBIF_BX0_BACO_CNTL,
465 baco_cntl);
466 }
467 }
468 }
469}
470
471static u64 nbio_v7_9_get_pcie_replay_count(struct amdgpu_device *adev)
472{
473 u32 val, nak_r, nak_g;
474
475 if (adev->flags & AMD_IS_APU)
476 return 0;
477
478 /* Get the number of NAKs received and generated */
479 val = RREG32_PCIE(smnPCIEP_NAK_COUNTER);
480 nak_r = val & 0xFFFF;
481 nak_g = val >> 16;
482
483 /* Add the total number of NAKs, i.e the number of replays */
484 return (nak_r + nak_g);
485}
486
487static void nbio_v7_9_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
488 uint64_t *count1)
489{
490 uint32_t perfctrrx = 0;
491 uint32_t perfctrtx = 0;
492
493 /* This reports 0 on APUs, so return to avoid writing/reading registers
494 * that may or may not be different from their GPU counterparts
495 */
496 if (adev->flags & AMD_IS_APU)
497 return;
498
499 /* Use TXCLK3 counter group for rx event */
500 /* Use TXCLK7 counter group for tx event */
501 /* Set the 2 events that we wish to watch, defined above */
502 /* 40 is event# for received msgs */
503 /* 2 is event# of posted requests sent */
504 perfctrrx = REG_SET_FIELD(perfctrrx, PCIE_PERF_CNTL_TXCLK3, EVENT0_SEL, 40);
505 perfctrtx = REG_SET_FIELD(perfctrtx, PCIE_PERF_CNTL_TXCLK7, EVENT0_SEL, 2);
506
507 /* Write to enable desired perf counters */
508 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3, perfctrrx);
509 WREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK7, perfctrtx);
510
511 /* Zero out and enable SHADOW_WR
512 * Write 0x6:
513 * Bit 1 = Global Shadow wr(1)
514 * Bit 2 = Global counter reset enable(1)
515 */
516 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006);
517
518 /* Enable Gloabl Counter
519 * Write 0x1:
520 * Bit 0 = Global Counter Enable(1)
521 */
522 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000001);
523
524 msleep(1000);
525
526 /* Disable Global Counter, Reset and enable SHADOW_WR
527 * Write 0x6:
528 * Bit 1 = Global Shadow wr(1)
529 * Bit 2 = Global counter reset enable(1)
530 */
531 WREG32_PCIE(smnPCIE_PERF_COUNT_CNTL, 0x00000006);
532
533 /* Get the upper and lower count */
534 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) |
535 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK3) << 32);
536 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK7) |
537 ((uint64_t)RREG32_PCIE(smnPCIE_PERF_COUNT0_UPVAL_TXCLK7) << 32);
538}
539
540const struct amdgpu_nbio_funcs nbio_v7_9_funcs = {
541 .get_hdp_flush_req_offset = nbio_v7_9_get_hdp_flush_req_offset,
542 .get_hdp_flush_done_offset = nbio_v7_9_get_hdp_flush_done_offset,
543 .get_pcie_index_offset = nbio_v7_9_get_pcie_index_offset,
544 .get_pcie_data_offset = nbio_v7_9_get_pcie_data_offset,
545 .get_pcie_index_hi_offset = nbio_v7_9_get_pcie_index_hi_offset,
546 .get_rev_id = nbio_v7_9_get_rev_id,
547 .mc_access_enable = nbio_v7_9_mc_access_enable,
548 .get_memsize = nbio_v7_9_get_memsize,
549 .sdma_doorbell_range = nbio_v7_9_sdma_doorbell_range,
550 .vcn_doorbell_range = nbio_v7_9_vcn_doorbell_range,
551 .enable_doorbell_aperture = nbio_v7_9_enable_doorbell_aperture,
552 .enable_doorbell_selfring_aperture = nbio_v7_9_enable_doorbell_selfring_aperture,
553 .ih_doorbell_range = nbio_v7_9_ih_doorbell_range,
554 .enable_doorbell_interrupt = nbio_v7_9_enable_doorbell_interrupt,
555 .update_medium_grain_clock_gating = nbio_v7_9_update_medium_grain_clock_gating,
556 .update_medium_grain_light_sleep = nbio_v7_9_update_medium_grain_light_sleep,
557 .get_clockgating_state = nbio_v7_9_get_clockgating_state,
558 .ih_control = nbio_v7_9_ih_control,
559 .remap_hdp_registers = nbio_v7_9_remap_hdp_registers,
560 .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode,
561 .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode,
562 .init_registers = nbio_v7_9_init_registers,
563 .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count,
564 .get_pcie_usage = nbio_v7_9_get_pcie_usage,
565};
566
567static void nbio_v7_9_query_ras_error_count(struct amdgpu_device *adev,
568 void *ras_error_status)
569{
570}
571
572static void nbio_v7_9_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
573{
574 uint32_t bif_doorbell_intr_cntl;
575 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
576 struct ras_err_data err_data;
577 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
578
579 if (amdgpu_ras_error_data_init(&err_data))
580 return;
581
582 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
583
584 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
585 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
586 /* driver has to clear the interrupt status when bif ring is disabled */
587 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
588 BIF_BX0_BIF_DOORBELL_INT_CNTL,
589 RAS_CNTLR_INTERRUPT_CLEAR, 1);
590 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
591
592 if (!ras->disable_ras_err_cnt_harvest) {
593 /*
594 * clear error status after ras_controller_intr
595 * according to hw team and count ue number
596 * for query
597 */
598 nbio_v7_9_query_ras_error_count(adev, &err_data);
599
600 /* logging on error cnt and printing for awareness */
601 obj->err_data.ue_count += err_data.ue_count;
602 obj->err_data.ce_count += err_data.ce_count;
603
604 if (err_data.ce_count)
605 dev_info(adev->dev, "%ld correctable hardware "
606 "errors detected in %s block\n",
607 obj->err_data.ce_count,
608 get_ras_block_str(adev->nbio.ras_if));
609
610 if (err_data.ue_count)
611 dev_info(adev->dev, "%ld uncorrectable hardware "
612 "errors detected in %s block\n",
613 obj->err_data.ue_count,
614 get_ras_block_str(adev->nbio.ras_if));
615 }
616
617 dev_info(adev->dev, "RAS controller interrupt triggered "
618 "by NBIF error\n");
619 }
620
621 amdgpu_ras_error_data_fini(&err_data);
622}
623
624static void nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
625{
626 uint32_t bif_doorbell_intr_cntl;
627
628 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
629
630 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
631 BIF_BX0_BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
632 /* driver has to clear the interrupt status when bif ring is disabled */
633 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
634 BIF_BX0_BIF_DOORBELL_INT_CNTL,
635 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
636
637 WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
638
639 amdgpu_ras_global_ras_isr(adev);
640 }
641}
642
643static int nbio_v7_9_set_ras_controller_irq_state(struct amdgpu_device *adev,
644 struct amdgpu_irq_src *src,
645 unsigned type,
646 enum amdgpu_interrupt_state state)
647{
648 /* Dummy function, there is no initialization operation in driver */
649
650 return 0;
651}
652
653static int nbio_v7_9_process_ras_controller_irq(struct amdgpu_device *adev,
654 struct amdgpu_irq_src *source,
655 struct amdgpu_iv_entry *entry)
656{
657 /* By design, the ih cookie for ras_controller_irq should be written
658 * to BIFring instead of general iv ring. However, due to known bif ring
659 * hw bug, it has to be disabled. There is no chance the process function
660 * will be involked. Just left it as a dummy one.
661 */
662 return 0;
663}
664
665static int nbio_v7_9_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
666 struct amdgpu_irq_src *src,
667 unsigned type,
668 enum amdgpu_interrupt_state state)
669{
670 /* Dummy function, there is no initialization operation in driver */
671
672 return 0;
673}
674
675static int nbio_v7_9_process_err_event_athub_irq(struct amdgpu_device *adev,
676 struct amdgpu_irq_src *source,
677 struct amdgpu_iv_entry *entry)
678{
679 /* By design, the ih cookie for err_event_athub_irq should be written
680 * to BIFring instead of general iv ring. However, due to known bif ring
681 * hw bug, it has to be disabled. There is no chance the process function
682 * will be involked. Just left it as a dummy one.
683 */
684 return 0;
685}
686
687static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_controller_irq_funcs = {
688 .set = nbio_v7_9_set_ras_controller_irq_state,
689 .process = nbio_v7_9_process_ras_controller_irq,
690};
691
692static const struct amdgpu_irq_src_funcs nbio_v7_9_ras_err_event_athub_irq_funcs = {
693 .set = nbio_v7_9_set_ras_err_event_athub_irq_state,
694 .process = nbio_v7_9_process_err_event_athub_irq,
695};
696
697static int nbio_v7_9_init_ras_controller_interrupt (struct amdgpu_device *adev)
698{
699 int r;
700
701 /* init the irq funcs */
702 adev->nbio.ras_controller_irq.funcs =
703 &nbio_v7_9_ras_controller_irq_funcs;
704 adev->nbio.ras_controller_irq.num_types = 1;
705
706 /* register ras controller interrupt */
707 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
708 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
709 &adev->nbio.ras_controller_irq);
710
711 return r;
712}
713
714static int nbio_v7_9_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
715{
716
717 int r;
718
719 /* init the irq funcs */
720 adev->nbio.ras_err_event_athub_irq.funcs =
721 &nbio_v7_9_ras_err_event_athub_irq_funcs;
722 adev->nbio.ras_err_event_athub_irq.num_types = 1;
723
724 /* register ras err event athub interrupt */
725 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
726 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
727 &adev->nbio.ras_err_event_athub_irq);
728
729 return r;
730}
731
732const struct amdgpu_ras_block_hw_ops nbio_v7_9_ras_hw_ops = {
733 .query_ras_error_count = nbio_v7_9_query_ras_error_count,
734};
735
736struct amdgpu_nbio_ras nbio_v7_9_ras = {
737 .ras_block = {
738 .ras_comm = {
739 .name = "pcie_bif",
740 .block = AMDGPU_RAS_BLOCK__PCIE_BIF,
741 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
742 },
743 .hw_ops = &nbio_v7_9_ras_hw_ops,
744 .ras_late_init = amdgpu_nbio_ras_late_init,
745 },
746 .handle_ras_controller_intr_no_bifring = nbio_v7_9_handle_ras_controller_intr_no_bifring,
747 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_9_handle_ras_err_event_athub_intr_no_bifring,
748 .init_ras_controller_interrupt = nbio_v7_9_init_ras_controller_interrupt,
749 .init_ras_err_event_athub_interrupt = nbio_v7_9_init_ras_err_event_athub_interrupt,
750};