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1/*
2 * intel-mid.h: Intel MID specific setup code
3 *
4 * (C) Copyright 2009 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; version 2
9 * of the License.
10 */
11#ifndef _ASM_X86_INTEL_MID_H
12#define _ASM_X86_INTEL_MID_H
13
14#include <linux/sfi.h>
15#include <linux/platform_device.h>
16
17extern int intel_mid_pci_init(void);
18extern int get_gpio_by_name(const char *name);
19extern void intel_scu_device_register(struct platform_device *pdev);
20extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
21extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
22extern int sfi_mrtc_num;
23extern struct sfi_rtc_table_entry sfi_mrtc_array[];
24
25/*
26 * Here defines the array of devices platform data that IAFW would export
27 * through SFI "DEVS" table, we use name and type to match the device and
28 * its platform data.
29 */
30struct devs_id {
31 char name[SFI_NAME_LEN + 1];
32 u8 type;
33 u8 delay;
34 void *(*get_platform_data)(void *info);
35 /* Custom handler for devices */
36 void (*device_handler)(struct sfi_device_table_entry *pentry,
37 struct devs_id *dev);
38};
39
40#define sfi_device(i) \
41 static const struct devs_id *const __intel_mid_sfi_##i##_dev __used \
42 __attribute__((__section__(".x86_intel_mid_dev.init"))) = &i
43
44/*
45 * Medfield is the follow-up of Moorestown, it combines two chip solution into
46 * one. Other than that it also added always-on and constant tsc and lapic
47 * timers. Medfield is the platform name, and the chip name is called Penwell
48 * we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
49 * identified via MSRs.
50 */
51enum intel_mid_cpu_type {
52 /* 1 was Moorestown */
53 INTEL_MID_CPU_CHIP_PENWELL = 2,
54 INTEL_MID_CPU_CHIP_CLOVERVIEW,
55 INTEL_MID_CPU_CHIP_TANGIER,
56};
57
58extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
59
60/**
61 * struct intel_mid_ops - Interface between intel-mid & sub archs
62 * @arch_setup: arch_setup function to re-initialize platform
63 * structures (x86_init, x86_platform_init)
64 *
65 * This structure can be extended if any new interface is required
66 * between intel-mid & its sub arch files.
67 */
68struct intel_mid_ops {
69 void (*arch_setup)(void);
70};
71
72/* Helper API's for INTEL_MID_OPS_INIT */
73#define DECLARE_INTEL_MID_OPS_INIT(cpuname, cpuid) \
74 [cpuid] = get_##cpuname##_ops
75
76/* Maximum number of CPU ops */
77#define MAX_CPU_OPS(a) (sizeof(a)/sizeof(void *))
78
79/*
80 * For every new cpu addition, a weak get_<cpuname>_ops() function needs be
81 * declared in arch/x86/platform/intel_mid/intel_mid_weak_decls.h.
82 */
83#define INTEL_MID_OPS_INIT {\
84 DECLARE_INTEL_MID_OPS_INIT(penwell, INTEL_MID_CPU_CHIP_PENWELL), \
85 DECLARE_INTEL_MID_OPS_INIT(cloverview, INTEL_MID_CPU_CHIP_CLOVERVIEW), \
86 DECLARE_INTEL_MID_OPS_INIT(tangier, INTEL_MID_CPU_CHIP_TANGIER) \
87};
88
89#ifdef CONFIG_X86_INTEL_MID
90
91static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
92{
93 return __intel_mid_cpu_chip;
94}
95
96static inline bool intel_mid_has_msic(void)
97{
98 return (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_PENWELL);
99}
100
101#else /* !CONFIG_X86_INTEL_MID */
102
103#define intel_mid_identify_cpu() (0)
104#define intel_mid_has_msic() (0)
105
106#endif /* !CONFIG_X86_INTEL_MID */
107
108enum intel_mid_timer_options {
109 INTEL_MID_TIMER_DEFAULT,
110 INTEL_MID_TIMER_APBT_ONLY,
111 INTEL_MID_TIMER_LAPIC_APBT,
112};
113
114extern enum intel_mid_timer_options intel_mid_timer_options;
115
116/*
117 * Penwell uses spread spectrum clock, so the freq number is not exactly
118 * the same as reported by MSR based on SDM.
119 */
120#define FSB_FREQ_83SKU 83200
121#define FSB_FREQ_100SKU 99840
122#define FSB_FREQ_133SKU 133000
123
124#define FSB_FREQ_167SKU 167000
125#define FSB_FREQ_200SKU 200000
126#define FSB_FREQ_267SKU 267000
127#define FSB_FREQ_333SKU 333000
128#define FSB_FREQ_400SKU 400000
129
130/* Bus Select SoC Fuse value */
131#define BSEL_SOC_FUSE_MASK 0x7
132#define BSEL_SOC_FUSE_001 0x1 /* FSB 133MHz */
133#define BSEL_SOC_FUSE_101 0x5 /* FSB 100MHz */
134#define BSEL_SOC_FUSE_111 0x7 /* FSB 83MHz */
135
136#define SFI_MTMR_MAX_NUM 8
137#define SFI_MRTC_MAX 8
138
139extern void intel_scu_devices_create(void);
140extern void intel_scu_devices_destroy(void);
141
142/* VRTC timer */
143#define MRST_VRTC_MAP_SZ (1024)
144/*#define MRST_VRTC_PGOFFSET (0xc00) */
145
146extern void intel_mid_rtc_init(void);
147
148/* the offset for the mapping of global gpio pin to irq */
149#define INTEL_MID_IRQ_OFFSET 0x100
150
151#endif /* _ASM_X86_INTEL_MID_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Intel MID specific setup code
4 *
5 * (C) Copyright 2009, 2021 Intel Corporation
6 */
7#ifndef _ASM_X86_INTEL_MID_H
8#define _ASM_X86_INTEL_MID_H
9
10#include <linux/pci.h>
11
12extern int intel_mid_pci_init(void);
13extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
14extern pci_power_t intel_mid_pci_get_power_state(struct pci_dev *pdev);
15
16extern void intel_mid_pwr_power_off(void);
17
18#define INTEL_MID_PWR_LSS_OFFSET 4
19#define INTEL_MID_PWR_LSS_TYPE (1 << 7)
20
21extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
22
23#endif /* _ASM_X86_INTEL_MID_H */