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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_INTEL_FAMILY_H
3#define _ASM_X86_INTEL_FAMILY_H
4
5/*
6 * "Big Core" Processors (Branded as Core, Xeon, etc...)
7 *
8 * While adding a new CPUID for a new microarchitecture, add a new
9 * group to keep logically sorted out in chronological order. Within
10 * that group keep the CPUID for the variants sorted by model number.
11 *
12 * The defined symbol names have the following form:
13 * INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
14 * where:
15 * OPTFAMILY Describes the family of CPUs that this belongs to. Default
16 * is assumed to be "_CORE" (and should be omitted). Other values
17 * currently in use are _ATOM and _XEON_PHI
18 * MICROARCH Is the code name for the micro-architecture for this core.
19 * N.B. Not the platform name.
20 * OPTDIFF If needed, a short string to differentiate by market segment.
21 *
22 * Common OPTDIFFs:
23 *
24 * - regular client parts
25 * _L - regular mobile parts
26 * _G - parts with extra graphics on
27 * _X - regular server parts
28 * _D - micro server parts
29 * _N,_P - other mobile parts
30 * _H - premium mobile parts
31 * _S - other client parts
32 *
33 * Historical OPTDIFFs:
34 *
35 * _EP - 2 socket server parts
36 * _EX - 4+ socket server parts
37 *
38 * The #define line may optionally include a comment including platform or core
39 * names. An exception is made for skylake/kabylake where steppings seem to have gotten
40 * their own names :-(
41 */
42
43/* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
44#define INTEL_FAM6_ANY X86_MODEL_ANY
45
46#define INTEL_FAM6_CORE_YONAH 0x0E
47
48#define INTEL_FAM6_CORE2_MEROM 0x0F
49#define INTEL_FAM6_CORE2_MEROM_L 0x16
50#define INTEL_FAM6_CORE2_PENRYN 0x17
51#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
52
53#define INTEL_FAM6_NEHALEM 0x1E
54#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
55#define INTEL_FAM6_NEHALEM_EP 0x1A
56#define INTEL_FAM6_NEHALEM_EX 0x2E
57
58#define INTEL_FAM6_WESTMERE 0x25
59#define INTEL_FAM6_WESTMERE_EP 0x2C
60#define INTEL_FAM6_WESTMERE_EX 0x2F
61
62#define INTEL_FAM6_SANDYBRIDGE 0x2A
63#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
64#define INTEL_FAM6_IVYBRIDGE 0x3A
65#define INTEL_FAM6_IVYBRIDGE_X 0x3E
66
67#define INTEL_FAM6_HASWELL 0x3C
68#define INTEL_FAM6_HASWELL_X 0x3F
69#define INTEL_FAM6_HASWELL_L 0x45
70#define INTEL_FAM6_HASWELL_G 0x46
71
72#define INTEL_FAM6_BROADWELL 0x3D
73#define INTEL_FAM6_BROADWELL_G 0x47
74#define INTEL_FAM6_BROADWELL_X 0x4F
75#define INTEL_FAM6_BROADWELL_D 0x56
76
77#define INTEL_FAM6_SKYLAKE_L 0x4E /* Sky Lake */
78#define INTEL_FAM6_SKYLAKE 0x5E /* Sky Lake */
79#define INTEL_FAM6_SKYLAKE_X 0x55 /* Sky Lake */
80/* CASCADELAKE_X 0x55 Sky Lake -- s: 7 */
81/* COOPERLAKE_X 0x55 Sky Lake -- s: 11 */
82
83#define INTEL_FAM6_KABYLAKE_L 0x8E /* Sky Lake */
84/* AMBERLAKE_L 0x8E Sky Lake -- s: 9 */
85/* COFFEELAKE_L 0x8E Sky Lake -- s: 10 */
86/* WHISKEYLAKE_L 0x8E Sky Lake -- s: 11,12 */
87
88#define INTEL_FAM6_KABYLAKE 0x9E /* Sky Lake */
89/* COFFEELAKE 0x9E Sky Lake -- s: 10-13 */
90
91#define INTEL_FAM6_COMETLAKE 0xA5 /* Sky Lake */
92#define INTEL_FAM6_COMETLAKE_L 0xA6 /* Sky Lake */
93
94#define INTEL_FAM6_CANNONLAKE_L 0x66 /* Palm Cove */
95
96#define INTEL_FAM6_ICELAKE_X 0x6A /* Sunny Cove */
97#define INTEL_FAM6_ICELAKE_D 0x6C /* Sunny Cove */
98#define INTEL_FAM6_ICELAKE 0x7D /* Sunny Cove */
99#define INTEL_FAM6_ICELAKE_L 0x7E /* Sunny Cove */
100#define INTEL_FAM6_ICELAKE_NNPI 0x9D /* Sunny Cove */
101
102#define INTEL_FAM6_ROCKETLAKE 0xA7 /* Cypress Cove */
103
104#define INTEL_FAM6_TIGERLAKE_L 0x8C /* Willow Cove */
105#define INTEL_FAM6_TIGERLAKE 0x8D /* Willow Cove */
106
107#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F /* Golden Cove */
108
109#define INTEL_FAM6_EMERALDRAPIDS_X 0xCF
110
111#define INTEL_FAM6_GRANITERAPIDS_X 0xAD
112#define INTEL_FAM6_GRANITERAPIDS_D 0xAE
113
114/* "Hybrid" Processors (P-Core/E-Core) */
115
116#define INTEL_FAM6_LAKEFIELD 0x8A /* Sunny Cove / Tremont */
117
118#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */
119#define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */
120
121#define INTEL_FAM6_RAPTORLAKE 0xB7 /* Raptor Cove / Enhanced Gracemont */
122#define INTEL_FAM6_RAPTORLAKE_P 0xBA
123#define INTEL_FAM6_RAPTORLAKE_S 0xBF
124
125#define INTEL_FAM6_METEORLAKE 0xAC
126#define INTEL_FAM6_METEORLAKE_L 0xAA
127
128#define INTEL_FAM6_ARROWLAKE_H 0xC5
129#define INTEL_FAM6_ARROWLAKE 0xC6
130
131#define INTEL_FAM6_LUNARLAKE_M 0xBD
132
133/* "Small Core" Processors (Atom/E-Core) */
134
135#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
136#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
137
138#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
139#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
140#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
141
142#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
143#define INTEL_FAM6_ATOM_SILVERMONT_D 0x4D /* Avaton, Rangely */
144#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
145
146#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
147#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
148#define INTEL_FAM6_ATOM_AIRMONT_NP 0x75 /* Lightning Mountain */
149
150#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
151#define INTEL_FAM6_ATOM_GOLDMONT_D 0x5F /* Denverton */
152
153/* Note: the micro-architecture is "Goldmont Plus" */
154#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
155
156#define INTEL_FAM6_ATOM_TREMONT_D 0x86 /* Jacobsville */
157#define INTEL_FAM6_ATOM_TREMONT 0x96 /* Elkhart Lake */
158#define INTEL_FAM6_ATOM_TREMONT_L 0x9C /* Jasper Lake */
159
160#define INTEL_FAM6_ATOM_GRACEMONT 0xBE /* Alderlake N */
161
162#define INTEL_FAM6_ATOM_CRESTMONT_X 0xAF /* Sierra Forest */
163#define INTEL_FAM6_ATOM_CRESTMONT 0xB6 /* Grand Ridge */
164
165#define INTEL_FAM6_ATOM_DARKMONT_X 0xDD /* Clearwater Forest */
166
167/* Xeon Phi */
168
169#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
170#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
171
172/* Family 5 */
173#define INTEL_FAM5_QUARK_X1000 0x09 /* Quark X1000 SoC */
174
175#endif /* _ASM_X86_INTEL_FAMILY_H */