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1/*
2 * linux/arch/arm/mm/alignment.c
3 *
4 * Copyright (C) 1995 Linus Torvalds
5 * Modifications for ARM processor (c) 1995-2001 Russell King
6 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
7 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
8 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14#include <linux/moduleparam.h>
15#include <linux/compiler.h>
16#include <linux/kernel.h>
17#include <linux/errno.h>
18#include <linux/string.h>
19#include <linux/proc_fs.h>
20#include <linux/seq_file.h>
21#include <linux/init.h>
22#include <linux/sched.h>
23#include <linux/uaccess.h>
24
25#include <asm/cp15.h>
26#include <asm/system_info.h>
27#include <asm/unaligned.h>
28#include <asm/opcodes.h>
29
30#include "fault.h"
31#include "mm.h"
32
33/*
34 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
35 * /proc/sys/debug/alignment, modified and integrated into
36 * Linux 2.1 by Russell King
37 *
38 * Speed optimisations and better fault handling by Russell King.
39 *
40 * *** NOTE ***
41 * This code is not portable to processors with late data abort handling.
42 */
43#define CODING_BITS(i) (i & 0x0e000000)
44#define COND_BITS(i) (i & 0xf0000000)
45
46#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
47#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
48#define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
49#define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
50#define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
51
52#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
53
54#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
55#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
56
57#define RN_BITS(i) ((i >> 16) & 15) /* Rn */
58#define RD_BITS(i) ((i >> 12) & 15) /* Rd */
59#define RM_BITS(i) (i & 15) /* Rm */
60
61#define REGMASK_BITS(i) (i & 0xffff)
62#define OFFSET_BITS(i) (i & 0x0fff)
63
64#define IS_SHIFT(i) (i & 0x0ff0)
65#define SHIFT_BITS(i) ((i >> 7) & 0x1f)
66#define SHIFT_TYPE(i) (i & 0x60)
67#define SHIFT_LSL 0x00
68#define SHIFT_LSR 0x20
69#define SHIFT_ASR 0x40
70#define SHIFT_RORRRX 0x60
71
72#define BAD_INSTR 0xdeadc0de
73
74/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
75#define IS_T32(hi16) \
76 (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
77
78static unsigned long ai_user;
79static unsigned long ai_sys;
80static void *ai_sys_last_pc;
81static unsigned long ai_skipped;
82static unsigned long ai_half;
83static unsigned long ai_word;
84static unsigned long ai_dword;
85static unsigned long ai_multi;
86static int ai_usermode;
87static unsigned long cr_no_alignment;
88
89core_param(alignment, ai_usermode, int, 0600);
90
91#define UM_WARN (1 << 0)
92#define UM_FIXUP (1 << 1)
93#define UM_SIGNAL (1 << 2)
94
95/* Return true if and only if the ARMv6 unaligned access model is in use. */
96static bool cpu_is_v6_unaligned(void)
97{
98 return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U;
99}
100
101static int safe_usermode(int new_usermode, bool warn)
102{
103 /*
104 * ARMv6 and later CPUs can perform unaligned accesses for
105 * most single load and store instructions up to word size.
106 * LDM, STM, LDRD and STRD still need to be handled.
107 *
108 * Ignoring the alignment fault is not an option on these
109 * CPUs since we spin re-faulting the instruction without
110 * making any progress.
111 */
112 if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
113 new_usermode |= UM_FIXUP;
114
115 if (warn)
116 pr_warn("alignment: ignoring faults is unsafe on this CPU. Defaulting to fixup mode.\n");
117 }
118
119 return new_usermode;
120}
121
122#ifdef CONFIG_PROC_FS
123static const char *usermode_action[] = {
124 "ignored",
125 "warn",
126 "fixup",
127 "fixup+warn",
128 "signal",
129 "signal+warn"
130};
131
132static int alignment_proc_show(struct seq_file *m, void *v)
133{
134 seq_printf(m, "User:\t\t%lu\n", ai_user);
135 seq_printf(m, "System:\t\t%lu (%pF)\n", ai_sys, ai_sys_last_pc);
136 seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
137 seq_printf(m, "Half:\t\t%lu\n", ai_half);
138 seq_printf(m, "Word:\t\t%lu\n", ai_word);
139 if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
140 seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
141 seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
142 seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
143 usermode_action[ai_usermode]);
144
145 return 0;
146}
147
148static int alignment_proc_open(struct inode *inode, struct file *file)
149{
150 return single_open(file, alignment_proc_show, NULL);
151}
152
153static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
154 size_t count, loff_t *pos)
155{
156 char mode;
157
158 if (count > 0) {
159 if (get_user(mode, buffer))
160 return -EFAULT;
161 if (mode >= '0' && mode <= '5')
162 ai_usermode = safe_usermode(mode - '0', true);
163 }
164 return count;
165}
166
167static const struct file_operations alignment_proc_fops = {
168 .open = alignment_proc_open,
169 .read = seq_read,
170 .llseek = seq_lseek,
171 .release = single_release,
172 .write = alignment_proc_write,
173};
174#endif /* CONFIG_PROC_FS */
175
176union offset_union {
177 unsigned long un;
178 signed long sn;
179};
180
181#define TYPE_ERROR 0
182#define TYPE_FAULT 1
183#define TYPE_LDST 2
184#define TYPE_DONE 3
185
186#ifdef __ARMEB__
187#define BE 1
188#define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
189#define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
190#define NEXT_BYTE "ror #24"
191#else
192#define BE 0
193#define FIRST_BYTE_16
194#define FIRST_BYTE_32
195#define NEXT_BYTE "lsr #8"
196#endif
197
198#define __get8_unaligned_check(ins,val,addr,err) \
199 __asm__( \
200 ARM( "1: "ins" %1, [%2], #1\n" ) \
201 THUMB( "1: "ins" %1, [%2]\n" ) \
202 THUMB( " add %2, %2, #1\n" ) \
203 "2:\n" \
204 " .pushsection .text.fixup,\"ax\"\n" \
205 " .align 2\n" \
206 "3: mov %0, #1\n" \
207 " b 2b\n" \
208 " .popsection\n" \
209 " .pushsection __ex_table,\"a\"\n" \
210 " .align 3\n" \
211 " .long 1b, 3b\n" \
212 " .popsection\n" \
213 : "=r" (err), "=&r" (val), "=r" (addr) \
214 : "0" (err), "2" (addr))
215
216#define __get16_unaligned_check(ins,val,addr) \
217 do { \
218 unsigned int err = 0, v, a = addr; \
219 __get8_unaligned_check(ins,v,a,err); \
220 val = v << ((BE) ? 8 : 0); \
221 __get8_unaligned_check(ins,v,a,err); \
222 val |= v << ((BE) ? 0 : 8); \
223 if (err) \
224 goto fault; \
225 } while (0)
226
227#define get16_unaligned_check(val,addr) \
228 __get16_unaligned_check("ldrb",val,addr)
229
230#define get16t_unaligned_check(val,addr) \
231 __get16_unaligned_check("ldrbt",val,addr)
232
233#define __get32_unaligned_check(ins,val,addr) \
234 do { \
235 unsigned int err = 0, v, a = addr; \
236 __get8_unaligned_check(ins,v,a,err); \
237 val = v << ((BE) ? 24 : 0); \
238 __get8_unaligned_check(ins,v,a,err); \
239 val |= v << ((BE) ? 16 : 8); \
240 __get8_unaligned_check(ins,v,a,err); \
241 val |= v << ((BE) ? 8 : 16); \
242 __get8_unaligned_check(ins,v,a,err); \
243 val |= v << ((BE) ? 0 : 24); \
244 if (err) \
245 goto fault; \
246 } while (0)
247
248#define get32_unaligned_check(val,addr) \
249 __get32_unaligned_check("ldrb",val,addr)
250
251#define get32t_unaligned_check(val,addr) \
252 __get32_unaligned_check("ldrbt",val,addr)
253
254#define __put16_unaligned_check(ins,val,addr) \
255 do { \
256 unsigned int err = 0, v = val, a = addr; \
257 __asm__( FIRST_BYTE_16 \
258 ARM( "1: "ins" %1, [%2], #1\n" ) \
259 THUMB( "1: "ins" %1, [%2]\n" ) \
260 THUMB( " add %2, %2, #1\n" ) \
261 " mov %1, %1, "NEXT_BYTE"\n" \
262 "2: "ins" %1, [%2]\n" \
263 "3:\n" \
264 " .pushsection .text.fixup,\"ax\"\n" \
265 " .align 2\n" \
266 "4: mov %0, #1\n" \
267 " b 3b\n" \
268 " .popsection\n" \
269 " .pushsection __ex_table,\"a\"\n" \
270 " .align 3\n" \
271 " .long 1b, 4b\n" \
272 " .long 2b, 4b\n" \
273 " .popsection\n" \
274 : "=r" (err), "=&r" (v), "=&r" (a) \
275 : "0" (err), "1" (v), "2" (a)); \
276 if (err) \
277 goto fault; \
278 } while (0)
279
280#define put16_unaligned_check(val,addr) \
281 __put16_unaligned_check("strb",val,addr)
282
283#define put16t_unaligned_check(val,addr) \
284 __put16_unaligned_check("strbt",val,addr)
285
286#define __put32_unaligned_check(ins,val,addr) \
287 do { \
288 unsigned int err = 0, v = val, a = addr; \
289 __asm__( FIRST_BYTE_32 \
290 ARM( "1: "ins" %1, [%2], #1\n" ) \
291 THUMB( "1: "ins" %1, [%2]\n" ) \
292 THUMB( " add %2, %2, #1\n" ) \
293 " mov %1, %1, "NEXT_BYTE"\n" \
294 ARM( "2: "ins" %1, [%2], #1\n" ) \
295 THUMB( "2: "ins" %1, [%2]\n" ) \
296 THUMB( " add %2, %2, #1\n" ) \
297 " mov %1, %1, "NEXT_BYTE"\n" \
298 ARM( "3: "ins" %1, [%2], #1\n" ) \
299 THUMB( "3: "ins" %1, [%2]\n" ) \
300 THUMB( " add %2, %2, #1\n" ) \
301 " mov %1, %1, "NEXT_BYTE"\n" \
302 "4: "ins" %1, [%2]\n" \
303 "5:\n" \
304 " .pushsection .text.fixup,\"ax\"\n" \
305 " .align 2\n" \
306 "6: mov %0, #1\n" \
307 " b 5b\n" \
308 " .popsection\n" \
309 " .pushsection __ex_table,\"a\"\n" \
310 " .align 3\n" \
311 " .long 1b, 6b\n" \
312 " .long 2b, 6b\n" \
313 " .long 3b, 6b\n" \
314 " .long 4b, 6b\n" \
315 " .popsection\n" \
316 : "=r" (err), "=&r" (v), "=&r" (a) \
317 : "0" (err), "1" (v), "2" (a)); \
318 if (err) \
319 goto fault; \
320 } while (0)
321
322#define put32_unaligned_check(val,addr) \
323 __put32_unaligned_check("strb", val, addr)
324
325#define put32t_unaligned_check(val,addr) \
326 __put32_unaligned_check("strbt", val, addr)
327
328static void
329do_alignment_finish_ldst(unsigned long addr, unsigned long instr, struct pt_regs *regs, union offset_union offset)
330{
331 if (!LDST_U_BIT(instr))
332 offset.un = -offset.un;
333
334 if (!LDST_P_BIT(instr))
335 addr += offset.un;
336
337 if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
338 regs->uregs[RN_BITS(instr)] = addr;
339}
340
341static int
342do_alignment_ldrhstrh(unsigned long addr, unsigned long instr, struct pt_regs *regs)
343{
344 unsigned int rd = RD_BITS(instr);
345
346 ai_half += 1;
347
348 if (user_mode(regs))
349 goto user;
350
351 if (LDST_L_BIT(instr)) {
352 unsigned long val;
353 get16_unaligned_check(val, addr);
354
355 /* signed half-word? */
356 if (instr & 0x40)
357 val = (signed long)((signed short) val);
358
359 regs->uregs[rd] = val;
360 } else
361 put16_unaligned_check(regs->uregs[rd], addr);
362
363 return TYPE_LDST;
364
365 user:
366 if (LDST_L_BIT(instr)) {
367 unsigned long val;
368 unsigned int __ua_flags = uaccess_save_and_enable();
369
370 get16t_unaligned_check(val, addr);
371 uaccess_restore(__ua_flags);
372
373 /* signed half-word? */
374 if (instr & 0x40)
375 val = (signed long)((signed short) val);
376
377 regs->uregs[rd] = val;
378 } else {
379 unsigned int __ua_flags = uaccess_save_and_enable();
380 put16t_unaligned_check(regs->uregs[rd], addr);
381 uaccess_restore(__ua_flags);
382 }
383
384 return TYPE_LDST;
385
386 fault:
387 return TYPE_FAULT;
388}
389
390static int
391do_alignment_ldrdstrd(unsigned long addr, unsigned long instr,
392 struct pt_regs *regs)
393{
394 unsigned int rd = RD_BITS(instr);
395 unsigned int rd2;
396 int load;
397
398 if ((instr & 0xfe000000) == 0xe8000000) {
399 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
400 rd2 = (instr >> 8) & 0xf;
401 load = !!(LDST_L_BIT(instr));
402 } else if (((rd & 1) == 1) || (rd == 14))
403 goto bad;
404 else {
405 load = ((instr & 0xf0) == 0xd0);
406 rd2 = rd + 1;
407 }
408
409 ai_dword += 1;
410
411 if (user_mode(regs))
412 goto user;
413
414 if (load) {
415 unsigned long val;
416 get32_unaligned_check(val, addr);
417 regs->uregs[rd] = val;
418 get32_unaligned_check(val, addr + 4);
419 regs->uregs[rd2] = val;
420 } else {
421 put32_unaligned_check(regs->uregs[rd], addr);
422 put32_unaligned_check(regs->uregs[rd2], addr + 4);
423 }
424
425 return TYPE_LDST;
426
427 user:
428 if (load) {
429 unsigned long val, val2;
430 unsigned int __ua_flags = uaccess_save_and_enable();
431
432 get32t_unaligned_check(val, addr);
433 get32t_unaligned_check(val2, addr + 4);
434
435 uaccess_restore(__ua_flags);
436
437 regs->uregs[rd] = val;
438 regs->uregs[rd2] = val2;
439 } else {
440 unsigned int __ua_flags = uaccess_save_and_enable();
441 put32t_unaligned_check(regs->uregs[rd], addr);
442 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
443 uaccess_restore(__ua_flags);
444 }
445
446 return TYPE_LDST;
447 bad:
448 return TYPE_ERROR;
449 fault:
450 return TYPE_FAULT;
451}
452
453static int
454do_alignment_ldrstr(unsigned long addr, unsigned long instr, struct pt_regs *regs)
455{
456 unsigned int rd = RD_BITS(instr);
457
458 ai_word += 1;
459
460 if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
461 goto trans;
462
463 if (LDST_L_BIT(instr)) {
464 unsigned int val;
465 get32_unaligned_check(val, addr);
466 regs->uregs[rd] = val;
467 } else
468 put32_unaligned_check(regs->uregs[rd], addr);
469 return TYPE_LDST;
470
471 trans:
472 if (LDST_L_BIT(instr)) {
473 unsigned int val;
474 unsigned int __ua_flags = uaccess_save_and_enable();
475 get32t_unaligned_check(val, addr);
476 uaccess_restore(__ua_flags);
477 regs->uregs[rd] = val;
478 } else {
479 unsigned int __ua_flags = uaccess_save_and_enable();
480 put32t_unaligned_check(regs->uregs[rd], addr);
481 uaccess_restore(__ua_flags);
482 }
483 return TYPE_LDST;
484
485 fault:
486 return TYPE_FAULT;
487}
488
489/*
490 * LDM/STM alignment handler.
491 *
492 * There are 4 variants of this instruction:
493 *
494 * B = rn pointer before instruction, A = rn pointer after instruction
495 * ------ increasing address ----->
496 * | | r0 | r1 | ... | rx | |
497 * PU = 01 B A
498 * PU = 11 B A
499 * PU = 00 A B
500 * PU = 10 A B
501 */
502static int
503do_alignment_ldmstm(unsigned long addr, unsigned long instr, struct pt_regs *regs)
504{
505 unsigned int rd, rn, correction, nr_regs, regbits;
506 unsigned long eaddr, newaddr;
507
508 if (LDM_S_BIT(instr))
509 goto bad;
510
511 correction = 4; /* processor implementation defined */
512 regs->ARM_pc += correction;
513
514 ai_multi += 1;
515
516 /* count the number of registers in the mask to be transferred */
517 nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
518
519 rn = RN_BITS(instr);
520 newaddr = eaddr = regs->uregs[rn];
521
522 if (!LDST_U_BIT(instr))
523 nr_regs = -nr_regs;
524 newaddr += nr_regs;
525 if (!LDST_U_BIT(instr))
526 eaddr = newaddr;
527
528 if (LDST_P_EQ_U(instr)) /* U = P */
529 eaddr += 4;
530
531 /*
532 * For alignment faults on the ARM922T/ARM920T the MMU makes
533 * the FSR (and hence addr) equal to the updated base address
534 * of the multiple access rather than the restored value.
535 * Switch this message off if we've got a ARM92[02], otherwise
536 * [ls]dm alignment faults are noisy!
537 */
538#if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
539 /*
540 * This is a "hint" - we already have eaddr worked out by the
541 * processor for us.
542 */
543 if (addr != eaddr) {
544 pr_err("LDMSTM: PC = %08lx, instr = %08lx, "
545 "addr = %08lx, eaddr = %08lx\n",
546 instruction_pointer(regs), instr, addr, eaddr);
547 show_regs(regs);
548 }
549#endif
550
551 if (user_mode(regs)) {
552 unsigned int __ua_flags = uaccess_save_and_enable();
553 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
554 regbits >>= 1, rd += 1)
555 if (regbits & 1) {
556 if (LDST_L_BIT(instr)) {
557 unsigned int val;
558 get32t_unaligned_check(val, eaddr);
559 regs->uregs[rd] = val;
560 } else
561 put32t_unaligned_check(regs->uregs[rd], eaddr);
562 eaddr += 4;
563 }
564 uaccess_restore(__ua_flags);
565 } else {
566 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
567 regbits >>= 1, rd += 1)
568 if (regbits & 1) {
569 if (LDST_L_BIT(instr)) {
570 unsigned int val;
571 get32_unaligned_check(val, eaddr);
572 regs->uregs[rd] = val;
573 } else
574 put32_unaligned_check(regs->uregs[rd], eaddr);
575 eaddr += 4;
576 }
577 }
578
579 if (LDST_W_BIT(instr))
580 regs->uregs[rn] = newaddr;
581 if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
582 regs->ARM_pc -= correction;
583 return TYPE_DONE;
584
585fault:
586 regs->ARM_pc -= correction;
587 return TYPE_FAULT;
588
589bad:
590 pr_err("Alignment trap: not handling ldm with s-bit set\n");
591 return TYPE_ERROR;
592}
593
594/*
595 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
596 * we can reuse ARM userland alignment fault fixups for Thumb.
597 *
598 * This implementation was initially based on the algorithm found in
599 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
600 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
601 *
602 * NOTES:
603 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
604 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
605 * decode, we return 0xdeadc0de. This should never happen under normal
606 * circumstances but if it does, we've got other problems to deal with
607 * elsewhere and we obviously can't fix those problems here.
608 */
609
610static unsigned long
611thumb2arm(u16 tinstr)
612{
613 u32 L = (tinstr & (1<<11)) >> 11;
614
615 switch ((tinstr & 0xf800) >> 11) {
616 /* 6.5.1 Format 1: */
617 case 0x6000 >> 11: /* 7.1.52 STR(1) */
618 case 0x6800 >> 11: /* 7.1.26 LDR(1) */
619 case 0x7000 >> 11: /* 7.1.55 STRB(1) */
620 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
621 return 0xe5800000 |
622 ((tinstr & (1<<12)) << (22-12)) | /* fixup */
623 (L<<20) | /* L==1? */
624 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
625 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
626 ((tinstr & (31<<6)) >> /* immed_5 */
627 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
628 case 0x8000 >> 11: /* 7.1.57 STRH(1) */
629 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
630 return 0xe1c000b0 |
631 (L<<20) | /* L==1? */
632 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
633 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
634 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */
635 ((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */
636
637 /* 6.5.1 Format 2: */
638 case 0x5000 >> 11:
639 case 0x5800 >> 11:
640 {
641 static const u32 subset[8] = {
642 0xe7800000, /* 7.1.53 STR(2) */
643 0xe18000b0, /* 7.1.58 STRH(2) */
644 0xe7c00000, /* 7.1.56 STRB(2) */
645 0xe19000d0, /* 7.1.34 LDRSB */
646 0xe7900000, /* 7.1.27 LDR(2) */
647 0xe19000b0, /* 7.1.33 LDRH(2) */
648 0xe7d00000, /* 7.1.31 LDRB(2) */
649 0xe19000f0 /* 7.1.35 LDRSH */
650 };
651 return subset[(tinstr & (7<<9)) >> 9] |
652 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
653 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
654 ((tinstr & (7<<6)) >> (6-0)); /* Rm */
655 }
656
657 /* 6.5.1 Format 3: */
658 case 0x4800 >> 11: /* 7.1.28 LDR(3) */
659 /* NOTE: This case is not technically possible. We're
660 * loading 32-bit memory data via PC relative
661 * addressing mode. So we can and should eliminate
662 * this case. But I'll leave it here for now.
663 */
664 return 0xe59f0000 |
665 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
666 ((tinstr & 255) << (2-0)); /* immed_8 */
667
668 /* 6.5.1 Format 4: */
669 case 0x9000 >> 11: /* 7.1.54 STR(3) */
670 case 0x9800 >> 11: /* 7.1.29 LDR(4) */
671 return 0xe58d0000 |
672 (L<<20) | /* L==1? */
673 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
674 ((tinstr & 255) << 2); /* immed_8 */
675
676 /* 6.6.1 Format 1: */
677 case 0xc000 >> 11: /* 7.1.51 STMIA */
678 case 0xc800 >> 11: /* 7.1.25 LDMIA */
679 {
680 u32 Rn = (tinstr & (7<<8)) >> 8;
681 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
682
683 return 0xe8800000 | W | (L<<20) | (Rn<<16) |
684 (tinstr&255);
685 }
686
687 /* 6.6.1 Format 2: */
688 case 0xb000 >> 11: /* 7.1.48 PUSH */
689 case 0xb800 >> 11: /* 7.1.47 POP */
690 if ((tinstr & (3 << 9)) == 0x0400) {
691 static const u32 subset[4] = {
692 0xe92d0000, /* STMDB sp!,{registers} */
693 0xe92d4000, /* STMDB sp!,{registers,lr} */
694 0xe8bd0000, /* LDMIA sp!,{registers} */
695 0xe8bd8000 /* LDMIA sp!,{registers,pc} */
696 };
697 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
698 (tinstr & 255); /* register_list */
699 }
700 /* Else fall through for illegal instruction case */
701
702 default:
703 return BAD_INSTR;
704 }
705}
706
707/*
708 * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
709 * handlable by ARM alignment handler, also find the corresponding handler,
710 * so that we can reuse ARM userland alignment fault fixups for Thumb.
711 *
712 * @pinstr: original Thumb-2 instruction; returns new handlable instruction
713 * @regs: register context.
714 * @poffset: return offset from faulted addr for later writeback
715 *
716 * NOTES:
717 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
718 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
719 */
720static void *
721do_alignment_t32_to_handler(unsigned long *pinstr, struct pt_regs *regs,
722 union offset_union *poffset)
723{
724 unsigned long instr = *pinstr;
725 u16 tinst1 = (instr >> 16) & 0xffff;
726 u16 tinst2 = instr & 0xffff;
727
728 switch (tinst1 & 0xffe0) {
729 /* A6.3.5 Load/Store multiple */
730 case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
731 case 0xe8a0: /* ...above writeback version */
732 case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */
733 case 0xe920: /* ...above writeback version */
734 /* no need offset decision since handler calculates it */
735 return do_alignment_ldmstm;
736
737 case 0xf840: /* POP/PUSH T3 (single register) */
738 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
739 u32 L = !!(LDST_L_BIT(instr));
740 const u32 subset[2] = {
741 0xe92d0000, /* STMDB sp!,{registers} */
742 0xe8bd0000, /* LDMIA sp!,{registers} */
743 };
744 *pinstr = subset[L] | (1<<RD_BITS(instr));
745 return do_alignment_ldmstm;
746 }
747 /* Else fall through for illegal instruction case */
748 break;
749
750 /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
751 case 0xe860:
752 case 0xe960:
753 case 0xe8e0:
754 case 0xe9e0:
755 poffset->un = (tinst2 & 0xff) << 2;
756 case 0xe940:
757 case 0xe9c0:
758 return do_alignment_ldrdstrd;
759
760 /*
761 * No need to handle load/store instructions up to word size
762 * since ARMv6 and later CPUs can perform unaligned accesses.
763 */
764 default:
765 break;
766 }
767 return NULL;
768}
769
770static int
771do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
772{
773 union offset_union uninitialized_var(offset);
774 unsigned long instr = 0, instrptr;
775 int (*handler)(unsigned long addr, unsigned long instr, struct pt_regs *regs);
776 unsigned int type;
777 unsigned int fault;
778 u16 tinstr = 0;
779 int isize = 4;
780 int thumb2_32b = 0;
781
782 if (interrupts_enabled(regs))
783 local_irq_enable();
784
785 instrptr = instruction_pointer(regs);
786
787 if (thumb_mode(regs)) {
788 u16 *ptr = (u16 *)(instrptr & ~1);
789 fault = probe_kernel_address(ptr, tinstr);
790 tinstr = __mem_to_opcode_thumb16(tinstr);
791 if (!fault) {
792 if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
793 IS_T32(tinstr)) {
794 /* Thumb-2 32-bit */
795 u16 tinst2 = 0;
796 fault = probe_kernel_address(ptr + 1, tinst2);
797 tinst2 = __mem_to_opcode_thumb16(tinst2);
798 instr = __opcode_thumb32_compose(tinstr, tinst2);
799 thumb2_32b = 1;
800 } else {
801 isize = 2;
802 instr = thumb2arm(tinstr);
803 }
804 }
805 } else {
806 fault = probe_kernel_address((void *)instrptr, instr);
807 instr = __mem_to_opcode_arm(instr);
808 }
809
810 if (fault) {
811 type = TYPE_FAULT;
812 goto bad_or_fault;
813 }
814
815 if (user_mode(regs))
816 goto user;
817
818 ai_sys += 1;
819 ai_sys_last_pc = (void *)instruction_pointer(regs);
820
821 fixup:
822
823 regs->ARM_pc += isize;
824
825 switch (CODING_BITS(instr)) {
826 case 0x00000000: /* 3.13.4 load/store instruction extensions */
827 if (LDSTHD_I_BIT(instr))
828 offset.un = (instr & 0xf00) >> 4 | (instr & 15);
829 else
830 offset.un = regs->uregs[RM_BITS(instr)];
831
832 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
833 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */
834 handler = do_alignment_ldrhstrh;
835 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
836 (instr & 0x001000f0) == 0x000000f0) /* STRD */
837 handler = do_alignment_ldrdstrd;
838 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
839 goto swp;
840 else
841 goto bad;
842 break;
843
844 case 0x04000000: /* ldr or str immediate */
845 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
846 goto bad;
847 offset.un = OFFSET_BITS(instr);
848 handler = do_alignment_ldrstr;
849 break;
850
851 case 0x06000000: /* ldr or str register */
852 offset.un = regs->uregs[RM_BITS(instr)];
853
854 if (IS_SHIFT(instr)) {
855 unsigned int shiftval = SHIFT_BITS(instr);
856
857 switch(SHIFT_TYPE(instr)) {
858 case SHIFT_LSL:
859 offset.un <<= shiftval;
860 break;
861
862 case SHIFT_LSR:
863 offset.un >>= shiftval;
864 break;
865
866 case SHIFT_ASR:
867 offset.sn >>= shiftval;
868 break;
869
870 case SHIFT_RORRRX:
871 if (shiftval == 0) {
872 offset.un >>= 1;
873 if (regs->ARM_cpsr & PSR_C_BIT)
874 offset.un |= 1 << 31;
875 } else
876 offset.un = offset.un >> shiftval |
877 offset.un << (32 - shiftval);
878 break;
879 }
880 }
881 handler = do_alignment_ldrstr;
882 break;
883
884 case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */
885 if (thumb2_32b) {
886 offset.un = 0;
887 handler = do_alignment_t32_to_handler(&instr, regs, &offset);
888 } else {
889 offset.un = 0;
890 handler = do_alignment_ldmstm;
891 }
892 break;
893
894 default:
895 goto bad;
896 }
897
898 if (!handler)
899 goto bad;
900 type = handler(addr, instr, regs);
901
902 if (type == TYPE_ERROR || type == TYPE_FAULT) {
903 regs->ARM_pc -= isize;
904 goto bad_or_fault;
905 }
906
907 if (type == TYPE_LDST)
908 do_alignment_finish_ldst(addr, instr, regs, offset);
909
910 return 0;
911
912 bad_or_fault:
913 if (type == TYPE_ERROR)
914 goto bad;
915 /*
916 * We got a fault - fix it up, or die.
917 */
918 do_bad_area(addr, fsr, regs);
919 return 0;
920
921 swp:
922 pr_err("Alignment trap: not handling swp instruction\n");
923
924 bad:
925 /*
926 * Oops, we didn't handle the instruction.
927 */
928 pr_err("Alignment trap: not handling instruction "
929 "%0*lx at [<%08lx>]\n",
930 isize << 1,
931 isize == 2 ? tinstr : instr, instrptr);
932 ai_skipped += 1;
933 return 1;
934
935 user:
936 ai_user += 1;
937
938 if (ai_usermode & UM_WARN)
939 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*lx "
940 "Address=0x%08lx FSR 0x%03x\n", current->comm,
941 task_pid_nr(current), instrptr,
942 isize << 1,
943 isize == 2 ? tinstr : instr,
944 addr, fsr);
945
946 if (ai_usermode & UM_FIXUP)
947 goto fixup;
948
949 if (ai_usermode & UM_SIGNAL) {
950 siginfo_t si;
951
952 si.si_signo = SIGBUS;
953 si.si_errno = 0;
954 si.si_code = BUS_ADRALN;
955 si.si_addr = (void __user *)addr;
956
957 force_sig_info(si.si_signo, &si, current);
958 } else {
959 /*
960 * We're about to disable the alignment trap and return to
961 * user space. But if an interrupt occurs before actually
962 * reaching user space, then the IRQ vector entry code will
963 * notice that we were still in kernel space and therefore
964 * the alignment trap won't be re-enabled in that case as it
965 * is presumed to be always on from kernel space.
966 * Let's prevent that race by disabling interrupts here (they
967 * are disabled on the way back to user space anyway in
968 * entry-common.S) and disable the alignment trap only if
969 * there is no work pending for this thread.
970 */
971 raw_local_irq_disable();
972 if (!(current_thread_info()->flags & _TIF_WORK_MASK))
973 set_cr(cr_no_alignment);
974 }
975
976 return 0;
977}
978
979static int __init noalign_setup(char *__unused)
980{
981 set_cr(__clear_cr(CR_A));
982 return 1;
983}
984__setup("noalign", noalign_setup);
985
986/*
987 * This needs to be done after sysctl_init, otherwise sys/ will be
988 * overwritten. Actually, this shouldn't be in sys/ at all since
989 * it isn't a sysctl, and it doesn't contain sysctl information.
990 * We now locate it in /proc/cpu/alignment instead.
991 */
992static int __init alignment_init(void)
993{
994#ifdef CONFIG_PROC_FS
995 struct proc_dir_entry *res;
996
997 res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
998 &alignment_proc_fops);
999 if (!res)
1000 return -ENOMEM;
1001#endif
1002
1003 if (cpu_is_v6_unaligned()) {
1004 set_cr(__clear_cr(CR_A));
1005 ai_usermode = safe_usermode(ai_usermode, false);
1006 }
1007
1008 cr_no_alignment = get_cr() & ~CR_A;
1009
1010 hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
1011 "alignment exception");
1012
1013 /*
1014 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
1015 * fault, not as alignment error.
1016 *
1017 * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
1018 * needed.
1019 */
1020 if (cpu_architecture() <= CPU_ARCH_ARMv6) {
1021 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
1022 "alignment exception");
1023 }
1024
1025 return 0;
1026}
1027
1028fs_initcall(alignment_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mm/alignment.c
4 *
5 * Copyright (C) 1995 Linus Torvalds
6 * Modifications for ARM processor (c) 1995-2001 Russell King
7 * Thumb alignment fault fixups (c) 2004 MontaVista Software, Inc.
8 * - Adapted from gdb/sim/arm/thumbemu.c -- Thumb instruction emulation.
9 * Copyright (C) 1996, Cygnus Software Technologies Ltd.
10 */
11#include <linux/moduleparam.h>
12#include <linux/compiler.h>
13#include <linux/kernel.h>
14#include <linux/sched/debug.h>
15#include <linux/errno.h>
16#include <linux/string.h>
17#include <linux/proc_fs.h>
18#include <linux/seq_file.h>
19#include <linux/init.h>
20#include <linux/sched/signal.h>
21#include <linux/uaccess.h>
22
23#include <asm/cp15.h>
24#include <asm/system_info.h>
25#include <asm/unaligned.h>
26#include <asm/opcodes.h>
27
28#include "fault.h"
29#include "mm.h"
30
31/*
32 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
33 * /proc/sys/debug/alignment, modified and integrated into
34 * Linux 2.1 by Russell King
35 *
36 * Speed optimisations and better fault handling by Russell King.
37 *
38 * *** NOTE ***
39 * This code is not portable to processors with late data abort handling.
40 */
41#define CODING_BITS(i) (i & 0x0e000000)
42#define COND_BITS(i) (i & 0xf0000000)
43
44#define LDST_I_BIT(i) (i & (1 << 26)) /* Immediate constant */
45#define LDST_P_BIT(i) (i & (1 << 24)) /* Preindex */
46#define LDST_U_BIT(i) (i & (1 << 23)) /* Add offset */
47#define LDST_W_BIT(i) (i & (1 << 21)) /* Writeback */
48#define LDST_L_BIT(i) (i & (1 << 20)) /* Load */
49
50#define LDST_P_EQ_U(i) ((((i) ^ ((i) >> 1)) & (1 << 23)) == 0)
51
52#define LDSTHD_I_BIT(i) (i & (1 << 22)) /* double/half-word immed */
53#define LDM_S_BIT(i) (i & (1 << 22)) /* write CPSR from SPSR */
54
55#define RN_BITS(i) ((i >> 16) & 15) /* Rn */
56#define RD_BITS(i) ((i >> 12) & 15) /* Rd */
57#define RM_BITS(i) (i & 15) /* Rm */
58
59#define REGMASK_BITS(i) (i & 0xffff)
60#define OFFSET_BITS(i) (i & 0x0fff)
61
62#define IS_SHIFT(i) (i & 0x0ff0)
63#define SHIFT_BITS(i) ((i >> 7) & 0x1f)
64#define SHIFT_TYPE(i) (i & 0x60)
65#define SHIFT_LSL 0x00
66#define SHIFT_LSR 0x20
67#define SHIFT_ASR 0x40
68#define SHIFT_RORRRX 0x60
69
70#define BAD_INSTR 0xdeadc0de
71
72/* Thumb-2 32 bit format per ARMv7 DDI0406A A6.3, either f800h,e800h,f800h */
73#define IS_T32(hi16) \
74 (((hi16) & 0xe000) == 0xe000 && ((hi16) & 0x1800))
75
76static unsigned long ai_user;
77static unsigned long ai_sys;
78static void *ai_sys_last_pc;
79static unsigned long ai_skipped;
80static unsigned long ai_half;
81static unsigned long ai_word;
82static unsigned long ai_dword;
83static unsigned long ai_multi;
84static int ai_usermode;
85static unsigned long cr_no_alignment;
86
87core_param(alignment, ai_usermode, int, 0600);
88
89#define UM_WARN (1 << 0)
90#define UM_FIXUP (1 << 1)
91#define UM_SIGNAL (1 << 2)
92
93/* Return true if and only if the ARMv6 unaligned access model is in use. */
94static bool cpu_is_v6_unaligned(void)
95{
96 return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U;
97}
98
99static int safe_usermode(int new_usermode, bool warn)
100{
101 /*
102 * ARMv6 and later CPUs can perform unaligned accesses for
103 * most single load and store instructions up to word size.
104 * LDM, STM, LDRD and STRD still need to be handled.
105 *
106 * Ignoring the alignment fault is not an option on these
107 * CPUs since we spin re-faulting the instruction without
108 * making any progress.
109 */
110 if (cpu_is_v6_unaligned() && !(new_usermode & (UM_FIXUP | UM_SIGNAL))) {
111 new_usermode |= UM_FIXUP;
112
113 if (warn)
114 pr_warn("alignment: ignoring faults is unsafe on this CPU. Defaulting to fixup mode.\n");
115 }
116
117 return new_usermode;
118}
119
120#ifdef CONFIG_PROC_FS
121static const char *usermode_action[] = {
122 "ignored",
123 "warn",
124 "fixup",
125 "fixup+warn",
126 "signal",
127 "signal+warn"
128};
129
130static int alignment_proc_show(struct seq_file *m, void *v)
131{
132 seq_printf(m, "User:\t\t%lu\n", ai_user);
133 seq_printf(m, "System:\t\t%lu (%pS)\n", ai_sys, ai_sys_last_pc);
134 seq_printf(m, "Skipped:\t%lu\n", ai_skipped);
135 seq_printf(m, "Half:\t\t%lu\n", ai_half);
136 seq_printf(m, "Word:\t\t%lu\n", ai_word);
137 if (cpu_architecture() >= CPU_ARCH_ARMv5TE)
138 seq_printf(m, "DWord:\t\t%lu\n", ai_dword);
139 seq_printf(m, "Multi:\t\t%lu\n", ai_multi);
140 seq_printf(m, "User faults:\t%i (%s)\n", ai_usermode,
141 usermode_action[ai_usermode]);
142
143 return 0;
144}
145
146static int alignment_proc_open(struct inode *inode, struct file *file)
147{
148 return single_open(file, alignment_proc_show, NULL);
149}
150
151static ssize_t alignment_proc_write(struct file *file, const char __user *buffer,
152 size_t count, loff_t *pos)
153{
154 char mode;
155
156 if (count > 0) {
157 if (get_user(mode, buffer))
158 return -EFAULT;
159 if (mode >= '0' && mode <= '5')
160 ai_usermode = safe_usermode(mode - '0', true);
161 }
162 return count;
163}
164
165static const struct proc_ops alignment_proc_ops = {
166 .proc_open = alignment_proc_open,
167 .proc_read = seq_read,
168 .proc_lseek = seq_lseek,
169 .proc_release = single_release,
170 .proc_write = alignment_proc_write,
171};
172#endif /* CONFIG_PROC_FS */
173
174union offset_union {
175 unsigned long un;
176 signed long sn;
177};
178
179#define TYPE_ERROR 0
180#define TYPE_FAULT 1
181#define TYPE_LDST 2
182#define TYPE_DONE 3
183
184#ifdef __ARMEB__
185#define BE 1
186#define FIRST_BYTE_16 "mov %1, %1, ror #8\n"
187#define FIRST_BYTE_32 "mov %1, %1, ror #24\n"
188#define NEXT_BYTE "ror #24"
189#else
190#define BE 0
191#define FIRST_BYTE_16
192#define FIRST_BYTE_32
193#define NEXT_BYTE "lsr #8"
194#endif
195
196#define __get8_unaligned_check(ins,val,addr,err) \
197 __asm__( \
198 ARM( "1: "ins" %1, [%2], #1\n" ) \
199 THUMB( "1: "ins" %1, [%2]\n" ) \
200 THUMB( " add %2, %2, #1\n" ) \
201 "2:\n" \
202 " .pushsection .text.fixup,\"ax\"\n" \
203 " .align 2\n" \
204 "3: mov %0, #1\n" \
205 " b 2b\n" \
206 " .popsection\n" \
207 " .pushsection __ex_table,\"a\"\n" \
208 " .align 3\n" \
209 " .long 1b, 3b\n" \
210 " .popsection\n" \
211 : "=r" (err), "=&r" (val), "=r" (addr) \
212 : "0" (err), "2" (addr))
213
214#define __get16_unaligned_check(ins,val,addr) \
215 do { \
216 unsigned int err = 0, v, a = addr; \
217 __get8_unaligned_check(ins,v,a,err); \
218 val = v << ((BE) ? 8 : 0); \
219 __get8_unaligned_check(ins,v,a,err); \
220 val |= v << ((BE) ? 0 : 8); \
221 if (err) \
222 goto fault; \
223 } while (0)
224
225#define get16_unaligned_check(val,addr) \
226 __get16_unaligned_check("ldrb",val,addr)
227
228#define get16t_unaligned_check(val,addr) \
229 __get16_unaligned_check("ldrbt",val,addr)
230
231#define __get32_unaligned_check(ins,val,addr) \
232 do { \
233 unsigned int err = 0, v, a = addr; \
234 __get8_unaligned_check(ins,v,a,err); \
235 val = v << ((BE) ? 24 : 0); \
236 __get8_unaligned_check(ins,v,a,err); \
237 val |= v << ((BE) ? 16 : 8); \
238 __get8_unaligned_check(ins,v,a,err); \
239 val |= v << ((BE) ? 8 : 16); \
240 __get8_unaligned_check(ins,v,a,err); \
241 val |= v << ((BE) ? 0 : 24); \
242 if (err) \
243 goto fault; \
244 } while (0)
245
246#define get32_unaligned_check(val,addr) \
247 __get32_unaligned_check("ldrb",val,addr)
248
249#define get32t_unaligned_check(val,addr) \
250 __get32_unaligned_check("ldrbt",val,addr)
251
252#define __put16_unaligned_check(ins,val,addr) \
253 do { \
254 unsigned int err = 0, v = val, a = addr; \
255 __asm__( FIRST_BYTE_16 \
256 ARM( "1: "ins" %1, [%2], #1\n" ) \
257 THUMB( "1: "ins" %1, [%2]\n" ) \
258 THUMB( " add %2, %2, #1\n" ) \
259 " mov %1, %1, "NEXT_BYTE"\n" \
260 "2: "ins" %1, [%2]\n" \
261 "3:\n" \
262 " .pushsection .text.fixup,\"ax\"\n" \
263 " .align 2\n" \
264 "4: mov %0, #1\n" \
265 " b 3b\n" \
266 " .popsection\n" \
267 " .pushsection __ex_table,\"a\"\n" \
268 " .align 3\n" \
269 " .long 1b, 4b\n" \
270 " .long 2b, 4b\n" \
271 " .popsection\n" \
272 : "=r" (err), "=&r" (v), "=&r" (a) \
273 : "0" (err), "1" (v), "2" (a)); \
274 if (err) \
275 goto fault; \
276 } while (0)
277
278#define put16_unaligned_check(val,addr) \
279 __put16_unaligned_check("strb",val,addr)
280
281#define put16t_unaligned_check(val,addr) \
282 __put16_unaligned_check("strbt",val,addr)
283
284#define __put32_unaligned_check(ins,val,addr) \
285 do { \
286 unsigned int err = 0, v = val, a = addr; \
287 __asm__( FIRST_BYTE_32 \
288 ARM( "1: "ins" %1, [%2], #1\n" ) \
289 THUMB( "1: "ins" %1, [%2]\n" ) \
290 THUMB( " add %2, %2, #1\n" ) \
291 " mov %1, %1, "NEXT_BYTE"\n" \
292 ARM( "2: "ins" %1, [%2], #1\n" ) \
293 THUMB( "2: "ins" %1, [%2]\n" ) \
294 THUMB( " add %2, %2, #1\n" ) \
295 " mov %1, %1, "NEXT_BYTE"\n" \
296 ARM( "3: "ins" %1, [%2], #1\n" ) \
297 THUMB( "3: "ins" %1, [%2]\n" ) \
298 THUMB( " add %2, %2, #1\n" ) \
299 " mov %1, %1, "NEXT_BYTE"\n" \
300 "4: "ins" %1, [%2]\n" \
301 "5:\n" \
302 " .pushsection .text.fixup,\"ax\"\n" \
303 " .align 2\n" \
304 "6: mov %0, #1\n" \
305 " b 5b\n" \
306 " .popsection\n" \
307 " .pushsection __ex_table,\"a\"\n" \
308 " .align 3\n" \
309 " .long 1b, 6b\n" \
310 " .long 2b, 6b\n" \
311 " .long 3b, 6b\n" \
312 " .long 4b, 6b\n" \
313 " .popsection\n" \
314 : "=r" (err), "=&r" (v), "=&r" (a) \
315 : "0" (err), "1" (v), "2" (a)); \
316 if (err) \
317 goto fault; \
318 } while (0)
319
320#define put32_unaligned_check(val,addr) \
321 __put32_unaligned_check("strb", val, addr)
322
323#define put32t_unaligned_check(val,addr) \
324 __put32_unaligned_check("strbt", val, addr)
325
326static void
327do_alignment_finish_ldst(unsigned long addr, u32 instr, struct pt_regs *regs, union offset_union offset)
328{
329 if (!LDST_U_BIT(instr))
330 offset.un = -offset.un;
331
332 if (!LDST_P_BIT(instr))
333 addr += offset.un;
334
335 if (!LDST_P_BIT(instr) || LDST_W_BIT(instr))
336 regs->uregs[RN_BITS(instr)] = addr;
337}
338
339static int
340do_alignment_ldrhstrh(unsigned long addr, u32 instr, struct pt_regs *regs)
341{
342 unsigned int rd = RD_BITS(instr);
343
344 ai_half += 1;
345
346 if (user_mode(regs))
347 goto user;
348
349 if (LDST_L_BIT(instr)) {
350 unsigned long val;
351 get16_unaligned_check(val, addr);
352
353 /* signed half-word? */
354 if (instr & 0x40)
355 val = (signed long)((signed short) val);
356
357 regs->uregs[rd] = val;
358 } else
359 put16_unaligned_check(regs->uregs[rd], addr);
360
361 return TYPE_LDST;
362
363 user:
364 if (LDST_L_BIT(instr)) {
365 unsigned long val;
366 unsigned int __ua_flags = uaccess_save_and_enable();
367
368 get16t_unaligned_check(val, addr);
369 uaccess_restore(__ua_flags);
370
371 /* signed half-word? */
372 if (instr & 0x40)
373 val = (signed long)((signed short) val);
374
375 regs->uregs[rd] = val;
376 } else {
377 unsigned int __ua_flags = uaccess_save_and_enable();
378 put16t_unaligned_check(regs->uregs[rd], addr);
379 uaccess_restore(__ua_flags);
380 }
381
382 return TYPE_LDST;
383
384 fault:
385 return TYPE_FAULT;
386}
387
388static int
389do_alignment_ldrdstrd(unsigned long addr, u32 instr, struct pt_regs *regs)
390{
391 unsigned int rd = RD_BITS(instr);
392 unsigned int rd2;
393 int load;
394
395 if ((instr & 0xfe000000) == 0xe8000000) {
396 /* ARMv7 Thumb-2 32-bit LDRD/STRD */
397 rd2 = (instr >> 8) & 0xf;
398 load = !!(LDST_L_BIT(instr));
399 } else if (((rd & 1) == 1) || (rd == 14))
400 goto bad;
401 else {
402 load = ((instr & 0xf0) == 0xd0);
403 rd2 = rd + 1;
404 }
405
406 ai_dword += 1;
407
408 if (user_mode(regs))
409 goto user;
410
411 if (load) {
412 unsigned long val;
413 get32_unaligned_check(val, addr);
414 regs->uregs[rd] = val;
415 get32_unaligned_check(val, addr + 4);
416 regs->uregs[rd2] = val;
417 } else {
418 put32_unaligned_check(regs->uregs[rd], addr);
419 put32_unaligned_check(regs->uregs[rd2], addr + 4);
420 }
421
422 return TYPE_LDST;
423
424 user:
425 if (load) {
426 unsigned long val, val2;
427 unsigned int __ua_flags = uaccess_save_and_enable();
428
429 get32t_unaligned_check(val, addr);
430 get32t_unaligned_check(val2, addr + 4);
431
432 uaccess_restore(__ua_flags);
433
434 regs->uregs[rd] = val;
435 regs->uregs[rd2] = val2;
436 } else {
437 unsigned int __ua_flags = uaccess_save_and_enable();
438 put32t_unaligned_check(regs->uregs[rd], addr);
439 put32t_unaligned_check(regs->uregs[rd2], addr + 4);
440 uaccess_restore(__ua_flags);
441 }
442
443 return TYPE_LDST;
444 bad:
445 return TYPE_ERROR;
446 fault:
447 return TYPE_FAULT;
448}
449
450static int
451do_alignment_ldrstr(unsigned long addr, u32 instr, struct pt_regs *regs)
452{
453 unsigned int rd = RD_BITS(instr);
454
455 ai_word += 1;
456
457 if ((!LDST_P_BIT(instr) && LDST_W_BIT(instr)) || user_mode(regs))
458 goto trans;
459
460 if (LDST_L_BIT(instr)) {
461 unsigned int val;
462 get32_unaligned_check(val, addr);
463 regs->uregs[rd] = val;
464 } else
465 put32_unaligned_check(regs->uregs[rd], addr);
466 return TYPE_LDST;
467
468 trans:
469 if (LDST_L_BIT(instr)) {
470 unsigned int val;
471 unsigned int __ua_flags = uaccess_save_and_enable();
472 get32t_unaligned_check(val, addr);
473 uaccess_restore(__ua_flags);
474 regs->uregs[rd] = val;
475 } else {
476 unsigned int __ua_flags = uaccess_save_and_enable();
477 put32t_unaligned_check(regs->uregs[rd], addr);
478 uaccess_restore(__ua_flags);
479 }
480 return TYPE_LDST;
481
482 fault:
483 return TYPE_FAULT;
484}
485
486/*
487 * LDM/STM alignment handler.
488 *
489 * There are 4 variants of this instruction:
490 *
491 * B = rn pointer before instruction, A = rn pointer after instruction
492 * ------ increasing address ----->
493 * | | r0 | r1 | ... | rx | |
494 * PU = 01 B A
495 * PU = 11 B A
496 * PU = 00 A B
497 * PU = 10 A B
498 */
499static int
500do_alignment_ldmstm(unsigned long addr, u32 instr, struct pt_regs *regs)
501{
502 unsigned int rd, rn, correction, nr_regs, regbits;
503 unsigned long eaddr, newaddr;
504
505 if (LDM_S_BIT(instr))
506 goto bad;
507
508 correction = 4; /* processor implementation defined */
509 regs->ARM_pc += correction;
510
511 ai_multi += 1;
512
513 /* count the number of registers in the mask to be transferred */
514 nr_regs = hweight16(REGMASK_BITS(instr)) * 4;
515
516 rn = RN_BITS(instr);
517 newaddr = eaddr = regs->uregs[rn];
518
519 if (!LDST_U_BIT(instr))
520 nr_regs = -nr_regs;
521 newaddr += nr_regs;
522 if (!LDST_U_BIT(instr))
523 eaddr = newaddr;
524
525 if (LDST_P_EQ_U(instr)) /* U = P */
526 eaddr += 4;
527
528 /*
529 * For alignment faults on the ARM922T/ARM920T the MMU makes
530 * the FSR (and hence addr) equal to the updated base address
531 * of the multiple access rather than the restored value.
532 * Switch this message off if we've got a ARM92[02], otherwise
533 * [ls]dm alignment faults are noisy!
534 */
535#if !(defined CONFIG_CPU_ARM922T) && !(defined CONFIG_CPU_ARM920T)
536 /*
537 * This is a "hint" - we already have eaddr worked out by the
538 * processor for us.
539 */
540 if (addr != eaddr) {
541 pr_err("LDMSTM: PC = %08lx, instr = %08x, "
542 "addr = %08lx, eaddr = %08lx\n",
543 instruction_pointer(regs), instr, addr, eaddr);
544 show_regs(regs);
545 }
546#endif
547
548 if (user_mode(regs)) {
549 unsigned int __ua_flags = uaccess_save_and_enable();
550 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
551 regbits >>= 1, rd += 1)
552 if (regbits & 1) {
553 if (LDST_L_BIT(instr)) {
554 unsigned int val;
555 get32t_unaligned_check(val, eaddr);
556 regs->uregs[rd] = val;
557 } else
558 put32t_unaligned_check(regs->uregs[rd], eaddr);
559 eaddr += 4;
560 }
561 uaccess_restore(__ua_flags);
562 } else {
563 for (regbits = REGMASK_BITS(instr), rd = 0; regbits;
564 regbits >>= 1, rd += 1)
565 if (regbits & 1) {
566 if (LDST_L_BIT(instr)) {
567 unsigned int val;
568 get32_unaligned_check(val, eaddr);
569 regs->uregs[rd] = val;
570 } else
571 put32_unaligned_check(regs->uregs[rd], eaddr);
572 eaddr += 4;
573 }
574 }
575
576 if (LDST_W_BIT(instr))
577 regs->uregs[rn] = newaddr;
578 if (!LDST_L_BIT(instr) || !(REGMASK_BITS(instr) & (1 << 15)))
579 regs->ARM_pc -= correction;
580 return TYPE_DONE;
581
582fault:
583 regs->ARM_pc -= correction;
584 return TYPE_FAULT;
585
586bad:
587 pr_err("Alignment trap: not handling ldm with s-bit set\n");
588 return TYPE_ERROR;
589}
590
591/*
592 * Convert Thumb ld/st instruction forms to equivalent ARM instructions so
593 * we can reuse ARM userland alignment fault fixups for Thumb.
594 *
595 * This implementation was initially based on the algorithm found in
596 * gdb/sim/arm/thumbemu.c. It is basically just a code reduction of same
597 * to convert only Thumb ld/st instruction forms to equivalent ARM forms.
598 *
599 * NOTES:
600 * 1. Comments below refer to ARM ARM DDI0100E Thumb Instruction sections.
601 * 2. If for some reason we're passed an non-ld/st Thumb instruction to
602 * decode, we return 0xdeadc0de. This should never happen under normal
603 * circumstances but if it does, we've got other problems to deal with
604 * elsewhere and we obviously can't fix those problems here.
605 */
606
607static unsigned long
608thumb2arm(u16 tinstr)
609{
610 u32 L = (tinstr & (1<<11)) >> 11;
611
612 switch ((tinstr & 0xf800) >> 11) {
613 /* 6.5.1 Format 1: */
614 case 0x6000 >> 11: /* 7.1.52 STR(1) */
615 case 0x6800 >> 11: /* 7.1.26 LDR(1) */
616 case 0x7000 >> 11: /* 7.1.55 STRB(1) */
617 case 0x7800 >> 11: /* 7.1.30 LDRB(1) */
618 return 0xe5800000 |
619 ((tinstr & (1<<12)) << (22-12)) | /* fixup */
620 (L<<20) | /* L==1? */
621 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
622 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
623 ((tinstr & (31<<6)) >> /* immed_5 */
624 (6 - ((tinstr & (1<<12)) ? 0 : 2)));
625 case 0x8000 >> 11: /* 7.1.57 STRH(1) */
626 case 0x8800 >> 11: /* 7.1.32 LDRH(1) */
627 return 0xe1c000b0 |
628 (L<<20) | /* L==1? */
629 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
630 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
631 ((tinstr & (7<<6)) >> (6-1)) | /* immed_5[2:0] */
632 ((tinstr & (3<<9)) >> (9-8)); /* immed_5[4:3] */
633
634 /* 6.5.1 Format 2: */
635 case 0x5000 >> 11:
636 case 0x5800 >> 11:
637 {
638 static const u32 subset[8] = {
639 0xe7800000, /* 7.1.53 STR(2) */
640 0xe18000b0, /* 7.1.58 STRH(2) */
641 0xe7c00000, /* 7.1.56 STRB(2) */
642 0xe19000d0, /* 7.1.34 LDRSB */
643 0xe7900000, /* 7.1.27 LDR(2) */
644 0xe19000b0, /* 7.1.33 LDRH(2) */
645 0xe7d00000, /* 7.1.31 LDRB(2) */
646 0xe19000f0 /* 7.1.35 LDRSH */
647 };
648 return subset[(tinstr & (7<<9)) >> 9] |
649 ((tinstr & (7<<0)) << (12-0)) | /* Rd */
650 ((tinstr & (7<<3)) << (16-3)) | /* Rn */
651 ((tinstr & (7<<6)) >> (6-0)); /* Rm */
652 }
653
654 /* 6.5.1 Format 3: */
655 case 0x4800 >> 11: /* 7.1.28 LDR(3) */
656 /* NOTE: This case is not technically possible. We're
657 * loading 32-bit memory data via PC relative
658 * addressing mode. So we can and should eliminate
659 * this case. But I'll leave it here for now.
660 */
661 return 0xe59f0000 |
662 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
663 ((tinstr & 255) << (2-0)); /* immed_8 */
664
665 /* 6.5.1 Format 4: */
666 case 0x9000 >> 11: /* 7.1.54 STR(3) */
667 case 0x9800 >> 11: /* 7.1.29 LDR(4) */
668 return 0xe58d0000 |
669 (L<<20) | /* L==1? */
670 ((tinstr & (7<<8)) << (12-8)) | /* Rd */
671 ((tinstr & 255) << 2); /* immed_8 */
672
673 /* 6.6.1 Format 1: */
674 case 0xc000 >> 11: /* 7.1.51 STMIA */
675 case 0xc800 >> 11: /* 7.1.25 LDMIA */
676 {
677 u32 Rn = (tinstr & (7<<8)) >> 8;
678 u32 W = ((L<<Rn) & (tinstr&255)) ? 0 : 1<<21;
679
680 return 0xe8800000 | W | (L<<20) | (Rn<<16) |
681 (tinstr&255);
682 }
683
684 /* 6.6.1 Format 2: */
685 case 0xb000 >> 11: /* 7.1.48 PUSH */
686 case 0xb800 >> 11: /* 7.1.47 POP */
687 if ((tinstr & (3 << 9)) == 0x0400) {
688 static const u32 subset[4] = {
689 0xe92d0000, /* STMDB sp!,{registers} */
690 0xe92d4000, /* STMDB sp!,{registers,lr} */
691 0xe8bd0000, /* LDMIA sp!,{registers} */
692 0xe8bd8000 /* LDMIA sp!,{registers,pc} */
693 };
694 return subset[(L<<1) | ((tinstr & (1<<8)) >> 8)] |
695 (tinstr & 255); /* register_list */
696 }
697 fallthrough; /* for illegal instruction case */
698
699 default:
700 return BAD_INSTR;
701 }
702}
703
704/*
705 * Convert Thumb-2 32 bit LDM, STM, LDRD, STRD to equivalent instruction
706 * handlable by ARM alignment handler, also find the corresponding handler,
707 * so that we can reuse ARM userland alignment fault fixups for Thumb.
708 *
709 * @pinstr: original Thumb-2 instruction; returns new handlable instruction
710 * @regs: register context.
711 * @poffset: return offset from faulted addr for later writeback
712 *
713 * NOTES:
714 * 1. Comments below refer to ARMv7 DDI0406A Thumb Instruction sections.
715 * 2. Register name Rt from ARMv7 is same as Rd from ARMv6 (Rd is Rt)
716 */
717static void *
718do_alignment_t32_to_handler(u32 *pinstr, struct pt_regs *regs,
719 union offset_union *poffset)
720{
721 u32 instr = *pinstr;
722 u16 tinst1 = (instr >> 16) & 0xffff;
723 u16 tinst2 = instr & 0xffff;
724
725 switch (tinst1 & 0xffe0) {
726 /* A6.3.5 Load/Store multiple */
727 case 0xe880: /* STM/STMIA/STMEA,LDM/LDMIA, PUSH/POP T2 */
728 case 0xe8a0: /* ...above writeback version */
729 case 0xe900: /* STMDB/STMFD, LDMDB/LDMEA */
730 case 0xe920: /* ...above writeback version */
731 /* no need offset decision since handler calculates it */
732 return do_alignment_ldmstm;
733
734 case 0xf840: /* POP/PUSH T3 (single register) */
735 if (RN_BITS(instr) == 13 && (tinst2 & 0x09ff) == 0x0904) {
736 u32 L = !!(LDST_L_BIT(instr));
737 const u32 subset[2] = {
738 0xe92d0000, /* STMDB sp!,{registers} */
739 0xe8bd0000, /* LDMIA sp!,{registers} */
740 };
741 *pinstr = subset[L] | (1<<RD_BITS(instr));
742 return do_alignment_ldmstm;
743 }
744 /* Else fall through for illegal instruction case */
745 break;
746
747 /* A6.3.6 Load/store double, STRD/LDRD(immed, lit, reg) */
748 case 0xe860:
749 case 0xe960:
750 case 0xe8e0:
751 case 0xe9e0:
752 poffset->un = (tinst2 & 0xff) << 2;
753 fallthrough;
754
755 case 0xe940:
756 case 0xe9c0:
757 return do_alignment_ldrdstrd;
758
759 /*
760 * No need to handle load/store instructions up to word size
761 * since ARMv6 and later CPUs can perform unaligned accesses.
762 */
763 default:
764 break;
765 }
766 return NULL;
767}
768
769static int alignment_get_arm(struct pt_regs *regs, u32 *ip, u32 *inst)
770{
771 u32 instr = 0;
772 int fault;
773
774 if (user_mode(regs))
775 fault = get_user(instr, ip);
776 else
777 fault = get_kernel_nofault(instr, ip);
778
779 *inst = __mem_to_opcode_arm(instr);
780
781 return fault;
782}
783
784static int alignment_get_thumb(struct pt_regs *regs, u16 *ip, u16 *inst)
785{
786 u16 instr = 0;
787 int fault;
788
789 if (user_mode(regs))
790 fault = get_user(instr, ip);
791 else
792 fault = get_kernel_nofault(instr, ip);
793
794 *inst = __mem_to_opcode_thumb16(instr);
795
796 return fault;
797}
798
799static int
800do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
801{
802 union offset_union offset;
803 unsigned long instrptr;
804 int (*handler)(unsigned long addr, u32 instr, struct pt_regs *regs);
805 unsigned int type;
806 u32 instr = 0;
807 u16 tinstr = 0;
808 int isize = 4;
809 int thumb2_32b = 0;
810 int fault;
811
812 if (interrupts_enabled(regs))
813 local_irq_enable();
814
815 instrptr = instruction_pointer(regs);
816
817 if (thumb_mode(regs)) {
818 u16 *ptr = (u16 *)(instrptr & ~1);
819
820 fault = alignment_get_thumb(regs, ptr, &tinstr);
821 if (!fault) {
822 if (cpu_architecture() >= CPU_ARCH_ARMv7 &&
823 IS_T32(tinstr)) {
824 /* Thumb-2 32-bit */
825 u16 tinst2;
826 fault = alignment_get_thumb(regs, ptr + 1, &tinst2);
827 instr = __opcode_thumb32_compose(tinstr, tinst2);
828 thumb2_32b = 1;
829 } else {
830 isize = 2;
831 instr = thumb2arm(tinstr);
832 }
833 }
834 } else {
835 fault = alignment_get_arm(regs, (void *)instrptr, &instr);
836 }
837
838 if (fault) {
839 type = TYPE_FAULT;
840 goto bad_or_fault;
841 }
842
843 if (user_mode(regs))
844 goto user;
845
846 ai_sys += 1;
847 ai_sys_last_pc = (void *)instruction_pointer(regs);
848
849 fixup:
850
851 regs->ARM_pc += isize;
852
853 switch (CODING_BITS(instr)) {
854 case 0x00000000: /* 3.13.4 load/store instruction extensions */
855 if (LDSTHD_I_BIT(instr))
856 offset.un = (instr & 0xf00) >> 4 | (instr & 15);
857 else
858 offset.un = regs->uregs[RM_BITS(instr)];
859
860 if ((instr & 0x000000f0) == 0x000000b0 || /* LDRH, STRH */
861 (instr & 0x001000f0) == 0x001000f0) /* LDRSH */
862 handler = do_alignment_ldrhstrh;
863 else if ((instr & 0x001000f0) == 0x000000d0 || /* LDRD */
864 (instr & 0x001000f0) == 0x000000f0) /* STRD */
865 handler = do_alignment_ldrdstrd;
866 else if ((instr & 0x01f00ff0) == 0x01000090) /* SWP */
867 goto swp;
868 else
869 goto bad;
870 break;
871
872 case 0x04000000: /* ldr or str immediate */
873 if (COND_BITS(instr) == 0xf0000000) /* NEON VLDn, VSTn */
874 goto bad;
875 offset.un = OFFSET_BITS(instr);
876 handler = do_alignment_ldrstr;
877 break;
878
879 case 0x06000000: /* ldr or str register */
880 offset.un = regs->uregs[RM_BITS(instr)];
881
882 if (IS_SHIFT(instr)) {
883 unsigned int shiftval = SHIFT_BITS(instr);
884
885 switch(SHIFT_TYPE(instr)) {
886 case SHIFT_LSL:
887 offset.un <<= shiftval;
888 break;
889
890 case SHIFT_LSR:
891 offset.un >>= shiftval;
892 break;
893
894 case SHIFT_ASR:
895 offset.sn >>= shiftval;
896 break;
897
898 case SHIFT_RORRRX:
899 if (shiftval == 0) {
900 offset.un >>= 1;
901 if (regs->ARM_cpsr & PSR_C_BIT)
902 offset.un |= 1 << 31;
903 } else
904 offset.un = offset.un >> shiftval |
905 offset.un << (32 - shiftval);
906 break;
907 }
908 }
909 handler = do_alignment_ldrstr;
910 break;
911
912 case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */
913 if (thumb2_32b) {
914 offset.un = 0;
915 handler = do_alignment_t32_to_handler(&instr, regs, &offset);
916 } else {
917 offset.un = 0;
918 handler = do_alignment_ldmstm;
919 }
920 break;
921
922 default:
923 goto bad;
924 }
925
926 if (!handler)
927 goto bad;
928 type = handler(addr, instr, regs);
929
930 if (type == TYPE_ERROR || type == TYPE_FAULT) {
931 regs->ARM_pc -= isize;
932 goto bad_or_fault;
933 }
934
935 if (type == TYPE_LDST)
936 do_alignment_finish_ldst(addr, instr, regs, offset);
937
938 if (thumb_mode(regs))
939 regs->ARM_cpsr = it_advance(regs->ARM_cpsr);
940
941 return 0;
942
943 bad_or_fault:
944 if (type == TYPE_ERROR)
945 goto bad;
946 /*
947 * We got a fault - fix it up, or die.
948 */
949 do_bad_area(addr, fsr, regs);
950 return 0;
951
952 swp:
953 pr_err("Alignment trap: not handling swp instruction\n");
954
955 bad:
956 /*
957 * Oops, we didn't handle the instruction.
958 */
959 pr_err("Alignment trap: not handling instruction "
960 "%0*x at [<%08lx>]\n",
961 isize << 1,
962 isize == 2 ? tinstr : instr, instrptr);
963 ai_skipped += 1;
964 return 1;
965
966 user:
967 ai_user += 1;
968
969 if (ai_usermode & UM_WARN)
970 printk("Alignment trap: %s (%d) PC=0x%08lx Instr=0x%0*x "
971 "Address=0x%08lx FSR 0x%03x\n", current->comm,
972 task_pid_nr(current), instrptr,
973 isize << 1,
974 isize == 2 ? tinstr : instr,
975 addr, fsr);
976
977 if (ai_usermode & UM_FIXUP)
978 goto fixup;
979
980 if (ai_usermode & UM_SIGNAL) {
981 force_sig_fault(SIGBUS, BUS_ADRALN, (void __user *)addr);
982 } else {
983 /*
984 * We're about to disable the alignment trap and return to
985 * user space. But if an interrupt occurs before actually
986 * reaching user space, then the IRQ vector entry code will
987 * notice that we were still in kernel space and therefore
988 * the alignment trap won't be re-enabled in that case as it
989 * is presumed to be always on from kernel space.
990 * Let's prevent that race by disabling interrupts here (they
991 * are disabled on the way back to user space anyway in
992 * entry-common.S) and disable the alignment trap only if
993 * there is no work pending for this thread.
994 */
995 raw_local_irq_disable();
996 if (!(read_thread_flags() & _TIF_WORK_MASK))
997 set_cr(cr_no_alignment);
998 }
999
1000 return 0;
1001}
1002
1003static int __init noalign_setup(char *__unused)
1004{
1005 set_cr(__clear_cr(CR_A));
1006 return 1;
1007}
1008__setup("noalign", noalign_setup);
1009
1010/*
1011 * This needs to be done after sysctl_init_bases(), otherwise sys/ will be
1012 * overwritten. Actually, this shouldn't be in sys/ at all since
1013 * it isn't a sysctl, and it doesn't contain sysctl information.
1014 * We now locate it in /proc/cpu/alignment instead.
1015 */
1016static int __init alignment_init(void)
1017{
1018#ifdef CONFIG_PROC_FS
1019 struct proc_dir_entry *res;
1020
1021 res = proc_create("cpu/alignment", S_IWUSR | S_IRUGO, NULL,
1022 &alignment_proc_ops);
1023 if (!res)
1024 return -ENOMEM;
1025#endif
1026
1027 if (cpu_is_v6_unaligned()) {
1028 set_cr(__clear_cr(CR_A));
1029 ai_usermode = safe_usermode(ai_usermode, false);
1030 }
1031
1032 cr_no_alignment = get_cr() & ~CR_A;
1033
1034 hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
1035 "alignment exception");
1036
1037 /*
1038 * ARMv6K and ARMv7 use fault status 3 (0b00011) as Access Flag section
1039 * fault, not as alignment error.
1040 *
1041 * TODO: handle ARMv6K properly. Runtime check for 'K' extension is
1042 * needed.
1043 */
1044 if (cpu_architecture() <= CPU_ARCH_ARMv6) {
1045 hook_fault_code(3, do_alignment, SIGBUS, BUS_ADRALN,
1046 "alignment exception");
1047 }
1048
1049 return 0;
1050}
1051
1052fs_initcall(alignment_init);