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1/*
2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
10#include <linux/clk.h>
11#include <linux/debugfs.h>
12#include <linux/gpio.h>
13#include <linux/hdmi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/reset.h>
16
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_crtc.h>
19#include <drm/drm_crtc_helper.h>
20
21#include "hdmi.h"
22#include "drm.h"
23#include "dc.h"
24
25struct tmds_config {
26 unsigned int pclk;
27 u32 pll0;
28 u32 pll1;
29 u32 pe_current;
30 u32 drive_current;
31 u32 peak_current;
32};
33
34struct tegra_hdmi_config {
35 const struct tmds_config *tmds;
36 unsigned int num_tmds;
37
38 unsigned long fuse_override_offset;
39 u32 fuse_override_value;
40
41 bool has_sor_io_peak_current;
42};
43
44struct tegra_hdmi {
45 struct host1x_client client;
46 struct tegra_output output;
47 struct device *dev;
48
49 struct regulator *hdmi;
50 struct regulator *pll;
51 struct regulator *vdd;
52
53 void __iomem *regs;
54 unsigned int irq;
55
56 struct clk *clk_parent;
57 struct clk *clk;
58 struct reset_control *rst;
59
60 const struct tegra_hdmi_config *config;
61
62 unsigned int audio_source;
63 unsigned int audio_freq;
64 bool stereo;
65 bool dvi;
66
67 struct drm_info_list *debugfs_files;
68 struct drm_minor *minor;
69 struct dentry *debugfs;
70};
71
72static inline struct tegra_hdmi *
73host1x_client_to_hdmi(struct host1x_client *client)
74{
75 return container_of(client, struct tegra_hdmi, client);
76}
77
78static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
79{
80 return container_of(output, struct tegra_hdmi, output);
81}
82
83#define HDMI_AUDIOCLK_FREQ 216000000
84#define HDMI_REKEY_DEFAULT 56
85
86enum {
87 AUTO = 0,
88 SPDIF,
89 HDA,
90};
91
92static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
93 unsigned long offset)
94{
95 return readl(hdmi->regs + (offset << 2));
96}
97
98static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
99 unsigned long offset)
100{
101 writel(value, hdmi->regs + (offset << 2));
102}
103
104struct tegra_hdmi_audio_config {
105 unsigned int pclk;
106 unsigned int n;
107 unsigned int cts;
108 unsigned int aval;
109};
110
111static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
112 { 25200000, 4096, 25200, 24000 },
113 { 27000000, 4096, 27000, 24000 },
114 { 74250000, 4096, 74250, 24000 },
115 { 148500000, 4096, 148500, 24000 },
116 { 0, 0, 0, 0 },
117};
118
119static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
120 { 25200000, 5880, 26250, 25000 },
121 { 27000000, 5880, 28125, 25000 },
122 { 74250000, 4704, 61875, 20000 },
123 { 148500000, 4704, 123750, 20000 },
124 { 0, 0, 0, 0 },
125};
126
127static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
128 { 25200000, 6144, 25200, 24000 },
129 { 27000000, 6144, 27000, 24000 },
130 { 74250000, 6144, 74250, 24000 },
131 { 148500000, 6144, 148500, 24000 },
132 { 0, 0, 0, 0 },
133};
134
135static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
136 { 25200000, 11760, 26250, 25000 },
137 { 27000000, 11760, 28125, 25000 },
138 { 74250000, 9408, 61875, 20000 },
139 { 148500000, 9408, 123750, 20000 },
140 { 0, 0, 0, 0 },
141};
142
143static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
144 { 25200000, 12288, 25200, 24000 },
145 { 27000000, 12288, 27000, 24000 },
146 { 74250000, 12288, 74250, 24000 },
147 { 148500000, 12288, 148500, 24000 },
148 { 0, 0, 0, 0 },
149};
150
151static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
152 { 25200000, 23520, 26250, 25000 },
153 { 27000000, 23520, 28125, 25000 },
154 { 74250000, 18816, 61875, 20000 },
155 { 148500000, 18816, 123750, 20000 },
156 { 0, 0, 0, 0 },
157};
158
159static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
160 { 25200000, 24576, 25200, 24000 },
161 { 27000000, 24576, 27000, 24000 },
162 { 74250000, 24576, 74250, 24000 },
163 { 148500000, 24576, 148500, 24000 },
164 { 0, 0, 0, 0 },
165};
166
167static const struct tmds_config tegra20_tmds_config[] = {
168 { /* slow pixel clock modes */
169 .pclk = 27000000,
170 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
171 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
172 SOR_PLL_TX_REG_LOAD(3),
173 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
174 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
175 PE_CURRENT1(PE_CURRENT_0_0_mA) |
176 PE_CURRENT2(PE_CURRENT_0_0_mA) |
177 PE_CURRENT3(PE_CURRENT_0_0_mA),
178 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
179 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
180 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
181 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
182 },
183 { /* high pixel clock modes */
184 .pclk = UINT_MAX,
185 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
186 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
187 SOR_PLL_TX_REG_LOAD(3),
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
189 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
190 PE_CURRENT1(PE_CURRENT_6_0_mA) |
191 PE_CURRENT2(PE_CURRENT_6_0_mA) |
192 PE_CURRENT3(PE_CURRENT_6_0_mA),
193 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
194 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
195 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
196 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
197 },
198};
199
200static const struct tmds_config tegra30_tmds_config[] = {
201 { /* 480p modes */
202 .pclk = 27000000,
203 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
204 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
205 SOR_PLL_TX_REG_LOAD(0),
206 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
207 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
208 PE_CURRENT1(PE_CURRENT_0_0_mA) |
209 PE_CURRENT2(PE_CURRENT_0_0_mA) |
210 PE_CURRENT3(PE_CURRENT_0_0_mA),
211 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
212 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
213 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
214 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
215 }, { /* 720p modes */
216 .pclk = 74250000,
217 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
218 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
219 SOR_PLL_TX_REG_LOAD(0),
220 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
221 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
222 PE_CURRENT1(PE_CURRENT_5_0_mA) |
223 PE_CURRENT2(PE_CURRENT_5_0_mA) |
224 PE_CURRENT3(PE_CURRENT_5_0_mA),
225 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
226 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
227 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
228 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
229 }, { /* 1080p modes */
230 .pclk = UINT_MAX,
231 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
232 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
233 SOR_PLL_TX_REG_LOAD(0),
234 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
235 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
236 PE_CURRENT1(PE_CURRENT_5_0_mA) |
237 PE_CURRENT2(PE_CURRENT_5_0_mA) |
238 PE_CURRENT3(PE_CURRENT_5_0_mA),
239 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
240 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
241 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
242 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
243 },
244};
245
246static const struct tmds_config tegra114_tmds_config[] = {
247 { /* 480p/576p / 25.2MHz/27MHz modes */
248 .pclk = 27000000,
249 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
250 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
251 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
252 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
253 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
254 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
255 PE_CURRENT3(PE_CURRENT_0_mA_T114),
256 .drive_current =
257 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
258 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
259 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
260 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
261 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
262 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
263 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
264 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
265 }, { /* 720p / 74.25MHz modes */
266 .pclk = 74250000,
267 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
268 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
269 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
270 SOR_PLL_TMDS_TERMADJ(0),
271 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
272 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
273 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
274 PE_CURRENT3(PE_CURRENT_15_mA_T114),
275 .drive_current =
276 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
277 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
278 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
279 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
280 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
281 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
282 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
283 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
284 }, { /* 1080p / 148.5MHz modes */
285 .pclk = 148500000,
286 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
287 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
288 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
289 SOR_PLL_TMDS_TERMADJ(0),
290 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
291 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
292 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
293 PE_CURRENT3(PE_CURRENT_10_mA_T114),
294 .drive_current =
295 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
296 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
297 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
298 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
299 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
300 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
301 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
302 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
303 }, { /* 225/297MHz modes */
304 .pclk = UINT_MAX,
305 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
306 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
307 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
308 | SOR_PLL_TMDS_TERM_ENABLE,
309 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
310 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
311 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
312 PE_CURRENT3(PE_CURRENT_0_mA_T114),
313 .drive_current =
314 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
315 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
316 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
317 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
318 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
319 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
320 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
321 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
322 },
323};
324
325static const struct tmds_config tegra124_tmds_config[] = {
326 { /* 480p/576p / 25.2MHz/27MHz modes */
327 .pclk = 27000000,
328 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
329 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
330 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
331 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
332 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
333 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
334 PE_CURRENT3(PE_CURRENT_0_mA_T114),
335 .drive_current =
336 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
337 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
338 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
339 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
340 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
341 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
342 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
343 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
344 }, { /* 720p / 74.25MHz modes */
345 .pclk = 74250000,
346 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
347 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
348 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
349 SOR_PLL_TMDS_TERMADJ(0),
350 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
351 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
352 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
353 PE_CURRENT3(PE_CURRENT_15_mA_T114),
354 .drive_current =
355 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
356 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
357 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
358 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
359 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
360 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
361 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
362 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
363 }, { /* 1080p / 148.5MHz modes */
364 .pclk = 148500000,
365 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
366 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
367 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
368 SOR_PLL_TMDS_TERMADJ(0),
369 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
370 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
371 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
372 PE_CURRENT3(PE_CURRENT_10_mA_T114),
373 .drive_current =
374 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
375 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
376 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
377 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
378 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
379 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
380 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
381 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
382 }, { /* 225/297MHz modes */
383 .pclk = UINT_MAX,
384 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
385 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
386 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
387 | SOR_PLL_TMDS_TERM_ENABLE,
388 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
389 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
390 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
391 PE_CURRENT3(PE_CURRENT_0_mA_T114),
392 .drive_current =
393 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
394 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
395 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
396 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
397 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
398 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
399 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
400 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
401 },
402};
403
404static const struct tegra_hdmi_audio_config *
405tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
406{
407 const struct tegra_hdmi_audio_config *table;
408
409 switch (audio_freq) {
410 case 32000:
411 table = tegra_hdmi_audio_32k;
412 break;
413
414 case 44100:
415 table = tegra_hdmi_audio_44_1k;
416 break;
417
418 case 48000:
419 table = tegra_hdmi_audio_48k;
420 break;
421
422 case 88200:
423 table = tegra_hdmi_audio_88_2k;
424 break;
425
426 case 96000:
427 table = tegra_hdmi_audio_96k;
428 break;
429
430 case 176400:
431 table = tegra_hdmi_audio_176_4k;
432 break;
433
434 case 192000:
435 table = tegra_hdmi_audio_192k;
436 break;
437
438 default:
439 return NULL;
440 }
441
442 while (table->pclk) {
443 if (table->pclk == pclk)
444 return table;
445
446 table++;
447 }
448
449 return NULL;
450}
451
452static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
453{
454 const unsigned int freqs[] = {
455 32000, 44100, 48000, 88200, 96000, 176400, 192000
456 };
457 unsigned int i;
458
459 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
460 unsigned int f = freqs[i];
461 unsigned int eight_half;
462 unsigned int delta;
463 u32 value;
464
465 if (f > 96000)
466 delta = 2;
467 else if (f > 48000)
468 delta = 6;
469 else
470 delta = 9;
471
472 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
473 value = AUDIO_FS_LOW(eight_half - delta) |
474 AUDIO_FS_HIGH(eight_half + delta);
475 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
476 }
477}
478
479static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
480{
481 struct device_node *node = hdmi->dev->of_node;
482 const struct tegra_hdmi_audio_config *config;
483 unsigned int offset = 0;
484 u32 value;
485
486 switch (hdmi->audio_source) {
487 case HDA:
488 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
489 break;
490
491 case SPDIF:
492 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
493 break;
494
495 default:
496 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
497 break;
498 }
499
500 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
501 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
502 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
503 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
504 } else {
505 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
506 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
507
508 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
509 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
510 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
511 }
512
513 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
514 if (!config) {
515 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
516 hdmi->audio_freq, pclk);
517 return -EINVAL;
518 }
519
520 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
521
522 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
523 AUDIO_N_VALUE(config->n - 1);
524 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
525
526 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
527 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
528
529 value = ACR_SUBPACK_CTS(config->cts);
530 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
531
532 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
533 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
534
535 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
536 value &= ~AUDIO_N_RESETF;
537 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
538
539 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
540 switch (hdmi->audio_freq) {
541 case 32000:
542 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
543 break;
544
545 case 44100:
546 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
547 break;
548
549 case 48000:
550 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
551 break;
552
553 case 88200:
554 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
555 break;
556
557 case 96000:
558 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
559 break;
560
561 case 176400:
562 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
563 break;
564
565 case 192000:
566 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
567 break;
568 }
569
570 tegra_hdmi_writel(hdmi, config->aval, offset);
571 }
572
573 tegra_hdmi_setup_audio_fs_tables(hdmi);
574
575 return 0;
576}
577
578static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
579{
580 u32 value = 0;
581 size_t i;
582
583 for (i = size; i > 0; i--)
584 value = (value << 8) | ptr[i - 1];
585
586 return value;
587}
588
589static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
590 size_t size)
591{
592 const u8 *ptr = data;
593 unsigned long offset;
594 size_t i, j;
595 u32 value;
596
597 switch (ptr[0]) {
598 case HDMI_INFOFRAME_TYPE_AVI:
599 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
600 break;
601
602 case HDMI_INFOFRAME_TYPE_AUDIO:
603 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
604 break;
605
606 case HDMI_INFOFRAME_TYPE_VENDOR:
607 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
608 break;
609
610 default:
611 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
612 ptr[0]);
613 return;
614 }
615
616 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
617 INFOFRAME_HEADER_VERSION(ptr[1]) |
618 INFOFRAME_HEADER_LEN(ptr[2]);
619 tegra_hdmi_writel(hdmi, value, offset);
620 offset++;
621
622 /*
623 * Each subpack contains 7 bytes, divided into:
624 * - subpack_low: bytes 0 - 3
625 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
626 */
627 for (i = 3, j = 0; i < size; i += 7, j += 8) {
628 size_t rem = size - i, num = min_t(size_t, rem, 4);
629
630 value = tegra_hdmi_subpack(&ptr[i], num);
631 tegra_hdmi_writel(hdmi, value, offset++);
632
633 num = min_t(size_t, rem - num, 3);
634
635 value = tegra_hdmi_subpack(&ptr[i + 4], num);
636 tegra_hdmi_writel(hdmi, value, offset++);
637 }
638}
639
640static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
641 struct drm_display_mode *mode)
642{
643 struct hdmi_avi_infoframe frame;
644 u8 buffer[17];
645 ssize_t err;
646
647 if (hdmi->dvi) {
648 tegra_hdmi_writel(hdmi, 0,
649 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
650 return;
651 }
652
653 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
654 if (err < 0) {
655 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
656 return;
657 }
658
659 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
660 if (err < 0) {
661 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
662 return;
663 }
664
665 tegra_hdmi_write_infopack(hdmi, buffer, err);
666
667 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
668 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
669}
670
671static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
672{
673 struct hdmi_audio_infoframe frame;
674 u8 buffer[14];
675 ssize_t err;
676
677 if (hdmi->dvi) {
678 tegra_hdmi_writel(hdmi, 0,
679 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
680 return;
681 }
682
683 err = hdmi_audio_infoframe_init(&frame);
684 if (err < 0) {
685 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
686 err);
687 return;
688 }
689
690 frame.channels = 2;
691
692 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
693 if (err < 0) {
694 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
695 err);
696 return;
697 }
698
699 /*
700 * The audio infoframe has only one set of subpack registers, so the
701 * infoframe needs to be truncated. One set of subpack registers can
702 * contain 7 bytes. Including the 3 byte header only the first 10
703 * bytes can be programmed.
704 */
705 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
706
707 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
708 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
709}
710
711static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
712{
713 struct hdmi_vendor_infoframe frame;
714 u8 buffer[10];
715 ssize_t err;
716 u32 value;
717
718 if (!hdmi->stereo) {
719 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
720 value &= ~GENERIC_CTRL_ENABLE;
721 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
722 return;
723 }
724
725 hdmi_vendor_infoframe_init(&frame);
726 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
727
728 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
729 if (err < 0) {
730 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
731 err);
732 return;
733 }
734
735 tegra_hdmi_write_infopack(hdmi, buffer, err);
736
737 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
738 value |= GENERIC_CTRL_ENABLE;
739 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
740}
741
742static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
743 const struct tmds_config *tmds)
744{
745 u32 value;
746
747 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
748 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
749 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
750
751 tegra_hdmi_writel(hdmi, tmds->drive_current,
752 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
753
754 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
755 value |= hdmi->config->fuse_override_value;
756 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
757
758 if (hdmi->config->has_sor_io_peak_current)
759 tegra_hdmi_writel(hdmi, tmds->peak_current,
760 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
761}
762
763static bool tegra_output_is_hdmi(struct tegra_output *output)
764{
765 struct edid *edid;
766
767 if (!output->connector.edid_blob_ptr)
768 return false;
769
770 edid = (struct edid *)output->connector.edid_blob_ptr->data;
771
772 return drm_detect_hdmi_monitor(edid);
773}
774
775static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
776 .dpms = drm_atomic_helper_connector_dpms,
777 .reset = drm_atomic_helper_connector_reset,
778 .detect = tegra_output_connector_detect,
779 .fill_modes = drm_helper_probe_single_connector_modes,
780 .destroy = tegra_output_connector_destroy,
781 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
782 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
783};
784
785static enum drm_mode_status
786tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
787 struct drm_display_mode *mode)
788{
789 struct tegra_output *output = connector_to_output(connector);
790 struct tegra_hdmi *hdmi = to_hdmi(output);
791 unsigned long pclk = mode->clock * 1000;
792 enum drm_mode_status status = MODE_OK;
793 struct clk *parent;
794 long err;
795
796 parent = clk_get_parent(hdmi->clk_parent);
797
798 err = clk_round_rate(parent, pclk * 4);
799 if (err <= 0)
800 status = MODE_NOCLOCK;
801
802 return status;
803}
804
805static const struct drm_connector_helper_funcs
806tegra_hdmi_connector_helper_funcs = {
807 .get_modes = tegra_output_connector_get_modes,
808 .mode_valid = tegra_hdmi_connector_mode_valid,
809 .best_encoder = tegra_output_connector_best_encoder,
810};
811
812static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
813 .destroy = tegra_output_encoder_destroy,
814};
815
816static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
817{
818 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
819 u32 value;
820
821 /*
822 * The following accesses registers of the display controller, so make
823 * sure it's only executed when the output is attached to one.
824 */
825 if (dc) {
826 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
827 value &= ~HDMI_ENABLE;
828 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
829
830 tegra_dc_commit(dc);
831 }
832}
833
834static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
835{
836 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
837 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
838 struct tegra_output *output = encoder_to_output(encoder);
839 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
840 struct device_node *node = output->dev->of_node;
841 struct tegra_hdmi *hdmi = to_hdmi(output);
842 unsigned int pulse_start, div82, pclk;
843 int retries = 1000;
844 u32 value;
845 int err;
846
847 hdmi->dvi = !tegra_output_is_hdmi(output);
848
849 pclk = mode->clock * 1000;
850 h_sync_width = mode->hsync_end - mode->hsync_start;
851 h_back_porch = mode->htotal - mode->hsync_end;
852 h_front_porch = mode->hsync_start - mode->hdisplay;
853
854 err = clk_set_rate(hdmi->clk, pclk);
855 if (err < 0) {
856 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
857 err);
858 }
859
860 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
861
862 /* power up sequence */
863 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
864 value &= ~SOR_PLL_PDBG;
865 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
866
867 usleep_range(10, 20);
868
869 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
870 value &= ~SOR_PLL_PWR;
871 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
872
873 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
874 DC_DISP_DISP_TIMING_OPTIONS);
875 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
876 DC_DISP_DISP_COLOR_CONTROL);
877
878 /* video_preamble uses h_pulse2 */
879 pulse_start = 1 + h_sync_width + h_back_porch - 10;
880
881 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
882
883 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
884 PULSE_LAST_END_A;
885 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
886
887 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
888 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
889
890 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
891 VSYNC_WINDOW_ENABLE;
892 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
893
894 if (dc->pipe)
895 value = HDMI_SRC_DISPLAYB;
896 else
897 value = HDMI_SRC_DISPLAYA;
898
899 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
900 (mode->vdisplay == 576)))
901 tegra_hdmi_writel(hdmi,
902 value | ARM_VIDEO_RANGE_FULL,
903 HDMI_NV_PDISP_INPUT_CONTROL);
904 else
905 tegra_hdmi_writel(hdmi,
906 value | ARM_VIDEO_RANGE_LIMITED,
907 HDMI_NV_PDISP_INPUT_CONTROL);
908
909 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
910 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
911 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
912
913 if (!hdmi->dvi) {
914 err = tegra_hdmi_setup_audio(hdmi, pclk);
915 if (err < 0)
916 hdmi->dvi = true;
917 }
918
919 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
920 /*
921 * TODO: add ELD support
922 */
923 }
924
925 rekey = HDMI_REKEY_DEFAULT;
926 value = HDMI_CTRL_REKEY(rekey);
927 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
928 h_front_porch - rekey - 18) / 32);
929
930 if (!hdmi->dvi)
931 value |= HDMI_CTRL_ENABLE;
932
933 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
934
935 if (hdmi->dvi)
936 tegra_hdmi_writel(hdmi, 0x0,
937 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
938 else
939 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
940 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
941
942 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
943 tegra_hdmi_setup_audio_infoframe(hdmi);
944 tegra_hdmi_setup_stereo_infoframe(hdmi);
945
946 /* TMDS CONFIG */
947 for (i = 0; i < hdmi->config->num_tmds; i++) {
948 if (pclk <= hdmi->config->tmds[i].pclk) {
949 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
950 break;
951 }
952 }
953
954 tegra_hdmi_writel(hdmi,
955 SOR_SEQ_PU_PC(0) |
956 SOR_SEQ_PU_PC_ALT(0) |
957 SOR_SEQ_PD_PC(8) |
958 SOR_SEQ_PD_PC_ALT(8),
959 HDMI_NV_PDISP_SOR_SEQ_CTL);
960
961 value = SOR_SEQ_INST_WAIT_TIME(1) |
962 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
963 SOR_SEQ_INST_HALT |
964 SOR_SEQ_INST_PIN_A_LOW |
965 SOR_SEQ_INST_PIN_B_LOW |
966 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
967
968 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
969 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
970
971 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
972 value &= ~SOR_CSTM_ROTCLK(~0);
973 value |= SOR_CSTM_ROTCLK(2);
974 value |= SOR_CSTM_PLLDIV;
975 value &= ~SOR_CSTM_LVDS_ENABLE;
976 value &= ~SOR_CSTM_MODE_MASK;
977 value |= SOR_CSTM_MODE_TMDS;
978 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
979
980 /* start SOR */
981 tegra_hdmi_writel(hdmi,
982 SOR_PWR_NORMAL_STATE_PU |
983 SOR_PWR_NORMAL_START_NORMAL |
984 SOR_PWR_SAFE_STATE_PD |
985 SOR_PWR_SETTING_NEW_TRIGGER,
986 HDMI_NV_PDISP_SOR_PWR);
987 tegra_hdmi_writel(hdmi,
988 SOR_PWR_NORMAL_STATE_PU |
989 SOR_PWR_NORMAL_START_NORMAL |
990 SOR_PWR_SAFE_STATE_PD |
991 SOR_PWR_SETTING_NEW_DONE,
992 HDMI_NV_PDISP_SOR_PWR);
993
994 do {
995 BUG_ON(--retries < 0);
996 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
997 } while (value & SOR_PWR_SETTING_NEW_PENDING);
998
999 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1000 SOR_STATE_ASY_OWNER_HEAD0 |
1001 SOR_STATE_ASY_SUBOWNER_BOTH |
1002 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1003 SOR_STATE_ASY_DEPOL_POS;
1004
1005 /* setup sync polarities */
1006 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1007 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1008
1009 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1010 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1011
1012 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1013 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1014
1015 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1016 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1017
1018 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1019
1020 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1021 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1022
1023 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1024 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1025 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1026 HDMI_NV_PDISP_SOR_STATE1);
1027 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1028
1029 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1030 value |= HDMI_ENABLE;
1031 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1032
1033 tegra_dc_commit(dc);
1034
1035 /* TODO: add HDCP support */
1036}
1037
1038static int
1039tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1040 struct drm_crtc_state *crtc_state,
1041 struct drm_connector_state *conn_state)
1042{
1043 struct tegra_output *output = encoder_to_output(encoder);
1044 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1045 unsigned long pclk = crtc_state->mode.clock * 1000;
1046 struct tegra_hdmi *hdmi = to_hdmi(output);
1047 int err;
1048
1049 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1050 pclk, 0);
1051 if (err < 0) {
1052 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1053 return err;
1054 }
1055
1056 return err;
1057}
1058
1059static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1060 .disable = tegra_hdmi_encoder_disable,
1061 .enable = tegra_hdmi_encoder_enable,
1062 .atomic_check = tegra_hdmi_encoder_atomic_check,
1063};
1064
1065static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1066{
1067 struct drm_info_node *node = s->private;
1068 struct tegra_hdmi *hdmi = node->info_ent->data;
1069 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1070 struct drm_device *drm = node->minor->dev;
1071 int err = 0;
1072
1073 drm_modeset_lock_all(drm);
1074
1075 if (!crtc || !crtc->state->active) {
1076 err = -EBUSY;
1077 goto unlock;
1078 }
1079
1080#define DUMP_REG(name) \
1081 seq_printf(s, "%-56s %#05x %08x\n", #name, name, \
1082 tegra_hdmi_readl(hdmi, name))
1083
1084 DUMP_REG(HDMI_CTXSW);
1085 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
1086 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
1087 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
1088 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
1089 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
1090 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
1091 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
1092 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
1093 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
1094 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
1095 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
1096 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
1097 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
1098 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
1099 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
1100 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
1101 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
1102 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
1103 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
1104 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
1105 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
1106 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
1107 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
1108 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
1109 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
1110 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
1111 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
1112 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
1113 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
1114 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1115 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
1116 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
1117 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
1118 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
1119 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1120 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
1121 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
1122 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1123 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
1124 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
1125 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
1126 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1127 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
1128 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
1129 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
1130 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
1131 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
1132 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
1133 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
1134 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
1135 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
1136 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
1137 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
1138 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
1139 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
1140 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1141 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1142 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
1143 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
1144 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
1145 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
1146 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
1147 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
1148 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
1149 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
1150 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1151 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1152 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1153 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1154 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1155 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1156 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1157 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1158 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1159 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1160 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1161 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1162 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1163 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1164 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1165 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1166 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1167 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1168 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1169 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1170 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1171 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1172 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1173 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1174 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1175 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1176 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1177 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1178 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1179 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1180 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1181 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1182 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1183 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1184 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1185 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1186 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1187 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1188 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1189 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1190 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1191 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1192 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1193 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1194 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1195 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1196 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1197 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1198 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1199 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1200 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1201 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1202 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1203 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1204 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1205 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1206 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1207 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1208 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1209 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1210 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1211 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1212 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1213 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1214 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1215 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1216 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1217 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1218 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1219 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1220 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1221 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1222 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1223 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1224 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1225 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1226 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1227 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1228 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1229 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1230 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1231 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1232 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1233 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1234 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1235 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1236 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1237 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1238 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1239 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1240 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1241 DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1242
1243#undef DUMP_REG
1244
1245unlock:
1246 drm_modeset_unlock_all(drm);
1247 return err;
1248}
1249
1250static struct drm_info_list debugfs_files[] = {
1251 { "regs", tegra_hdmi_show_regs, 0, NULL },
1252};
1253
1254static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1255 struct drm_minor *minor)
1256{
1257 unsigned int i;
1258 int err;
1259
1260 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1261 if (!hdmi->debugfs)
1262 return -ENOMEM;
1263
1264 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1265 GFP_KERNEL);
1266 if (!hdmi->debugfs_files) {
1267 err = -ENOMEM;
1268 goto remove;
1269 }
1270
1271 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1272 hdmi->debugfs_files[i].data = hdmi;
1273
1274 err = drm_debugfs_create_files(hdmi->debugfs_files,
1275 ARRAY_SIZE(debugfs_files),
1276 hdmi->debugfs, minor);
1277 if (err < 0)
1278 goto free;
1279
1280 hdmi->minor = minor;
1281
1282 return 0;
1283
1284free:
1285 kfree(hdmi->debugfs_files);
1286 hdmi->debugfs_files = NULL;
1287remove:
1288 debugfs_remove(hdmi->debugfs);
1289 hdmi->debugfs = NULL;
1290
1291 return err;
1292}
1293
1294static void tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1295{
1296 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1297 hdmi->minor);
1298 hdmi->minor = NULL;
1299
1300 kfree(hdmi->debugfs_files);
1301 hdmi->debugfs_files = NULL;
1302
1303 debugfs_remove(hdmi->debugfs);
1304 hdmi->debugfs = NULL;
1305}
1306
1307static int tegra_hdmi_init(struct host1x_client *client)
1308{
1309 struct drm_device *drm = dev_get_drvdata(client->parent);
1310 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1311 int err;
1312
1313 hdmi->output.dev = client->dev;
1314
1315 drm_connector_init(drm, &hdmi->output.connector,
1316 &tegra_hdmi_connector_funcs,
1317 DRM_MODE_CONNECTOR_HDMIA);
1318 drm_connector_helper_add(&hdmi->output.connector,
1319 &tegra_hdmi_connector_helper_funcs);
1320 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1321
1322 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1323 DRM_MODE_ENCODER_TMDS, NULL);
1324 drm_encoder_helper_add(&hdmi->output.encoder,
1325 &tegra_hdmi_encoder_helper_funcs);
1326
1327 drm_mode_connector_attach_encoder(&hdmi->output.connector,
1328 &hdmi->output.encoder);
1329 drm_connector_register(&hdmi->output.connector);
1330
1331 err = tegra_output_init(drm, &hdmi->output);
1332 if (err < 0) {
1333 dev_err(client->dev, "failed to initialize output: %d\n", err);
1334 return err;
1335 }
1336
1337 hdmi->output.encoder.possible_crtcs = 0x3;
1338
1339 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1340 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1341 if (err < 0)
1342 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1343 }
1344
1345 err = regulator_enable(hdmi->hdmi);
1346 if (err < 0) {
1347 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1348 err);
1349 return err;
1350 }
1351
1352 err = regulator_enable(hdmi->pll);
1353 if (err < 0) {
1354 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1355 return err;
1356 }
1357
1358 err = regulator_enable(hdmi->vdd);
1359 if (err < 0) {
1360 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1361 return err;
1362 }
1363
1364 err = clk_prepare_enable(hdmi->clk);
1365 if (err < 0) {
1366 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
1367 return err;
1368 }
1369
1370 reset_control_deassert(hdmi->rst);
1371
1372 return 0;
1373}
1374
1375static int tegra_hdmi_exit(struct host1x_client *client)
1376{
1377 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1378
1379 tegra_output_exit(&hdmi->output);
1380
1381 reset_control_assert(hdmi->rst);
1382 clk_disable_unprepare(hdmi->clk);
1383
1384 regulator_disable(hdmi->vdd);
1385 regulator_disable(hdmi->pll);
1386 regulator_disable(hdmi->hdmi);
1387
1388 if (IS_ENABLED(CONFIG_DEBUG_FS))
1389 tegra_hdmi_debugfs_exit(hdmi);
1390
1391 return 0;
1392}
1393
1394static const struct host1x_client_ops hdmi_client_ops = {
1395 .init = tegra_hdmi_init,
1396 .exit = tegra_hdmi_exit,
1397};
1398
1399static const struct tegra_hdmi_config tegra20_hdmi_config = {
1400 .tmds = tegra20_tmds_config,
1401 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1402 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1403 .fuse_override_value = 1 << 31,
1404 .has_sor_io_peak_current = false,
1405};
1406
1407static const struct tegra_hdmi_config tegra30_hdmi_config = {
1408 .tmds = tegra30_tmds_config,
1409 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1410 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1411 .fuse_override_value = 1 << 31,
1412 .has_sor_io_peak_current = false,
1413};
1414
1415static const struct tegra_hdmi_config tegra114_hdmi_config = {
1416 .tmds = tegra114_tmds_config,
1417 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1418 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1419 .fuse_override_value = 1 << 31,
1420 .has_sor_io_peak_current = true,
1421};
1422
1423static const struct tegra_hdmi_config tegra124_hdmi_config = {
1424 .tmds = tegra124_tmds_config,
1425 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1426 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1427 .fuse_override_value = 1 << 31,
1428 .has_sor_io_peak_current = true,
1429};
1430
1431static const struct of_device_id tegra_hdmi_of_match[] = {
1432 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1433 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1434 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1435 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1436 { },
1437};
1438MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1439
1440static int tegra_hdmi_probe(struct platform_device *pdev)
1441{
1442 const struct of_device_id *match;
1443 struct tegra_hdmi *hdmi;
1444 struct resource *regs;
1445 int err;
1446
1447 match = of_match_node(tegra_hdmi_of_match, pdev->dev.of_node);
1448 if (!match)
1449 return -ENODEV;
1450
1451 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1452 if (!hdmi)
1453 return -ENOMEM;
1454
1455 hdmi->config = match->data;
1456 hdmi->dev = &pdev->dev;
1457 hdmi->audio_source = AUTO;
1458 hdmi->audio_freq = 44100;
1459 hdmi->stereo = false;
1460 hdmi->dvi = false;
1461
1462 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1463 if (IS_ERR(hdmi->clk)) {
1464 dev_err(&pdev->dev, "failed to get clock\n");
1465 return PTR_ERR(hdmi->clk);
1466 }
1467
1468 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1469 if (IS_ERR(hdmi->rst)) {
1470 dev_err(&pdev->dev, "failed to get reset\n");
1471 return PTR_ERR(hdmi->rst);
1472 }
1473
1474 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1475 if (IS_ERR(hdmi->clk_parent))
1476 return PTR_ERR(hdmi->clk_parent);
1477
1478 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1479 if (err < 0) {
1480 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1481 return err;
1482 }
1483
1484 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1485 if (IS_ERR(hdmi->hdmi)) {
1486 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1487 return PTR_ERR(hdmi->hdmi);
1488 }
1489
1490 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1491 if (IS_ERR(hdmi->pll)) {
1492 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1493 return PTR_ERR(hdmi->pll);
1494 }
1495
1496 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1497 if (IS_ERR(hdmi->vdd)) {
1498 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1499 return PTR_ERR(hdmi->vdd);
1500 }
1501
1502 hdmi->output.dev = &pdev->dev;
1503
1504 err = tegra_output_probe(&hdmi->output);
1505 if (err < 0)
1506 return err;
1507
1508 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1509 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1510 if (IS_ERR(hdmi->regs))
1511 return PTR_ERR(hdmi->regs);
1512
1513 err = platform_get_irq(pdev, 0);
1514 if (err < 0)
1515 return err;
1516
1517 hdmi->irq = err;
1518
1519 INIT_LIST_HEAD(&hdmi->client.list);
1520 hdmi->client.ops = &hdmi_client_ops;
1521 hdmi->client.dev = &pdev->dev;
1522
1523 err = host1x_client_register(&hdmi->client);
1524 if (err < 0) {
1525 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1526 err);
1527 return err;
1528 }
1529
1530 platform_set_drvdata(pdev, hdmi);
1531
1532 return 0;
1533}
1534
1535static int tegra_hdmi_remove(struct platform_device *pdev)
1536{
1537 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1538 int err;
1539
1540 err = host1x_client_unregister(&hdmi->client);
1541 if (err < 0) {
1542 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1543 err);
1544 return err;
1545 }
1546
1547 tegra_output_remove(&hdmi->output);
1548
1549 clk_disable_unprepare(hdmi->clk_parent);
1550 clk_disable_unprepare(hdmi->clk);
1551
1552 return 0;
1553}
1554
1555struct platform_driver tegra_hdmi_driver = {
1556 .driver = {
1557 .name = "tegra-hdmi",
1558 .owner = THIS_MODULE,
1559 .of_match_table = tegra_hdmi_of_match,
1560 },
1561 .probe = tegra_hdmi_probe,
1562 .remove = tegra_hdmi_remove,
1563};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Avionic Design GmbH
4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 */
6
7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/delay.h>
10#include <linux/hdmi.h>
11#include <linux/math64.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/platform_device.h>
15#include <linux/pm_opp.h>
16#include <linux/pm_runtime.h>
17#include <linux/regulator/consumer.h>
18#include <linux/reset.h>
19
20#include <soc/tegra/common.h>
21#include <sound/hdmi-codec.h>
22
23#include <drm/drm_bridge_connector.h>
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_crtc.h>
26#include <drm/drm_debugfs.h>
27#include <drm/drm_eld.h>
28#include <drm/drm_file.h>
29#include <drm/drm_fourcc.h>
30#include <drm/drm_probe_helper.h>
31#include <drm/drm_simple_kms_helper.h>
32
33#include "hda.h"
34#include "hdmi.h"
35#include "drm.h"
36#include "dc.h"
37#include "trace.h"
38
39#define HDMI_ELD_BUFFER_SIZE 96
40
41struct tmds_config {
42 unsigned int pclk;
43 u32 pll0;
44 u32 pll1;
45 u32 pe_current;
46 u32 drive_current;
47 u32 peak_current;
48};
49
50struct tegra_hdmi_config {
51 const struct tmds_config *tmds;
52 unsigned int num_tmds;
53
54 unsigned long fuse_override_offset;
55 u32 fuse_override_value;
56
57 bool has_sor_io_peak_current;
58 bool has_hda;
59 bool has_hbr;
60};
61
62struct tegra_hdmi {
63 struct host1x_client client;
64 struct tegra_output output;
65 struct device *dev;
66
67 struct regulator *hdmi;
68 struct regulator *pll;
69 struct regulator *vdd;
70
71 void __iomem *regs;
72 unsigned int irq;
73
74 struct clk *clk_parent;
75 struct clk *clk;
76 struct reset_control *rst;
77
78 const struct tegra_hdmi_config *config;
79
80 unsigned int audio_source;
81 struct tegra_hda_format format;
82
83 unsigned int pixel_clock;
84 bool stereo;
85 bool dvi;
86
87 struct drm_info_list *debugfs_files;
88
89 struct platform_device *audio_pdev;
90 struct mutex audio_lock;
91};
92
93static inline struct tegra_hdmi *
94host1x_client_to_hdmi(struct host1x_client *client)
95{
96 return container_of(client, struct tegra_hdmi, client);
97}
98
99static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
100{
101 return container_of(output, struct tegra_hdmi, output);
102}
103
104#define HDMI_AUDIOCLK_FREQ 216000000
105#define HDMI_REKEY_DEFAULT 56
106
107enum {
108 AUTO = 0,
109 SPDIF,
110 HDA,
111};
112
113static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
114 unsigned int offset)
115{
116 u32 value = readl(hdmi->regs + (offset << 2));
117
118 trace_hdmi_readl(hdmi->dev, offset, value);
119
120 return value;
121}
122
123static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
124 unsigned int offset)
125{
126 trace_hdmi_writel(hdmi->dev, offset, value);
127 writel(value, hdmi->regs + (offset << 2));
128}
129
130struct tegra_hdmi_audio_config {
131 unsigned int n;
132 unsigned int cts;
133 unsigned int aval;
134};
135
136static const struct tmds_config tegra20_tmds_config[] = {
137 { /* slow pixel clock modes */
138 .pclk = 27000000,
139 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
140 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
141 SOR_PLL_TX_REG_LOAD(3),
142 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
143 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
144 PE_CURRENT1(PE_CURRENT_0_0_mA) |
145 PE_CURRENT2(PE_CURRENT_0_0_mA) |
146 PE_CURRENT3(PE_CURRENT_0_0_mA),
147 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
148 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
149 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
150 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
151 },
152 { /* high pixel clock modes */
153 .pclk = UINT_MAX,
154 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
155 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
156 SOR_PLL_TX_REG_LOAD(3),
157 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
158 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
159 PE_CURRENT1(PE_CURRENT_6_0_mA) |
160 PE_CURRENT2(PE_CURRENT_6_0_mA) |
161 PE_CURRENT3(PE_CURRENT_6_0_mA),
162 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
163 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
164 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
165 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
166 },
167};
168
169static const struct tmds_config tegra30_tmds_config[] = {
170 { /* 480p modes */
171 .pclk = 27000000,
172 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
173 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
174 SOR_PLL_TX_REG_LOAD(0),
175 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
176 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
177 PE_CURRENT1(PE_CURRENT_0_0_mA) |
178 PE_CURRENT2(PE_CURRENT_0_0_mA) |
179 PE_CURRENT3(PE_CURRENT_0_0_mA),
180 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
181 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
182 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
183 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
184 }, { /* 720p modes */
185 .pclk = 74250000,
186 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
187 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
188 SOR_PLL_TX_REG_LOAD(0),
189 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
190 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
191 PE_CURRENT1(PE_CURRENT_5_0_mA) |
192 PE_CURRENT2(PE_CURRENT_5_0_mA) |
193 PE_CURRENT3(PE_CURRENT_5_0_mA),
194 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
195 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
196 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
197 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
198 }, { /* 1080p modes */
199 .pclk = UINT_MAX,
200 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
201 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
202 SOR_PLL_TX_REG_LOAD(0),
203 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
204 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
205 PE_CURRENT1(PE_CURRENT_5_0_mA) |
206 PE_CURRENT2(PE_CURRENT_5_0_mA) |
207 PE_CURRENT3(PE_CURRENT_5_0_mA),
208 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
209 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
210 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
211 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
212 },
213};
214
215static const struct tmds_config tegra114_tmds_config[] = {
216 { /* 480p/576p / 25.2MHz/27MHz modes */
217 .pclk = 27000000,
218 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
219 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
220 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
221 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
222 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
223 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
224 PE_CURRENT3(PE_CURRENT_0_mA_T114),
225 .drive_current =
226 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
227 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
228 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
229 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
230 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
231 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
232 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
233 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
234 }, { /* 720p / 74.25MHz modes */
235 .pclk = 74250000,
236 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
237 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
238 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
239 SOR_PLL_TMDS_TERMADJ(0),
240 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
241 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
242 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
243 PE_CURRENT3(PE_CURRENT_15_mA_T114),
244 .drive_current =
245 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
246 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
247 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
248 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
249 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
250 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
251 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
252 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
253 }, { /* 1080p / 148.5MHz modes */
254 .pclk = 148500000,
255 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
256 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
257 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
258 SOR_PLL_TMDS_TERMADJ(0),
259 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
260 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
261 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
262 PE_CURRENT3(PE_CURRENT_10_mA_T114),
263 .drive_current =
264 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
265 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
266 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
267 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
268 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
269 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
270 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
271 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
272 }, { /* 225/297MHz modes */
273 .pclk = UINT_MAX,
274 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
275 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
276 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
277 | SOR_PLL_TMDS_TERM_ENABLE,
278 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
279 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
280 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
281 PE_CURRENT3(PE_CURRENT_0_mA_T114),
282 .drive_current =
283 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
284 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
285 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
286 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
287 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
288 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
289 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
290 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
291 },
292};
293
294static const struct tmds_config tegra124_tmds_config[] = {
295 { /* 480p/576p / 25.2MHz/27MHz modes */
296 .pclk = 27000000,
297 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
298 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
299 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
300 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
301 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
302 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
303 PE_CURRENT3(PE_CURRENT_0_mA_T114),
304 .drive_current =
305 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
306 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
307 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
308 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
309 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
310 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
311 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
312 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
313 }, { /* 720p / 74.25MHz modes */
314 .pclk = 74250000,
315 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
316 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
317 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
318 SOR_PLL_TMDS_TERMADJ(0),
319 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
320 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
321 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
322 PE_CURRENT3(PE_CURRENT_15_mA_T114),
323 .drive_current =
324 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
325 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
326 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
327 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
328 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
329 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
330 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
331 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
332 }, { /* 1080p / 148.5MHz modes */
333 .pclk = 148500000,
334 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
335 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
336 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
337 SOR_PLL_TMDS_TERMADJ(0),
338 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
339 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
340 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
341 PE_CURRENT3(PE_CURRENT_10_mA_T114),
342 .drive_current =
343 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
344 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
345 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
346 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
347 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
348 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
349 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
350 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
351 }, { /* 225/297MHz modes */
352 .pclk = UINT_MAX,
353 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
354 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
355 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
356 | SOR_PLL_TMDS_TERM_ENABLE,
357 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
358 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
359 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
360 PE_CURRENT3(PE_CURRENT_0_mA_T114),
361 .drive_current =
362 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
363 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
364 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
365 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
366 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
367 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
368 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
369 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
370 },
371};
372
373static void tegra_hdmi_audio_lock(struct tegra_hdmi *hdmi)
374{
375 mutex_lock(&hdmi->audio_lock);
376 disable_irq(hdmi->irq);
377}
378
379static void tegra_hdmi_audio_unlock(struct tegra_hdmi *hdmi)
380{
381 enable_irq(hdmi->irq);
382 mutex_unlock(&hdmi->audio_lock);
383}
384
385static int
386tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
387 struct tegra_hdmi_audio_config *config)
388{
389 const unsigned int afreq = 128 * audio_freq;
390 const unsigned int min_n = afreq / 1500;
391 const unsigned int max_n = afreq / 300;
392 const unsigned int ideal_n = afreq / 1000;
393 int64_t min_err = (uint64_t)-1 >> 1;
394 unsigned int min_delta = -1;
395 int n;
396
397 memset(config, 0, sizeof(*config));
398 config->n = -1;
399
400 for (n = min_n; n <= max_n; n++) {
401 uint64_t cts_f, aval_f;
402 unsigned int delta;
403 int64_t cts, err;
404
405 /* compute aval in 48.16 fixed point */
406 aval_f = ((int64_t)24000000 << 16) * n;
407 do_div(aval_f, afreq);
408 /* It should round without any rest */
409 if (aval_f & 0xFFFF)
410 continue;
411
412 /* Compute cts in 48.16 fixed point */
413 cts_f = ((int64_t)pix_clock << 16) * n;
414 do_div(cts_f, afreq);
415 /* Round it to the nearest integer */
416 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
417
418 delta = abs(n - ideal_n);
419
420 /* Compute the absolute error */
421 err = abs((int64_t)cts_f - cts);
422 if (err < min_err || (err == min_err && delta < min_delta)) {
423 config->n = n;
424 config->cts = cts >> 16;
425 config->aval = aval_f >> 16;
426 min_delta = delta;
427 min_err = err;
428 }
429 }
430
431 return config->n != -1 ? 0 : -EINVAL;
432}
433
434static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
435{
436 const unsigned int freqs[] = {
437 32000, 44100, 48000, 88200, 96000, 176400, 192000
438 };
439 unsigned int i;
440
441 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
442 unsigned int f = freqs[i];
443 unsigned int eight_half;
444 unsigned int delta;
445 u32 value;
446
447 if (f > 96000)
448 delta = 2;
449 else if (f > 48000)
450 delta = 6;
451 else
452 delta = 9;
453
454 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
455 value = AUDIO_FS_LOW(eight_half - delta) |
456 AUDIO_FS_HIGH(eight_half + delta);
457 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
458 }
459}
460
461static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
462{
463 static const struct {
464 unsigned int sample_rate;
465 unsigned int offset;
466 } regs[] = {
467 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
468 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
469 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
470 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
471 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
472 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
473 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
474 };
475 unsigned int i;
476
477 for (i = 0; i < ARRAY_SIZE(regs); i++) {
478 if (regs[i].sample_rate == hdmi->format.sample_rate) {
479 tegra_hdmi_writel(hdmi, value, regs[i].offset);
480 break;
481 }
482 }
483}
484
485static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
486{
487 struct tegra_hdmi_audio_config config;
488 u32 source, value;
489 int err;
490
491 switch (hdmi->audio_source) {
492 case HDA:
493 if (hdmi->config->has_hda)
494 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
495 else
496 return -EINVAL;
497
498 break;
499
500 case SPDIF:
501 if (hdmi->config->has_hda)
502 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
503 else
504 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
505 break;
506
507 default:
508 if (hdmi->config->has_hda)
509 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
510 else
511 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
512 break;
513 }
514
515 /*
516 * Tegra30 and later use a slightly modified version of the register
517 * layout to accomodate for changes related to supporting HDA as the
518 * audio input source for HDMI. The source select field has moved to
519 * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
520 * per block fields remain in the AUDIO_CNTRL0 register.
521 */
522 if (hdmi->config->has_hda) {
523 /*
524 * Inject null samples into the audio FIFO for every frame in
525 * which the codec did not receive any samples. This applies
526 * to stereo LPCM only.
527 *
528 * XXX: This seems to be a remnant of MCP days when this was
529 * used to work around issues with monitors not being able to
530 * play back system startup sounds early. It is possibly not
531 * needed on Linux at all.
532 */
533 if (hdmi->format.channels == 2)
534 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
535 else
536 value = 0;
537
538 value |= source;
539
540 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
541 }
542
543 /*
544 * On Tegra20, HDA is not a supported audio source and the source
545 * select field is part of the AUDIO_CNTRL0 register.
546 */
547 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
548 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
549
550 if (!hdmi->config->has_hda)
551 value |= source;
552
553 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
554
555 /*
556 * Advertise support for High Bit-Rate on Tegra114 and later.
557 */
558 if (hdmi->config->has_hbr) {
559 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
560 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
561 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
562 }
563
564 err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
565 hdmi->pixel_clock, &config);
566 if (err < 0) {
567 dev_err(hdmi->dev,
568 "cannot set audio to %u Hz at %u Hz pixel clock\n",
569 hdmi->format.sample_rate, hdmi->pixel_clock);
570 return err;
571 }
572
573 dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
574 hdmi->pixel_clock, config.n, config.cts, config.aval);
575
576 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
577
578 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
579 AUDIO_N_VALUE(config.n - 1);
580 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
581
582 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
583 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
584
585 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
586 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
587
588 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
589 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
590
591 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
592 value &= ~AUDIO_N_RESETF;
593 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
594
595 if (hdmi->config->has_hda)
596 tegra_hdmi_write_aval(hdmi, config.aval);
597
598 tegra_hdmi_setup_audio_fs_tables(hdmi);
599
600 return 0;
601}
602
603static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
604{
605 u32 value;
606
607 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
608 value &= ~GENERIC_CTRL_AUDIO;
609 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
610}
611
612static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
613{
614 u32 value;
615
616 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
617 value |= GENERIC_CTRL_AUDIO;
618 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
619}
620
621static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
622{
623 size_t length = drm_eld_size(hdmi->output.connector.eld), i;
624 u32 value;
625
626 for (i = 0; i < length; i++)
627 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
628 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
629
630 /*
631 * The HDA codec will always report an ELD buffer size of 96 bytes and
632 * the HDA codec driver will check that each byte read from the buffer
633 * is valid. Therefore every byte must be written, even if no 96 bytes
634 * were parsed from EDID.
635 */
636 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
637 tegra_hdmi_writel(hdmi, i << 8 | 0,
638 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
639
640 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
641 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
642}
643
644static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
645{
646 u32 value = 0;
647 size_t i;
648
649 for (i = size; i > 0; i--)
650 value = (value << 8) | ptr[i - 1];
651
652 return value;
653}
654
655static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
656 size_t size)
657{
658 const u8 *ptr = data;
659 unsigned long offset;
660 size_t i, j;
661 u32 value;
662
663 switch (ptr[0]) {
664 case HDMI_INFOFRAME_TYPE_AVI:
665 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
666 break;
667
668 case HDMI_INFOFRAME_TYPE_AUDIO:
669 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
670 break;
671
672 case HDMI_INFOFRAME_TYPE_VENDOR:
673 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
674 break;
675
676 default:
677 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
678 ptr[0]);
679 return;
680 }
681
682 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
683 INFOFRAME_HEADER_VERSION(ptr[1]) |
684 INFOFRAME_HEADER_LEN(ptr[2]);
685 tegra_hdmi_writel(hdmi, value, offset);
686 offset++;
687
688 /*
689 * Each subpack contains 7 bytes, divided into:
690 * - subpack_low: bytes 0 - 3
691 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
692 */
693 for (i = 3, j = 0; i < size; i += 7, j += 8) {
694 size_t rem = size - i, num = min_t(size_t, rem, 4);
695
696 value = tegra_hdmi_subpack(&ptr[i], num);
697 tegra_hdmi_writel(hdmi, value, offset++);
698
699 num = min_t(size_t, rem - num, 3);
700
701 value = tegra_hdmi_subpack(&ptr[i + 4], num);
702 tegra_hdmi_writel(hdmi, value, offset++);
703 }
704}
705
706static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
707 struct drm_display_mode *mode)
708{
709 struct hdmi_avi_infoframe frame;
710 u8 buffer[17];
711 ssize_t err;
712
713 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
714 &hdmi->output.connector, mode);
715 if (err < 0) {
716 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
717 return;
718 }
719
720 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
721 if (err < 0) {
722 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
723 return;
724 }
725
726 tegra_hdmi_write_infopack(hdmi, buffer, err);
727}
728
729static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
730{
731 u32 value;
732
733 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
734 value &= ~INFOFRAME_CTRL_ENABLE;
735 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
736}
737
738static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
739{
740 u32 value;
741
742 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
743 value |= INFOFRAME_CTRL_ENABLE;
744 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
745}
746
747static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
748{
749 struct hdmi_audio_infoframe frame;
750 u8 buffer[14];
751 ssize_t err;
752
753 err = hdmi_audio_infoframe_init(&frame);
754 if (err < 0) {
755 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
756 err);
757 return;
758 }
759
760 frame.channels = hdmi->format.channels;
761
762 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
763 if (err < 0) {
764 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
765 err);
766 return;
767 }
768
769 /*
770 * The audio infoframe has only one set of subpack registers, so the
771 * infoframe needs to be truncated. One set of subpack registers can
772 * contain 7 bytes. Including the 3 byte header only the first 10
773 * bytes can be programmed.
774 */
775 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
776}
777
778static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
779{
780 u32 value;
781
782 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
783 value &= ~INFOFRAME_CTRL_ENABLE;
784 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
785}
786
787static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
788{
789 u32 value;
790
791 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
792 value |= INFOFRAME_CTRL_ENABLE;
793 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
794}
795
796static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
797{
798 struct hdmi_vendor_infoframe frame;
799 u8 buffer[10];
800 ssize_t err;
801
802 hdmi_vendor_infoframe_init(&frame);
803 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
804
805 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
806 if (err < 0) {
807 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
808 err);
809 return;
810 }
811
812 tegra_hdmi_write_infopack(hdmi, buffer, err);
813}
814
815static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
816{
817 u32 value;
818
819 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
820 value &= ~GENERIC_CTRL_ENABLE;
821 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
822}
823
824static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
825{
826 u32 value;
827
828 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
829 value |= GENERIC_CTRL_ENABLE;
830 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
831}
832
833static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
834 const struct tmds_config *tmds)
835{
836 u32 value;
837
838 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
839 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
840 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
841
842 tegra_hdmi_writel(hdmi, tmds->drive_current,
843 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
844
845 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
846 value |= hdmi->config->fuse_override_value;
847 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
848
849 if (hdmi->config->has_sor_io_peak_current)
850 tegra_hdmi_writel(hdmi, tmds->peak_current,
851 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
852}
853
854static int tegra_hdmi_reconfigure_audio(struct tegra_hdmi *hdmi)
855{
856 int err;
857
858 err = tegra_hdmi_setup_audio(hdmi);
859 if (err < 0) {
860 tegra_hdmi_disable_audio_infoframe(hdmi);
861 tegra_hdmi_disable_audio(hdmi);
862 } else {
863 tegra_hdmi_setup_audio_infoframe(hdmi);
864 tegra_hdmi_enable_audio_infoframe(hdmi);
865 tegra_hdmi_enable_audio(hdmi);
866 }
867
868 return err;
869}
870
871static bool tegra_output_is_hdmi(struct tegra_output *output)
872{
873 return output->connector.display_info.is_hdmi;
874}
875
876static enum drm_connector_status
877tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
878{
879 struct tegra_output *output = connector_to_output(connector);
880 struct tegra_hdmi *hdmi = to_hdmi(output);
881 enum drm_connector_status status;
882
883 status = tegra_output_connector_detect(connector, force);
884 if (status == connector_status_connected)
885 return status;
886
887 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
888 return status;
889}
890
891#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
892
893static const struct debugfs_reg32 tegra_hdmi_regs[] = {
894 DEBUGFS_REG32(HDMI_CTXSW),
895 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
896 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
897 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
898 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
899 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
900 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
901 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
902 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
903 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
904 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
905 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
906 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
907 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
908 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
909 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
910 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
911 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
912 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
913 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
914 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
915 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
916 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
917 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
918 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
919 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
920 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
921 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
922 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
923 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
924 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
925 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
926 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
927 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
928 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
929 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
930 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
931 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
932 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
933 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
934 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
935 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
936 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
937 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
938 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
939 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
940 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
941 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
942 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
943 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
944 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
945 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
946 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
947 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
948 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
949 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
950 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
951 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
952 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
953 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
954 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
955 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
956 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
957 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
958 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
959 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
960 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
961 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
962 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
963 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
964 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
965 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
966 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
967 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
968 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
969 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
970 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
971 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
972 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
973 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
974 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
975 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
976 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
977 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
978 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
979 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
980 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
981 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
982 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
983 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
984 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
985 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
986 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
987 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
988 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
989 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
990 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
991 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
992 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
993 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
994 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
995 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
996 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
997 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
998 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
999 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
1000 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
1001 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
1002 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1003 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1004 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1005 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1006 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1007 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1008 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1009 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1010 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1011 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1012 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1013 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1014 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1015 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1016 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1017 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1018 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1019 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1020 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1021 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1022 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1023 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1024 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1025 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1026 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1027 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1028 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1029 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1030 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1031 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1032 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1033 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1034 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1035 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1036 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1037 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1038 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1039 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1040 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1041 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1042 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1043 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1044 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1045 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1046 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1047 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1048 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1049 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1050 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1051 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1052 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1053 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1054 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1055 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1056 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1057 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1058};
1059
1060static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1061{
1062 struct drm_info_node *node = s->private;
1063 struct tegra_hdmi *hdmi = node->info_ent->data;
1064 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1065 struct drm_device *drm = node->minor->dev;
1066 unsigned int i;
1067 int err = 0;
1068
1069 drm_modeset_lock_all(drm);
1070
1071 if (!crtc || !crtc->state->active) {
1072 err = -EBUSY;
1073 goto unlock;
1074 }
1075
1076 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1077 unsigned int offset = tegra_hdmi_regs[i].offset;
1078
1079 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1080 offset, tegra_hdmi_readl(hdmi, offset));
1081 }
1082
1083unlock:
1084 drm_modeset_unlock_all(drm);
1085 return err;
1086}
1087
1088static struct drm_info_list debugfs_files[] = {
1089 { "regs", tegra_hdmi_show_regs, 0, NULL },
1090};
1091
1092static int tegra_hdmi_late_register(struct drm_connector *connector)
1093{
1094 struct tegra_output *output = connector_to_output(connector);
1095 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1096 struct drm_minor *minor = connector->dev->primary;
1097 struct dentry *root = connector->debugfs_entry;
1098 struct tegra_hdmi *hdmi = to_hdmi(output);
1099
1100 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1101 GFP_KERNEL);
1102 if (!hdmi->debugfs_files)
1103 return -ENOMEM;
1104
1105 for (i = 0; i < count; i++)
1106 hdmi->debugfs_files[i].data = hdmi;
1107
1108 drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1109
1110 return 0;
1111}
1112
1113static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1114{
1115 struct tegra_output *output = connector_to_output(connector);
1116 struct drm_minor *minor = connector->dev->primary;
1117 unsigned int count = ARRAY_SIZE(debugfs_files);
1118 struct tegra_hdmi *hdmi = to_hdmi(output);
1119
1120 drm_debugfs_remove_files(hdmi->debugfs_files, count,
1121 connector->debugfs_entry, minor);
1122 kfree(hdmi->debugfs_files);
1123 hdmi->debugfs_files = NULL;
1124}
1125
1126static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1127 .reset = drm_atomic_helper_connector_reset,
1128 .detect = tegra_hdmi_connector_detect,
1129 .fill_modes = drm_helper_probe_single_connector_modes,
1130 .destroy = tegra_output_connector_destroy,
1131 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1132 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1133 .late_register = tegra_hdmi_late_register,
1134 .early_unregister = tegra_hdmi_early_unregister,
1135};
1136
1137static enum drm_mode_status
1138tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1139 struct drm_display_mode *mode)
1140{
1141 struct tegra_output *output = connector_to_output(connector);
1142 struct tegra_hdmi *hdmi = to_hdmi(output);
1143 unsigned long pclk = mode->clock * 1000;
1144 enum drm_mode_status status = MODE_OK;
1145 struct clk *parent;
1146 long err;
1147
1148 parent = clk_get_parent(hdmi->clk_parent);
1149
1150 err = clk_round_rate(parent, pclk * 4);
1151 if (err <= 0)
1152 status = MODE_NOCLOCK;
1153
1154 return status;
1155}
1156
1157static const struct drm_connector_helper_funcs
1158tegra_hdmi_connector_helper_funcs = {
1159 .get_modes = tegra_output_connector_get_modes,
1160 .mode_valid = tegra_hdmi_connector_mode_valid,
1161};
1162
1163static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1164{
1165 struct tegra_output *output = encoder_to_output(encoder);
1166 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1167 struct tegra_hdmi *hdmi = to_hdmi(output);
1168 u32 value;
1169 int err;
1170
1171 tegra_hdmi_audio_lock(hdmi);
1172
1173 /*
1174 * The following accesses registers of the display controller, so make
1175 * sure it's only executed when the output is attached to one.
1176 */
1177 if (dc) {
1178 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1179 value &= ~HDMI_ENABLE;
1180 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1181
1182 tegra_dc_commit(dc);
1183 }
1184
1185 if (!hdmi->dvi) {
1186 if (hdmi->stereo)
1187 tegra_hdmi_disable_stereo_infoframe(hdmi);
1188
1189 tegra_hdmi_disable_audio_infoframe(hdmi);
1190 tegra_hdmi_disable_avi_infoframe(hdmi);
1191 tegra_hdmi_disable_audio(hdmi);
1192 }
1193
1194 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1195 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1196
1197 hdmi->pixel_clock = 0;
1198
1199 tegra_hdmi_audio_unlock(hdmi);
1200
1201 err = host1x_client_suspend(&hdmi->client);
1202 if (err < 0)
1203 dev_err(hdmi->dev, "failed to suspend: %d\n", err);
1204}
1205
1206static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1207{
1208 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1209 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1210 struct tegra_output *output = encoder_to_output(encoder);
1211 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1212 struct tegra_hdmi *hdmi = to_hdmi(output);
1213 unsigned int pulse_start, div82;
1214 int retries = 1000;
1215 u32 value;
1216 int err;
1217
1218 err = host1x_client_resume(&hdmi->client);
1219 if (err < 0) {
1220 dev_err(hdmi->dev, "failed to resume: %d\n", err);
1221 return;
1222 }
1223
1224 tegra_hdmi_audio_lock(hdmi);
1225
1226 /*
1227 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1228 * is used for interoperability between the HDA codec driver and the
1229 * HDMI driver.
1230 */
1231 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1232 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1233
1234 hdmi->pixel_clock = mode->clock * 1000;
1235 h_sync_width = mode->hsync_end - mode->hsync_start;
1236 h_back_porch = mode->htotal - mode->hsync_end;
1237 h_front_porch = mode->hsync_start - mode->hdisplay;
1238
1239 err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock);
1240 if (err < 0) {
1241 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1242 err);
1243 }
1244
1245 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1246
1247 /* power up sequence */
1248 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1249 value &= ~SOR_PLL_PDBG;
1250 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1251
1252 usleep_range(10, 20);
1253
1254 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1255 value &= ~SOR_PLL_PWR;
1256 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1257
1258 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1259 DC_DISP_DISP_TIMING_OPTIONS);
1260 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1261 DC_DISP_DISP_COLOR_CONTROL);
1262
1263 /* video_preamble uses h_pulse2 */
1264 pulse_start = 1 + h_sync_width + h_back_porch - 10;
1265
1266 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1267
1268 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1269 PULSE_LAST_END_A;
1270 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1271
1272 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1273 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1274
1275 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1276 VSYNC_WINDOW_ENABLE;
1277 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1278
1279 if (dc->pipe)
1280 value = HDMI_SRC_DISPLAYB;
1281 else
1282 value = HDMI_SRC_DISPLAYA;
1283
1284 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1285 (mode->vdisplay == 576)))
1286 tegra_hdmi_writel(hdmi,
1287 value | ARM_VIDEO_RANGE_FULL,
1288 HDMI_NV_PDISP_INPUT_CONTROL);
1289 else
1290 tegra_hdmi_writel(hdmi,
1291 value | ARM_VIDEO_RANGE_LIMITED,
1292 HDMI_NV_PDISP_INPUT_CONTROL);
1293
1294 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1295 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1296 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1297
1298 hdmi->dvi = !tegra_output_is_hdmi(output);
1299 if (!hdmi->dvi) {
1300 /*
1301 * Make sure that the audio format has been configured before
1302 * enabling audio, otherwise we may try to divide by zero.
1303 */
1304 if (hdmi->format.sample_rate > 0) {
1305 err = tegra_hdmi_setup_audio(hdmi);
1306 if (err < 0)
1307 hdmi->dvi = true;
1308 }
1309 }
1310
1311 if (hdmi->config->has_hda)
1312 tegra_hdmi_write_eld(hdmi);
1313
1314 rekey = HDMI_REKEY_DEFAULT;
1315 value = HDMI_CTRL_REKEY(rekey);
1316 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1317 h_front_porch - rekey - 18) / 32);
1318
1319 if (!hdmi->dvi)
1320 value |= HDMI_CTRL_ENABLE;
1321
1322 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1323
1324 if (!hdmi->dvi) {
1325 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1326 tegra_hdmi_setup_audio_infoframe(hdmi);
1327
1328 if (hdmi->stereo)
1329 tegra_hdmi_setup_stereo_infoframe(hdmi);
1330 }
1331
1332 /* TMDS CONFIG */
1333 for (i = 0; i < hdmi->config->num_tmds; i++) {
1334 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1335 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1336 break;
1337 }
1338 }
1339
1340 tegra_hdmi_writel(hdmi,
1341 SOR_SEQ_PU_PC(0) |
1342 SOR_SEQ_PU_PC_ALT(0) |
1343 SOR_SEQ_PD_PC(8) |
1344 SOR_SEQ_PD_PC_ALT(8),
1345 HDMI_NV_PDISP_SOR_SEQ_CTL);
1346
1347 value = SOR_SEQ_INST_WAIT_TIME(1) |
1348 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1349 SOR_SEQ_INST_HALT |
1350 SOR_SEQ_INST_PIN_A_LOW |
1351 SOR_SEQ_INST_PIN_B_LOW |
1352 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1353
1354 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1355 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1356
1357 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1358 value &= ~SOR_CSTM_ROTCLK(~0);
1359 value |= SOR_CSTM_ROTCLK(2);
1360 value |= SOR_CSTM_PLLDIV;
1361 value &= ~SOR_CSTM_LVDS_ENABLE;
1362 value &= ~SOR_CSTM_MODE_MASK;
1363 value |= SOR_CSTM_MODE_TMDS;
1364 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1365
1366 /* start SOR */
1367 tegra_hdmi_writel(hdmi,
1368 SOR_PWR_NORMAL_STATE_PU |
1369 SOR_PWR_NORMAL_START_NORMAL |
1370 SOR_PWR_SAFE_STATE_PD |
1371 SOR_PWR_SETTING_NEW_TRIGGER,
1372 HDMI_NV_PDISP_SOR_PWR);
1373 tegra_hdmi_writel(hdmi,
1374 SOR_PWR_NORMAL_STATE_PU |
1375 SOR_PWR_NORMAL_START_NORMAL |
1376 SOR_PWR_SAFE_STATE_PD |
1377 SOR_PWR_SETTING_NEW_DONE,
1378 HDMI_NV_PDISP_SOR_PWR);
1379
1380 do {
1381 BUG_ON(--retries < 0);
1382 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1383 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1384
1385 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1386 SOR_STATE_ASY_OWNER_HEAD0 |
1387 SOR_STATE_ASY_SUBOWNER_BOTH |
1388 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1389 SOR_STATE_ASY_DEPOL_POS;
1390
1391 /* setup sync polarities */
1392 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1393 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1394
1395 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1396 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1397
1398 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1399 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1400
1401 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1402 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1403
1404 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1405
1406 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1407 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1408
1409 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1410 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1411 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1412 HDMI_NV_PDISP_SOR_STATE1);
1413 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1414
1415 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1416 value |= HDMI_ENABLE;
1417 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1418
1419 tegra_dc_commit(dc);
1420
1421 if (!hdmi->dvi) {
1422 tegra_hdmi_enable_avi_infoframe(hdmi);
1423 tegra_hdmi_enable_audio_infoframe(hdmi);
1424 tegra_hdmi_enable_audio(hdmi);
1425
1426 if (hdmi->stereo)
1427 tegra_hdmi_enable_stereo_infoframe(hdmi);
1428 }
1429
1430 /* TODO: add HDCP support */
1431
1432 tegra_hdmi_audio_unlock(hdmi);
1433}
1434
1435static int
1436tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1437 struct drm_crtc_state *crtc_state,
1438 struct drm_connector_state *conn_state)
1439{
1440 struct tegra_output *output = encoder_to_output(encoder);
1441 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1442 unsigned long pclk = crtc_state->mode.clock * 1000;
1443 struct tegra_hdmi *hdmi = to_hdmi(output);
1444 int err;
1445
1446 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1447 pclk, 0);
1448 if (err < 0) {
1449 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1450 return err;
1451 }
1452
1453 return err;
1454}
1455
1456static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1457 .disable = tegra_hdmi_encoder_disable,
1458 .enable = tegra_hdmi_encoder_enable,
1459 .atomic_check = tegra_hdmi_encoder_atomic_check,
1460};
1461
1462static int tegra_hdmi_hw_params(struct device *dev, void *data,
1463 struct hdmi_codec_daifmt *fmt,
1464 struct hdmi_codec_params *hparms)
1465{
1466 struct tegra_hdmi *hdmi = data;
1467 int ret = 0;
1468
1469 tegra_hdmi_audio_lock(hdmi);
1470
1471 hdmi->format.sample_rate = hparms->sample_rate;
1472 hdmi->format.channels = hparms->channels;
1473
1474 if (hdmi->pixel_clock && !hdmi->dvi)
1475 ret = tegra_hdmi_reconfigure_audio(hdmi);
1476
1477 tegra_hdmi_audio_unlock(hdmi);
1478
1479 return ret;
1480}
1481
1482static int tegra_hdmi_audio_startup(struct device *dev, void *data)
1483{
1484 struct tegra_hdmi *hdmi = data;
1485 int ret;
1486
1487 ret = host1x_client_resume(&hdmi->client);
1488 if (ret < 0)
1489 dev_err(hdmi->dev, "failed to resume: %d\n", ret);
1490
1491 return ret;
1492}
1493
1494static void tegra_hdmi_audio_shutdown(struct device *dev, void *data)
1495{
1496 struct tegra_hdmi *hdmi = data;
1497 int ret;
1498
1499 tegra_hdmi_audio_lock(hdmi);
1500
1501 hdmi->format.sample_rate = 0;
1502 hdmi->format.channels = 0;
1503
1504 tegra_hdmi_audio_unlock(hdmi);
1505
1506 ret = host1x_client_suspend(&hdmi->client);
1507 if (ret < 0)
1508 dev_err(hdmi->dev, "failed to suspend: %d\n", ret);
1509}
1510
1511static const struct hdmi_codec_ops tegra_hdmi_codec_ops = {
1512 .hw_params = tegra_hdmi_hw_params,
1513 .audio_startup = tegra_hdmi_audio_startup,
1514 .audio_shutdown = tegra_hdmi_audio_shutdown,
1515};
1516
1517static int tegra_hdmi_codec_register(struct tegra_hdmi *hdmi)
1518{
1519 struct hdmi_codec_pdata codec_data = {};
1520
1521 if (hdmi->config->has_hda)
1522 return 0;
1523
1524 codec_data.ops = &tegra_hdmi_codec_ops;
1525 codec_data.data = hdmi;
1526 codec_data.spdif = 1;
1527
1528 hdmi->audio_pdev = platform_device_register_data(hdmi->dev,
1529 HDMI_CODEC_DRV_NAME,
1530 PLATFORM_DEVID_AUTO,
1531 &codec_data,
1532 sizeof(codec_data));
1533 if (IS_ERR(hdmi->audio_pdev))
1534 return PTR_ERR(hdmi->audio_pdev);
1535
1536 hdmi->format.channels = 2;
1537
1538 return 0;
1539}
1540
1541static void tegra_hdmi_codec_unregister(struct tegra_hdmi *hdmi)
1542{
1543 if (hdmi->audio_pdev)
1544 platform_device_unregister(hdmi->audio_pdev);
1545}
1546
1547static int tegra_hdmi_init(struct host1x_client *client)
1548{
1549 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1550 struct drm_device *drm = dev_get_drvdata(client->host);
1551 struct drm_connector *connector;
1552 int err;
1553
1554 hdmi->output.dev = client->dev;
1555
1556 drm_simple_encoder_init(drm, &hdmi->output.encoder,
1557 DRM_MODE_ENCODER_TMDS);
1558 drm_encoder_helper_add(&hdmi->output.encoder,
1559 &tegra_hdmi_encoder_helper_funcs);
1560
1561 if (hdmi->output.bridge) {
1562 err = drm_bridge_attach(&hdmi->output.encoder, hdmi->output.bridge,
1563 NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1564 if (err) {
1565 dev_err(client->dev, "failed to attach bridge: %d\n",
1566 err);
1567 return err;
1568 }
1569
1570 connector = drm_bridge_connector_init(drm, &hdmi->output.encoder);
1571 if (IS_ERR(connector)) {
1572 dev_err(client->dev,
1573 "failed to initialize bridge connector: %pe\n",
1574 connector);
1575 return PTR_ERR(connector);
1576 }
1577
1578 drm_connector_attach_encoder(connector, &hdmi->output.encoder);
1579 } else {
1580 drm_connector_init_with_ddc(drm, &hdmi->output.connector,
1581 &tegra_hdmi_connector_funcs,
1582 DRM_MODE_CONNECTOR_HDMIA,
1583 hdmi->output.ddc);
1584 drm_connector_helper_add(&hdmi->output.connector,
1585 &tegra_hdmi_connector_helper_funcs);
1586 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1587
1588 drm_connector_attach_encoder(&hdmi->output.connector,
1589 &hdmi->output.encoder);
1590 drm_connector_register(&hdmi->output.connector);
1591 }
1592
1593 err = tegra_output_init(drm, &hdmi->output);
1594 if (err < 0) {
1595 dev_err(client->dev, "failed to initialize output: %d\n", err);
1596 return err;
1597 }
1598
1599 hdmi->output.encoder.possible_crtcs = 0x3;
1600
1601 err = regulator_enable(hdmi->hdmi);
1602 if (err < 0) {
1603 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1604 err);
1605 goto output_exit;
1606 }
1607
1608 err = regulator_enable(hdmi->pll);
1609 if (err < 0) {
1610 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1611 goto disable_hdmi;
1612 }
1613
1614 err = regulator_enable(hdmi->vdd);
1615 if (err < 0) {
1616 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1617 goto disable_pll;
1618 }
1619
1620 err = tegra_hdmi_codec_register(hdmi);
1621 if (err < 0) {
1622 dev_err(hdmi->dev, "failed to register audio codec: %d\n", err);
1623 goto disable_vdd;
1624 }
1625
1626 return 0;
1627
1628disable_vdd:
1629 regulator_disable(hdmi->vdd);
1630disable_pll:
1631 regulator_disable(hdmi->pll);
1632disable_hdmi:
1633 regulator_disable(hdmi->hdmi);
1634output_exit:
1635 tegra_output_exit(&hdmi->output);
1636
1637 return err;
1638}
1639
1640static int tegra_hdmi_exit(struct host1x_client *client)
1641{
1642 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1643
1644 tegra_hdmi_codec_unregister(hdmi);
1645
1646 tegra_output_exit(&hdmi->output);
1647
1648 regulator_disable(hdmi->vdd);
1649 regulator_disable(hdmi->pll);
1650 regulator_disable(hdmi->hdmi);
1651
1652 return 0;
1653}
1654
1655static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
1656{
1657 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1658 struct device *dev = client->dev;
1659 int err;
1660
1661 err = reset_control_assert(hdmi->rst);
1662 if (err < 0) {
1663 dev_err(dev, "failed to assert reset: %d\n", err);
1664 return err;
1665 }
1666
1667 usleep_range(1000, 2000);
1668
1669 clk_disable_unprepare(hdmi->clk);
1670 pm_runtime_put_sync(dev);
1671
1672 return 0;
1673}
1674
1675static int tegra_hdmi_runtime_resume(struct host1x_client *client)
1676{
1677 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1678 struct device *dev = client->dev;
1679 int err;
1680
1681 err = pm_runtime_resume_and_get(dev);
1682 if (err < 0) {
1683 dev_err(dev, "failed to get runtime PM: %d\n", err);
1684 return err;
1685 }
1686
1687 err = clk_prepare_enable(hdmi->clk);
1688 if (err < 0) {
1689 dev_err(dev, "failed to enable clock: %d\n", err);
1690 goto put_rpm;
1691 }
1692
1693 usleep_range(1000, 2000);
1694
1695 err = reset_control_deassert(hdmi->rst);
1696 if (err < 0) {
1697 dev_err(dev, "failed to deassert reset: %d\n", err);
1698 goto disable_clk;
1699 }
1700
1701 return 0;
1702
1703disable_clk:
1704 clk_disable_unprepare(hdmi->clk);
1705put_rpm:
1706 pm_runtime_put_sync(dev);
1707 return err;
1708}
1709
1710static const struct host1x_client_ops hdmi_client_ops = {
1711 .init = tegra_hdmi_init,
1712 .exit = tegra_hdmi_exit,
1713 .suspend = tegra_hdmi_runtime_suspend,
1714 .resume = tegra_hdmi_runtime_resume,
1715};
1716
1717static const struct tegra_hdmi_config tegra20_hdmi_config = {
1718 .tmds = tegra20_tmds_config,
1719 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1720 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1721 .fuse_override_value = 1 << 31,
1722 .has_sor_io_peak_current = false,
1723 .has_hda = false,
1724 .has_hbr = false,
1725};
1726
1727static const struct tegra_hdmi_config tegra30_hdmi_config = {
1728 .tmds = tegra30_tmds_config,
1729 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1730 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1731 .fuse_override_value = 1 << 31,
1732 .has_sor_io_peak_current = false,
1733 .has_hda = true,
1734 .has_hbr = false,
1735};
1736
1737static const struct tegra_hdmi_config tegra114_hdmi_config = {
1738 .tmds = tegra114_tmds_config,
1739 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1740 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1741 .fuse_override_value = 1 << 31,
1742 .has_sor_io_peak_current = true,
1743 .has_hda = true,
1744 .has_hbr = true,
1745};
1746
1747static const struct tegra_hdmi_config tegra124_hdmi_config = {
1748 .tmds = tegra124_tmds_config,
1749 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1750 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1751 .fuse_override_value = 1 << 31,
1752 .has_sor_io_peak_current = true,
1753 .has_hda = true,
1754 .has_hbr = true,
1755};
1756
1757static const struct of_device_id tegra_hdmi_of_match[] = {
1758 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1759 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1760 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1761 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1762 { },
1763};
1764MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1765
1766static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1767{
1768 struct tegra_hdmi *hdmi = data;
1769 u32 value;
1770
1771 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1772 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1773
1774 if (value & INT_CODEC_SCRATCH0) {
1775 unsigned int format;
1776 u32 value;
1777
1778 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1779
1780 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1781 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1782
1783 tegra_hda_parse_format(format, &hdmi->format);
1784 tegra_hdmi_reconfigure_audio(hdmi);
1785 } else {
1786 tegra_hdmi_disable_audio_infoframe(hdmi);
1787 tegra_hdmi_disable_audio(hdmi);
1788 }
1789 }
1790
1791 return IRQ_HANDLED;
1792}
1793
1794static int tegra_hdmi_probe(struct platform_device *pdev)
1795{
1796 struct tegra_hdmi *hdmi;
1797 int err;
1798
1799 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1800 if (!hdmi)
1801 return -ENOMEM;
1802
1803 hdmi->config = of_device_get_match_data(&pdev->dev);
1804 hdmi->dev = &pdev->dev;
1805
1806 hdmi->audio_source = AUTO;
1807 hdmi->stereo = false;
1808 hdmi->dvi = false;
1809
1810 mutex_init(&hdmi->audio_lock);
1811
1812 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1813 if (IS_ERR(hdmi->clk)) {
1814 dev_err(&pdev->dev, "failed to get clock\n");
1815 return PTR_ERR(hdmi->clk);
1816 }
1817
1818 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1819 if (IS_ERR(hdmi->rst)) {
1820 dev_err(&pdev->dev, "failed to get reset\n");
1821 return PTR_ERR(hdmi->rst);
1822 }
1823
1824 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1825 if (IS_ERR(hdmi->clk_parent))
1826 return PTR_ERR(hdmi->clk_parent);
1827
1828 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1829 if (err < 0) {
1830 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1831 return err;
1832 }
1833
1834 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1835 err = PTR_ERR_OR_ZERO(hdmi->hdmi);
1836 if (err)
1837 return dev_err_probe(&pdev->dev, err,
1838 "failed to get HDMI regulator\n");
1839
1840 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1841 err = PTR_ERR_OR_ZERO(hdmi->pll);
1842 if (err)
1843 return dev_err_probe(&pdev->dev, err,
1844 "failed to get PLL regulator\n");
1845
1846 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1847 err = PTR_ERR_OR_ZERO(hdmi->vdd);
1848 if (err)
1849 return dev_err_probe(&pdev->dev, err,
1850 "failed to get VDD regulator\n");
1851
1852 hdmi->output.dev = &pdev->dev;
1853
1854 err = tegra_output_probe(&hdmi->output);
1855 if (err < 0)
1856 return err;
1857
1858 hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
1859 if (IS_ERR(hdmi->regs))
1860 return PTR_ERR(hdmi->regs);
1861
1862 err = platform_get_irq(pdev, 0);
1863 if (err < 0)
1864 return err;
1865
1866 hdmi->irq = err;
1867
1868 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1869 dev_name(hdmi->dev), hdmi);
1870 if (err < 0) {
1871 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1872 hdmi->irq, err);
1873 return err;
1874 }
1875
1876 platform_set_drvdata(pdev, hdmi);
1877
1878 err = devm_pm_runtime_enable(&pdev->dev);
1879 if (err)
1880 return err;
1881
1882 err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1883 if (err)
1884 return err;
1885
1886 INIT_LIST_HEAD(&hdmi->client.list);
1887 hdmi->client.ops = &hdmi_client_ops;
1888 hdmi->client.dev = &pdev->dev;
1889
1890 err = host1x_client_register(&hdmi->client);
1891 if (err < 0) {
1892 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1893 err);
1894 return err;
1895 }
1896
1897 return 0;
1898}
1899
1900static void tegra_hdmi_remove(struct platform_device *pdev)
1901{
1902 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1903
1904 host1x_client_unregister(&hdmi->client);
1905
1906 tegra_output_remove(&hdmi->output);
1907}
1908
1909struct platform_driver tegra_hdmi_driver = {
1910 .driver = {
1911 .name = "tegra-hdmi",
1912 .of_match_table = tegra_hdmi_of_match,
1913 },
1914 .probe = tegra_hdmi_probe,
1915 .remove_new = tegra_hdmi_remove,
1916};