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1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28
29#include <linux/delay.h>
30#include <linux/export.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33
34#include <drm/display/drm_hdmi_helper.h>
35#include <drm/drm_atomic_helper.h>
36#include <drm/drm_crtc.h>
37#include <drm/drm_edid.h>
38#include <drm/drm_eld.h>
39
40#include "i915_drv.h"
41#include "i915_reg.h"
42#include "intel_atomic.h"
43#include "intel_audio.h"
44#include "intel_connector.h"
45#include "intel_crtc.h"
46#include "intel_de.h"
47#include "intel_display_types.h"
48#include "intel_fdi.h"
49#include "intel_fifo_underrun.h"
50#include "intel_gmbus.h"
51#include "intel_hdmi.h"
52#include "intel_hotplug.h"
53#include "intel_panel.h"
54#include "intel_sdvo.h"
55#include "intel_sdvo_regs.h"
56
57#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
58#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
59#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
60#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
61
62#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK | SDVO_TV_MASK)
63
64#define IS_TV(c) ((c)->output_flag & SDVO_TV_MASK)
65#define IS_TMDS(c) ((c)->output_flag & SDVO_TMDS_MASK)
66#define IS_LVDS(c) ((c)->output_flag & SDVO_LVDS_MASK)
67#define IS_TV_OR_LVDS(c) ((c)->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
68#define IS_DIGITAL(c) ((c)->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
69
70#define HAS_DDC(c) ((c)->output_flag & (SDVO_RGB_MASK | SDVO_TMDS_MASK | \
71 SDVO_LVDS_MASK))
72
73static const char * const tv_format_names[] = {
74 "NTSC_M" , "NTSC_J" , "NTSC_443",
75 "PAL_B" , "PAL_D" , "PAL_G" ,
76 "PAL_H" , "PAL_I" , "PAL_M" ,
77 "PAL_N" , "PAL_NC" , "PAL_60" ,
78 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
79 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
80 "SECAM_60"
81};
82
83#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
84
85struct intel_sdvo;
86
87struct intel_sdvo_ddc {
88 struct i2c_adapter ddc;
89 struct intel_sdvo *sdvo;
90 u8 ddc_bus;
91};
92
93struct intel_sdvo {
94 struct intel_encoder base;
95
96 struct i2c_adapter *i2c;
97 u8 slave_addr;
98
99 struct intel_sdvo_ddc ddc[3];
100
101 /* Register for the SDVO device: SDVOB or SDVOC */
102 i915_reg_t sdvo_reg;
103
104 /*
105 * Capabilities of the SDVO device returned by
106 * intel_sdvo_get_capabilities()
107 */
108 struct intel_sdvo_caps caps;
109
110 u8 colorimetry_cap;
111
112 /* Pixel clock limitations reported by the SDVO device, in kHz */
113 int pixel_clock_min, pixel_clock_max;
114
115 /*
116 * Hotplug activation bits for this device
117 */
118 u16 hotplug_active;
119
120 /*
121 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
122 */
123 u8 dtd_sdvo_flags;
124};
125
126struct intel_sdvo_connector {
127 struct intel_connector base;
128
129 /* Mark the type of connector */
130 u16 output_flag;
131
132 /* This contains all current supported TV format */
133 u8 tv_format_supported[TV_FORMAT_NUM];
134 int format_supported_num;
135 struct drm_property *tv_format;
136
137 /* add the property for the SDVO-TV */
138 struct drm_property *left;
139 struct drm_property *right;
140 struct drm_property *top;
141 struct drm_property *bottom;
142 struct drm_property *hpos;
143 struct drm_property *vpos;
144 struct drm_property *contrast;
145 struct drm_property *saturation;
146 struct drm_property *hue;
147 struct drm_property *sharpness;
148 struct drm_property *flicker_filter;
149 struct drm_property *flicker_filter_adaptive;
150 struct drm_property *flicker_filter_2d;
151 struct drm_property *tv_chroma_filter;
152 struct drm_property *tv_luma_filter;
153 struct drm_property *dot_crawl;
154
155 /* add the property for the SDVO-TV/LVDS */
156 struct drm_property *brightness;
157
158 /* this is to get the range of margin.*/
159 u32 max_hscan, max_vscan;
160
161 /**
162 * This is set if we treat the device as HDMI, instead of DVI.
163 */
164 bool is_hdmi;
165};
166
167struct intel_sdvo_connector_state {
168 /* base.base: tv.saturation/contrast/hue/brightness */
169 struct intel_digital_connector_state base;
170
171 struct {
172 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
173 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
174 unsigned chroma_filter, luma_filter, dot_crawl;
175 } tv;
176};
177
178static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
179{
180 return container_of(encoder, struct intel_sdvo, base);
181}
182
183static struct intel_sdvo *intel_attached_sdvo(struct intel_connector *connector)
184{
185 return to_sdvo(intel_attached_encoder(connector));
186}
187
188static struct intel_sdvo_connector *
189to_intel_sdvo_connector(struct drm_connector *connector)
190{
191 return container_of(connector, struct intel_sdvo_connector, base.base);
192}
193
194#define to_intel_sdvo_connector_state(conn_state) \
195 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
196
197static bool
198intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo);
199static bool
200intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
201 struct intel_sdvo_connector *intel_sdvo_connector,
202 int type);
203static bool
204intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
205 struct intel_sdvo_connector *intel_sdvo_connector);
206
207/*
208 * Writes the SDVOB or SDVOC with the given value, but always writes both
209 * SDVOB and SDVOC to work around apparent hardware issues (according to
210 * comments in the BIOS).
211 */
212static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
213{
214 struct drm_device *dev = intel_sdvo->base.base.dev;
215 struct drm_i915_private *dev_priv = to_i915(dev);
216 u32 bval = val, cval = val;
217 int i;
218
219 if (HAS_PCH_SPLIT(dev_priv)) {
220 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
221 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
222 /*
223 * HW workaround, need to write this twice for issue
224 * that may result in first write getting masked.
225 */
226 if (HAS_PCH_IBX(dev_priv)) {
227 intel_de_write(dev_priv, intel_sdvo->sdvo_reg, val);
228 intel_de_posting_read(dev_priv, intel_sdvo->sdvo_reg);
229 }
230 return;
231 }
232
233 if (intel_sdvo->base.port == PORT_B)
234 cval = intel_de_read(dev_priv, GEN3_SDVOC);
235 else
236 bval = intel_de_read(dev_priv, GEN3_SDVOB);
237
238 /*
239 * Write the registers twice for luck. Sometimes,
240 * writing them only once doesn't appear to 'stick'.
241 * The BIOS does this too. Yay, magic
242 */
243 for (i = 0; i < 2; i++) {
244 intel_de_write(dev_priv, GEN3_SDVOB, bval);
245 intel_de_posting_read(dev_priv, GEN3_SDVOB);
246
247 intel_de_write(dev_priv, GEN3_SDVOC, cval);
248 intel_de_posting_read(dev_priv, GEN3_SDVOC);
249 }
250}
251
252static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
253{
254 struct i2c_msg msgs[] = {
255 {
256 .addr = intel_sdvo->slave_addr,
257 .flags = 0,
258 .len = 1,
259 .buf = &addr,
260 },
261 {
262 .addr = intel_sdvo->slave_addr,
263 .flags = I2C_M_RD,
264 .len = 1,
265 .buf = ch,
266 }
267 };
268 int ret;
269
270 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
271 return true;
272
273 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
274 return false;
275}
276
277#define SDVO_CMD_NAME_ENTRY(cmd_) { .cmd = SDVO_CMD_ ## cmd_, .name = #cmd_ }
278
279/** Mapping of command numbers to names, for debug output */
280static const struct {
281 u8 cmd;
282 const char *name;
283} __packed sdvo_cmd_names[] = {
284 SDVO_CMD_NAME_ENTRY(RESET),
285 SDVO_CMD_NAME_ENTRY(GET_DEVICE_CAPS),
286 SDVO_CMD_NAME_ENTRY(GET_FIRMWARE_REV),
287 SDVO_CMD_NAME_ENTRY(GET_TRAINED_INPUTS),
288 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_OUTPUTS),
289 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_OUTPUTS),
290 SDVO_CMD_NAME_ENTRY(GET_IN_OUT_MAP),
291 SDVO_CMD_NAME_ENTRY(SET_IN_OUT_MAP),
292 SDVO_CMD_NAME_ENTRY(GET_ATTACHED_DISPLAYS),
293 SDVO_CMD_NAME_ENTRY(GET_HOT_PLUG_SUPPORT),
294 SDVO_CMD_NAME_ENTRY(SET_ACTIVE_HOT_PLUG),
295 SDVO_CMD_NAME_ENTRY(GET_ACTIVE_HOT_PLUG),
296 SDVO_CMD_NAME_ENTRY(GET_INTERRUPT_EVENT_SOURCE),
297 SDVO_CMD_NAME_ENTRY(SET_TARGET_INPUT),
298 SDVO_CMD_NAME_ENTRY(SET_TARGET_OUTPUT),
299 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART1),
300 SDVO_CMD_NAME_ENTRY(GET_INPUT_TIMINGS_PART2),
301 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART1),
302 SDVO_CMD_NAME_ENTRY(SET_INPUT_TIMINGS_PART2),
303 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART1),
304 SDVO_CMD_NAME_ENTRY(SET_OUTPUT_TIMINGS_PART2),
305 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART1),
306 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_TIMINGS_PART2),
307 SDVO_CMD_NAME_ENTRY(CREATE_PREFERRED_INPUT_TIMING),
308 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART1),
309 SDVO_CMD_NAME_ENTRY(GET_PREFERRED_INPUT_TIMING_PART2),
310 SDVO_CMD_NAME_ENTRY(GET_INPUT_PIXEL_CLOCK_RANGE),
311 SDVO_CMD_NAME_ENTRY(GET_OUTPUT_PIXEL_CLOCK_RANGE),
312 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_CLOCK_RATE_MULTS),
313 SDVO_CMD_NAME_ENTRY(GET_CLOCK_RATE_MULT),
314 SDVO_CMD_NAME_ENTRY(SET_CLOCK_RATE_MULT),
315 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_TV_FORMATS),
316 SDVO_CMD_NAME_ENTRY(GET_TV_FORMAT),
317 SDVO_CMD_NAME_ENTRY(SET_TV_FORMAT),
318 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_POWER_STATES),
319 SDVO_CMD_NAME_ENTRY(GET_POWER_STATE),
320 SDVO_CMD_NAME_ENTRY(SET_ENCODER_POWER_STATE),
321 SDVO_CMD_NAME_ENTRY(SET_DISPLAY_POWER_STATE),
322 SDVO_CMD_NAME_ENTRY(SET_CONTROL_BUS_SWITCH),
323 SDVO_CMD_NAME_ENTRY(GET_SDTV_RESOLUTION_SUPPORT),
324 SDVO_CMD_NAME_ENTRY(GET_SCALED_HDTV_RESOLUTION_SUPPORT),
325 SDVO_CMD_NAME_ENTRY(GET_SUPPORTED_ENHANCEMENTS),
326
327 /* Add the op code for SDVO enhancements */
328 SDVO_CMD_NAME_ENTRY(GET_MAX_HPOS),
329 SDVO_CMD_NAME_ENTRY(GET_HPOS),
330 SDVO_CMD_NAME_ENTRY(SET_HPOS),
331 SDVO_CMD_NAME_ENTRY(GET_MAX_VPOS),
332 SDVO_CMD_NAME_ENTRY(GET_VPOS),
333 SDVO_CMD_NAME_ENTRY(SET_VPOS),
334 SDVO_CMD_NAME_ENTRY(GET_MAX_SATURATION),
335 SDVO_CMD_NAME_ENTRY(GET_SATURATION),
336 SDVO_CMD_NAME_ENTRY(SET_SATURATION),
337 SDVO_CMD_NAME_ENTRY(GET_MAX_HUE),
338 SDVO_CMD_NAME_ENTRY(GET_HUE),
339 SDVO_CMD_NAME_ENTRY(SET_HUE),
340 SDVO_CMD_NAME_ENTRY(GET_MAX_CONTRAST),
341 SDVO_CMD_NAME_ENTRY(GET_CONTRAST),
342 SDVO_CMD_NAME_ENTRY(SET_CONTRAST),
343 SDVO_CMD_NAME_ENTRY(GET_MAX_BRIGHTNESS),
344 SDVO_CMD_NAME_ENTRY(GET_BRIGHTNESS),
345 SDVO_CMD_NAME_ENTRY(SET_BRIGHTNESS),
346 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_H),
347 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_H),
348 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_H),
349 SDVO_CMD_NAME_ENTRY(GET_MAX_OVERSCAN_V),
350 SDVO_CMD_NAME_ENTRY(GET_OVERSCAN_V),
351 SDVO_CMD_NAME_ENTRY(SET_OVERSCAN_V),
352 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER),
353 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER),
354 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER),
355 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_ADAPTIVE),
356 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_ADAPTIVE),
357 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_ADAPTIVE),
358 SDVO_CMD_NAME_ENTRY(GET_MAX_FLICKER_FILTER_2D),
359 SDVO_CMD_NAME_ENTRY(GET_FLICKER_FILTER_2D),
360 SDVO_CMD_NAME_ENTRY(SET_FLICKER_FILTER_2D),
361 SDVO_CMD_NAME_ENTRY(GET_MAX_SHARPNESS),
362 SDVO_CMD_NAME_ENTRY(GET_SHARPNESS),
363 SDVO_CMD_NAME_ENTRY(SET_SHARPNESS),
364 SDVO_CMD_NAME_ENTRY(GET_DOT_CRAWL),
365 SDVO_CMD_NAME_ENTRY(SET_DOT_CRAWL),
366 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_CHROMA_FILTER),
367 SDVO_CMD_NAME_ENTRY(GET_TV_CHROMA_FILTER),
368 SDVO_CMD_NAME_ENTRY(SET_TV_CHROMA_FILTER),
369 SDVO_CMD_NAME_ENTRY(GET_MAX_TV_LUMA_FILTER),
370 SDVO_CMD_NAME_ENTRY(GET_TV_LUMA_FILTER),
371 SDVO_CMD_NAME_ENTRY(SET_TV_LUMA_FILTER),
372
373 /* HDMI op code */
374 SDVO_CMD_NAME_ENTRY(GET_SUPP_ENCODE),
375 SDVO_CMD_NAME_ENTRY(GET_ENCODE),
376 SDVO_CMD_NAME_ENTRY(SET_ENCODE),
377 SDVO_CMD_NAME_ENTRY(SET_PIXEL_REPLI),
378 SDVO_CMD_NAME_ENTRY(GET_PIXEL_REPLI),
379 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY_CAP),
380 SDVO_CMD_NAME_ENTRY(SET_COLORIMETRY),
381 SDVO_CMD_NAME_ENTRY(GET_COLORIMETRY),
382 SDVO_CMD_NAME_ENTRY(GET_AUDIO_ENCRYPT_PREFER),
383 SDVO_CMD_NAME_ENTRY(SET_AUDIO_STAT),
384 SDVO_CMD_NAME_ENTRY(GET_AUDIO_STAT),
385 SDVO_CMD_NAME_ENTRY(GET_HBUF_INDEX),
386 SDVO_CMD_NAME_ENTRY(SET_HBUF_INDEX),
387 SDVO_CMD_NAME_ENTRY(GET_HBUF_INFO),
388 SDVO_CMD_NAME_ENTRY(GET_HBUF_AV_SPLIT),
389 SDVO_CMD_NAME_ENTRY(SET_HBUF_AV_SPLIT),
390 SDVO_CMD_NAME_ENTRY(GET_HBUF_TXRATE),
391 SDVO_CMD_NAME_ENTRY(SET_HBUF_TXRATE),
392 SDVO_CMD_NAME_ENTRY(SET_HBUF_DATA),
393 SDVO_CMD_NAME_ENTRY(GET_HBUF_DATA),
394};
395
396#undef SDVO_CMD_NAME_ENTRY
397
398static const char *sdvo_cmd_name(u8 cmd)
399{
400 int i;
401
402 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
403 if (cmd == sdvo_cmd_names[i].cmd)
404 return sdvo_cmd_names[i].name;
405 }
406
407 return NULL;
408}
409
410#define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")
411
412static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
413 const void *args, int args_len)
414{
415 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
416 const char *cmd_name;
417 int i, pos = 0;
418 char buffer[64];
419
420#define BUF_PRINT(args...) \
421 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
422
423 for (i = 0; i < args_len; i++) {
424 BUF_PRINT("%02X ", ((u8 *)args)[i]);
425 }
426 for (; i < 8; i++) {
427 BUF_PRINT(" ");
428 }
429
430 cmd_name = sdvo_cmd_name(cmd);
431 if (cmd_name)
432 BUF_PRINT("(%s)", cmd_name);
433 else
434 BUF_PRINT("(%02X)", cmd);
435
436 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
437#undef BUF_PRINT
438
439 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
440}
441
442static const char * const cmd_status_names[] = {
443 [SDVO_CMD_STATUS_POWER_ON] = "Power on",
444 [SDVO_CMD_STATUS_SUCCESS] = "Success",
445 [SDVO_CMD_STATUS_NOTSUPP] = "Not supported",
446 [SDVO_CMD_STATUS_INVALID_ARG] = "Invalid arg",
447 [SDVO_CMD_STATUS_PENDING] = "Pending",
448 [SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED] = "Target not specified",
449 [SDVO_CMD_STATUS_SCALING_NOT_SUPP] = "Scaling not supported",
450};
451
452static const char *sdvo_cmd_status(u8 status)
453{
454 if (status < ARRAY_SIZE(cmd_status_names))
455 return cmd_status_names[status];
456 else
457 return NULL;
458}
459
460static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
461 const void *args, int args_len,
462 bool unlocked)
463{
464 u8 *buf, status;
465 struct i2c_msg *msgs;
466 int i, ret = true;
467
468 /* Would be simpler to allocate both in one go ? */
469 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
470 if (!buf)
471 return false;
472
473 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
474 if (!msgs) {
475 kfree(buf);
476 return false;
477 }
478
479 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
480
481 for (i = 0; i < args_len; i++) {
482 msgs[i].addr = intel_sdvo->slave_addr;
483 msgs[i].flags = 0;
484 msgs[i].len = 2;
485 msgs[i].buf = buf + 2 *i;
486 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
487 buf[2*i + 1] = ((u8*)args)[i];
488 }
489 msgs[i].addr = intel_sdvo->slave_addr;
490 msgs[i].flags = 0;
491 msgs[i].len = 2;
492 msgs[i].buf = buf + 2*i;
493 buf[2*i + 0] = SDVO_I2C_OPCODE;
494 buf[2*i + 1] = cmd;
495
496 /* the following two are to read the response */
497 status = SDVO_I2C_CMD_STATUS;
498 msgs[i+1].addr = intel_sdvo->slave_addr;
499 msgs[i+1].flags = 0;
500 msgs[i+1].len = 1;
501 msgs[i+1].buf = &status;
502
503 msgs[i+2].addr = intel_sdvo->slave_addr;
504 msgs[i+2].flags = I2C_M_RD;
505 msgs[i+2].len = 1;
506 msgs[i+2].buf = &status;
507
508 if (unlocked)
509 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
510 else
511 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
512 if (ret < 0) {
513 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
514 ret = false;
515 goto out;
516 }
517 if (ret != i+3) {
518 /* failure in I2C transfer */
519 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
520 ret = false;
521 }
522
523out:
524 kfree(msgs);
525 kfree(buf);
526 return ret;
527}
528
529static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
530 const void *args, int args_len)
531{
532 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
533}
534
535static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
536 void *response, int response_len)
537{
538 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
539 const char *cmd_status;
540 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
541 u8 status;
542 int i, pos = 0;
543 char buffer[64];
544
545 buffer[0] = '\0';
546
547 /*
548 * The documentation states that all commands will be
549 * processed within 15µs, and that we need only poll
550 * the status byte a maximum of 3 times in order for the
551 * command to be complete.
552 *
553 * Check 5 times in case the hardware failed to read the docs.
554 *
555 * Also beware that the first response by many devices is to
556 * reply PENDING and stall for time. TVs are notorious for
557 * requiring longer than specified to complete their replies.
558 * Originally (in the DDX long ago), the delay was only ever 15ms
559 * with an additional delay of 30ms applied for TVs added later after
560 * many experiments. To accommodate both sets of delays, we do a
561 * sequence of slow checks if the device is falling behind and fails
562 * to reply within 5*15µs.
563 */
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_CMD_STATUS,
566 &status))
567 goto log_fail;
568
569 while ((status == SDVO_CMD_STATUS_PENDING ||
570 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
571 if (retry < 10)
572 msleep(15);
573 else
574 udelay(15);
575
576 if (!intel_sdvo_read_byte(intel_sdvo,
577 SDVO_I2C_CMD_STATUS,
578 &status))
579 goto log_fail;
580 }
581
582#define BUF_PRINT(args...) \
583 pos += snprintf(buffer + pos, max_t(int, sizeof(buffer) - pos, 0), args)
584
585 cmd_status = sdvo_cmd_status(status);
586 if (cmd_status)
587 BUF_PRINT("(%s)", cmd_status);
588 else
589 BUF_PRINT("(??? %d)", status);
590
591 if (status != SDVO_CMD_STATUS_SUCCESS)
592 goto log_fail;
593
594 /* Read the command response */
595 for (i = 0; i < response_len; i++) {
596 if (!intel_sdvo_read_byte(intel_sdvo,
597 SDVO_I2C_RETURN_0 + i,
598 &((u8 *)response)[i]))
599 goto log_fail;
600 BUF_PRINT(" %02X", ((u8 *)response)[i]);
601 }
602
603 drm_WARN_ON(&dev_priv->drm, pos >= sizeof(buffer) - 1);
604#undef BUF_PRINT
605
606 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
607 return true;
608
609log_fail:
610 DRM_DEBUG_KMS("%s: R: ... failed %s\n",
611 SDVO_NAME(intel_sdvo), buffer);
612 return false;
613}
614
615static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
616{
617 if (adjusted_mode->crtc_clock >= 100000)
618 return 1;
619 else if (adjusted_mode->crtc_clock >= 50000)
620 return 2;
621 else
622 return 4;
623}
624
625static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
626 u8 ddc_bus)
627{
628 /* This must be the immediately preceding write before the i2c xfer */
629 return __intel_sdvo_write_cmd(intel_sdvo,
630 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
631 &ddc_bus, 1, false);
632}
633
634static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
635{
636 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
637 return false;
638
639 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
640}
641
642static bool
643intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
644{
645 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
646 return false;
647
648 return intel_sdvo_read_response(intel_sdvo, value, len);
649}
650
651static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
652{
653 struct intel_sdvo_set_target_input_args targets = {};
654 return intel_sdvo_set_value(intel_sdvo,
655 SDVO_CMD_SET_TARGET_INPUT,
656 &targets, sizeof(targets));
657}
658
659/*
660 * Return whether each input is trained.
661 *
662 * This function is making an assumption about the layout of the response,
663 * which should be checked against the docs.
664 */
665static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
666{
667 struct intel_sdvo_get_trained_inputs_response response;
668
669 BUILD_BUG_ON(sizeof(response) != 1);
670 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
671 &response, sizeof(response)))
672 return false;
673
674 *input_1 = response.input0_trained;
675 *input_2 = response.input1_trained;
676 return true;
677}
678
679static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
680 u16 outputs)
681{
682 return intel_sdvo_set_value(intel_sdvo,
683 SDVO_CMD_SET_ACTIVE_OUTPUTS,
684 &outputs, sizeof(outputs));
685}
686
687static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
688 u16 *outputs)
689{
690 return intel_sdvo_get_value(intel_sdvo,
691 SDVO_CMD_GET_ACTIVE_OUTPUTS,
692 outputs, sizeof(*outputs));
693}
694
695static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
696 int mode)
697{
698 u8 state = SDVO_ENCODER_STATE_ON;
699
700 switch (mode) {
701 case DRM_MODE_DPMS_ON:
702 state = SDVO_ENCODER_STATE_ON;
703 break;
704 case DRM_MODE_DPMS_STANDBY:
705 state = SDVO_ENCODER_STATE_STANDBY;
706 break;
707 case DRM_MODE_DPMS_SUSPEND:
708 state = SDVO_ENCODER_STATE_SUSPEND;
709 break;
710 case DRM_MODE_DPMS_OFF:
711 state = SDVO_ENCODER_STATE_OFF;
712 break;
713 }
714
715 return intel_sdvo_set_value(intel_sdvo,
716 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
717}
718
719static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
720 int *clock_min,
721 int *clock_max)
722{
723 struct intel_sdvo_pixel_clock_range clocks;
724
725 BUILD_BUG_ON(sizeof(clocks) != 4);
726 if (!intel_sdvo_get_value(intel_sdvo,
727 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
728 &clocks, sizeof(clocks)))
729 return false;
730
731 /* Convert the values from units of 10 kHz to kHz. */
732 *clock_min = clocks.min * 10;
733 *clock_max = clocks.max * 10;
734 return true;
735}
736
737static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
738 u16 outputs)
739{
740 return intel_sdvo_set_value(intel_sdvo,
741 SDVO_CMD_SET_TARGET_OUTPUT,
742 &outputs, sizeof(outputs));
743}
744
745static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
746 struct intel_sdvo_dtd *dtd)
747{
748 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
749 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
750}
751
752static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
753 struct intel_sdvo_dtd *dtd)
754{
755 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
756 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
757}
758
759static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
760 struct intel_sdvo_dtd *dtd)
761{
762 return intel_sdvo_set_timing(intel_sdvo,
763 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
764}
765
766static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
767 struct intel_sdvo_dtd *dtd)
768{
769 return intel_sdvo_set_timing(intel_sdvo,
770 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
771}
772
773static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
774 struct intel_sdvo_dtd *dtd)
775{
776 return intel_sdvo_get_timing(intel_sdvo,
777 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
778}
779
780static bool
781intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
782 struct intel_sdvo_connector *intel_sdvo_connector,
783 const struct drm_display_mode *mode)
784{
785 struct intel_sdvo_preferred_input_timing_args args;
786
787 memset(&args, 0, sizeof(args));
788 args.clock = mode->clock / 10;
789 args.width = mode->hdisplay;
790 args.height = mode->vdisplay;
791 args.interlace = 0;
792
793 if (IS_LVDS(intel_sdvo_connector)) {
794 const struct drm_display_mode *fixed_mode =
795 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
796
797 if (fixed_mode->hdisplay != args.width ||
798 fixed_mode->vdisplay != args.height)
799 args.scaled = 1;
800 }
801
802 return intel_sdvo_set_value(intel_sdvo,
803 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
804 &args, sizeof(args));
805}
806
807static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
808 struct intel_sdvo_dtd *dtd)
809{
810 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
811 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
812 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
813 &dtd->part1, sizeof(dtd->part1)) &&
814 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
815 &dtd->part2, sizeof(dtd->part2));
816}
817
818static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
819{
820 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
821}
822
823static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
824 const struct drm_display_mode *mode)
825{
826 u16 width, height;
827 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
828 u16 h_sync_offset, v_sync_offset;
829 int mode_clock;
830
831 memset(dtd, 0, sizeof(*dtd));
832
833 width = mode->hdisplay;
834 height = mode->vdisplay;
835
836 /* do some mode translations */
837 h_blank_len = mode->htotal - mode->hdisplay;
838 h_sync_len = mode->hsync_end - mode->hsync_start;
839
840 v_blank_len = mode->vtotal - mode->vdisplay;
841 v_sync_len = mode->vsync_end - mode->vsync_start;
842
843 h_sync_offset = mode->hsync_start - mode->hdisplay;
844 v_sync_offset = mode->vsync_start - mode->vdisplay;
845
846 mode_clock = mode->clock;
847 mode_clock /= 10;
848 dtd->part1.clock = mode_clock;
849
850 dtd->part1.h_active = width & 0xff;
851 dtd->part1.h_blank = h_blank_len & 0xff;
852 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
853 ((h_blank_len >> 8) & 0xf);
854 dtd->part1.v_active = height & 0xff;
855 dtd->part1.v_blank = v_blank_len & 0xff;
856 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
857 ((v_blank_len >> 8) & 0xf);
858
859 dtd->part2.h_sync_off = h_sync_offset & 0xff;
860 dtd->part2.h_sync_width = h_sync_len & 0xff;
861 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
862 (v_sync_len & 0xf);
863 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
864 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
865 ((v_sync_len & 0x30) >> 4);
866
867 dtd->part2.dtd_flags = 0x18;
868 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
869 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
870 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
871 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
872 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
873 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
874
875 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
876}
877
878static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
879 const struct intel_sdvo_dtd *dtd)
880{
881 struct drm_display_mode mode = {};
882
883 mode.hdisplay = dtd->part1.h_active;
884 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
885 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
886 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
887 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
888 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
889 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
890 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
891
892 mode.vdisplay = dtd->part1.v_active;
893 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
894 mode.vsync_start = mode.vdisplay;
895 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
896 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
897 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
898 mode.vsync_end = mode.vsync_start +
899 (dtd->part2.v_sync_off_width & 0xf);
900 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
901 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
902 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
903
904 mode.clock = dtd->part1.clock * 10;
905
906 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
907 mode.flags |= DRM_MODE_FLAG_INTERLACE;
908 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
909 mode.flags |= DRM_MODE_FLAG_PHSYNC;
910 else
911 mode.flags |= DRM_MODE_FLAG_NHSYNC;
912 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
913 mode.flags |= DRM_MODE_FLAG_PVSYNC;
914 else
915 mode.flags |= DRM_MODE_FLAG_NVSYNC;
916
917 drm_mode_set_crtcinfo(&mode, 0);
918
919 drm_mode_copy(pmode, &mode);
920}
921
922static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
923{
924 struct intel_sdvo_encode encode;
925
926 BUILD_BUG_ON(sizeof(encode) != 2);
927 return intel_sdvo_get_value(intel_sdvo,
928 SDVO_CMD_GET_SUPP_ENCODE,
929 &encode, sizeof(encode));
930}
931
932static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
933 u8 mode)
934{
935 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
936}
937
938static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
939 u8 mode)
940{
941 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
942}
943
944static bool intel_sdvo_set_pixel_replication(struct intel_sdvo *intel_sdvo,
945 u8 pixel_repeat)
946{
947 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_PIXEL_REPLI,
948 &pixel_repeat, 1);
949}
950
951static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
952 u8 audio_state)
953{
954 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
955 &audio_state, 1);
956}
957
958static bool intel_sdvo_get_hbuf_size(struct intel_sdvo *intel_sdvo,
959 u8 *hbuf_size)
960{
961 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
962 hbuf_size, 1))
963 return false;
964
965 /* Buffer size is 0 based, hooray! However zero means zero. */
966 if (*hbuf_size)
967 (*hbuf_size)++;
968
969 return true;
970}
971
972#if 0
973static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
974{
975 int i, j;
976 u8 set_buf_index[2];
977 u8 av_split;
978 u8 buf_size;
979 u8 buf[48];
980 u8 *pos;
981
982 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
983
984 for (i = 0; i <= av_split; i++) {
985 set_buf_index[0] = i; set_buf_index[1] = 0;
986 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
987 set_buf_index, 2);
988 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
989 intel_sdvo_read_response(encoder, &buf_size, 1);
990
991 pos = buf;
992 for (j = 0; j <= buf_size; j += 8) {
993 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
994 NULL, 0);
995 intel_sdvo_read_response(encoder, pos, 8);
996 pos += 8;
997 }
998 }
999}
1000#endif
1001
1002static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
1003 unsigned int if_index, u8 tx_rate,
1004 const u8 *data, unsigned int length)
1005{
1006 u8 set_buf_index[2] = { if_index, 0 };
1007 u8 hbuf_size, tmp[8];
1008 int i;
1009
1010 if (!intel_sdvo_set_value(intel_sdvo,
1011 SDVO_CMD_SET_HBUF_INDEX,
1012 set_buf_index, 2))
1013 return false;
1014
1015 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1016 return false;
1017
1018 DRM_DEBUG_KMS("writing sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1019 if_index, length, hbuf_size);
1020
1021 if (hbuf_size < length)
1022 return false;
1023
1024 for (i = 0; i < hbuf_size; i += 8) {
1025 memset(tmp, 0, 8);
1026 if (i < length)
1027 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
1028
1029 if (!intel_sdvo_set_value(intel_sdvo,
1030 SDVO_CMD_SET_HBUF_DATA,
1031 tmp, 8))
1032 return false;
1033 }
1034
1035 return intel_sdvo_set_value(intel_sdvo,
1036 SDVO_CMD_SET_HBUF_TXRATE,
1037 &tx_rate, 1);
1038}
1039
1040static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
1041 unsigned int if_index,
1042 u8 *data, unsigned int length)
1043{
1044 u8 set_buf_index[2] = { if_index, 0 };
1045 u8 hbuf_size, tx_rate, av_split;
1046 int i;
1047
1048 if (!intel_sdvo_get_value(intel_sdvo,
1049 SDVO_CMD_GET_HBUF_AV_SPLIT,
1050 &av_split, 1))
1051 return -ENXIO;
1052
1053 if (av_split < if_index)
1054 return 0;
1055
1056 if (!intel_sdvo_set_value(intel_sdvo,
1057 SDVO_CMD_SET_HBUF_INDEX,
1058 set_buf_index, 2))
1059 return -ENXIO;
1060
1061 if (!intel_sdvo_get_value(intel_sdvo,
1062 SDVO_CMD_GET_HBUF_TXRATE,
1063 &tx_rate, 1))
1064 return -ENXIO;
1065
1066 /* TX_DISABLED doesn't mean disabled for ELD */
1067 if (if_index != SDVO_HBUF_INDEX_ELD && tx_rate == SDVO_HBUF_TX_DISABLED)
1068 return 0;
1069
1070 if (!intel_sdvo_get_hbuf_size(intel_sdvo, &hbuf_size))
1071 return false;
1072
1073 DRM_DEBUG_KMS("reading sdvo hbuf: %i, length %u, hbuf_size: %i\n",
1074 if_index, length, hbuf_size);
1075
1076 hbuf_size = min_t(unsigned int, length, hbuf_size);
1077
1078 for (i = 0; i < hbuf_size; i += 8) {
1079 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0))
1080 return -ENXIO;
1081 if (!intel_sdvo_read_response(intel_sdvo, &data[i],
1082 min_t(unsigned int, 8, hbuf_size - i)))
1083 return -ENXIO;
1084 }
1085
1086 return hbuf_size;
1087}
1088
1089static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
1090 struct intel_crtc_state *crtc_state,
1091 struct drm_connector_state *conn_state)
1092{
1093 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1094 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
1095 const struct drm_display_mode *adjusted_mode =
1096 &crtc_state->hw.adjusted_mode;
1097 int ret;
1098
1099 if (!crtc_state->has_hdmi_sink)
1100 return true;
1101
1102 crtc_state->infoframes.enable |=
1103 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1104
1105 ret = drm_hdmi_avi_infoframe_from_display_mode(frame,
1106 conn_state->connector,
1107 adjusted_mode);
1108 if (ret)
1109 return false;
1110
1111 drm_hdmi_avi_infoframe_quant_range(frame,
1112 conn_state->connector,
1113 adjusted_mode,
1114 crtc_state->limited_color_range ?
1115 HDMI_QUANTIZATION_RANGE_LIMITED :
1116 HDMI_QUANTIZATION_RANGE_FULL);
1117
1118 ret = hdmi_avi_infoframe_check(frame);
1119 if (drm_WARN_ON(&dev_priv->drm, ret))
1120 return false;
1121
1122 return true;
1123}
1124
1125static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1126 const struct intel_crtc_state *crtc_state)
1127{
1128 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1129 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1130 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1131 ssize_t len;
1132
1133 if ((crtc_state->infoframes.enable &
1134 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
1135 return true;
1136
1137 if (drm_WARN_ON(&dev_priv->drm,
1138 frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
1139 return false;
1140
1141 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
1142 if (drm_WARN_ON(&dev_priv->drm, len < 0))
1143 return false;
1144
1145 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1146 SDVO_HBUF_TX_VSYNC,
1147 sdvo_data, len);
1148}
1149
1150static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
1151 struct intel_crtc_state *crtc_state)
1152{
1153 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1154 union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1155 ssize_t len;
1156 int ret;
1157
1158 if (!crtc_state->has_hdmi_sink)
1159 return;
1160
1161 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1162 sdvo_data, sizeof(sdvo_data));
1163 if (len < 0) {
1164 DRM_DEBUG_KMS("failed to read AVI infoframe\n");
1165 return;
1166 } else if (len == 0) {
1167 return;
1168 }
1169
1170 crtc_state->infoframes.enable |=
1171 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1172
1173 ret = hdmi_infoframe_unpack(frame, sdvo_data, len);
1174 if (ret) {
1175 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
1176 return;
1177 }
1178
1179 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
1180 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
1181 frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
1182}
1183
1184static void intel_sdvo_get_eld(struct intel_sdvo *intel_sdvo,
1185 struct intel_crtc_state *crtc_state)
1186{
1187 struct drm_i915_private *i915 = to_i915(intel_sdvo->base.base.dev);
1188 ssize_t len;
1189 u8 val;
1190
1191 if (!crtc_state->has_audio)
1192 return;
1193
1194 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT, &val, 1))
1195 return;
1196
1197 if ((val & SDVO_AUDIO_ELD_VALID) == 0)
1198 return;
1199
1200 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1201 crtc_state->eld, sizeof(crtc_state->eld));
1202 if (len < 0)
1203 drm_dbg_kms(&i915->drm, "failed to read ELD\n");
1204}
1205
1206static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1207 const struct drm_connector_state *conn_state)
1208{
1209 struct intel_sdvo_tv_format format;
1210 u32 format_map;
1211
1212 format_map = 1 << conn_state->tv.legacy_mode;
1213 memset(&format, 0, sizeof(format));
1214 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1215
1216 BUILD_BUG_ON(sizeof(format) != 6);
1217 return intel_sdvo_set_value(intel_sdvo,
1218 SDVO_CMD_SET_TV_FORMAT,
1219 &format, sizeof(format));
1220}
1221
1222static bool
1223intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1224 struct intel_sdvo_connector *intel_sdvo_connector,
1225 const struct drm_display_mode *mode)
1226{
1227 struct intel_sdvo_dtd output_dtd;
1228
1229 if (!intel_sdvo_set_target_output(intel_sdvo,
1230 intel_sdvo_connector->output_flag))
1231 return false;
1232
1233 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1234 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1235 return false;
1236
1237 return true;
1238}
1239
1240/*
1241 * Asks the sdvo controller for the preferred input mode given the output mode.
1242 * Unfortunately we have to set up the full output mode to do that.
1243 */
1244static bool
1245intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1246 struct intel_sdvo_connector *intel_sdvo_connector,
1247 const struct drm_display_mode *mode,
1248 struct drm_display_mode *adjusted_mode)
1249{
1250 struct intel_sdvo_dtd input_dtd;
1251
1252 /* Reset the input timing to the screen. Assume always input 0. */
1253 if (!intel_sdvo_set_target_input(intel_sdvo))
1254 return false;
1255
1256 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1257 intel_sdvo_connector,
1258 mode))
1259 return false;
1260
1261 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1262 &input_dtd))
1263 return false;
1264
1265 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1266 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1267
1268 return true;
1269}
1270
1271static int i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1272{
1273 struct drm_i915_private *dev_priv = to_i915(pipe_config->uapi.crtc->dev);
1274 unsigned int dotclock = pipe_config->hw.adjusted_mode.crtc_clock;
1275 struct dpll *clock = &pipe_config->dpll;
1276
1277 /*
1278 * SDVO TV has fixed PLL values depend on its clock range,
1279 * this mirrors vbios setting.
1280 */
1281 if (dotclock >= 100000 && dotclock < 140500) {
1282 clock->p1 = 2;
1283 clock->p2 = 10;
1284 clock->n = 3;
1285 clock->m1 = 16;
1286 clock->m2 = 8;
1287 } else if (dotclock >= 140500 && dotclock <= 200000) {
1288 clock->p1 = 1;
1289 clock->p2 = 10;
1290 clock->n = 6;
1291 clock->m1 = 12;
1292 clock->m2 = 8;
1293 } else {
1294 drm_dbg_kms(&dev_priv->drm,
1295 "SDVO TV clock out of range: %i\n", dotclock);
1296 return -EINVAL;
1297 }
1298
1299 pipe_config->clock_set = true;
1300
1301 return 0;
1302}
1303
1304static bool intel_has_hdmi_sink(struct intel_sdvo_connector *intel_sdvo_connector,
1305 const struct drm_connector_state *conn_state)
1306{
1307 struct drm_connector *connector = conn_state->connector;
1308
1309 return intel_sdvo_connector->is_hdmi &&
1310 connector->display_info.is_hdmi &&
1311 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1312}
1313
1314static bool intel_sdvo_limited_color_range(struct intel_encoder *encoder,
1315 const struct intel_crtc_state *crtc_state,
1316 const struct drm_connector_state *conn_state)
1317{
1318 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1319
1320 if ((intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220) == 0)
1321 return false;
1322
1323 return intel_hdmi_limited_color_range(crtc_state, conn_state);
1324}
1325
1326static bool intel_sdvo_has_audio(struct intel_encoder *encoder,
1327 const struct intel_crtc_state *crtc_state,
1328 const struct drm_connector_state *conn_state)
1329{
1330 struct drm_connector *connector = conn_state->connector;
1331 struct intel_sdvo_connector *intel_sdvo_connector =
1332 to_intel_sdvo_connector(connector);
1333 const struct intel_digital_connector_state *intel_conn_state =
1334 to_intel_digital_connector_state(conn_state);
1335
1336 if (!crtc_state->has_hdmi_sink)
1337 return false;
1338
1339 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1340 return intel_sdvo_connector->is_hdmi &&
1341 connector->display_info.has_audio;
1342 else
1343 return intel_conn_state->force_audio == HDMI_AUDIO_ON;
1344}
1345
1346static int intel_sdvo_compute_config(struct intel_encoder *encoder,
1347 struct intel_crtc_state *pipe_config,
1348 struct drm_connector_state *conn_state)
1349{
1350 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1351 struct intel_sdvo_connector *intel_sdvo_connector =
1352 to_intel_sdvo_connector(conn_state->connector);
1353 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
1354 struct drm_display_mode *mode = &pipe_config->hw.mode;
1355
1356 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
1357 pipe_config->has_pch_encoder = true;
1358 if (!intel_fdi_compute_pipe_bpp(pipe_config))
1359 return -EINVAL;
1360 }
1361
1362 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1363 /* FIXME: Don't increase pipe_bpp */
1364 pipe_config->pipe_bpp = 8*3;
1365 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1366 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1367
1368 /*
1369 * We need to construct preferred input timings based on our
1370 * output timings. To do that, we have to set the output
1371 * timings, even though this isn't really the right place in
1372 * the sequence to do it. Oh well.
1373 */
1374 if (IS_TV(intel_sdvo_connector)) {
1375 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1376 intel_sdvo_connector,
1377 mode))
1378 return -EINVAL;
1379
1380 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1381 intel_sdvo_connector,
1382 mode,
1383 adjusted_mode);
1384 pipe_config->sdvo_tv_clock = true;
1385 } else if (IS_LVDS(intel_sdvo_connector)) {
1386 const struct drm_display_mode *fixed_mode =
1387 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
1388 int ret;
1389
1390 ret = intel_panel_compute_config(&intel_sdvo_connector->base,
1391 adjusted_mode);
1392 if (ret)
1393 return ret;
1394
1395 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1396 intel_sdvo_connector,
1397 fixed_mode))
1398 return -EINVAL;
1399
1400 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1401 intel_sdvo_connector,
1402 mode,
1403 adjusted_mode);
1404 }
1405
1406 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1407 return -EINVAL;
1408
1409 /*
1410 * Make the CRTC code factor in the SDVO pixel multiplier. The
1411 * SDVO device will factor out the multiplier during mode_set.
1412 */
1413 pipe_config->pixel_multiplier =
1414 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1415
1416 pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, conn_state);
1417
1418 pipe_config->has_audio =
1419 intel_sdvo_has_audio(encoder, pipe_config, conn_state) &&
1420 intel_audio_compute_config(encoder, pipe_config, conn_state);
1421
1422 pipe_config->limited_color_range =
1423 intel_sdvo_limited_color_range(encoder, pipe_config,
1424 conn_state);
1425
1426 /* Clock computation needs to happen after pixel multiplier. */
1427 if (IS_TV(intel_sdvo_connector)) {
1428 int ret;
1429
1430 ret = i9xx_adjust_sdvo_tv_clock(pipe_config);
1431 if (ret)
1432 return ret;
1433 }
1434
1435 if (conn_state->picture_aspect_ratio)
1436 adjusted_mode->picture_aspect_ratio =
1437 conn_state->picture_aspect_ratio;
1438
1439 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
1440 pipe_config, conn_state)) {
1441 DRM_DEBUG_KMS("bad AVI infoframe\n");
1442 return -EINVAL;
1443 }
1444
1445 return 0;
1446}
1447
1448#define UPDATE_PROPERTY(input, NAME) \
1449 do { \
1450 val = input; \
1451 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1452 } while (0)
1453
1454static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1455 const struct intel_sdvo_connector_state *sdvo_state)
1456{
1457 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1458 struct intel_sdvo_connector *intel_sdvo_conn =
1459 to_intel_sdvo_connector(conn_state->connector);
1460 u16 val;
1461
1462 if (intel_sdvo_conn->left)
1463 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1464
1465 if (intel_sdvo_conn->top)
1466 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1467
1468 if (intel_sdvo_conn->hpos)
1469 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1470
1471 if (intel_sdvo_conn->vpos)
1472 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1473
1474 if (intel_sdvo_conn->saturation)
1475 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1476
1477 if (intel_sdvo_conn->contrast)
1478 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1479
1480 if (intel_sdvo_conn->hue)
1481 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1482
1483 if (intel_sdvo_conn->brightness)
1484 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1485
1486 if (intel_sdvo_conn->sharpness)
1487 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1488
1489 if (intel_sdvo_conn->flicker_filter)
1490 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1491
1492 if (intel_sdvo_conn->flicker_filter_2d)
1493 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1494
1495 if (intel_sdvo_conn->flicker_filter_adaptive)
1496 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1497
1498 if (intel_sdvo_conn->tv_chroma_filter)
1499 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1500
1501 if (intel_sdvo_conn->tv_luma_filter)
1502 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1503
1504 if (intel_sdvo_conn->dot_crawl)
1505 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1506
1507#undef UPDATE_PROPERTY
1508}
1509
1510static void intel_sdvo_pre_enable(struct intel_atomic_state *state,
1511 struct intel_encoder *intel_encoder,
1512 const struct intel_crtc_state *crtc_state,
1513 const struct drm_connector_state *conn_state)
1514{
1515 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1517 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1518 const struct intel_sdvo_connector_state *sdvo_state =
1519 to_intel_sdvo_connector_state(conn_state);
1520 struct intel_sdvo_connector *intel_sdvo_connector =
1521 to_intel_sdvo_connector(conn_state->connector);
1522 const struct drm_display_mode *mode = &crtc_state->hw.mode;
1523 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1524 u32 sdvox;
1525 struct intel_sdvo_in_out_map in_out;
1526 struct intel_sdvo_dtd input_dtd, output_dtd;
1527 int rate;
1528
1529 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1530
1531 /*
1532 * First, set the input mapping for the first input to our controlled
1533 * output. This is only correct if we're a single-input device, in
1534 * which case the first input is the output from the appropriate SDVO
1535 * channel on the motherboard. In a two-input device, the first input
1536 * will be SDVOB and the second SDVOC.
1537 */
1538 in_out.in0 = intel_sdvo_connector->output_flag;
1539 in_out.in1 = 0;
1540
1541 intel_sdvo_set_value(intel_sdvo,
1542 SDVO_CMD_SET_IN_OUT_MAP,
1543 &in_out, sizeof(in_out));
1544
1545 /* Set the output timings to the screen */
1546 if (!intel_sdvo_set_target_output(intel_sdvo,
1547 intel_sdvo_connector->output_flag))
1548 return;
1549
1550 /* lvds has a special fixed output timing. */
1551 if (IS_LVDS(intel_sdvo_connector)) {
1552 const struct drm_display_mode *fixed_mode =
1553 intel_panel_fixed_mode(&intel_sdvo_connector->base, mode);
1554
1555 intel_sdvo_get_dtd_from_mode(&output_dtd, fixed_mode);
1556 } else {
1557 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1558 }
1559 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1560 drm_info(&dev_priv->drm,
1561 "Setting output timings on %s failed\n",
1562 SDVO_NAME(intel_sdvo));
1563
1564 /* Set the input timing to the screen. Assume always input 0. */
1565 if (!intel_sdvo_set_target_input(intel_sdvo))
1566 return;
1567
1568 if (crtc_state->has_hdmi_sink) {
1569 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1570 intel_sdvo_set_colorimetry(intel_sdvo,
1571 crtc_state->limited_color_range ?
1572 SDVO_COLORIMETRY_RGB220 :
1573 SDVO_COLORIMETRY_RGB256);
1574 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1575 intel_sdvo_set_pixel_replication(intel_sdvo,
1576 !!(adjusted_mode->flags &
1577 DRM_MODE_FLAG_DBLCLK));
1578 } else
1579 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1580
1581 if (IS_TV(intel_sdvo_connector) &&
1582 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1583 return;
1584
1585 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1586
1587 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
1588 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1589 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1590 drm_info(&dev_priv->drm,
1591 "Setting input timings on %s failed\n",
1592 SDVO_NAME(intel_sdvo));
1593
1594 switch (crtc_state->pixel_multiplier) {
1595 default:
1596 drm_WARN(&dev_priv->drm, 1,
1597 "unknown pixel multiplier specified\n");
1598 fallthrough;
1599 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1600 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1601 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1602 }
1603 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1604 return;
1605
1606 /* Set the SDVO control regs. */
1607 if (DISPLAY_VER(dev_priv) >= 4) {
1608 /* The real mode polarity is set by the SDVO commands, using
1609 * struct intel_sdvo_dtd. */
1610 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1611 if (DISPLAY_VER(dev_priv) < 5)
1612 sdvox |= SDVO_BORDER_ENABLE;
1613 } else {
1614 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1615 if (intel_sdvo->base.port == PORT_B)
1616 sdvox &= SDVOB_PRESERVE_MASK;
1617 else
1618 sdvox &= SDVOC_PRESERVE_MASK;
1619 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1620 }
1621
1622 if (HAS_PCH_CPT(dev_priv))
1623 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1624 else
1625 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1626
1627 if (DISPLAY_VER(dev_priv) >= 4) {
1628 /* done in crtc_mode_set as the dpll_md reg must be written early */
1629 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1630 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1631 /* done in crtc_mode_set as it lives inside the dpll register */
1632 } else {
1633 sdvox |= (crtc_state->pixel_multiplier - 1)
1634 << SDVO_PORT_MULTIPLY_SHIFT;
1635 }
1636
1637 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1638 DISPLAY_VER(dev_priv) < 5)
1639 sdvox |= SDVO_STALL_SELECT;
1640 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1641}
1642
1643static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1644{
1645 struct intel_sdvo_connector *intel_sdvo_connector =
1646 to_intel_sdvo_connector(&connector->base);
1647 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1648 u16 active_outputs = 0;
1649
1650 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1651
1652 return active_outputs & intel_sdvo_connector->output_flag;
1653}
1654
1655bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1656 i915_reg_t sdvo_reg, enum pipe *pipe)
1657{
1658 u32 val;
1659
1660 val = intel_de_read(dev_priv, sdvo_reg);
1661
1662 /* asserts want to know the pipe even if the port is disabled */
1663 if (HAS_PCH_CPT(dev_priv))
1664 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1665 else if (IS_CHERRYVIEW(dev_priv))
1666 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1667 else
1668 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1669
1670 return val & SDVO_ENABLE;
1671}
1672
1673static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1674 enum pipe *pipe)
1675{
1676 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1677 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1678 u16 active_outputs = 0;
1679 bool ret;
1680
1681 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1682
1683 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1684
1685 return ret || active_outputs;
1686}
1687
1688static void intel_sdvo_get_config(struct intel_encoder *encoder,
1689 struct intel_crtc_state *pipe_config)
1690{
1691 struct drm_device *dev = encoder->base.dev;
1692 struct drm_i915_private *dev_priv = to_i915(dev);
1693 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1694 struct intel_sdvo_dtd dtd;
1695 int encoder_pixel_multiplier = 0;
1696 int dotclock;
1697 u32 flags = 0, sdvox;
1698 u8 val;
1699 bool ret;
1700
1701 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1702
1703 sdvox = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1704
1705 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1706 if (!ret) {
1707 /*
1708 * Some sdvo encoders are not spec compliant and don't
1709 * implement the mandatory get_timings function.
1710 */
1711 drm_dbg(&dev_priv->drm, "failed to retrieve SDVO DTD\n");
1712 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1713 } else {
1714 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1715 flags |= DRM_MODE_FLAG_PHSYNC;
1716 else
1717 flags |= DRM_MODE_FLAG_NHSYNC;
1718
1719 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1720 flags |= DRM_MODE_FLAG_PVSYNC;
1721 else
1722 flags |= DRM_MODE_FLAG_NVSYNC;
1723 }
1724
1725 pipe_config->hw.adjusted_mode.flags |= flags;
1726
1727 /*
1728 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1729 * the sdvo port register, on all other platforms it is part of the dpll
1730 * state. Since the general pipe state readout happens before the
1731 * encoder->get_config we so already have a valid pixel multplier on all
1732 * other platfroms.
1733 */
1734 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1735 pipe_config->pixel_multiplier =
1736 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1737 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1738 }
1739
1740 dotclock = pipe_config->port_clock;
1741
1742 if (pipe_config->pixel_multiplier)
1743 dotclock /= pipe_config->pixel_multiplier;
1744
1745 pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1746
1747 /* Cross check the port pixel multiplier with the sdvo encoder state. */
1748 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1749 &val, 1)) {
1750 switch (val) {
1751 case SDVO_CLOCK_RATE_MULT_1X:
1752 encoder_pixel_multiplier = 1;
1753 break;
1754 case SDVO_CLOCK_RATE_MULT_2X:
1755 encoder_pixel_multiplier = 2;
1756 break;
1757 case SDVO_CLOCK_RATE_MULT_4X:
1758 encoder_pixel_multiplier = 4;
1759 break;
1760 }
1761 }
1762
1763 drm_WARN(dev,
1764 encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1765 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1766 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1767
1768 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY,
1769 &val, 1)) {
1770 if (val == SDVO_COLORIMETRY_RGB220)
1771 pipe_config->limited_color_range = true;
1772 }
1773
1774 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1775 &val, 1)) {
1776 if (val & SDVO_AUDIO_PRESENCE_DETECT)
1777 pipe_config->has_audio = true;
1778 }
1779
1780 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1781 &val, 1)) {
1782 if (val == SDVO_ENCODE_HDMI)
1783 pipe_config->has_hdmi_sink = true;
1784 }
1785
1786 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
1787
1788 intel_sdvo_get_eld(intel_sdvo, pipe_config);
1789}
1790
1791static void intel_sdvo_disable_audio(struct intel_encoder *encoder,
1792 const struct intel_crtc_state *old_crtc_state,
1793 const struct drm_connector_state *old_conn_state)
1794{
1795 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1796
1797 if (!old_crtc_state->has_audio)
1798 return;
1799
1800 intel_sdvo_set_audio_state(intel_sdvo, 0);
1801}
1802
1803static void intel_sdvo_enable_audio(struct intel_encoder *encoder,
1804 const struct intel_crtc_state *crtc_state,
1805 const struct drm_connector_state *conn_state)
1806{
1807 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1808 const u8 *eld = crtc_state->eld;
1809
1810 if (!crtc_state->has_audio)
1811 return;
1812
1813 intel_sdvo_set_audio_state(intel_sdvo, 0);
1814
1815 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1816 SDVO_HBUF_TX_DISABLED,
1817 eld, drm_eld_size(eld));
1818
1819 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1820 SDVO_AUDIO_PRESENCE_DETECT);
1821}
1822
1823static void intel_disable_sdvo(struct intel_atomic_state *state,
1824 struct intel_encoder *encoder,
1825 const struct intel_crtc_state *old_crtc_state,
1826 const struct drm_connector_state *conn_state)
1827{
1828 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1829 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1830 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1831 u32 temp;
1832
1833 encoder->audio_disable(encoder, old_crtc_state, conn_state);
1834
1835 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1836 if (0)
1837 intel_sdvo_set_encoder_power_state(intel_sdvo,
1838 DRM_MODE_DPMS_OFF);
1839
1840 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1841
1842 temp &= ~SDVO_ENABLE;
1843 intel_sdvo_write_sdvox(intel_sdvo, temp);
1844
1845 /*
1846 * HW workaround for IBX, we need to move the port
1847 * to transcoder A after disabling it to allow the
1848 * matching DP port to be enabled on transcoder A.
1849 */
1850 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1851 /*
1852 * We get CPU/PCH FIFO underruns on the other pipe when
1853 * doing the workaround. Sweep them under the rug.
1854 */
1855 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1856 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1857
1858 temp &= ~SDVO_PIPE_SEL_MASK;
1859 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1860 intel_sdvo_write_sdvox(intel_sdvo, temp);
1861
1862 temp &= ~SDVO_ENABLE;
1863 intel_sdvo_write_sdvox(intel_sdvo, temp);
1864
1865 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1866 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1867 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1868 }
1869}
1870
1871static void pch_disable_sdvo(struct intel_atomic_state *state,
1872 struct intel_encoder *encoder,
1873 const struct intel_crtc_state *old_crtc_state,
1874 const struct drm_connector_state *old_conn_state)
1875{
1876}
1877
1878static void pch_post_disable_sdvo(struct intel_atomic_state *state,
1879 struct intel_encoder *encoder,
1880 const struct intel_crtc_state *old_crtc_state,
1881 const struct drm_connector_state *old_conn_state)
1882{
1883 intel_disable_sdvo(state, encoder, old_crtc_state, old_conn_state);
1884}
1885
1886static void intel_enable_sdvo(struct intel_atomic_state *state,
1887 struct intel_encoder *encoder,
1888 const struct intel_crtc_state *pipe_config,
1889 const struct drm_connector_state *conn_state)
1890{
1891 struct drm_device *dev = encoder->base.dev;
1892 struct drm_i915_private *dev_priv = to_i915(dev);
1893 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1894 struct intel_sdvo_connector *intel_sdvo_connector =
1895 to_intel_sdvo_connector(conn_state->connector);
1896 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1897 u32 temp;
1898 bool input1, input2;
1899 int i;
1900 bool success;
1901
1902 temp = intel_de_read(dev_priv, intel_sdvo->sdvo_reg);
1903 temp |= SDVO_ENABLE;
1904 intel_sdvo_write_sdvox(intel_sdvo, temp);
1905
1906 for (i = 0; i < 2; i++)
1907 intel_crtc_wait_for_next_vblank(crtc);
1908
1909 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1910 /*
1911 * Warn if the device reported failure to sync.
1912 *
1913 * A lot of SDVO devices fail to notify of sync, but it's
1914 * a given it the status is a success, we succeeded.
1915 */
1916 if (success && !input1) {
1917 drm_dbg_kms(&dev_priv->drm,
1918 "First %s output reported failure to "
1919 "sync\n", SDVO_NAME(intel_sdvo));
1920 }
1921
1922 if (0)
1923 intel_sdvo_set_encoder_power_state(intel_sdvo,
1924 DRM_MODE_DPMS_ON);
1925 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo_connector->output_flag);
1926
1927 encoder->audio_enable(encoder, pipe_config, conn_state);
1928}
1929
1930static enum drm_mode_status
1931intel_sdvo_mode_valid(struct drm_connector *connector,
1932 struct drm_display_mode *mode)
1933{
1934 struct drm_i915_private *i915 = to_i915(connector->dev);
1935 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
1936 struct intel_sdvo_connector *intel_sdvo_connector =
1937 to_intel_sdvo_connector(connector);
1938 bool has_hdmi_sink = intel_has_hdmi_sink(intel_sdvo_connector, connector->state);
1939 int max_dotclk = i915->max_dotclk_freq;
1940 enum drm_mode_status status;
1941 int clock = mode->clock;
1942
1943 status = intel_cpu_transcoder_mode_valid(i915, mode);
1944 if (status != MODE_OK)
1945 return status;
1946
1947 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1948 return MODE_NO_DBLESCAN;
1949
1950 if (clock > max_dotclk)
1951 return MODE_CLOCK_HIGH;
1952
1953 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1954 if (!has_hdmi_sink)
1955 return MODE_CLOCK_LOW;
1956 clock *= 2;
1957 }
1958
1959 if (intel_sdvo->pixel_clock_min > clock)
1960 return MODE_CLOCK_LOW;
1961
1962 if (intel_sdvo->pixel_clock_max < clock)
1963 return MODE_CLOCK_HIGH;
1964
1965 if (IS_LVDS(intel_sdvo_connector)) {
1966 enum drm_mode_status status;
1967
1968 status = intel_panel_mode_valid(&intel_sdvo_connector->base, mode);
1969 if (status != MODE_OK)
1970 return status;
1971 }
1972
1973 return MODE_OK;
1974}
1975
1976static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1977{
1978 BUILD_BUG_ON(sizeof(*caps) != 8);
1979 if (!intel_sdvo_get_value(intel_sdvo,
1980 SDVO_CMD_GET_DEVICE_CAPS,
1981 caps, sizeof(*caps)))
1982 return false;
1983
1984 DRM_DEBUG_KMS("SDVO capabilities:\n"
1985 " vendor_id: %d\n"
1986 " device_id: %d\n"
1987 " device_rev_id: %d\n"
1988 " sdvo_version_major: %d\n"
1989 " sdvo_version_minor: %d\n"
1990 " sdvo_num_inputs: %d\n"
1991 " smooth_scaling: %d\n"
1992 " sharp_scaling: %d\n"
1993 " up_scaling: %d\n"
1994 " down_scaling: %d\n"
1995 " stall_support: %d\n"
1996 " output_flags: %d\n",
1997 caps->vendor_id,
1998 caps->device_id,
1999 caps->device_rev_id,
2000 caps->sdvo_version_major,
2001 caps->sdvo_version_minor,
2002 caps->sdvo_num_inputs,
2003 caps->smooth_scaling,
2004 caps->sharp_scaling,
2005 caps->up_scaling,
2006 caps->down_scaling,
2007 caps->stall_support,
2008 caps->output_flags);
2009
2010 return true;
2011}
2012
2013static u8 intel_sdvo_get_colorimetry_cap(struct intel_sdvo *intel_sdvo)
2014{
2015 u8 cap;
2016
2017 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_COLORIMETRY_CAP,
2018 &cap, sizeof(cap)))
2019 return SDVO_COLORIMETRY_RGB256;
2020
2021 return cap;
2022}
2023
2024static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
2025{
2026 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
2027 u16 hotplug;
2028
2029 if (!I915_HAS_HOTPLUG(dev_priv))
2030 return 0;
2031
2032 /*
2033 * HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
2034 * on the line.
2035 */
2036 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
2037 return 0;
2038
2039 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
2040 &hotplug, sizeof(hotplug)))
2041 return 0;
2042
2043 return hotplug;
2044}
2045
2046static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
2047{
2048 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2049
2050 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
2051 &intel_sdvo->hotplug_active, 2);
2052}
2053
2054static enum intel_hotplug_state
2055intel_sdvo_hotplug(struct intel_encoder *encoder,
2056 struct intel_connector *connector)
2057{
2058 intel_sdvo_enable_hotplug(encoder);
2059
2060 return intel_encoder_hotplug(encoder, connector);
2061}
2062
2063static const struct drm_edid *
2064intel_sdvo_get_edid(struct drm_connector *connector)
2065{
2066 struct i2c_adapter *ddc = connector->ddc;
2067
2068 if (!ddc)
2069 return NULL;
2070
2071 return drm_edid_read_ddc(connector, ddc);
2072}
2073
2074/* Mac mini hack -- use the same DDC as the analog connector */
2075static const struct drm_edid *
2076intel_sdvo_get_analog_edid(struct drm_connector *connector)
2077{
2078 struct drm_i915_private *i915 = to_i915(connector->dev);
2079 struct i2c_adapter *ddc;
2080
2081 ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
2082 if (!ddc)
2083 return NULL;
2084
2085 return drm_edid_read_ddc(connector, ddc);
2086}
2087
2088static enum drm_connector_status
2089intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
2090{
2091 enum drm_connector_status status;
2092 const struct drm_edid *drm_edid;
2093
2094 drm_edid = intel_sdvo_get_edid(connector);
2095
2096 /*
2097 * When there is no edid and no monitor is connected with VGA
2098 * port, try to use the CRT ddc to read the EDID for DVI-connector.
2099 */
2100 if (!drm_edid)
2101 drm_edid = intel_sdvo_get_analog_edid(connector);
2102
2103 status = connector_status_unknown;
2104 if (drm_edid) {
2105 /* DDC bus is shared, match EDID to connector type */
2106 if (drm_edid_is_digital(drm_edid))
2107 status = connector_status_connected;
2108 else
2109 status = connector_status_disconnected;
2110 drm_edid_free(drm_edid);
2111 }
2112
2113 return status;
2114}
2115
2116static bool
2117intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
2118 const struct drm_edid *drm_edid)
2119{
2120 bool monitor_is_digital = drm_edid_is_digital(drm_edid);
2121 bool connector_is_digital = !!IS_DIGITAL(sdvo);
2122
2123 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
2124 connector_is_digital, monitor_is_digital);
2125 return connector_is_digital == monitor_is_digital;
2126}
2127
2128static enum drm_connector_status
2129intel_sdvo_detect(struct drm_connector *connector, bool force)
2130{
2131 struct drm_i915_private *i915 = to_i915(connector->dev);
2132 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2133 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2134 enum drm_connector_status ret;
2135 u16 response;
2136
2137 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2138 connector->base.id, connector->name);
2139
2140 if (!intel_display_device_enabled(i915))
2141 return connector_status_disconnected;
2142
2143 if (!intel_sdvo_set_target_output(intel_sdvo,
2144 intel_sdvo_connector->output_flag))
2145 return connector_status_unknown;
2146
2147 if (!intel_sdvo_get_value(intel_sdvo,
2148 SDVO_CMD_GET_ATTACHED_DISPLAYS,
2149 &response, 2))
2150 return connector_status_unknown;
2151
2152 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
2153 response & 0xff, response >> 8,
2154 intel_sdvo_connector->output_flag);
2155
2156 if (response == 0)
2157 return connector_status_disconnected;
2158
2159 if ((intel_sdvo_connector->output_flag & response) == 0)
2160 ret = connector_status_disconnected;
2161 else if (IS_TMDS(intel_sdvo_connector))
2162 ret = intel_sdvo_tmds_sink_detect(connector);
2163 else {
2164 const struct drm_edid *drm_edid;
2165
2166 /* if we have an edid check it matches the connection */
2167 drm_edid = intel_sdvo_get_edid(connector);
2168 if (!drm_edid)
2169 drm_edid = intel_sdvo_get_analog_edid(connector);
2170 if (drm_edid) {
2171 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
2172 drm_edid))
2173 ret = connector_status_connected;
2174 else
2175 ret = connector_status_disconnected;
2176
2177 drm_edid_free(drm_edid);
2178 } else {
2179 ret = connector_status_connected;
2180 }
2181 }
2182
2183 return ret;
2184}
2185
2186static int intel_sdvo_get_ddc_modes(struct drm_connector *connector)
2187{
2188 int num_modes = 0;
2189 const struct drm_edid *drm_edid;
2190
2191 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2192 connector->base.id, connector->name);
2193
2194 /* set the bus switch and get the modes */
2195 drm_edid = intel_sdvo_get_edid(connector);
2196
2197 /*
2198 * Mac mini hack. On this device, the DVI-I connector shares one DDC
2199 * link between analog and digital outputs. So, if the regular SDVO
2200 * DDC fails, check to see if the analog output is disconnected, in
2201 * which case we'll look there for the digital DDC data.
2202 */
2203 if (!drm_edid)
2204 drm_edid = intel_sdvo_get_analog_edid(connector);
2205
2206 if (!drm_edid)
2207 return 0;
2208
2209 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
2210 drm_edid))
2211 num_modes += intel_connector_update_modes(connector, drm_edid);
2212
2213 drm_edid_free(drm_edid);
2214
2215 return num_modes;
2216}
2217
2218/*
2219 * Set of SDVO TV modes.
2220 * Note! This is in reply order (see loop in get_tv_modes).
2221 * XXX: all 60Hz refresh?
2222 */
2223static const struct drm_display_mode sdvo_tv_modes[] = {
2224 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
2225 416, 0, 200, 201, 232, 233, 0,
2226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2227 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
2228 416, 0, 240, 241, 272, 273, 0,
2229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2230 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
2231 496, 0, 300, 301, 332, 333, 0,
2232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2233 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
2234 736, 0, 350, 351, 382, 383, 0,
2235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2236 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
2237 736, 0, 400, 401, 432, 433, 0,
2238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2239 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
2240 736, 0, 480, 481, 512, 513, 0,
2241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2242 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
2243 800, 0, 480, 481, 512, 513, 0,
2244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2245 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
2246 800, 0, 576, 577, 608, 609, 0,
2247 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2248 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
2249 816, 0, 350, 351, 382, 383, 0,
2250 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2251 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
2252 816, 0, 400, 401, 432, 433, 0,
2253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2254 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
2255 816, 0, 480, 481, 512, 513, 0,
2256 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2257 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2258 816, 0, 540, 541, 572, 573, 0,
2259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2260 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2261 816, 0, 576, 577, 608, 609, 0,
2262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2263 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2264 864, 0, 576, 577, 608, 609, 0,
2265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2266 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2267 896, 0, 600, 601, 632, 633, 0,
2268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2269 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2270 928, 0, 624, 625, 656, 657, 0,
2271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2272 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2273 1016, 0, 766, 767, 798, 799, 0,
2274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2275 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2276 1120, 0, 768, 769, 800, 801, 0,
2277 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2278 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2279 1376, 0, 1024, 1025, 1056, 1057, 0,
2280 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2281};
2282
2283static int intel_sdvo_get_tv_modes(struct drm_connector *connector)
2284{
2285 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(to_intel_connector(connector));
2286 struct intel_sdvo_connector *intel_sdvo_connector =
2287 to_intel_sdvo_connector(connector);
2288 const struct drm_connector_state *conn_state = connector->state;
2289 struct intel_sdvo_sdtv_resolution_request tv_res;
2290 u32 reply = 0, format_map = 0;
2291 int num_modes = 0;
2292 int i;
2293
2294 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2295 connector->base.id, connector->name);
2296
2297 /*
2298 * Read the list of supported input resolutions for the selected TV
2299 * format.
2300 */
2301 format_map = 1 << conn_state->tv.legacy_mode;
2302 memcpy(&tv_res, &format_map,
2303 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
2304
2305 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo_connector->output_flag))
2306 return 0;
2307
2308 BUILD_BUG_ON(sizeof(tv_res) != 3);
2309 if (!intel_sdvo_write_cmd(intel_sdvo,
2310 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
2311 &tv_res, sizeof(tv_res)))
2312 return 0;
2313 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
2314 return 0;
2315
2316 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) {
2317 if (reply & (1 << i)) {
2318 struct drm_display_mode *nmode;
2319 nmode = drm_mode_duplicate(connector->dev,
2320 &sdvo_tv_modes[i]);
2321 if (nmode) {
2322 drm_mode_probed_add(connector, nmode);
2323 num_modes++;
2324 }
2325 }
2326 }
2327
2328 return num_modes;
2329}
2330
2331static int intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2332{
2333 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2334
2335 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2336 connector->base.id, connector->name);
2337
2338 return intel_panel_get_modes(to_intel_connector(connector));
2339}
2340
2341static int intel_sdvo_get_modes(struct drm_connector *connector)
2342{
2343 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2344
2345 if (IS_TV(intel_sdvo_connector))
2346 return intel_sdvo_get_tv_modes(connector);
2347 else if (IS_LVDS(intel_sdvo_connector))
2348 return intel_sdvo_get_lvds_modes(connector);
2349 else
2350 return intel_sdvo_get_ddc_modes(connector);
2351}
2352
2353static int
2354intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2355 const struct drm_connector_state *state,
2356 struct drm_property *property,
2357 u64 *val)
2358{
2359 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2360 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2361
2362 if (property == intel_sdvo_connector->tv_format) {
2363 int i;
2364
2365 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2366 if (state->tv.legacy_mode == intel_sdvo_connector->tv_format_supported[i]) {
2367 *val = i;
2368
2369 return 0;
2370 }
2371
2372 drm_WARN_ON(connector->dev, 1);
2373 *val = 0;
2374 } else if (property == intel_sdvo_connector->top ||
2375 property == intel_sdvo_connector->bottom)
2376 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2377 else if (property == intel_sdvo_connector->left ||
2378 property == intel_sdvo_connector->right)
2379 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2380 else if (property == intel_sdvo_connector->hpos)
2381 *val = sdvo_state->tv.hpos;
2382 else if (property == intel_sdvo_connector->vpos)
2383 *val = sdvo_state->tv.vpos;
2384 else if (property == intel_sdvo_connector->saturation)
2385 *val = state->tv.saturation;
2386 else if (property == intel_sdvo_connector->contrast)
2387 *val = state->tv.contrast;
2388 else if (property == intel_sdvo_connector->hue)
2389 *val = state->tv.hue;
2390 else if (property == intel_sdvo_connector->brightness)
2391 *val = state->tv.brightness;
2392 else if (property == intel_sdvo_connector->sharpness)
2393 *val = sdvo_state->tv.sharpness;
2394 else if (property == intel_sdvo_connector->flicker_filter)
2395 *val = sdvo_state->tv.flicker_filter;
2396 else if (property == intel_sdvo_connector->flicker_filter_2d)
2397 *val = sdvo_state->tv.flicker_filter_2d;
2398 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2399 *val = sdvo_state->tv.flicker_filter_adaptive;
2400 else if (property == intel_sdvo_connector->tv_chroma_filter)
2401 *val = sdvo_state->tv.chroma_filter;
2402 else if (property == intel_sdvo_connector->tv_luma_filter)
2403 *val = sdvo_state->tv.luma_filter;
2404 else if (property == intel_sdvo_connector->dot_crawl)
2405 *val = sdvo_state->tv.dot_crawl;
2406 else
2407 return intel_digital_connector_atomic_get_property(connector, state, property, val);
2408
2409 return 0;
2410}
2411
2412static int
2413intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2414 struct drm_connector_state *state,
2415 struct drm_property *property,
2416 u64 val)
2417{
2418 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2419 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2420
2421 if (property == intel_sdvo_connector->tv_format) {
2422 state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[val];
2423
2424 if (state->crtc) {
2425 struct drm_crtc_state *crtc_state =
2426 drm_atomic_get_new_crtc_state(state->state, state->crtc);
2427
2428 crtc_state->connectors_changed = true;
2429 }
2430 } else if (property == intel_sdvo_connector->top ||
2431 property == intel_sdvo_connector->bottom)
2432 /* Cannot set these independent from each other */
2433 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2434 else if (property == intel_sdvo_connector->left ||
2435 property == intel_sdvo_connector->right)
2436 /* Cannot set these independent from each other */
2437 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2438 else if (property == intel_sdvo_connector->hpos)
2439 sdvo_state->tv.hpos = val;
2440 else if (property == intel_sdvo_connector->vpos)
2441 sdvo_state->tv.vpos = val;
2442 else if (property == intel_sdvo_connector->saturation)
2443 state->tv.saturation = val;
2444 else if (property == intel_sdvo_connector->contrast)
2445 state->tv.contrast = val;
2446 else if (property == intel_sdvo_connector->hue)
2447 state->tv.hue = val;
2448 else if (property == intel_sdvo_connector->brightness)
2449 state->tv.brightness = val;
2450 else if (property == intel_sdvo_connector->sharpness)
2451 sdvo_state->tv.sharpness = val;
2452 else if (property == intel_sdvo_connector->flicker_filter)
2453 sdvo_state->tv.flicker_filter = val;
2454 else if (property == intel_sdvo_connector->flicker_filter_2d)
2455 sdvo_state->tv.flicker_filter_2d = val;
2456 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2457 sdvo_state->tv.flicker_filter_adaptive = val;
2458 else if (property == intel_sdvo_connector->tv_chroma_filter)
2459 sdvo_state->tv.chroma_filter = val;
2460 else if (property == intel_sdvo_connector->tv_luma_filter)
2461 sdvo_state->tv.luma_filter = val;
2462 else if (property == intel_sdvo_connector->dot_crawl)
2463 sdvo_state->tv.dot_crawl = val;
2464 else
2465 return intel_digital_connector_atomic_set_property(connector, state, property, val);
2466
2467 return 0;
2468}
2469
2470static struct drm_connector_state *
2471intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2472{
2473 struct intel_sdvo_connector_state *state;
2474
2475 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2476 if (!state)
2477 return NULL;
2478
2479 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2480 return &state->base.base;
2481}
2482
2483static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2484 .detect = intel_sdvo_detect,
2485 .fill_modes = drm_helper_probe_single_connector_modes,
2486 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2487 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
2488 .late_register = intel_connector_register,
2489 .early_unregister = intel_connector_unregister,
2490 .destroy = intel_connector_destroy,
2491 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2492 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2493};
2494
2495static int intel_sdvo_atomic_check(struct drm_connector *conn,
2496 struct drm_atomic_state *state)
2497{
2498 struct drm_connector_state *new_conn_state =
2499 drm_atomic_get_new_connector_state(state, conn);
2500 struct drm_connector_state *old_conn_state =
2501 drm_atomic_get_old_connector_state(state, conn);
2502 struct intel_sdvo_connector_state *old_state =
2503 to_intel_sdvo_connector_state(old_conn_state);
2504 struct intel_sdvo_connector_state *new_state =
2505 to_intel_sdvo_connector_state(new_conn_state);
2506
2507 if (new_conn_state->crtc &&
2508 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2509 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2510 struct drm_crtc_state *crtc_state =
2511 drm_atomic_get_new_crtc_state(state,
2512 new_conn_state->crtc);
2513
2514 crtc_state->connectors_changed = true;
2515 }
2516
2517 return intel_digital_connector_atomic_check(conn, state);
2518}
2519
2520static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2521 .get_modes = intel_sdvo_get_modes,
2522 .mode_valid = intel_sdvo_mode_valid,
2523 .atomic_check = intel_sdvo_atomic_check,
2524};
2525
2526static void intel_sdvo_encoder_destroy(struct drm_encoder *_encoder)
2527{
2528 struct intel_encoder *encoder = to_intel_encoder(_encoder);
2529 struct intel_sdvo *sdvo = to_sdvo(encoder);
2530 int i;
2531
2532 for (i = 0; i < ARRAY_SIZE(sdvo->ddc); i++) {
2533 if (sdvo->ddc[i].ddc_bus)
2534 i2c_del_adapter(&sdvo->ddc[i].ddc);
2535 }
2536
2537 drm_encoder_cleanup(&encoder->base);
2538 kfree(sdvo);
2539};
2540
2541static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2542 .destroy = intel_sdvo_encoder_destroy,
2543};
2544
2545static int
2546intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo,
2547 struct intel_sdvo_connector *connector)
2548{
2549 u16 mask = 0;
2550 int num_bits;
2551
2552 /*
2553 * Make a mask of outputs less than or equal to our own priority in the
2554 * list.
2555 */
2556 switch (connector->output_flag) {
2557 case SDVO_OUTPUT_LVDS1:
2558 mask |= SDVO_OUTPUT_LVDS1;
2559 fallthrough;
2560 case SDVO_OUTPUT_LVDS0:
2561 mask |= SDVO_OUTPUT_LVDS0;
2562 fallthrough;
2563 case SDVO_OUTPUT_TMDS1:
2564 mask |= SDVO_OUTPUT_TMDS1;
2565 fallthrough;
2566 case SDVO_OUTPUT_TMDS0:
2567 mask |= SDVO_OUTPUT_TMDS0;
2568 fallthrough;
2569 case SDVO_OUTPUT_RGB1:
2570 mask |= SDVO_OUTPUT_RGB1;
2571 fallthrough;
2572 case SDVO_OUTPUT_RGB0:
2573 mask |= SDVO_OUTPUT_RGB0;
2574 break;
2575 }
2576
2577 /* Count bits to find what number we are in the priority list. */
2578 mask &= sdvo->caps.output_flags;
2579 num_bits = hweight16(mask);
2580 /* If more than 3 outputs, default to DDC bus 3 for now. */
2581 if (num_bits > 3)
2582 num_bits = 3;
2583
2584 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2585 return num_bits;
2586}
2587
2588/*
2589 * Choose the appropriate DDC bus for control bus switch command for this
2590 * SDVO output based on the controlled output.
2591 *
2592 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2593 * outputs, then LVDS outputs.
2594 */
2595static struct intel_sdvo_ddc *
2596intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
2597 struct intel_sdvo_connector *connector)
2598{
2599 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2600 const struct sdvo_device_mapping *mapping;
2601 int ddc_bus;
2602
2603 if (sdvo->base.port == PORT_B)
2604 mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2605 else
2606 mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2607
2608 if (mapping->initialized)
2609 ddc_bus = (mapping->ddc_pin & 0xf0) >> 4;
2610 else
2611 ddc_bus = intel_sdvo_guess_ddc_bus(sdvo, connector);
2612
2613 if (ddc_bus < 1 || ddc_bus > 3)
2614 return NULL;
2615
2616 return &sdvo->ddc[ddc_bus - 1];
2617}
2618
2619static void
2620intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
2621{
2622 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2623 const struct sdvo_device_mapping *mapping;
2624 u8 pin;
2625
2626 if (sdvo->base.port == PORT_B)
2627 mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2628 else
2629 mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2630
2631 if (mapping->initialized &&
2632 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2633 pin = mapping->i2c_pin;
2634 else
2635 pin = GMBUS_PIN_DPB;
2636
2637 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] I2C pin %d, slave addr 0x%x\n",
2638 sdvo->base.base.base.id, sdvo->base.base.name,
2639 pin, sdvo->slave_addr);
2640
2641 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2642
2643 /*
2644 * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2645 * our code totally fails once we start using gmbus. Hence fall back to
2646 * bit banging for now.
2647 */
2648 intel_gmbus_force_bit(sdvo->i2c, true);
2649}
2650
2651/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2652static void
2653intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2654{
2655 intel_gmbus_force_bit(sdvo->i2c, false);
2656}
2657
2658static bool
2659intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo)
2660{
2661 return intel_sdvo_check_supp_encode(intel_sdvo);
2662}
2663
2664static u8
2665intel_sdvo_get_slave_addr(struct intel_sdvo *sdvo)
2666{
2667 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
2668 const struct sdvo_device_mapping *my_mapping, *other_mapping;
2669
2670 if (sdvo->base.port == PORT_B) {
2671 my_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2672 other_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2673 } else {
2674 my_mapping = &dev_priv->display.vbt.sdvo_mappings[1];
2675 other_mapping = &dev_priv->display.vbt.sdvo_mappings[0];
2676 }
2677
2678 /* If the BIOS described our SDVO device, take advantage of it. */
2679 if (my_mapping->slave_addr)
2680 return my_mapping->slave_addr;
2681
2682 /*
2683 * If the BIOS only described a different SDVO device, use the
2684 * address that it isn't using.
2685 */
2686 if (other_mapping->slave_addr) {
2687 if (other_mapping->slave_addr == 0x70)
2688 return 0x72;
2689 else
2690 return 0x70;
2691 }
2692
2693 /*
2694 * No SDVO device info is found for another DVO port,
2695 * so use mapping assumption we had before BIOS parsing.
2696 */
2697 if (sdvo->base.port == PORT_B)
2698 return 0x70;
2699 else
2700 return 0x72;
2701}
2702
2703static int
2704intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
2705 struct intel_sdvo *sdvo, int bit);
2706
2707static int
2708intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2709 struct intel_sdvo *encoder)
2710{
2711 struct drm_i915_private *i915 = to_i915(encoder->base.base.dev);
2712 struct intel_sdvo_ddc *ddc = NULL;
2713 int ret;
2714
2715 if (HAS_DDC(connector))
2716 ddc = intel_sdvo_select_ddc_bus(encoder, connector);
2717
2718 ret = drm_connector_init_with_ddc(encoder->base.base.dev,
2719 &connector->base.base,
2720 &intel_sdvo_connector_funcs,
2721 connector->base.base.connector_type,
2722 ddc ? &ddc->ddc : NULL);
2723 if (ret < 0)
2724 return ret;
2725
2726 drm_connector_helper_add(&connector->base.base,
2727 &intel_sdvo_connector_helper_funcs);
2728
2729 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2730 connector->base.base.interlace_allowed = true;
2731 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2732
2733 intel_connector_attach_encoder(&connector->base, &encoder->base);
2734
2735 if (ddc)
2736 drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] using %s\n",
2737 connector->base.base.base.id, connector->base.base.name,
2738 ddc->ddc.name);
2739
2740 return 0;
2741}
2742
2743static void
2744intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2745 struct intel_sdvo_connector *connector)
2746{
2747 intel_attach_force_audio_property(&connector->base.base);
2748 if (intel_sdvo->colorimetry_cap & SDVO_COLORIMETRY_RGB220)
2749 intel_attach_broadcast_rgb_property(&connector->base.base);
2750 intel_attach_aspect_ratio_property(&connector->base.base);
2751}
2752
2753static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2754{
2755 struct intel_sdvo_connector *sdvo_connector;
2756 struct intel_sdvo_connector_state *conn_state;
2757
2758 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2759 if (!sdvo_connector)
2760 return NULL;
2761
2762 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2763 if (!conn_state) {
2764 kfree(sdvo_connector);
2765 return NULL;
2766 }
2767
2768 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2769 &conn_state->base.base);
2770
2771 intel_panel_init_alloc(&sdvo_connector->base);
2772
2773 return sdvo_connector;
2774}
2775
2776static bool
2777intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, u16 type)
2778{
2779 struct drm_encoder *encoder = &intel_sdvo->base.base;
2780 struct drm_connector *connector;
2781 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2782 struct intel_connector *intel_connector;
2783 struct intel_sdvo_connector *intel_sdvo_connector;
2784
2785 DRM_DEBUG_KMS("initialising DVI type 0x%x\n", type);
2786
2787 intel_sdvo_connector = intel_sdvo_connector_alloc();
2788 if (!intel_sdvo_connector)
2789 return false;
2790
2791 intel_sdvo_connector->output_flag = type;
2792
2793 intel_connector = &intel_sdvo_connector->base;
2794 connector = &intel_connector->base;
2795 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2796 intel_sdvo_connector->output_flag) {
2797 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2798 /*
2799 * Some SDVO devices have one-shot hotplug interrupts.
2800 * Ensure that they get re-enabled when an interrupt happens.
2801 */
2802 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
2803 intel_encoder->hotplug = intel_sdvo_hotplug;
2804 intel_sdvo_enable_hotplug(intel_encoder);
2805 } else {
2806 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2807 }
2808 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2809 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2810
2811 if (intel_sdvo_is_hdmi_connector(intel_sdvo)) {
2812 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2813 intel_sdvo_connector->is_hdmi = true;
2814 }
2815
2816 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2817 kfree(intel_sdvo_connector);
2818 return false;
2819 }
2820
2821 if (intel_sdvo_connector->is_hdmi)
2822 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2823
2824 return true;
2825}
2826
2827static bool
2828intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, u16 type)
2829{
2830 struct drm_encoder *encoder = &intel_sdvo->base.base;
2831 struct drm_connector *connector;
2832 struct intel_connector *intel_connector;
2833 struct intel_sdvo_connector *intel_sdvo_connector;
2834
2835 DRM_DEBUG_KMS("initialising TV type 0x%x\n", type);
2836
2837 intel_sdvo_connector = intel_sdvo_connector_alloc();
2838 if (!intel_sdvo_connector)
2839 return false;
2840
2841 intel_connector = &intel_sdvo_connector->base;
2842 connector = &intel_connector->base;
2843 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2844 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2845
2846 intel_sdvo_connector->output_flag = type;
2847
2848 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2849 kfree(intel_sdvo_connector);
2850 return false;
2851 }
2852
2853 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2854 goto err;
2855
2856 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2857 goto err;
2858
2859 return true;
2860
2861err:
2862 intel_connector_destroy(connector);
2863 return false;
2864}
2865
2866static bool
2867intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, u16 type)
2868{
2869 struct drm_encoder *encoder = &intel_sdvo->base.base;
2870 struct drm_connector *connector;
2871 struct intel_connector *intel_connector;
2872 struct intel_sdvo_connector *intel_sdvo_connector;
2873
2874 DRM_DEBUG_KMS("initialising analog type 0x%x\n", type);
2875
2876 intel_sdvo_connector = intel_sdvo_connector_alloc();
2877 if (!intel_sdvo_connector)
2878 return false;
2879
2880 intel_connector = &intel_sdvo_connector->base;
2881 connector = &intel_connector->base;
2882 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2883 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2884 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2885
2886 intel_sdvo_connector->output_flag = type;
2887
2888 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2889 kfree(intel_sdvo_connector);
2890 return false;
2891 }
2892
2893 return true;
2894}
2895
2896static bool
2897intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, u16 type)
2898{
2899 struct drm_encoder *encoder = &intel_sdvo->base.base;
2900 struct drm_i915_private *i915 = to_i915(encoder->dev);
2901 struct drm_connector *connector;
2902 struct intel_connector *intel_connector;
2903 struct intel_sdvo_connector *intel_sdvo_connector;
2904
2905 DRM_DEBUG_KMS("initialising LVDS type 0x%x\n", type);
2906
2907 intel_sdvo_connector = intel_sdvo_connector_alloc();
2908 if (!intel_sdvo_connector)
2909 return false;
2910
2911 intel_connector = &intel_sdvo_connector->base;
2912 connector = &intel_connector->base;
2913 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2914 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2915
2916 intel_sdvo_connector->output_flag = type;
2917
2918 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2919 kfree(intel_sdvo_connector);
2920 return false;
2921 }
2922
2923 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2924 goto err;
2925
2926 intel_bios_init_panel_late(i915, &intel_connector->panel, NULL, NULL);
2927
2928 /*
2929 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
2930 * SDVO->LVDS transcoders can't cope with the EDID mode.
2931 */
2932 intel_panel_add_vbt_sdvo_fixed_mode(intel_connector);
2933
2934 if (!intel_panel_preferred_fixed_mode(intel_connector)) {
2935 mutex_lock(&i915->drm.mode_config.mutex);
2936
2937 intel_ddc_get_modes(connector, connector->ddc);
2938 intel_panel_add_edid_fixed_modes(intel_connector, false);
2939
2940 mutex_unlock(&i915->drm.mode_config.mutex);
2941 }
2942
2943 intel_panel_init(intel_connector, NULL);
2944
2945 if (!intel_panel_preferred_fixed_mode(intel_connector))
2946 goto err;
2947
2948 return true;
2949
2950err:
2951 intel_connector_destroy(connector);
2952 return false;
2953}
2954
2955static u16 intel_sdvo_filter_output_flags(u16 flags)
2956{
2957 flags &= SDVO_OUTPUT_MASK;
2958
2959 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
2960 if (!(flags & SDVO_OUTPUT_TMDS0))
2961 flags &= ~SDVO_OUTPUT_TMDS1;
2962
2963 if (!(flags & SDVO_OUTPUT_RGB0))
2964 flags &= ~SDVO_OUTPUT_RGB1;
2965
2966 if (!(flags & SDVO_OUTPUT_LVDS0))
2967 flags &= ~SDVO_OUTPUT_LVDS1;
2968
2969 return flags;
2970}
2971
2972static bool intel_sdvo_output_init(struct intel_sdvo *sdvo, u16 type)
2973{
2974 if (type & SDVO_TMDS_MASK)
2975 return intel_sdvo_dvi_init(sdvo, type);
2976 else if (type & SDVO_TV_MASK)
2977 return intel_sdvo_tv_init(sdvo, type);
2978 else if (type & SDVO_RGB_MASK)
2979 return intel_sdvo_analog_init(sdvo, type);
2980 else if (type & SDVO_LVDS_MASK)
2981 return intel_sdvo_lvds_init(sdvo, type);
2982 else
2983 return false;
2984}
2985
2986static bool
2987intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo)
2988{
2989 static const u16 probe_order[] = {
2990 SDVO_OUTPUT_TMDS0,
2991 SDVO_OUTPUT_TMDS1,
2992 /* TV has no XXX1 function block */
2993 SDVO_OUTPUT_SVID0,
2994 SDVO_OUTPUT_CVBS0,
2995 SDVO_OUTPUT_YPRPB0,
2996 SDVO_OUTPUT_RGB0,
2997 SDVO_OUTPUT_RGB1,
2998 SDVO_OUTPUT_LVDS0,
2999 SDVO_OUTPUT_LVDS1,
3000 };
3001 u16 flags;
3002 int i;
3003
3004 flags = intel_sdvo_filter_output_flags(intel_sdvo->caps.output_flags);
3005
3006 if (flags == 0) {
3007 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%04x)\n",
3008 SDVO_NAME(intel_sdvo), intel_sdvo->caps.output_flags);
3009 return false;
3010 }
3011
3012 for (i = 0; i < ARRAY_SIZE(probe_order); i++) {
3013 u16 type = flags & probe_order[i];
3014
3015 if (!type)
3016 continue;
3017
3018 if (!intel_sdvo_output_init(intel_sdvo, type))
3019 return false;
3020 }
3021
3022 intel_sdvo->base.pipe_mask = ~0;
3023
3024 return true;
3025}
3026
3027static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
3028{
3029 struct drm_device *dev = intel_sdvo->base.base.dev;
3030 struct drm_connector *connector, *tmp;
3031
3032 list_for_each_entry_safe(connector, tmp,
3033 &dev->mode_config.connector_list, head) {
3034 if (intel_attached_encoder(to_intel_connector(connector)) == &intel_sdvo->base) {
3035 drm_connector_unregister(connector);
3036 intel_connector_destroy(connector);
3037 }
3038 }
3039}
3040
3041static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
3042 struct intel_sdvo_connector *intel_sdvo_connector,
3043 int type)
3044{
3045 struct drm_device *dev = intel_sdvo->base.base.dev;
3046 struct intel_sdvo_tv_format format;
3047 u32 format_map, i;
3048
3049 if (!intel_sdvo_set_target_output(intel_sdvo, type))
3050 return false;
3051
3052 BUILD_BUG_ON(sizeof(format) != 6);
3053 if (!intel_sdvo_get_value(intel_sdvo,
3054 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
3055 &format, sizeof(format)))
3056 return false;
3057
3058 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
3059
3060 if (format_map == 0)
3061 return false;
3062
3063 intel_sdvo_connector->format_supported_num = 0;
3064 for (i = 0 ; i < TV_FORMAT_NUM; i++)
3065 if (format_map & (1 << i))
3066 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
3067
3068
3069 intel_sdvo_connector->tv_format =
3070 drm_property_create(dev, DRM_MODE_PROP_ENUM,
3071 "mode", intel_sdvo_connector->format_supported_num);
3072 if (!intel_sdvo_connector->tv_format)
3073 return false;
3074
3075 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
3076 drm_property_add_enum(intel_sdvo_connector->tv_format, i,
3077 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
3078
3079 intel_sdvo_connector->base.base.state->tv.legacy_mode = intel_sdvo_connector->tv_format_supported[0];
3080 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
3081 intel_sdvo_connector->tv_format, 0);
3082 return true;
3083
3084}
3085
3086#define _ENHANCEMENT(state_assignment, name, NAME) do { \
3087 if (enhancements.name) { \
3088 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
3089 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
3090 return false; \
3091 intel_sdvo_connector->name = \
3092 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
3093 if (!intel_sdvo_connector->name) return false; \
3094 state_assignment = response; \
3095 drm_object_attach_property(&connector->base, \
3096 intel_sdvo_connector->name, 0); \
3097 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
3098 data_value[0], data_value[1], response); \
3099 } \
3100} while (0)
3101
3102#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
3103
3104static bool
3105intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
3106 struct intel_sdvo_connector *intel_sdvo_connector,
3107 struct intel_sdvo_enhancements_reply enhancements)
3108{
3109 struct drm_device *dev = intel_sdvo->base.base.dev;
3110 struct drm_connector *connector = &intel_sdvo_connector->base.base;
3111 struct drm_connector_state *conn_state = connector->state;
3112 struct intel_sdvo_connector_state *sdvo_state =
3113 to_intel_sdvo_connector_state(conn_state);
3114 u16 response, data_value[2];
3115
3116 /* when horizontal overscan is supported, Add the left/right property */
3117 if (enhancements.overscan_h) {
3118 if (!intel_sdvo_get_value(intel_sdvo,
3119 SDVO_CMD_GET_MAX_OVERSCAN_H,
3120 &data_value, 4))
3121 return false;
3122
3123 if (!intel_sdvo_get_value(intel_sdvo,
3124 SDVO_CMD_GET_OVERSCAN_H,
3125 &response, 2))
3126 return false;
3127
3128 sdvo_state->tv.overscan_h = response;
3129
3130 intel_sdvo_connector->max_hscan = data_value[0];
3131 intel_sdvo_connector->left =
3132 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
3133 if (!intel_sdvo_connector->left)
3134 return false;
3135
3136 drm_object_attach_property(&connector->base,
3137 intel_sdvo_connector->left, 0);
3138
3139 intel_sdvo_connector->right =
3140 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
3141 if (!intel_sdvo_connector->right)
3142 return false;
3143
3144 drm_object_attach_property(&connector->base,
3145 intel_sdvo_connector->right, 0);
3146 DRM_DEBUG_KMS("h_overscan: max %d, "
3147 "default %d, current %d\n",
3148 data_value[0], data_value[1], response);
3149 }
3150
3151 if (enhancements.overscan_v) {
3152 if (!intel_sdvo_get_value(intel_sdvo,
3153 SDVO_CMD_GET_MAX_OVERSCAN_V,
3154 &data_value, 4))
3155 return false;
3156
3157 if (!intel_sdvo_get_value(intel_sdvo,
3158 SDVO_CMD_GET_OVERSCAN_V,
3159 &response, 2))
3160 return false;
3161
3162 sdvo_state->tv.overscan_v = response;
3163
3164 intel_sdvo_connector->max_vscan = data_value[0];
3165 intel_sdvo_connector->top =
3166 drm_property_create_range(dev, 0,
3167 "top_margin", 0, data_value[0]);
3168 if (!intel_sdvo_connector->top)
3169 return false;
3170
3171 drm_object_attach_property(&connector->base,
3172 intel_sdvo_connector->top, 0);
3173
3174 intel_sdvo_connector->bottom =
3175 drm_property_create_range(dev, 0,
3176 "bottom_margin", 0, data_value[0]);
3177 if (!intel_sdvo_connector->bottom)
3178 return false;
3179
3180 drm_object_attach_property(&connector->base,
3181 intel_sdvo_connector->bottom, 0);
3182 DRM_DEBUG_KMS("v_overscan: max %d, "
3183 "default %d, current %d\n",
3184 data_value[0], data_value[1], response);
3185 }
3186
3187 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
3188 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
3189 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
3190 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
3191 ENHANCEMENT(&conn_state->tv, hue, HUE);
3192 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
3193 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
3194 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
3195 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
3196 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
3197 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
3198 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
3199
3200 if (enhancements.dot_crawl) {
3201 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
3202 return false;
3203
3204 sdvo_state->tv.dot_crawl = response & 0x1;
3205 intel_sdvo_connector->dot_crawl =
3206 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
3207 if (!intel_sdvo_connector->dot_crawl)
3208 return false;
3209
3210 drm_object_attach_property(&connector->base,
3211 intel_sdvo_connector->dot_crawl, 0);
3212 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
3213 }
3214
3215 return true;
3216}
3217
3218static bool
3219intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
3220 struct intel_sdvo_connector *intel_sdvo_connector,
3221 struct intel_sdvo_enhancements_reply enhancements)
3222{
3223 struct drm_device *dev = intel_sdvo->base.base.dev;
3224 struct drm_connector *connector = &intel_sdvo_connector->base.base;
3225 u16 response, data_value[2];
3226
3227 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
3228
3229 return true;
3230}
3231#undef ENHANCEMENT
3232#undef _ENHANCEMENT
3233
3234static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
3235 struct intel_sdvo_connector *intel_sdvo_connector)
3236{
3237 union {
3238 struct intel_sdvo_enhancements_reply reply;
3239 u16 response;
3240 } enhancements;
3241
3242 BUILD_BUG_ON(sizeof(enhancements) != 2);
3243
3244 if (!intel_sdvo_get_value(intel_sdvo,
3245 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3246 &enhancements, sizeof(enhancements)) ||
3247 enhancements.response == 0) {
3248 DRM_DEBUG_KMS("No enhancement is supported\n");
3249 return true;
3250 }
3251
3252 if (IS_TV(intel_sdvo_connector))
3253 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3254 else if (IS_LVDS(intel_sdvo_connector))
3255 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3256 else
3257 return true;
3258}
3259
3260static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3261 struct i2c_msg *msgs,
3262 int num)
3263{
3264 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3265 struct intel_sdvo *sdvo = ddc->sdvo;
3266
3267 if (!__intel_sdvo_set_control_bus_switch(sdvo, 1 << ddc->ddc_bus))
3268 return -EIO;
3269
3270 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3271}
3272
3273static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3274{
3275 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3276 struct intel_sdvo *sdvo = ddc->sdvo;
3277
3278 return sdvo->i2c->algo->functionality(sdvo->i2c);
3279}
3280
3281static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3282 .master_xfer = intel_sdvo_ddc_proxy_xfer,
3283 .functionality = intel_sdvo_ddc_proxy_func
3284};
3285
3286static void proxy_lock_bus(struct i2c_adapter *adapter,
3287 unsigned int flags)
3288{
3289 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3290 struct intel_sdvo *sdvo = ddc->sdvo;
3291
3292 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3293}
3294
3295static int proxy_trylock_bus(struct i2c_adapter *adapter,
3296 unsigned int flags)
3297{
3298 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3299 struct intel_sdvo *sdvo = ddc->sdvo;
3300
3301 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3302}
3303
3304static void proxy_unlock_bus(struct i2c_adapter *adapter,
3305 unsigned int flags)
3306{
3307 struct intel_sdvo_ddc *ddc = adapter->algo_data;
3308 struct intel_sdvo *sdvo = ddc->sdvo;
3309
3310 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3311}
3312
3313static const struct i2c_lock_operations proxy_lock_ops = {
3314 .lock_bus = proxy_lock_bus,
3315 .trylock_bus = proxy_trylock_bus,
3316 .unlock_bus = proxy_unlock_bus,
3317};
3318
3319static int
3320intel_sdvo_init_ddc_proxy(struct intel_sdvo_ddc *ddc,
3321 struct intel_sdvo *sdvo, int ddc_bus)
3322{
3323 struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
3324 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
3325
3326 ddc->sdvo = sdvo;
3327 ddc->ddc_bus = ddc_bus;
3328
3329 ddc->ddc.owner = THIS_MODULE;
3330 snprintf(ddc->ddc.name, I2C_NAME_SIZE, "SDVO %c DDC%d",
3331 port_name(sdvo->base.port), ddc_bus);
3332 ddc->ddc.dev.parent = &pdev->dev;
3333 ddc->ddc.algo_data = ddc;
3334 ddc->ddc.algo = &intel_sdvo_ddc_proxy;
3335 ddc->ddc.lock_ops = &proxy_lock_ops;
3336
3337 return i2c_add_adapter(&ddc->ddc);
3338}
3339
3340static bool is_sdvo_port_valid(struct drm_i915_private *dev_priv, enum port port)
3341{
3342 if (HAS_PCH_SPLIT(dev_priv))
3343 return port == PORT_B;
3344 else
3345 return port == PORT_B || port == PORT_C;
3346}
3347
3348static bool assert_sdvo_port_valid(struct drm_i915_private *dev_priv,
3349 enum port port)
3350{
3351 return !drm_WARN(&dev_priv->drm, !is_sdvo_port_valid(dev_priv, port),
3352 "Platform does not support SDVO %c\n", port_name(port));
3353}
3354
3355bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3356 i915_reg_t sdvo_reg, enum port port)
3357{
3358 struct intel_encoder *intel_encoder;
3359 struct intel_sdvo *intel_sdvo;
3360 int i;
3361
3362 if (!assert_port_valid(dev_priv, port))
3363 return false;
3364
3365 if (!assert_sdvo_port_valid(dev_priv, port))
3366 return false;
3367
3368 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3369 if (!intel_sdvo)
3370 return false;
3371
3372 /* encoder type will be decided later */
3373 intel_encoder = &intel_sdvo->base;
3374 intel_encoder->type = INTEL_OUTPUT_SDVO;
3375 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3376 intel_encoder->port = port;
3377
3378 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3379 &intel_sdvo_enc_funcs, 0,
3380 "SDVO %c", port_name(port));
3381
3382 intel_sdvo->sdvo_reg = sdvo_reg;
3383 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(intel_sdvo) >> 1;
3384
3385 intel_sdvo_select_i2c_bus(intel_sdvo);
3386
3387 /* Read the regs to test if we can talk to the device */
3388 for (i = 0; i < 0x40; i++) {
3389 u8 byte;
3390
3391 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3392 drm_dbg_kms(&dev_priv->drm,
3393 "No SDVO device found on %s\n",
3394 SDVO_NAME(intel_sdvo));
3395 goto err;
3396 }
3397 }
3398
3399 intel_encoder->compute_config = intel_sdvo_compute_config;
3400 if (HAS_PCH_SPLIT(dev_priv)) {
3401 intel_encoder->disable = pch_disable_sdvo;
3402 intel_encoder->post_disable = pch_post_disable_sdvo;
3403 } else {
3404 intel_encoder->disable = intel_disable_sdvo;
3405 }
3406 intel_encoder->pre_enable = intel_sdvo_pre_enable;
3407 intel_encoder->enable = intel_enable_sdvo;
3408 intel_encoder->audio_enable = intel_sdvo_enable_audio;
3409 intel_encoder->audio_disable = intel_sdvo_disable_audio;
3410 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3411 intel_encoder->get_config = intel_sdvo_get_config;
3412
3413 /* In default case sdvo lvds is false */
3414 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3415 goto err;
3416
3417 intel_sdvo->colorimetry_cap =
3418 intel_sdvo_get_colorimetry_cap(intel_sdvo);
3419
3420 for (i = 0; i < ARRAY_SIZE(intel_sdvo->ddc); i++) {
3421 int ret;
3422
3423 ret = intel_sdvo_init_ddc_proxy(&intel_sdvo->ddc[i],
3424 intel_sdvo, i + 1);
3425 if (ret)
3426 goto err;
3427 }
3428
3429 if (!intel_sdvo_output_setup(intel_sdvo)) {
3430 drm_dbg_kms(&dev_priv->drm,
3431 "SDVO output failed to setup on %s\n",
3432 SDVO_NAME(intel_sdvo));
3433 /* Output_setup can leave behind connectors! */
3434 goto err_output;
3435 }
3436
3437 /*
3438 * Only enable the hotplug irq if we need it, to work around noisy
3439 * hotplug lines.
3440 */
3441 if (intel_sdvo->hotplug_active) {
3442 if (intel_sdvo->base.port == PORT_B)
3443 intel_encoder->hpd_pin = HPD_SDVO_B;
3444 else
3445 intel_encoder->hpd_pin = HPD_SDVO_C;
3446 }
3447
3448 /*
3449 * Cloning SDVO with anything is often impossible, since the SDVO
3450 * encoder can request a special input timing mode. And even if that's
3451 * not the case we have evidence that cloning a plain unscaled mode with
3452 * VGA doesn't really work. Furthermore the cloning flags are way too
3453 * simplistic anyway to express such constraints, so just give up on
3454 * cloning for SDVO encoders.
3455 */
3456 intel_sdvo->base.cloneable = 0;
3457
3458 /* Set the input timing to the screen. Assume always input 0. */
3459 if (!intel_sdvo_set_target_input(intel_sdvo))
3460 goto err_output;
3461
3462 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3463 &intel_sdvo->pixel_clock_min,
3464 &intel_sdvo->pixel_clock_max))
3465 goto err_output;
3466
3467 drm_dbg_kms(&dev_priv->drm, "%s device VID/DID: %02X:%02X.%02X, "
3468 "clock range %dMHz - %dMHz, "
3469 "num inputs: %d, "
3470 "output 1: %c, output 2: %c\n",
3471 SDVO_NAME(intel_sdvo),
3472 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3473 intel_sdvo->caps.device_rev_id,
3474 intel_sdvo->pixel_clock_min / 1000,
3475 intel_sdvo->pixel_clock_max / 1000,
3476 intel_sdvo->caps.sdvo_num_inputs,
3477 /* check currently supported outputs */
3478 intel_sdvo->caps.output_flags &
3479 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0 |
3480 SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_SVID0 |
3481 SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_YPRPB0) ? 'Y' : 'N',
3482 intel_sdvo->caps.output_flags &
3483 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1 |
3484 SDVO_OUTPUT_LVDS1) ? 'Y' : 'N');
3485 return true;
3486
3487err_output:
3488 intel_sdvo_output_cleanup(intel_sdvo);
3489err:
3490 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3491 intel_sdvo_encoder_destroy(&intel_encoder->base);
3492
3493 return false;
3494}