Loading...
1/*
2 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H
15#define _DT_BINDINGS_RESET_MSM_GCC_8660_H
16
17#define AFAB_CORE_RESET 0
18#define SCSS_SYS_RESET 1
19#define SCSS_SYS_POR_RESET 2
20#define AFAB_SMPSS_S_RESET 3
21#define AFAB_SMPSS_M1_RESET 4
22#define AFAB_SMPSS_M0_RESET 5
23#define AFAB_EBI1_S_RESET 6
24#define SFAB_CORE_RESET 7
25#define SFAB_ADM0_M0_RESET 8
26#define SFAB_ADM0_M1_RESET 9
27#define SFAB_ADM0_M2_RESET 10
28#define ADM0_C2_RESET 11
29#define ADM0_C1_RESET 12
30#define ADM0_C0_RESET 13
31#define ADM0_PBUS_RESET 14
32#define ADM0_RESET 15
33#define SFAB_ADM1_M0_RESET 16
34#define SFAB_ADM1_M1_RESET 17
35#define SFAB_ADM1_M2_RESET 18
36#define MMFAB_ADM1_M3_RESET 19
37#define ADM1_C3_RESET 20
38#define ADM1_C2_RESET 21
39#define ADM1_C1_RESET 22
40#define ADM1_C0_RESET 23
41#define ADM1_PBUS_RESET 24
42#define ADM1_RESET 25
43#define IMEM0_RESET 26
44#define SFAB_LPASS_Q6_RESET 27
45#define SFAB_AFAB_M_RESET 28
46#define AFAB_SFAB_M0_RESET 29
47#define AFAB_SFAB_M1_RESET 30
48#define DFAB_CORE_RESET 31
49#define SFAB_DFAB_M_RESET 32
50#define DFAB_SFAB_M_RESET 33
51#define DFAB_SWAY0_RESET 34
52#define DFAB_SWAY1_RESET 35
53#define DFAB_ARB0_RESET 36
54#define DFAB_ARB1_RESET 37
55#define PPSS_PROC_RESET 38
56#define PPSS_RESET 39
57#define PMEM_RESET 40
58#define DMA_BAM_RESET 41
59#define SIC_RESET 42
60#define SPS_TIC_RESET 43
61#define CFBP0_RESET 44
62#define CFBP1_RESET 45
63#define CFBP2_RESET 46
64#define EBI2_RESET 47
65#define SFAB_CFPB_M_RESET 48
66#define CFPB_MASTER_RESET 49
67#define SFAB_CFPB_S_RESET 50
68#define CFPB_SPLITTER_RESET 51
69#define TSIF_RESET 52
70#define CE1_RESET 53
71#define CE2_RESET 54
72#define SFAB_SFPB_M_RESET 55
73#define SFAB_SFPB_S_RESET 56
74#define RPM_PROC_RESET 57
75#define RPM_BUS_RESET 58
76#define RPM_MSG_RAM_RESET 59
77#define PMIC_ARB0_RESET 60
78#define PMIC_ARB1_RESET 61
79#define PMIC_SSBI2_RESET 62
80#define SDC1_RESET 63
81#define SDC2_RESET 64
82#define SDC3_RESET 65
83#define SDC4_RESET 66
84#define SDC5_RESET 67
85#define USB_HS1_RESET 68
86#define USB_HS2_XCVR_RESET 69
87#define USB_HS2_RESET 70
88#define USB_FS1_XCVR_RESET 71
89#define USB_FS1_RESET 72
90#define USB_FS2_XCVR_RESET 73
91#define USB_FS2_RESET 74
92#define GSBI1_RESET 75
93#define GSBI2_RESET 76
94#define GSBI3_RESET 77
95#define GSBI4_RESET 78
96#define GSBI5_RESET 79
97#define GSBI6_RESET 80
98#define GSBI7_RESET 81
99#define GSBI8_RESET 82
100#define GSBI9_RESET 83
101#define GSBI10_RESET 84
102#define GSBI11_RESET 85
103#define GSBI12_RESET 86
104#define SPDM_RESET 87
105#define SEC_CTRL_RESET 88
106#define TLMM_H_RESET 89
107#define TLMM_RESET 90
108#define MARRM_PWRON_RESET 91
109#define MARM_RESET 92
110#define MAHB1_RESET 93
111#define SFAB_MSS_S_RESET 94
112#define MAHB2_RESET 95
113#define MODEM_SW_AHB_RESET 96
114#define MODEM_RESET 97
115#define SFAB_MSS_MDM1_RESET 98
116#define SFAB_MSS_MDM0_RESET 99
117#define MSS_SLP_RESET 100
118#define MSS_MARM_SAW_RESET 101
119#define MSS_WDOG_RESET 102
120#define TSSC_RESET 103
121#define PDM_RESET 104
122#define SCSS_CORE0_RESET 105
123#define SCSS_CORE0_POR_RESET 106
124#define SCSS_CORE1_RESET 107
125#define SCSS_CORE1_POR_RESET 108
126#define MPM_RESET 109
127#define EBI1_1X_DIV_RESET 110
128#define EBI1_RESET 111
129#define SFAB_SMPSS_S_RESET 112
130#define USB_PHY0_RESET 113
131#define USB_PHY1_RESET 114
132#define PRNG_RESET 115
133
134#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _DT_BINDINGS_RESET_MSM_GCC_8660_H
7#define _DT_BINDINGS_RESET_MSM_GCC_8660_H
8
9#define AFAB_CORE_RESET 0
10#define SCSS_SYS_RESET 1
11#define SCSS_SYS_POR_RESET 2
12#define AFAB_SMPSS_S_RESET 3
13#define AFAB_SMPSS_M1_RESET 4
14#define AFAB_SMPSS_M0_RESET 5
15#define AFAB_EBI1_S_RESET 6
16#define SFAB_CORE_RESET 7
17#define SFAB_ADM0_M0_RESET 8
18#define SFAB_ADM0_M1_RESET 9
19#define SFAB_ADM0_M2_RESET 10
20#define ADM0_C2_RESET 11
21#define ADM0_C1_RESET 12
22#define ADM0_C0_RESET 13
23#define ADM0_PBUS_RESET 14
24#define ADM0_RESET 15
25#define SFAB_ADM1_M0_RESET 16
26#define SFAB_ADM1_M1_RESET 17
27#define SFAB_ADM1_M2_RESET 18
28#define MMFAB_ADM1_M3_RESET 19
29#define ADM1_C3_RESET 20
30#define ADM1_C2_RESET 21
31#define ADM1_C1_RESET 22
32#define ADM1_C0_RESET 23
33#define ADM1_PBUS_RESET 24
34#define ADM1_RESET 25
35#define IMEM0_RESET 26
36#define SFAB_LPASS_Q6_RESET 27
37#define SFAB_AFAB_M_RESET 28
38#define AFAB_SFAB_M0_RESET 29
39#define AFAB_SFAB_M1_RESET 30
40#define DFAB_CORE_RESET 31
41#define SFAB_DFAB_M_RESET 32
42#define DFAB_SFAB_M_RESET 33
43#define DFAB_SWAY0_RESET 34
44#define DFAB_SWAY1_RESET 35
45#define DFAB_ARB0_RESET 36
46#define DFAB_ARB1_RESET 37
47#define PPSS_PROC_RESET 38
48#define PPSS_RESET 39
49#define PMEM_RESET 40
50#define DMA_BAM_RESET 41
51#define SIC_RESET 42
52#define SPS_TIC_RESET 43
53#define CFBP0_RESET 44
54#define CFBP1_RESET 45
55#define CFBP2_RESET 46
56#define EBI2_RESET 47
57#define SFAB_CFPB_M_RESET 48
58#define CFPB_MASTER_RESET 49
59#define SFAB_CFPB_S_RESET 50
60#define CFPB_SPLITTER_RESET 51
61#define TSIF_RESET 52
62#define CE1_RESET 53
63#define CE2_RESET 54
64#define SFAB_SFPB_M_RESET 55
65#define SFAB_SFPB_S_RESET 56
66#define RPM_PROC_RESET 57
67#define RPM_BUS_RESET 58
68#define RPM_MSG_RAM_RESET 59
69#define PMIC_ARB0_RESET 60
70#define PMIC_ARB1_RESET 61
71#define PMIC_SSBI2_RESET 62
72#define SDC1_RESET 63
73#define SDC2_RESET 64
74#define SDC3_RESET 65
75#define SDC4_RESET 66
76#define SDC5_RESET 67
77#define USB_HS1_RESET 68
78#define USB_HS2_XCVR_RESET 69
79#define USB_HS2_RESET 70
80#define USB_FS1_XCVR_RESET 71
81#define USB_FS1_RESET 72
82#define USB_FS2_XCVR_RESET 73
83#define USB_FS2_RESET 74
84#define GSBI1_RESET 75
85#define GSBI2_RESET 76
86#define GSBI3_RESET 77
87#define GSBI4_RESET 78
88#define GSBI5_RESET 79
89#define GSBI6_RESET 80
90#define GSBI7_RESET 81
91#define GSBI8_RESET 82
92#define GSBI9_RESET 83
93#define GSBI10_RESET 84
94#define GSBI11_RESET 85
95#define GSBI12_RESET 86
96#define SPDM_RESET 87
97#define SEC_CTRL_RESET 88
98#define TLMM_H_RESET 89
99#define TLMM_RESET 90
100#define MARRM_PWRON_RESET 91
101#define MARM_RESET 92
102#define MAHB1_RESET 93
103#define SFAB_MSS_S_RESET 94
104#define MAHB2_RESET 95
105#define MODEM_SW_AHB_RESET 96
106#define MODEM_RESET 97
107#define SFAB_MSS_MDM1_RESET 98
108#define SFAB_MSS_MDM0_RESET 99
109#define MSS_SLP_RESET 100
110#define MSS_MARM_SAW_RESET 101
111#define MSS_WDOG_RESET 102
112#define TSSC_RESET 103
113#define PDM_RESET 104
114#define SCSS_CORE0_RESET 105
115#define SCSS_CORE0_POR_RESET 106
116#define SCSS_CORE1_RESET 107
117#define SCSS_CORE1_POR_RESET 108
118#define MPM_RESET 109
119#define EBI1_1X_DIV_RESET 110
120#define EBI1_RESET 111
121#define SFAB_SMPSS_S_RESET 112
122#define USB_PHY0_RESET 113
123#define USB_PHY1_RESET 114
124#define PRNG_RESET 115
125
126#endif