1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/*
  3 * Copyright (c) 2016 BayLibre, SAS.
  4 * Author: Neil Armstrong <narmstrong@baylibre.com>
  5 */
  6#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
  7#define _DT_BINDINGS_AMLOGIC_MESON8B_RESET_H
  8
  9/*	RESET0					*/
 10#define RESET_HIU			0
 11#define RESET_VLD			1
 12#define RESET_IQIDCT			2
 13#define RESET_MC			3
 14/*					8	*/
 15#define RESET_VIU			5
 16#define RESET_AIU			6
 17#define RESET_MCPU			7
 18#define RESET_CCPU			8
 19#define RESET_PMUX			9
 20#define RESET_VENC			10
 21#define RESET_ASSIST			11
 22#define RESET_AFIFO2			12
 23#define RESET_MDEC			13
 24#define RESET_VLD_PART			14
 25#define RESET_VIFIFO			15
 26/*					16-31	*/
 27/*	RESET1					*/
 28/*					32	*/
 29#define RESET_DEMUX			33
 30#define RESET_USB_OTG			34
 31#define RESET_DDR			35
 32#define RESET_VDAC_1			36
 33#define RESET_BT656			37
 34#define RESET_AHB_SRAM			38
 35#define RESET_AHB_BRIDGE		39
 36#define RESET_PARSER			40
 37#define RESET_BLKMV			41
 38#define RESET_ISA			42
 39#define RESET_ETHERNET			43
 40#define RESET_ABUF			44
 41#define RESET_AHB_DATA			45
 42#define RESET_AHB_CNTL			46
 43#define RESET_ROM_BOOT			47
 44/*					48-63	*/
 45/*	RESET2					*/
 46#define RESET_VD_RMEM			64
 47#define RESET_AUDIN			65
 48#define RESET_DBLK			66
 49#define RESET_PIC_DC			67
 50#define RESET_PSC			68
 51#define RESET_NAND			69
 52#define RESET_GE2D			70
 53#define RESET_PARSER_REG		71
 54#define RESET_PARSER_FETCH		72
 55#define RESET_PARSER_CTL		73
 56#define RESET_PARSER_TOP		74
 57#define RESET_HDMI_APB			75
 58#define RESET_AUDIO_APB			76
 59#define RESET_MEDIA_CPU			77
 60#define RESET_MALI			78
 61#define RESET_HDMI_SYSTEM_RESET		79
 62/*					80-95	*/
 63/*	RESET3					*/
 64#define RESET_RING_OSCILLATOR		96
 65#define RESET_SYS_CPU_0			97
 66#define RESET_EFUSE			98
 67#define RESET_SYS_CPU_BVCI		99
 68#define RESET_AIFIFO			100
 69#define RESET_AUDIO_PLL_MODULATOR	101
 70#define RESET_AHB_BRIDGE_CNTL		102
 71#define RESET_SYS_CPU_1			103
 72#define RESET_AUDIO_DAC			104
 73#define RESET_DEMUX_TOP			105
 74#define RESET_DEMUX_DES			106
 75#define RESET_DEMUX_S2P_0		107
 76#define RESET_DEMUX_S2P_1		108
 77#define RESET_DEMUX_RESET_0		109
 78#define RESET_DEMUX_RESET_1		110
 79#define RESET_DEMUX_RESET_2		111
 80/*					112-127	*/
 81/*	RESET4					*/
 82#define RESET_PL310			128
 83#define RESET_A5_APB			129
 84#define RESET_A5_AXI			130
 85#define RESET_A5			131
 86#define RESET_DVIN			132
 87#define RESET_RDMA			133
 88#define RESET_VENCI			134
 89#define RESET_VENCP			135
 90#define RESET_VENCT			136
 91#define RESET_VDAC_4			137
 92#define RESET_RTC			138
 93#define RESET_A5_DEBUG			139
 94#define RESET_VDI6			140
 95#define RESET_VENCL			141
 96/*					142-159	*/
 97/*	RESET5					*/
 98#define RESET_DDR_PLL			160
 99#define RESET_MISC_PLL			161
100#define RESET_SYS_PLL			162
101#define RESET_HPLL_PLL			163
102#define RESET_AUDIO_PLL			164
103#define RESET_VID2_PLL			165
104/*					166-191	*/
105/*	RESET6					*/
106#define RESET_PERIPHS_GENERAL		192
107#define RESET_PERIPHS_IR_REMOTE		193
108#define RESET_PERIPHS_SMART_CARD	194
109#define RESET_PERIPHS_SAR_ADC		195
110#define RESET_PERIPHS_I2C_MASTER_0	196
111#define RESET_PERIPHS_I2C_MASTER_1	197
112#define RESET_PERIPHS_I2C_SLAVE		198
113#define RESET_PERIPHS_STREAM_INTERFACE	199
114#define RESET_PERIPHS_SDIO		200
115#define RESET_PERIPHS_UART_0		201
116#define RESET_PERIPHS_UART_1		202
117#define RESET_PERIPHS_ASYNC_0		203
118#define RESET_PERIPHS_ASYNC_1		204
119#define RESET_PERIPHS_SPI_0		205
120#define RESET_PERIPHS_SPI_1		206
121#define RESET_PERIPHS_LED_PWM		207
122/*					208-223	*/
123/*	RESET7					*/
124/*					224-255	*/
125
126#endif