1/* vi: ts=8 sw=8
  2 *
  3 * TI 3410/5052 USB Serial Driver Header
  4 *
  5 * Copyright (C) 2004 Texas Instruments
  6 *
  7 * This driver is based on the Linux io_ti driver, which is
  8 *   Copyright (C) 2000-2002 Inside Out Networks
  9 *   Copyright (C) 2001-2002 Greg Kroah-Hartman
 10 *
 11 * This program is free software; you can redistribute it and/or modify
 12 * it under the terms of the GNU General Public License as published by
 13 * the Free Software Foundation; either version 2 of the License, or
 14 * (at your option) any later version.
 15 *
 16 * For questions or problems with this driver, contact Texas Instruments
 17 * technical support, or Al Borchers <alborchers@steinerpoint.com>, or
 18 * Peter Berger <pberger@brimson.com>.
 19 */
 20
 21#ifndef _TI_3410_5052_H_
 22#define _TI_3410_5052_H_
 23
 24/* Configuration ids */
 25#define TI_BOOT_CONFIG			1
 26#define TI_ACTIVE_CONFIG		2
 27
 28/* Vendor and product ids */
 29#define TI_VENDOR_ID			0x0451
 30#define IBM_VENDOR_ID			0x04b3
 31#define TI_3410_PRODUCT_ID		0x3410
 32#define IBM_4543_PRODUCT_ID		0x4543
 33#define IBM_454B_PRODUCT_ID		0x454b
 34#define IBM_454C_PRODUCT_ID		0x454c
 35#define TI_3410_EZ430_ID		0xF430  /* TI ez430 development tool */
 36#define TI_5052_BOOT_PRODUCT_ID		0x5052	/* no EEPROM, no firmware */
 37#define TI_5152_BOOT_PRODUCT_ID		0x5152	/* no EEPROM, no firmware */
 38#define TI_5052_EEPROM_PRODUCT_ID	0x505A	/* EEPROM, no firmware */
 39#define TI_5052_FIRMWARE_PRODUCT_ID	0x505F	/* firmware is running */
 40#define FRI2_PRODUCT_ID			0x5053  /* Fish River Island II */
 41
 42/* Multi-Tech vendor and product ids */
 43#define MTS_VENDOR_ID			0x06E0
 44#define MTS_GSM_NO_FW_PRODUCT_ID	0xF108
 45#define MTS_CDMA_NO_FW_PRODUCT_ID	0xF109
 46#define MTS_CDMA_PRODUCT_ID		0xF110
 47#define MTS_GSM_PRODUCT_ID		0xF111
 48#define MTS_EDGE_PRODUCT_ID		0xF112
 49#define MTS_MT9234MU_PRODUCT_ID		0xF114
 50#define MTS_MT9234ZBA_PRODUCT_ID	0xF115
 51#define MTS_MT9234ZBAOLD_PRODUCT_ID	0x0319
 52
 53/* Abbott Diabetics vendor and product ids */
 54#define ABBOTT_VENDOR_ID		0x1a61
 55#define ABBOTT_STEREO_PLUG_ID		0x3410
 56#define ABBOTT_PRODUCT_ID		ABBOTT_STEREO_PLUG_ID
 57#define ABBOTT_STRIP_PORT_ID		0x3420
 58
 59/* Honeywell vendor and product IDs */
 60#define HONEYWELL_VENDOR_ID		0x10ac
 61#define HONEYWELL_HGI80_PRODUCT_ID	0x0102  /* Honeywell HGI80 */
 62
 63/* Commands */
 64#define TI_GET_VERSION			0x01
 65#define TI_GET_PORT_STATUS		0x02
 66#define TI_GET_PORT_DEV_INFO		0x03
 67#define TI_GET_CONFIG			0x04
 68#define TI_SET_CONFIG			0x05
 69#define TI_OPEN_PORT			0x06
 70#define TI_CLOSE_PORT			0x07
 71#define TI_START_PORT			0x08
 72#define TI_STOP_PORT			0x09
 73#define TI_TEST_PORT			0x0A
 74#define TI_PURGE_PORT			0x0B
 75#define TI_RESET_EXT_DEVICE		0x0C
 76#define TI_WRITE_DATA			0x80
 77#define TI_READ_DATA			0x81
 78#define TI_REQ_TYPE_CLASS		0x82
 79
 80/* Module identifiers */
 81#define TI_I2C_PORT			0x01
 82#define TI_IEEE1284_PORT		0x02
 83#define TI_UART1_PORT			0x03
 84#define TI_UART2_PORT			0x04
 85#define TI_RAM_PORT			0x05
 86
 87/* Modem status */
 88#define TI_MSR_DELTA_CTS		0x01
 89#define TI_MSR_DELTA_DSR		0x02
 90#define TI_MSR_DELTA_RI			0x04
 91#define TI_MSR_DELTA_CD			0x08
 92#define TI_MSR_CTS			0x10
 93#define TI_MSR_DSR			0x20
 94#define TI_MSR_RI			0x40
 95#define TI_MSR_CD			0x80
 96#define TI_MSR_DELTA_MASK		0x0F
 97#define TI_MSR_MASK			0xF0
 98
 99/* Line status */
100#define TI_LSR_OVERRUN_ERROR		0x01
101#define TI_LSR_PARITY_ERROR		0x02
102#define TI_LSR_FRAMING_ERROR		0x04
103#define TI_LSR_BREAK			0x08
104#define TI_LSR_ERROR			0x0F
105#define TI_LSR_RX_FULL			0x10
106#define TI_LSR_TX_EMPTY			0x20
107
108/* Line control */
109#define TI_LCR_BREAK			0x40
110
111/* Modem control */
112#define TI_MCR_LOOP			0x04
113#define TI_MCR_DTR			0x10
114#define TI_MCR_RTS			0x20
115
116/* Mask settings */
117#define TI_UART_ENABLE_RTS_IN		0x0001
118#define TI_UART_DISABLE_RTS		0x0002
119#define TI_UART_ENABLE_PARITY_CHECKING	0x0008
120#define TI_UART_ENABLE_DSR_OUT		0x0010
121#define TI_UART_ENABLE_CTS_OUT		0x0020
122#define TI_UART_ENABLE_X_OUT		0x0040
123#define TI_UART_ENABLE_XA_OUT		0x0080
124#define TI_UART_ENABLE_X_IN		0x0100
125#define TI_UART_ENABLE_DTR_IN		0x0800
126#define TI_UART_DISABLE_DTR		0x1000
127#define TI_UART_ENABLE_MS_INTS		0x2000
128#define TI_UART_ENABLE_AUTO_START_DMA	0x4000
129
130/* Parity */
131#define TI_UART_NO_PARITY		0x00
132#define TI_UART_ODD_PARITY		0x01
133#define TI_UART_EVEN_PARITY		0x02
134#define TI_UART_MARK_PARITY		0x03
135#define TI_UART_SPACE_PARITY		0x04
136
137/* Stop bits */
138#define TI_UART_1_STOP_BITS		0x00
139#define TI_UART_1_5_STOP_BITS		0x01
140#define TI_UART_2_STOP_BITS		0x02
141
142/* Bits per character */
143#define TI_UART_5_DATA_BITS		0x00
144#define TI_UART_6_DATA_BITS		0x01
145#define TI_UART_7_DATA_BITS		0x02
146#define TI_UART_8_DATA_BITS		0x03
147
148/* 232/485 modes */
149#define TI_UART_232			0x00
150#define TI_UART_485_RECEIVER_DISABLED	0x01
151#define TI_UART_485_RECEIVER_ENABLED	0x02
152
153/* Pipe transfer mode and timeout */
154#define TI_PIPE_MODE_CONTINOUS		0x01
155#define TI_PIPE_MODE_MASK		0x03
156#define TI_PIPE_TIMEOUT_MASK		0x7C
157#define TI_PIPE_TIMEOUT_ENABLE		0x80
158
159/* Config struct */
160struct ti_uart_config {
161	__u16	wBaudRate;
162	__u16	wFlags;
163	__u8	bDataBits;
164	__u8	bParity;
165	__u8	bStopBits;
166	char	cXon;
167	char	cXoff;
168	__u8	bUartMode;
169} __attribute__((packed));
170
171/* Get port status */
172struct ti_port_status {
173	__u8	bCmdCode;
174	__u8	bModuleId;
175	__u8	bErrorCode;
176	__u8	bMSR;
177	__u8	bLSR;
178} __attribute__((packed));
179
180/* Purge modes */
181#define TI_PURGE_OUTPUT			0x00
182#define TI_PURGE_INPUT			0x80
183
184/* Read/Write data */
185#define TI_RW_DATA_ADDR_SFR		0x10
186#define TI_RW_DATA_ADDR_IDATA		0x20
187#define TI_RW_DATA_ADDR_XDATA		0x30
188#define TI_RW_DATA_ADDR_CODE		0x40
189#define TI_RW_DATA_ADDR_GPIO		0x50
190#define TI_RW_DATA_ADDR_I2C		0x60
191#define TI_RW_DATA_ADDR_FLASH		0x70
192#define TI_RW_DATA_ADDR_DSP		0x80
193
194#define TI_RW_DATA_UNSPECIFIED		0x00
195#define TI_RW_DATA_BYTE			0x01
196#define TI_RW_DATA_WORD			0x02
197#define TI_RW_DATA_DOUBLE_WORD		0x04
198
199struct ti_write_data_bytes {
200	__u8	bAddrType;
201	__u8	bDataType;
202	__u8	bDataCounter;
203	__be16	wBaseAddrHi;
204	__be16	wBaseAddrLo;
205	__u8	bData[0];
206} __attribute__((packed));
207
208struct ti_read_data_request {
209	__u8	bAddrType;
210	__u8	bDataType;
211	__u8	bDataCounter;
212	__be16	wBaseAddrHi;
213	__be16	wBaseAddrLo;
214} __attribute__((packed));
215
216struct ti_read_data_bytes {
217	__u8	bCmdCode;
218	__u8	bModuleId;
219	__u8	bErrorCode;
220	__u8	bData[0];
221} __attribute__((packed));
222
223/* Interrupt struct */
224struct ti_interrupt {
225	__u8	bICode;
226	__u8	bIInfo;
227} __attribute__((packed));
228
229/* Interrupt codes */
230#define TI_GET_PORT_FROM_CODE(c)	(((c) >> 4) - 3)
231#define TI_GET_FUNC_FROM_CODE(c)	((c) & 0x0f)
232#define TI_CODE_HARDWARE_ERROR		0xFF
233#define TI_CODE_DATA_ERROR		0x03
234#define TI_CODE_MODEM_STATUS		0x04
235
236/* Download firmware max packet size */
237#define TI_DOWNLOAD_MAX_PACKET_SIZE	64
238
239/* Firmware image header */
240struct ti_firmware_header {
241	__le16	wLength;
242	__u8	bCheckSum;
243} __attribute__((packed));
244
245/* UART addresses */
246#define TI_UART1_BASE_ADDR		0xFFA0	/* UART 1 base address */
247#define TI_UART2_BASE_ADDR		0xFFB0	/* UART 2 base address */
248#define TI_UART_OFFSET_LCR		0x0002	/* UART MCR register offset */
249#define TI_UART_OFFSET_MCR		0x0004	/* UART MCR register offset */
250
251#endif /* _TI_3410_5052_H_ */