Loading...
1/*
2 * MediaTek xHCI Host Controller Driver
3 *
4 * Copyright (c) 2015 MediaTek Inc.
5 * Author:
6 * Chunfeng Yun <chunfeng.yun@mediatek.com>
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 */
18
19#include <linux/clk.h>
20#include <linux/dma-mapping.h>
21#include <linux/iopoll.h>
22#include <linux/kernel.h>
23#include <linux/mfd/syscon.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/phy/phy.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/regmap.h>
30#include <linux/regulator/consumer.h>
31
32#include "xhci.h"
33#include "xhci-mtk.h"
34
35/* ip_pw_ctrl0 register */
36#define CTRL0_IP_SW_RST BIT(0)
37
38/* ip_pw_ctrl1 register */
39#define CTRL1_IP_HOST_PDN BIT(0)
40
41/* ip_pw_ctrl2 register */
42#define CTRL2_IP_DEV_PDN BIT(0)
43
44/* ip_pw_sts1 register */
45#define STS1_IP_SLEEP_STS BIT(30)
46#define STS1_XHCI_RST BIT(11)
47#define STS1_SYS125_RST BIT(10)
48#define STS1_REF_RST BIT(8)
49#define STS1_SYSPLL_STABLE BIT(0)
50
51/* ip_xhci_cap register */
52#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
53#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
54
55/* u3_ctrl_p register */
56#define CTRL_U3_PORT_HOST_SEL BIT(2)
57#define CTRL_U3_PORT_PDN BIT(1)
58#define CTRL_U3_PORT_DIS BIT(0)
59
60/* u2_ctrl_p register */
61#define CTRL_U2_PORT_HOST_SEL BIT(2)
62#define CTRL_U2_PORT_PDN BIT(1)
63#define CTRL_U2_PORT_DIS BIT(0)
64
65/* u2_phy_pll register */
66#define CTRL_U2_FORCE_PLL_STB BIT(28)
67
68#define PERI_WK_CTRL0 0x400
69#define UWK_CTR0_0P_LS_PE BIT(8) /* posedge */
70#define UWK_CTR0_0P_LS_NE BIT(7) /* negedge for 0p linestate*/
71#define UWK_CTL1_1P_LS_C(x) (((x) & 0xf) << 1)
72#define UWK_CTL1_1P_LS_E BIT(0)
73
74#define PERI_WK_CTRL1 0x404
75#define UWK_CTL1_IS_C(x) (((x) & 0xf) << 26)
76#define UWK_CTL1_IS_E BIT(25)
77#define UWK_CTL1_0P_LS_C(x) (((x) & 0xf) << 21)
78#define UWK_CTL1_0P_LS_E BIT(20)
79#define UWK_CTL1_IDDIG_C(x) (((x) & 0xf) << 11) /* cycle debounce */
80#define UWK_CTL1_IDDIG_E BIT(10) /* enable debounce */
81#define UWK_CTL1_IDDIG_P BIT(9) /* polarity */
82#define UWK_CTL1_0P_LS_P BIT(7)
83#define UWK_CTL1_IS_P BIT(6) /* polarity for ip sleep */
84
85enum ssusb_wakeup_src {
86 SSUSB_WK_IP_SLEEP = 1,
87 SSUSB_WK_LINE_STATE = 2,
88};
89
90static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
91{
92 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
93 u32 value, check_val;
94 int ret;
95 int i;
96
97 /* power on host ip */
98 value = readl(&ippc->ip_pw_ctr1);
99 value &= ~CTRL1_IP_HOST_PDN;
100 writel(value, &ippc->ip_pw_ctr1);
101
102 /* power on and enable all u3 ports */
103 for (i = 0; i < mtk->num_u3_ports; i++) {
104 value = readl(&ippc->u3_ctrl_p[i]);
105 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
106 value |= CTRL_U3_PORT_HOST_SEL;
107 writel(value, &ippc->u3_ctrl_p[i]);
108 }
109
110 /* power on and enable all u2 ports */
111 for (i = 0; i < mtk->num_u2_ports; i++) {
112 value = readl(&ippc->u2_ctrl_p[i]);
113 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
114 value |= CTRL_U2_PORT_HOST_SEL;
115 writel(value, &ippc->u2_ctrl_p[i]);
116 }
117
118 /*
119 * wait for clocks to be stable, and clock domains reset to
120 * be inactive after power on and enable ports
121 */
122 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
123 STS1_SYS125_RST | STS1_XHCI_RST;
124
125 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
126 (check_val == (value & check_val)), 100, 20000);
127 if (ret) {
128 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
129 return ret;
130 }
131
132 return 0;
133}
134
135static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
136{
137 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
138 u32 value;
139 int ret;
140 int i;
141
142 /* power down all u3 ports */
143 for (i = 0; i < mtk->num_u3_ports; i++) {
144 value = readl(&ippc->u3_ctrl_p[i]);
145 value |= CTRL_U3_PORT_PDN;
146 writel(value, &ippc->u3_ctrl_p[i]);
147 }
148
149 /* power down all u2 ports */
150 for (i = 0; i < mtk->num_u2_ports; i++) {
151 value = readl(&ippc->u2_ctrl_p[i]);
152 value |= CTRL_U2_PORT_PDN;
153 writel(value, &ippc->u2_ctrl_p[i]);
154 }
155
156 /* power down host ip */
157 value = readl(&ippc->ip_pw_ctr1);
158 value |= CTRL1_IP_HOST_PDN;
159 writel(value, &ippc->ip_pw_ctr1);
160
161 /* wait for host ip to sleep */
162 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
163 (value & STS1_IP_SLEEP_STS), 100, 100000);
164 if (ret) {
165 dev_err(mtk->dev, "ip sleep failed!!!\n");
166 return ret;
167 }
168 return 0;
169}
170
171static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
172{
173 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
174 u32 value;
175
176 /* reset whole ip */
177 value = readl(&ippc->ip_pw_ctr0);
178 value |= CTRL0_IP_SW_RST;
179 writel(value, &ippc->ip_pw_ctr0);
180 udelay(1);
181 value = readl(&ippc->ip_pw_ctr0);
182 value &= ~CTRL0_IP_SW_RST;
183 writel(value, &ippc->ip_pw_ctr0);
184
185 /*
186 * device ip is default power-on in fact
187 * power down device ip, otherwise ip-sleep will fail
188 */
189 value = readl(&ippc->ip_pw_ctr2);
190 value |= CTRL2_IP_DEV_PDN;
191 writel(value, &ippc->ip_pw_ctr2);
192
193 value = readl(&ippc->ip_xhci_cap);
194 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
195 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
196 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
197 mtk->num_u2_ports, mtk->num_u3_ports);
198
199 return xhci_mtk_host_enable(mtk);
200}
201
202static int xhci_mtk_clks_enable(struct xhci_hcd_mtk *mtk)
203{
204 int ret;
205
206 ret = clk_prepare_enable(mtk->sys_clk);
207 if (ret) {
208 dev_err(mtk->dev, "failed to enable sys_clk\n");
209 goto sys_clk_err;
210 }
211
212 if (mtk->wakeup_src) {
213 ret = clk_prepare_enable(mtk->wk_deb_p0);
214 if (ret) {
215 dev_err(mtk->dev, "failed to enable wk_deb_p0\n");
216 goto usb_p0_err;
217 }
218
219 ret = clk_prepare_enable(mtk->wk_deb_p1);
220 if (ret) {
221 dev_err(mtk->dev, "failed to enable wk_deb_p1\n");
222 goto usb_p1_err;
223 }
224 }
225 return 0;
226
227usb_p1_err:
228 clk_disable_unprepare(mtk->wk_deb_p0);
229usb_p0_err:
230 clk_disable_unprepare(mtk->sys_clk);
231sys_clk_err:
232 return -EINVAL;
233}
234
235static void xhci_mtk_clks_disable(struct xhci_hcd_mtk *mtk)
236{
237 if (mtk->wakeup_src) {
238 clk_disable_unprepare(mtk->wk_deb_p1);
239 clk_disable_unprepare(mtk->wk_deb_p0);
240 }
241 clk_disable_unprepare(mtk->sys_clk);
242}
243
244/* only clocks can be turn off for ip-sleep wakeup mode */
245static void usb_wakeup_ip_sleep_en(struct xhci_hcd_mtk *mtk)
246{
247 u32 tmp;
248 struct regmap *pericfg = mtk->pericfg;
249
250 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
251 tmp &= ~UWK_CTL1_IS_P;
252 tmp &= ~(UWK_CTL1_IS_C(0xf));
253 tmp |= UWK_CTL1_IS_C(0x8);
254 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
255 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_IS_E);
256
257 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
258 dev_dbg(mtk->dev, "%s(): WK_CTRL1[P6,E25,C26:29]=%#x\n",
259 __func__, tmp);
260}
261
262static void usb_wakeup_ip_sleep_dis(struct xhci_hcd_mtk *mtk)
263{
264 u32 tmp;
265
266 regmap_read(mtk->pericfg, PERI_WK_CTRL1, &tmp);
267 tmp &= ~UWK_CTL1_IS_E;
268 regmap_write(mtk->pericfg, PERI_WK_CTRL1, tmp);
269}
270
271/*
272* for line-state wakeup mode, phy's power should not power-down
273* and only support cable plug in/out
274*/
275static void usb_wakeup_line_state_en(struct xhci_hcd_mtk *mtk)
276{
277 u32 tmp;
278 struct regmap *pericfg = mtk->pericfg;
279
280 /* line-state of u2-port0 */
281 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
282 tmp &= ~UWK_CTL1_0P_LS_P;
283 tmp &= ~(UWK_CTL1_0P_LS_C(0xf));
284 tmp |= UWK_CTL1_0P_LS_C(0x8);
285 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
286 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
287 regmap_write(pericfg, PERI_WK_CTRL1, tmp | UWK_CTL1_0P_LS_E);
288
289 /* line-state of u2-port1 */
290 regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
291 tmp &= ~(UWK_CTL1_1P_LS_C(0xf));
292 tmp |= UWK_CTL1_1P_LS_C(0x8);
293 regmap_write(pericfg, PERI_WK_CTRL0, tmp);
294 regmap_write(pericfg, PERI_WK_CTRL0, tmp | UWK_CTL1_1P_LS_E);
295}
296
297static void usb_wakeup_line_state_dis(struct xhci_hcd_mtk *mtk)
298{
299 u32 tmp;
300 struct regmap *pericfg = mtk->pericfg;
301
302 /* line-state of u2-port0 */
303 regmap_read(pericfg, PERI_WK_CTRL1, &tmp);
304 tmp &= ~UWK_CTL1_0P_LS_E;
305 regmap_write(pericfg, PERI_WK_CTRL1, tmp);
306
307 /* line-state of u2-port1 */
308 regmap_read(pericfg, PERI_WK_CTRL0, &tmp);
309 tmp &= ~UWK_CTL1_1P_LS_E;
310 regmap_write(pericfg, PERI_WK_CTRL0, tmp);
311}
312
313static void usb_wakeup_enable(struct xhci_hcd_mtk *mtk)
314{
315 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
316 usb_wakeup_ip_sleep_en(mtk);
317 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
318 usb_wakeup_line_state_en(mtk);
319}
320
321static void usb_wakeup_disable(struct xhci_hcd_mtk *mtk)
322{
323 if (mtk->wakeup_src == SSUSB_WK_IP_SLEEP)
324 usb_wakeup_ip_sleep_dis(mtk);
325 else if (mtk->wakeup_src == SSUSB_WK_LINE_STATE)
326 usb_wakeup_line_state_dis(mtk);
327}
328
329static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
330 struct device_node *dn)
331{
332 struct device *dev = mtk->dev;
333
334 /*
335 * wakeup function is optional, so it is not an error if this property
336 * does not exist, and in such case, no need to get relative
337 * properties anymore.
338 */
339 of_property_read_u32(dn, "mediatek,wakeup-src", &mtk->wakeup_src);
340 if (!mtk->wakeup_src)
341 return 0;
342
343 mtk->wk_deb_p0 = devm_clk_get(dev, "wakeup_deb_p0");
344 if (IS_ERR(mtk->wk_deb_p0)) {
345 dev_err(dev, "fail to get wakeup_deb_p0\n");
346 return PTR_ERR(mtk->wk_deb_p0);
347 }
348
349 mtk->wk_deb_p1 = devm_clk_get(dev, "wakeup_deb_p1");
350 if (IS_ERR(mtk->wk_deb_p1)) {
351 dev_err(dev, "fail to get wakeup_deb_p1\n");
352 return PTR_ERR(mtk->wk_deb_p1);
353 }
354
355 mtk->pericfg = syscon_regmap_lookup_by_phandle(dn,
356 "mediatek,syscon-wakeup");
357 if (IS_ERR(mtk->pericfg)) {
358 dev_err(dev, "fail to get pericfg regs\n");
359 return PTR_ERR(mtk->pericfg);
360 }
361
362 return 0;
363}
364
365static int xhci_mtk_setup(struct usb_hcd *hcd);
366static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
367 .extra_priv_size = sizeof(struct xhci_hcd),
368 .reset = xhci_mtk_setup,
369};
370
371static struct hc_driver __read_mostly xhci_mtk_hc_driver;
372
373static int xhci_mtk_phy_init(struct xhci_hcd_mtk *mtk)
374{
375 int i;
376 int ret;
377
378 for (i = 0; i < mtk->num_phys; i++) {
379 ret = phy_init(mtk->phys[i]);
380 if (ret)
381 goto exit_phy;
382 }
383 return 0;
384
385exit_phy:
386 for (; i > 0; i--)
387 phy_exit(mtk->phys[i - 1]);
388
389 return ret;
390}
391
392static int xhci_mtk_phy_exit(struct xhci_hcd_mtk *mtk)
393{
394 int i;
395
396 for (i = 0; i < mtk->num_phys; i++)
397 phy_exit(mtk->phys[i]);
398
399 return 0;
400}
401
402static int xhci_mtk_phy_power_on(struct xhci_hcd_mtk *mtk)
403{
404 int i;
405 int ret;
406
407 for (i = 0; i < mtk->num_phys; i++) {
408 ret = phy_power_on(mtk->phys[i]);
409 if (ret)
410 goto power_off_phy;
411 }
412 return 0;
413
414power_off_phy:
415 for (; i > 0; i--)
416 phy_power_off(mtk->phys[i - 1]);
417
418 return ret;
419}
420
421static void xhci_mtk_phy_power_off(struct xhci_hcd_mtk *mtk)
422{
423 unsigned int i;
424
425 for (i = 0; i < mtk->num_phys; i++)
426 phy_power_off(mtk->phys[i]);
427}
428
429static int xhci_mtk_ldos_enable(struct xhci_hcd_mtk *mtk)
430{
431 int ret;
432
433 ret = regulator_enable(mtk->vbus);
434 if (ret) {
435 dev_err(mtk->dev, "failed to enable vbus\n");
436 return ret;
437 }
438
439 ret = regulator_enable(mtk->vusb33);
440 if (ret) {
441 dev_err(mtk->dev, "failed to enable vusb33\n");
442 regulator_disable(mtk->vbus);
443 return ret;
444 }
445 return 0;
446}
447
448static void xhci_mtk_ldos_disable(struct xhci_hcd_mtk *mtk)
449{
450 regulator_disable(mtk->vbus);
451 regulator_disable(mtk->vusb33);
452}
453
454static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
455{
456 struct usb_hcd *hcd = xhci_to_hcd(xhci);
457 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
458
459 /*
460 * As of now platform drivers don't provide MSI support so we ensure
461 * here that the generic code does not try to make a pci_dev from our
462 * dev struct in order to setup MSI
463 */
464 xhci->quirks |= XHCI_PLAT;
465 xhci->quirks |= XHCI_MTK_HOST;
466 /*
467 * MTK host controller gives a spurious successful event after a
468 * short transfer. Ignore it.
469 */
470 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
471 if (mtk->lpm_support)
472 xhci->quirks |= XHCI_LPM_SUPPORT;
473}
474
475/* called during probe() after chip reset completes */
476static int xhci_mtk_setup(struct usb_hcd *hcd)
477{
478 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
479 int ret;
480
481 if (usb_hcd_is_primary_hcd(hcd)) {
482 ret = xhci_mtk_ssusb_config(mtk);
483 if (ret)
484 return ret;
485 ret = xhci_mtk_sch_init(mtk);
486 if (ret)
487 return ret;
488 }
489
490 return xhci_gen_setup(hcd, xhci_mtk_quirks);
491}
492
493static int xhci_mtk_probe(struct platform_device *pdev)
494{
495 struct device *dev = &pdev->dev;
496 struct device_node *node = dev->of_node;
497 struct xhci_hcd_mtk *mtk;
498 const struct hc_driver *driver;
499 struct xhci_hcd *xhci;
500 struct resource *res;
501 struct usb_hcd *hcd;
502 struct phy *phy;
503 int phy_num;
504 int ret = -ENODEV;
505 int irq;
506
507 if (usb_disabled())
508 return -ENODEV;
509
510 driver = &xhci_mtk_hc_driver;
511 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
512 if (!mtk)
513 return -ENOMEM;
514
515 mtk->dev = dev;
516 mtk->vbus = devm_regulator_get(dev, "vbus");
517 if (IS_ERR(mtk->vbus)) {
518 dev_err(dev, "fail to get vbus\n");
519 return PTR_ERR(mtk->vbus);
520 }
521
522 mtk->vusb33 = devm_regulator_get(dev, "vusb33");
523 if (IS_ERR(mtk->vusb33)) {
524 dev_err(dev, "fail to get vusb33\n");
525 return PTR_ERR(mtk->vusb33);
526 }
527
528 mtk->sys_clk = devm_clk_get(dev, "sys_ck");
529 if (IS_ERR(mtk->sys_clk)) {
530 dev_err(dev, "fail to get sys_ck\n");
531 return PTR_ERR(mtk->sys_clk);
532 }
533
534 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
535
536 ret = usb_wakeup_of_property_parse(mtk, node);
537 if (ret)
538 return ret;
539
540 mtk->num_phys = of_count_phandle_with_args(node,
541 "phys", "#phy-cells");
542 if (mtk->num_phys > 0) {
543 mtk->phys = devm_kcalloc(dev, mtk->num_phys,
544 sizeof(*mtk->phys), GFP_KERNEL);
545 if (!mtk->phys)
546 return -ENOMEM;
547 } else {
548 mtk->num_phys = 0;
549 }
550 pm_runtime_enable(dev);
551 pm_runtime_get_sync(dev);
552 device_enable_async_suspend(dev);
553
554 ret = xhci_mtk_ldos_enable(mtk);
555 if (ret)
556 goto disable_pm;
557
558 ret = xhci_mtk_clks_enable(mtk);
559 if (ret)
560 goto disable_ldos;
561
562 irq = platform_get_irq(pdev, 0);
563 if (irq < 0)
564 goto disable_clk;
565
566 /* Initialize dma_mask and coherent_dma_mask to 32-bits */
567 ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
568 if (ret)
569 goto disable_clk;
570
571 if (!dev->dma_mask)
572 dev->dma_mask = &dev->coherent_dma_mask;
573 else
574 dma_set_mask(dev, DMA_BIT_MASK(32));
575
576 hcd = usb_create_hcd(driver, dev, dev_name(dev));
577 if (!hcd) {
578 ret = -ENOMEM;
579 goto disable_clk;
580 }
581
582 /*
583 * USB 2.0 roothub is stored in the platform_device.
584 * Swap it with mtk HCD.
585 */
586 mtk->hcd = platform_get_drvdata(pdev);
587 platform_set_drvdata(pdev, mtk);
588
589 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
590 hcd->regs = devm_ioremap_resource(dev, res);
591 if (IS_ERR(hcd->regs)) {
592 ret = PTR_ERR(hcd->regs);
593 goto put_usb2_hcd;
594 }
595 hcd->rsrc_start = res->start;
596 hcd->rsrc_len = resource_size(res);
597
598 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
599 mtk->ippc_regs = devm_ioremap_resource(dev, res);
600 if (IS_ERR(mtk->ippc_regs)) {
601 ret = PTR_ERR(mtk->ippc_regs);
602 goto put_usb2_hcd;
603 }
604
605 for (phy_num = 0; phy_num < mtk->num_phys; phy_num++) {
606 phy = devm_of_phy_get_by_index(dev, node, phy_num);
607 if (IS_ERR(phy)) {
608 ret = PTR_ERR(phy);
609 goto put_usb2_hcd;
610 }
611 mtk->phys[phy_num] = phy;
612 }
613
614 ret = xhci_mtk_phy_init(mtk);
615 if (ret)
616 goto put_usb2_hcd;
617
618 ret = xhci_mtk_phy_power_on(mtk);
619 if (ret)
620 goto exit_phys;
621
622 device_init_wakeup(dev, true);
623
624 xhci = hcd_to_xhci(hcd);
625 xhci->main_hcd = hcd;
626 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
627 dev_name(dev), hcd);
628 if (!xhci->shared_hcd) {
629 ret = -ENOMEM;
630 goto power_off_phys;
631 }
632
633 if (HCC_MAX_PSA(xhci->hcc_params) >= 4)
634 xhci->shared_hcd->can_do_streams = 1;
635
636 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
637 if (ret)
638 goto put_usb3_hcd;
639
640 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
641 if (ret)
642 goto dealloc_usb2_hcd;
643
644 return 0;
645
646dealloc_usb2_hcd:
647 usb_remove_hcd(hcd);
648
649put_usb3_hcd:
650 xhci_mtk_sch_exit(mtk);
651 usb_put_hcd(xhci->shared_hcd);
652
653power_off_phys:
654 xhci_mtk_phy_power_off(mtk);
655 device_init_wakeup(dev, false);
656
657exit_phys:
658 xhci_mtk_phy_exit(mtk);
659
660put_usb2_hcd:
661 usb_put_hcd(hcd);
662
663disable_clk:
664 xhci_mtk_clks_disable(mtk);
665
666disable_ldos:
667 xhci_mtk_ldos_disable(mtk);
668
669disable_pm:
670 pm_runtime_put_sync(dev);
671 pm_runtime_disable(dev);
672 return ret;
673}
674
675static int xhci_mtk_remove(struct platform_device *dev)
676{
677 struct xhci_hcd_mtk *mtk = platform_get_drvdata(dev);
678 struct usb_hcd *hcd = mtk->hcd;
679 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
680
681 usb_remove_hcd(xhci->shared_hcd);
682 xhci_mtk_phy_power_off(mtk);
683 xhci_mtk_phy_exit(mtk);
684 device_init_wakeup(&dev->dev, false);
685
686 usb_remove_hcd(hcd);
687 usb_put_hcd(xhci->shared_hcd);
688 usb_put_hcd(hcd);
689 xhci_mtk_sch_exit(mtk);
690 xhci_mtk_clks_disable(mtk);
691 xhci_mtk_ldos_disable(mtk);
692 pm_runtime_put_sync(&dev->dev);
693 pm_runtime_disable(&dev->dev);
694
695 return 0;
696}
697
698/*
699 * if ip sleep fails, and all clocks are disabled, access register will hang
700 * AHB bus, so stop polling roothubs to avoid regs access on bus suspend.
701 * and no need to check whether ip sleep failed or not; this will cause SPM
702 * to wake up system immediately after system suspend complete if ip sleep
703 * fails, it is what we wanted.
704 */
705static int __maybe_unused xhci_mtk_suspend(struct device *dev)
706{
707 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
708 struct usb_hcd *hcd = mtk->hcd;
709 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
710
711 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
712 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
713 del_timer_sync(&hcd->rh_timer);
714 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
715 del_timer_sync(&xhci->shared_hcd->rh_timer);
716
717 xhci_mtk_host_disable(mtk);
718 xhci_mtk_phy_power_off(mtk);
719 xhci_mtk_clks_disable(mtk);
720 usb_wakeup_enable(mtk);
721 return 0;
722}
723
724static int __maybe_unused xhci_mtk_resume(struct device *dev)
725{
726 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
727 struct usb_hcd *hcd = mtk->hcd;
728 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
729
730 usb_wakeup_disable(mtk);
731 xhci_mtk_clks_enable(mtk);
732 xhci_mtk_phy_power_on(mtk);
733 xhci_mtk_host_enable(mtk);
734
735 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
736 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
737 usb_hcd_poll_rh_status(hcd);
738 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
739 usb_hcd_poll_rh_status(xhci->shared_hcd);
740 return 0;
741}
742
743static const struct dev_pm_ops xhci_mtk_pm_ops = {
744 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
745};
746#define DEV_PM_OPS IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL
747
748#ifdef CONFIG_OF
749static const struct of_device_id mtk_xhci_of_match[] = {
750 { .compatible = "mediatek,mt8173-xhci"},
751 { },
752};
753MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
754#endif
755
756static struct platform_driver mtk_xhci_driver = {
757 .probe = xhci_mtk_probe,
758 .remove = xhci_mtk_remove,
759 .driver = {
760 .name = "xhci-mtk",
761 .pm = DEV_PM_OPS,
762 .of_match_table = of_match_ptr(mtk_xhci_of_match),
763 },
764};
765MODULE_ALIAS("platform:xhci-mtk");
766
767static int __init xhci_mtk_init(void)
768{
769 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
770 return platform_driver_register(&mtk_xhci_driver);
771}
772module_init(xhci_mtk_init);
773
774static void __exit xhci_mtk_exit(void)
775{
776 platform_driver_unregister(&mtk_xhci_driver);
777}
778module_exit(xhci_mtk_exit);
779
780MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
781MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
782MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MediaTek xHCI Host Controller Driver
4 *
5 * Copyright (c) 2015 MediaTek Inc.
6 * Author:
7 * Chunfeng Yun <chunfeng.yun@mediatek.com>
8 */
9
10#include <linux/dma-mapping.h>
11#include <linux/iopoll.h>
12#include <linux/kernel.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/pm_wakeirq.h>
19#include <linux/regmap.h>
20#include <linux/regulator/consumer.h>
21#include <linux/reset.h>
22
23#include "xhci.h"
24#include "xhci-mtk.h"
25
26/* ip_pw_ctrl0 register */
27#define CTRL0_IP_SW_RST BIT(0)
28
29/* ip_pw_ctrl1 register */
30#define CTRL1_IP_HOST_PDN BIT(0)
31
32/* ip_pw_ctrl2 register */
33#define CTRL2_IP_DEV_PDN BIT(0)
34
35/* ip_pw_sts1 register */
36#define STS1_IP_SLEEP_STS BIT(30)
37#define STS1_U3_MAC_RST BIT(16)
38#define STS1_XHCI_RST BIT(11)
39#define STS1_SYS125_RST BIT(10)
40#define STS1_REF_RST BIT(8)
41#define STS1_SYSPLL_STABLE BIT(0)
42
43/* ip_xhci_cap register */
44#define CAP_U3_PORT_NUM(p) ((p) & 0xff)
45#define CAP_U2_PORT_NUM(p) (((p) >> 8) & 0xff)
46
47/* u3_ctrl_p register */
48#define CTRL_U3_PORT_HOST_SEL BIT(2)
49#define CTRL_U3_PORT_PDN BIT(1)
50#define CTRL_U3_PORT_DIS BIT(0)
51
52/* u2_ctrl_p register */
53#define CTRL_U2_PORT_HOST_SEL BIT(2)
54#define CTRL_U2_PORT_PDN BIT(1)
55#define CTRL_U2_PORT_DIS BIT(0)
56
57/* u2_phy_pll register */
58#define CTRL_U2_FORCE_PLL_STB BIT(28)
59
60/* xHCI CSR */
61#define LS_EOF_CFG 0x930
62#define LSEOF_OFFSET 0x89
63
64#define FS_EOF_CFG 0x934
65#define FSEOF_OFFSET 0x2e
66
67#define SS_GEN1_EOF_CFG 0x93c
68#define SSG1EOF_OFFSET 0x78
69
70#define HFCNTR_CFG 0x944
71#define ITP_DELTA_CLK (0xa << 1)
72#define ITP_DELTA_CLK_MASK GENMASK(5, 1)
73#define FRMCNT_LEV1_RANG (0x12b << 8)
74#define FRMCNT_LEV1_RANG_MASK GENMASK(19, 8)
75
76#define SS_GEN2_EOF_CFG 0x990
77#define SSG2EOF_OFFSET 0x3c
78
79#define XSEOF_OFFSET_MASK GENMASK(11, 0)
80
81/* usb remote wakeup registers in syscon */
82
83/* mt8173 etc */
84#define PERI_WK_CTRL1 0x4
85#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
86#define WC1_IS_EN BIT(25)
87#define WC1_IS_P BIT(6) /* polarity for ip sleep */
88
89/* mt8183 */
90#define PERI_WK_CTRL0 0x0
91#define WC0_IS_C(x) ((u32)(((x) & 0xf) << 28)) /* cycle debounce */
92#define WC0_IS_P BIT(12) /* polarity */
93#define WC0_IS_EN BIT(6)
94
95/* mt8192 */
96#define WC0_SSUSB0_CDEN BIT(6)
97#define WC0_IS_SPM_EN BIT(1)
98
99/* mt8195 */
100#define PERI_WK_CTRL0_8195 0x04
101#define WC0_IS_P_95 BIT(30) /* polarity */
102#define WC0_IS_C_95(x) ((u32)(((x) & 0x7) << 27))
103#define WC0_IS_EN_P3_95 BIT(26)
104#define WC0_IS_EN_P2_95 BIT(25)
105#define WC0_IS_EN_P1_95 BIT(24)
106
107#define PERI_WK_CTRL1_8195 0x20
108#define WC1_IS_C_95(x) ((u32)(((x) & 0xf) << 28))
109#define WC1_IS_P_95 BIT(12)
110#define WC1_IS_EN_P0_95 BIT(6)
111
112/* mt2712 etc */
113#define PERI_SSUSB_SPM_CTRL 0x0
114#define SSC_IP_SLEEP_EN BIT(4)
115#define SSC_SPM_INT_EN BIT(1)
116
117enum ssusb_uwk_vers {
118 SSUSB_UWK_V1 = 1,
119 SSUSB_UWK_V2,
120 SSUSB_UWK_V1_1 = 101, /* specific revision 1.01 */
121 SSUSB_UWK_V1_2, /* specific revision 1.2 */
122 SSUSB_UWK_V1_3, /* mt8195 IP0 */
123 SSUSB_UWK_V1_4, /* mt8195 IP1 */
124 SSUSB_UWK_V1_5, /* mt8195 IP2 */
125 SSUSB_UWK_V1_6, /* mt8195 IP3 */
126};
127
128/*
129 * MT8195 has 4 controllers, the controller1~3's default SOF/ITP interval
130 * is calculated from the frame counter clock 24M, but in fact, the clock
131 * is 48M, add workaround for it.
132 */
133static void xhci_mtk_set_frame_interval(struct xhci_hcd_mtk *mtk)
134{
135 struct device *dev = mtk->dev;
136 struct usb_hcd *hcd = mtk->hcd;
137 u32 value;
138
139 if (!of_device_is_compatible(dev->of_node, "mediatek,mt8195-xhci"))
140 return;
141
142 value = readl(hcd->regs + HFCNTR_CFG);
143 value &= ~(ITP_DELTA_CLK_MASK | FRMCNT_LEV1_RANG_MASK);
144 value |= (ITP_DELTA_CLK | FRMCNT_LEV1_RANG);
145 writel(value, hcd->regs + HFCNTR_CFG);
146
147 value = readl(hcd->regs + LS_EOF_CFG);
148 value &= ~XSEOF_OFFSET_MASK;
149 value |= LSEOF_OFFSET;
150 writel(value, hcd->regs + LS_EOF_CFG);
151
152 value = readl(hcd->regs + FS_EOF_CFG);
153 value &= ~XSEOF_OFFSET_MASK;
154 value |= FSEOF_OFFSET;
155 writel(value, hcd->regs + FS_EOF_CFG);
156
157 value = readl(hcd->regs + SS_GEN1_EOF_CFG);
158 value &= ~XSEOF_OFFSET_MASK;
159 value |= SSG1EOF_OFFSET;
160 writel(value, hcd->regs + SS_GEN1_EOF_CFG);
161
162 value = readl(hcd->regs + SS_GEN2_EOF_CFG);
163 value &= ~XSEOF_OFFSET_MASK;
164 value |= SSG2EOF_OFFSET;
165 writel(value, hcd->regs + SS_GEN2_EOF_CFG);
166}
167
168static int xhci_mtk_host_enable(struct xhci_hcd_mtk *mtk)
169{
170 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
171 u32 value, check_val;
172 int u3_ports_disabled = 0;
173 int ret;
174 int i;
175
176 if (!mtk->has_ippc)
177 return 0;
178
179 /* power on host ip */
180 value = readl(&ippc->ip_pw_ctr1);
181 value &= ~CTRL1_IP_HOST_PDN;
182 writel(value, &ippc->ip_pw_ctr1);
183
184 /* power on and enable u3 ports except skipped ones */
185 for (i = 0; i < mtk->num_u3_ports; i++) {
186 if ((0x1 << i) & mtk->u3p_dis_msk) {
187 u3_ports_disabled++;
188 continue;
189 }
190
191 value = readl(&ippc->u3_ctrl_p[i]);
192 value &= ~(CTRL_U3_PORT_PDN | CTRL_U3_PORT_DIS);
193 value |= CTRL_U3_PORT_HOST_SEL;
194 writel(value, &ippc->u3_ctrl_p[i]);
195 }
196
197 /* power on and enable all u2 ports except skipped ones */
198 for (i = 0; i < mtk->num_u2_ports; i++) {
199 if (BIT(i) & mtk->u2p_dis_msk)
200 continue;
201
202 value = readl(&ippc->u2_ctrl_p[i]);
203 value &= ~(CTRL_U2_PORT_PDN | CTRL_U2_PORT_DIS);
204 value |= CTRL_U2_PORT_HOST_SEL;
205 writel(value, &ippc->u2_ctrl_p[i]);
206 }
207
208 /*
209 * wait for clocks to be stable, and clock domains reset to
210 * be inactive after power on and enable ports
211 */
212 check_val = STS1_SYSPLL_STABLE | STS1_REF_RST |
213 STS1_SYS125_RST | STS1_XHCI_RST;
214
215 if (mtk->num_u3_ports > u3_ports_disabled)
216 check_val |= STS1_U3_MAC_RST;
217
218 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
219 (check_val == (value & check_val)), 100, 20000);
220 if (ret) {
221 dev_err(mtk->dev, "clocks are not stable (0x%x)\n", value);
222 return ret;
223 }
224
225 return 0;
226}
227
228static int xhci_mtk_host_disable(struct xhci_hcd_mtk *mtk)
229{
230 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
231 u32 value;
232 int ret;
233 int i;
234
235 if (!mtk->has_ippc)
236 return 0;
237
238 /* power down u3 ports except skipped ones */
239 for (i = 0; i < mtk->num_u3_ports; i++) {
240 if ((0x1 << i) & mtk->u3p_dis_msk)
241 continue;
242
243 value = readl(&ippc->u3_ctrl_p[i]);
244 value |= CTRL_U3_PORT_PDN;
245 writel(value, &ippc->u3_ctrl_p[i]);
246 }
247
248 /* power down all u2 ports except skipped ones */
249 for (i = 0; i < mtk->num_u2_ports; i++) {
250 if (BIT(i) & mtk->u2p_dis_msk)
251 continue;
252
253 value = readl(&ippc->u2_ctrl_p[i]);
254 value |= CTRL_U2_PORT_PDN;
255 writel(value, &ippc->u2_ctrl_p[i]);
256 }
257
258 /* power down host ip */
259 value = readl(&ippc->ip_pw_ctr1);
260 value |= CTRL1_IP_HOST_PDN;
261 writel(value, &ippc->ip_pw_ctr1);
262
263 /* wait for host ip to sleep */
264 ret = readl_poll_timeout(&ippc->ip_pw_sts1, value,
265 (value & STS1_IP_SLEEP_STS), 100, 100000);
266 if (ret)
267 dev_err(mtk->dev, "ip sleep failed!!!\n");
268 else /* workaound for platforms using low level latch */
269 usleep_range(100, 200);
270
271 return ret;
272}
273
274static int xhci_mtk_ssusb_config(struct xhci_hcd_mtk *mtk)
275{
276 struct mu3c_ippc_regs __iomem *ippc = mtk->ippc_regs;
277 u32 value;
278
279 if (!mtk->has_ippc)
280 return 0;
281
282 /* reset whole ip */
283 value = readl(&ippc->ip_pw_ctr0);
284 value |= CTRL0_IP_SW_RST;
285 writel(value, &ippc->ip_pw_ctr0);
286 udelay(1);
287 value = readl(&ippc->ip_pw_ctr0);
288 value &= ~CTRL0_IP_SW_RST;
289 writel(value, &ippc->ip_pw_ctr0);
290
291 /*
292 * device ip is default power-on in fact
293 * power down device ip, otherwise ip-sleep will fail
294 */
295 value = readl(&ippc->ip_pw_ctr2);
296 value |= CTRL2_IP_DEV_PDN;
297 writel(value, &ippc->ip_pw_ctr2);
298
299 value = readl(&ippc->ip_xhci_cap);
300 mtk->num_u3_ports = CAP_U3_PORT_NUM(value);
301 mtk->num_u2_ports = CAP_U2_PORT_NUM(value);
302 dev_dbg(mtk->dev, "%s u2p:%d, u3p:%d\n", __func__,
303 mtk->num_u2_ports, mtk->num_u3_ports);
304
305 return xhci_mtk_host_enable(mtk);
306}
307
308/* only clocks can be turn off for ip-sleep wakeup mode */
309static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
310{
311 u32 reg, msk, val;
312
313 switch (mtk->uwk_vers) {
314 case SSUSB_UWK_V1:
315 reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
316 msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
317 val = enable ? (WC1_IS_EN | WC1_IS_C(0x8)) : 0;
318 break;
319 case SSUSB_UWK_V1_1:
320 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
321 msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
322 val = enable ? (WC0_IS_EN | WC0_IS_C(0x1)) : 0;
323 break;
324 case SSUSB_UWK_V1_2:
325 reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
326 msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
327 val = enable ? msk : 0;
328 break;
329 case SSUSB_UWK_V1_3:
330 reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
331 msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
332 val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
333 break;
334 case SSUSB_UWK_V1_4:
335 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
336 msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
337 val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
338 break;
339 case SSUSB_UWK_V1_5:
340 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
341 msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
342 val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
343 break;
344 case SSUSB_UWK_V1_6:
345 reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
346 msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
347 val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
348 break;
349 case SSUSB_UWK_V2:
350 reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
351 msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
352 val = enable ? msk : 0;
353 break;
354 default:
355 return;
356 }
357 regmap_update_bits(mtk->uwk, reg, msk, val);
358}
359
360static int usb_wakeup_of_property_parse(struct xhci_hcd_mtk *mtk,
361 struct device_node *dn)
362{
363 struct of_phandle_args args;
364 int ret;
365
366 /* Wakeup function is optional */
367 mtk->uwk_en = of_property_read_bool(dn, "wakeup-source");
368 if (!mtk->uwk_en)
369 return 0;
370
371 ret = of_parse_phandle_with_fixed_args(dn,
372 "mediatek,syscon-wakeup", 2, 0, &args);
373 if (ret)
374 return ret;
375
376 mtk->uwk_reg_base = args.args[0];
377 mtk->uwk_vers = args.args[1];
378 mtk->uwk = syscon_node_to_regmap(args.np);
379 of_node_put(args.np);
380 dev_info(mtk->dev, "uwk - reg:0x%x, version:%d\n",
381 mtk->uwk_reg_base, mtk->uwk_vers);
382
383 return PTR_ERR_OR_ZERO(mtk->uwk);
384}
385
386static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
387{
388 if (mtk->uwk_en)
389 usb_wakeup_ip_sleep_set(mtk, enable);
390}
391
392static int xhci_mtk_clks_get(struct xhci_hcd_mtk *mtk)
393{
394 struct clk_bulk_data *clks = mtk->clks;
395
396 clks[0].id = "sys_ck";
397 clks[1].id = "xhci_ck";
398 clks[2].id = "ref_ck";
399 clks[3].id = "mcu_ck";
400 clks[4].id = "dma_ck";
401
402 return devm_clk_bulk_get_optional(mtk->dev, BULK_CLKS_NUM, clks);
403}
404
405static int xhci_mtk_vregs_get(struct xhci_hcd_mtk *mtk)
406{
407 struct regulator_bulk_data *supplies = mtk->supplies;
408
409 supplies[0].supply = "vbus";
410 supplies[1].supply = "vusb33";
411
412 return devm_regulator_bulk_get(mtk->dev, BULK_VREGS_NUM, supplies);
413}
414
415static void xhci_mtk_quirks(struct device *dev, struct xhci_hcd *xhci)
416{
417 struct usb_hcd *hcd = xhci_to_hcd(xhci);
418 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
419
420 /*
421 * As of now platform drivers don't provide MSI support so we ensure
422 * here that the generic code does not try to make a pci_dev from our
423 * dev struct in order to setup MSI
424 */
425 xhci->quirks |= XHCI_PLAT;
426 xhci->quirks |= XHCI_MTK_HOST;
427 /*
428 * MTK host controller gives a spurious successful event after a
429 * short transfer. Ignore it.
430 */
431 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
432 if (mtk->lpm_support)
433 xhci->quirks |= XHCI_LPM_SUPPORT;
434 if (mtk->u2_lpm_disable)
435 xhci->quirks |= XHCI_HW_LPM_DISABLE;
436
437 /*
438 * MTK xHCI 0.96: PSA is 1 by default even if doesn't support stream,
439 * and it's 3 when support it.
440 */
441 if (xhci->hci_version < 0x100 && HCC_MAX_PSA(xhci->hcc_params) == 4)
442 xhci->quirks |= XHCI_BROKEN_STREAMS;
443}
444
445/* called during probe() after chip reset completes */
446static int xhci_mtk_setup(struct usb_hcd *hcd)
447{
448 struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
449 int ret;
450
451 if (usb_hcd_is_primary_hcd(hcd)) {
452 ret = xhci_mtk_ssusb_config(mtk);
453 if (ret)
454 return ret;
455
456 /* workaround only for mt8195 */
457 xhci_mtk_set_frame_interval(mtk);
458 }
459
460 ret = xhci_gen_setup(hcd, xhci_mtk_quirks);
461 if (ret)
462 return ret;
463
464 if (usb_hcd_is_primary_hcd(hcd))
465 ret = xhci_mtk_sch_init(mtk);
466
467 return ret;
468}
469
470static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
471 .reset = xhci_mtk_setup,
472 .add_endpoint = xhci_mtk_add_ep,
473 .drop_endpoint = xhci_mtk_drop_ep,
474 .check_bandwidth = xhci_mtk_check_bandwidth,
475 .reset_bandwidth = xhci_mtk_reset_bandwidth,
476};
477
478static struct hc_driver __read_mostly xhci_mtk_hc_driver;
479
480static int xhci_mtk_probe(struct platform_device *pdev)
481{
482 struct device *dev = &pdev->dev;
483 struct device_node *node = dev->of_node;
484 struct xhci_hcd_mtk *mtk;
485 const struct hc_driver *driver;
486 struct xhci_hcd *xhci;
487 struct resource *res;
488 struct usb_hcd *usb3_hcd;
489 struct usb_hcd *hcd;
490 int ret = -ENODEV;
491 int wakeup_irq;
492 int irq;
493
494 if (usb_disabled())
495 return -ENODEV;
496
497 driver = &xhci_mtk_hc_driver;
498 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
499 if (!mtk)
500 return -ENOMEM;
501
502 mtk->dev = dev;
503
504 ret = xhci_mtk_vregs_get(mtk);
505 if (ret)
506 return dev_err_probe(dev, ret, "Failed to get regulators\n");
507
508 ret = xhci_mtk_clks_get(mtk);
509 if (ret)
510 return ret;
511
512 irq = platform_get_irq_byname_optional(pdev, "host");
513 if (irq < 0) {
514 if (irq == -EPROBE_DEFER)
515 return irq;
516
517 /* for backward compatibility */
518 irq = platform_get_irq(pdev, 0);
519 if (irq < 0)
520 return irq;
521 }
522
523 wakeup_irq = platform_get_irq_byname_optional(pdev, "wakeup");
524 if (wakeup_irq == -EPROBE_DEFER)
525 return wakeup_irq;
526
527 mtk->lpm_support = of_property_read_bool(node, "usb3-lpm-capable");
528 mtk->u2_lpm_disable = of_property_read_bool(node, "usb2-lpm-disable");
529 /* optional property, ignore the error if it does not exist */
530 of_property_read_u32(node, "mediatek,u3p-dis-msk",
531 &mtk->u3p_dis_msk);
532 of_property_read_u32(node, "mediatek,u2p-dis-msk",
533 &mtk->u2p_dis_msk);
534
535 ret = usb_wakeup_of_property_parse(mtk, node);
536 if (ret) {
537 dev_err(dev, "failed to parse uwk property\n");
538 return ret;
539 }
540
541 pm_runtime_set_active(dev);
542 pm_runtime_use_autosuspend(dev);
543 pm_runtime_set_autosuspend_delay(dev, 4000);
544 pm_runtime_enable(dev);
545 pm_runtime_get_sync(dev);
546
547 ret = regulator_bulk_enable(BULK_VREGS_NUM, mtk->supplies);
548 if (ret)
549 goto disable_pm;
550
551 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
552 if (ret)
553 goto disable_ldos;
554
555 ret = device_reset_optional(dev);
556 if (ret) {
557 dev_err_probe(dev, ret, "failed to reset controller\n");
558 goto disable_clk;
559 }
560
561 hcd = usb_create_hcd(driver, dev, dev_name(dev));
562 if (!hcd) {
563 ret = -ENOMEM;
564 goto disable_clk;
565 }
566
567 /*
568 * USB 2.0 roothub is stored in the platform_device.
569 * Swap it with mtk HCD.
570 */
571 mtk->hcd = platform_get_drvdata(pdev);
572 platform_set_drvdata(pdev, mtk);
573
574 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
575 hcd->regs = devm_ioremap_resource(dev, res);
576 if (IS_ERR(hcd->regs)) {
577 ret = PTR_ERR(hcd->regs);
578 goto put_usb2_hcd;
579 }
580 hcd->rsrc_start = res->start;
581 hcd->rsrc_len = resource_size(res);
582
583 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
584 if (res) { /* ippc register is optional */
585 mtk->ippc_regs = devm_ioremap_resource(dev, res);
586 if (IS_ERR(mtk->ippc_regs)) {
587 ret = PTR_ERR(mtk->ippc_regs);
588 goto put_usb2_hcd;
589 }
590 mtk->has_ippc = true;
591 }
592
593 device_init_wakeup(dev, true);
594
595 xhci = hcd_to_xhci(hcd);
596 xhci->main_hcd = hcd;
597 xhci->allow_single_roothub = 1;
598
599 /*
600 * imod_interval is the interrupt moderation value in nanoseconds.
601 * The increment interval is 8 times as much as that defined in
602 * the xHCI spec on MTK's controller.
603 */
604 xhci->imod_interval = 5000;
605 device_property_read_u32(dev, "imod-interval-ns", &xhci->imod_interval);
606
607 ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
608 if (ret)
609 goto disable_device_wakeup;
610
611 if (!xhci_has_one_roothub(xhci)) {
612 xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
613 dev_name(dev), hcd);
614 if (!xhci->shared_hcd) {
615 ret = -ENOMEM;
616 goto dealloc_usb2_hcd;
617 }
618 }
619
620 usb3_hcd = xhci_get_usb3_hcd(xhci);
621 if (usb3_hcd && HCC_MAX_PSA(xhci->hcc_params) >= 4 &&
622 !(xhci->quirks & XHCI_BROKEN_STREAMS))
623 usb3_hcd->can_do_streams = 1;
624
625 if (xhci->shared_hcd) {
626 ret = usb_add_hcd(xhci->shared_hcd, irq, IRQF_SHARED);
627 if (ret)
628 goto put_usb3_hcd;
629 }
630
631 if (wakeup_irq > 0) {
632 ret = dev_pm_set_dedicated_wake_irq_reverse(dev, wakeup_irq);
633 if (ret) {
634 dev_err(dev, "set wakeup irq %d failed\n", wakeup_irq);
635 goto dealloc_usb3_hcd;
636 }
637 dev_info(dev, "wakeup irq %d\n", wakeup_irq);
638 }
639
640 device_enable_async_suspend(dev);
641 pm_runtime_mark_last_busy(dev);
642 pm_runtime_put_autosuspend(dev);
643 pm_runtime_forbid(dev);
644
645 return 0;
646
647dealloc_usb3_hcd:
648 usb_remove_hcd(xhci->shared_hcd);
649
650put_usb3_hcd:
651 usb_put_hcd(xhci->shared_hcd);
652
653dealloc_usb2_hcd:
654 xhci_mtk_sch_exit(mtk);
655 usb_remove_hcd(hcd);
656
657disable_device_wakeup:
658 device_init_wakeup(dev, false);
659
660put_usb2_hcd:
661 usb_put_hcd(hcd);
662
663disable_clk:
664 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
665
666disable_ldos:
667 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
668
669disable_pm:
670 pm_runtime_put_noidle(dev);
671 pm_runtime_disable(dev);
672 return ret;
673}
674
675static int xhci_mtk_remove(struct platform_device *pdev)
676{
677 struct xhci_hcd_mtk *mtk = platform_get_drvdata(pdev);
678 struct usb_hcd *hcd = mtk->hcd;
679 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
680 struct usb_hcd *shared_hcd = xhci->shared_hcd;
681 struct device *dev = &pdev->dev;
682
683 pm_runtime_get_sync(dev);
684 xhci->xhc_state |= XHCI_STATE_REMOVING;
685 dev_pm_clear_wake_irq(dev);
686 device_init_wakeup(dev, false);
687
688 if (shared_hcd) {
689 usb_remove_hcd(shared_hcd);
690 xhci->shared_hcd = NULL;
691 }
692 usb_remove_hcd(hcd);
693
694 if (shared_hcd)
695 usb_put_hcd(shared_hcd);
696
697 usb_put_hcd(hcd);
698 xhci_mtk_sch_exit(mtk);
699 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
700 regulator_bulk_disable(BULK_VREGS_NUM, mtk->supplies);
701
702 pm_runtime_disable(dev);
703 pm_runtime_put_noidle(dev);
704 pm_runtime_set_suspended(dev);
705
706 return 0;
707}
708
709static int __maybe_unused xhci_mtk_suspend(struct device *dev)
710{
711 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
712 struct usb_hcd *hcd = mtk->hcd;
713 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
714 struct usb_hcd *shared_hcd = xhci->shared_hcd;
715 int ret;
716
717 xhci_dbg(xhci, "%s: stop port polling\n", __func__);
718 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
719 del_timer_sync(&hcd->rh_timer);
720 if (shared_hcd) {
721 clear_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
722 del_timer_sync(&shared_hcd->rh_timer);
723 }
724
725 ret = xhci_mtk_host_disable(mtk);
726 if (ret)
727 goto restart_poll_rh;
728
729 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
730 usb_wakeup_set(mtk, true);
731 return 0;
732
733restart_poll_rh:
734 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
735 if (shared_hcd) {
736 set_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
737 usb_hcd_poll_rh_status(shared_hcd);
738 }
739 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
740 usb_hcd_poll_rh_status(hcd);
741 return ret;
742}
743
744static int __maybe_unused xhci_mtk_resume(struct device *dev)
745{
746 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
747 struct usb_hcd *hcd = mtk->hcd;
748 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
749 struct usb_hcd *shared_hcd = xhci->shared_hcd;
750 int ret;
751
752 usb_wakeup_set(mtk, false);
753 ret = clk_bulk_prepare_enable(BULK_CLKS_NUM, mtk->clks);
754 if (ret)
755 goto enable_wakeup;
756
757 ret = xhci_mtk_host_enable(mtk);
758 if (ret)
759 goto disable_clks;
760
761 xhci_dbg(xhci, "%s: restart port polling\n", __func__);
762 if (shared_hcd) {
763 set_bit(HCD_FLAG_POLL_RH, &shared_hcd->flags);
764 usb_hcd_poll_rh_status(shared_hcd);
765 }
766 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
767 usb_hcd_poll_rh_status(hcd);
768 return 0;
769
770disable_clks:
771 clk_bulk_disable_unprepare(BULK_CLKS_NUM, mtk->clks);
772enable_wakeup:
773 usb_wakeup_set(mtk, true);
774 return ret;
775}
776
777static int __maybe_unused xhci_mtk_runtime_suspend(struct device *dev)
778{
779 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
780 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
781 int ret = 0;
782
783 if (xhci->xhc_state)
784 return -ESHUTDOWN;
785
786 if (device_may_wakeup(dev))
787 ret = xhci_mtk_suspend(dev);
788
789 /* -EBUSY: let PM automatically reschedule another autosuspend */
790 return ret ? -EBUSY : 0;
791}
792
793static int __maybe_unused xhci_mtk_runtime_resume(struct device *dev)
794{
795 struct xhci_hcd_mtk *mtk = dev_get_drvdata(dev);
796 struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
797 int ret = 0;
798
799 if (xhci->xhc_state)
800 return -ESHUTDOWN;
801
802 if (device_may_wakeup(dev))
803 ret = xhci_mtk_resume(dev);
804
805 return ret;
806}
807
808static const struct dev_pm_ops xhci_mtk_pm_ops = {
809 SET_SYSTEM_SLEEP_PM_OPS(xhci_mtk_suspend, xhci_mtk_resume)
810 SET_RUNTIME_PM_OPS(xhci_mtk_runtime_suspend,
811 xhci_mtk_runtime_resume, NULL)
812};
813
814#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &xhci_mtk_pm_ops : NULL)
815
816static const struct of_device_id mtk_xhci_of_match[] = {
817 { .compatible = "mediatek,mt8173-xhci"},
818 { .compatible = "mediatek,mt8195-xhci"},
819 { .compatible = "mediatek,mtk-xhci"},
820 { },
821};
822MODULE_DEVICE_TABLE(of, mtk_xhci_of_match);
823
824static struct platform_driver mtk_xhci_driver = {
825 .probe = xhci_mtk_probe,
826 .remove = xhci_mtk_remove,
827 .driver = {
828 .name = "xhci-mtk",
829 .pm = DEV_PM_OPS,
830 .of_match_table = mtk_xhci_of_match,
831 },
832};
833
834static int __init xhci_mtk_init(void)
835{
836 xhci_init_driver(&xhci_mtk_hc_driver, &xhci_mtk_overrides);
837 return platform_driver_register(&mtk_xhci_driver);
838}
839module_init(xhci_mtk_init);
840
841static void __exit xhci_mtk_exit(void)
842{
843 platform_driver_unregister(&mtk_xhci_driver);
844}
845module_exit(xhci_mtk_exit);
846
847MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
848MODULE_DESCRIPTION("MediaTek xHCI Host Controller Driver");
849MODULE_LICENSE("GPL v2");