Loading...
1/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22/* Up to 16 ms to halt an HC */
23#define XHCI_MAX_HALT_USEC (16*1000)
24/* HC not running - set to 1 when run/stop bit is cleared. */
25#define XHCI_STS_HALT (1<<0)
26
27/* HCCPARAMS offset from PCI base address */
28#define XHCI_HCC_PARAMS_OFFSET 0x10
29/* HCCPARAMS contains the first extended capability pointer */
30#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
31
32/* Command and Status registers offset from the Operational Registers address */
33#define XHCI_CMD_OFFSET 0x00
34#define XHCI_STS_OFFSET 0x04
35
36#define XHCI_MAX_EXT_CAPS 50
37
38/* Capability Register */
39/* bits 7:0 - how long is the Capabilities register */
40#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
41
42/* Extended capability register fields */
43#define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
44#define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
45#define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
46/* Extended capability IDs - ID 0 reserved */
47#define XHCI_EXT_CAPS_LEGACY 1
48#define XHCI_EXT_CAPS_PROTOCOL 2
49#define XHCI_EXT_CAPS_PM 3
50#define XHCI_EXT_CAPS_VIRT 4
51#define XHCI_EXT_CAPS_ROUTE 5
52/* IDs 6-9 reserved */
53#define XHCI_EXT_CAPS_DEBUG 10
54/* USB Legacy Support Capability - section 7.1.1 */
55#define XHCI_HC_BIOS_OWNED (1 << 16)
56#define XHCI_HC_OS_OWNED (1 << 24)
57
58/* USB Legacy Support Capability - section 7.1.1 */
59/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
60#define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
61
62/* USB Legacy Support Control and Status Register - section 7.1.2 */
63/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
64#define XHCI_LEGACY_CONTROL_OFFSET (0x04)
65/* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
66#define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
67#define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
68
69/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
70#define XHCI_L1C (1 << 16)
71
72/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
73#define XHCI_HLC (1 << 19)
74#define XHCI_BLC (1 << 20)
75
76/* command register values to disable interrupts and halt the HC */
77/* start/stop HC execution - do not write unless HC is halted*/
78#define XHCI_CMD_RUN (1 << 0)
79/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
80#define XHCI_CMD_EIE (1 << 2)
81/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
82#define XHCI_CMD_HSEIE (1 << 3)
83/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
84#define XHCI_CMD_EWE (1 << 10)
85
86#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
87
88/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
89#define XHCI_STS_CNR (1 << 11)
90
91#include <linux/io.h>
92
93/**
94 * Find the offset of the extended capabilities with capability ID id.
95 *
96 * @base PCI MMIO registers base address.
97 * @start address at which to start looking, (0 or HCC_PARAMS to start at
98 * beginning of list)
99 * @id Extended capability ID to search for.
100 *
101 * Returns the offset of the next matching extended capability structure.
102 * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
103 * and this provides a way to find them all.
104 */
105
106static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
107{
108 u32 val;
109 u32 next;
110 u32 offset;
111
112 offset = start;
113 if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
114 val = readl(base + XHCI_HCC_PARAMS_OFFSET);
115 if (val == ~0)
116 return 0;
117 offset = XHCI_HCC_EXT_CAPS(val) << 2;
118 if (!offset)
119 return 0;
120 };
121 do {
122 val = readl(base + offset);
123 if (val == ~0)
124 return 0;
125 if (XHCI_EXT_CAPS_ID(val) == id && offset != start)
126 return offset;
127
128 next = XHCI_EXT_CAPS_NEXT(val);
129 offset += next << 2;
130 } while (next);
131
132 return 0;
133}
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * xHCI host controller driver
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11/* HC should halt within 16 ms, but use 32 ms as some hosts take longer */
12#define XHCI_MAX_HALT_USEC (32 * 1000)
13/* HC not running - set to 1 when run/stop bit is cleared. */
14#define XHCI_STS_HALT (1<<0)
15
16/* HCCPARAMS offset from PCI base address */
17#define XHCI_HCC_PARAMS_OFFSET 0x10
18/* HCCPARAMS contains the first extended capability pointer */
19#define XHCI_HCC_EXT_CAPS(p) (((p)>>16)&0xffff)
20
21/* Command and Status registers offset from the Operational Registers address */
22#define XHCI_CMD_OFFSET 0x00
23#define XHCI_STS_OFFSET 0x04
24
25#define XHCI_MAX_EXT_CAPS 50
26
27/* Capability Register */
28/* bits 7:0 - how long is the Capabilities register */
29#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
30
31/* Extended capability register fields */
32#define XHCI_EXT_CAPS_ID(p) (((p)>>0)&0xff)
33#define XHCI_EXT_CAPS_NEXT(p) (((p)>>8)&0xff)
34#define XHCI_EXT_CAPS_VAL(p) ((p)>>16)
35/* Extended capability IDs - ID 0 reserved */
36#define XHCI_EXT_CAPS_LEGACY 1
37#define XHCI_EXT_CAPS_PROTOCOL 2
38#define XHCI_EXT_CAPS_PM 3
39#define XHCI_EXT_CAPS_VIRT 4
40#define XHCI_EXT_CAPS_ROUTE 5
41/* IDs 6-9 reserved */
42#define XHCI_EXT_CAPS_DEBUG 10
43/* Vendor caps */
44#define XHCI_EXT_CAPS_VENDOR_INTEL 192
45/* USB Legacy Support Capability - section 7.1.1 */
46#define XHCI_HC_BIOS_OWNED (1 << 16)
47#define XHCI_HC_OS_OWNED (1 << 24)
48
49/* USB Legacy Support Capability - section 7.1.1 */
50/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
51#define XHCI_LEGACY_SUPPORT_OFFSET (0x00)
52
53/* USB Legacy Support Control and Status Register - section 7.1.2 */
54/* Add this offset, plus the value of xECP in HCCPARAMS to the base address */
55#define XHCI_LEGACY_CONTROL_OFFSET (0x04)
56/* bits 1:3, 5:12, and 17:19 need to be preserved; bits 21:28 should be zero */
57#define XHCI_LEGACY_DISABLE_SMI ((0x7 << 1) + (0xff << 5) + (0x7 << 17))
58#define XHCI_LEGACY_SMI_EVENTS (0x7 << 29)
59
60/* USB 2.0 xHCI 0.96 L1C capability - section 7.2.2.1.3.2 */
61#define XHCI_L1C (1 << 16)
62
63/* USB 2.0 xHCI 1.0 hardware LMP capability - section 7.2.2.1.3.2 */
64#define XHCI_HLC (1 << 19)
65#define XHCI_BLC (1 << 20)
66
67/* command register values to disable interrupts and halt the HC */
68/* start/stop HC execution - do not write unless HC is halted*/
69#define XHCI_CMD_RUN (1 << 0)
70/* Event Interrupt Enable - get irq when EINT bit is set in USBSTS register */
71#define XHCI_CMD_EIE (1 << 2)
72/* Host System Error Interrupt Enable - get irq when HSEIE bit set in USBSTS */
73#define XHCI_CMD_HSEIE (1 << 3)
74/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
75#define XHCI_CMD_EWE (1 << 10)
76
77#define XHCI_IRQS (XHCI_CMD_EIE | XHCI_CMD_HSEIE | XHCI_CMD_EWE)
78
79/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
80#define XHCI_STS_CNR (1 << 11)
81
82#include <linux/io.h>
83
84/**
85 * Find the offset of the extended capabilities with capability ID id.
86 *
87 * @base PCI MMIO registers base address.
88 * @start address at which to start looking, (0 or HCC_PARAMS to start at
89 * beginning of list)
90 * @id Extended capability ID to search for, or 0 for the next
91 * capability
92 *
93 * Returns the offset of the next matching extended capability structure.
94 * Some capabilities can occur several times, e.g., the XHCI_EXT_CAPS_PROTOCOL,
95 * and this provides a way to find them all.
96 */
97
98static inline int xhci_find_next_ext_cap(void __iomem *base, u32 start, int id)
99{
100 u32 val;
101 u32 next;
102 u32 offset;
103
104 offset = start;
105 if (!start || start == XHCI_HCC_PARAMS_OFFSET) {
106 val = readl(base + XHCI_HCC_PARAMS_OFFSET);
107 if (val == ~0)
108 return 0;
109 offset = XHCI_HCC_EXT_CAPS(val) << 2;
110 if (!offset)
111 return 0;
112 }
113 do {
114 val = readl(base + offset);
115 if (val == ~0)
116 return 0;
117 if (offset != start && (id == 0 || XHCI_EXT_CAPS_ID(val) == id))
118 return offset;
119
120 next = XHCI_EXT_CAPS_NEXT(val);
121 offset += next << 2;
122 } while (next);
123
124 return 0;
125}