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1/**
2 * core.h - DesignWare USB3 DRD Core Header
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __DRIVERS_USB_DWC3_CORE_H
20#define __DRIVERS_USB_DWC3_CORE_H
21
22#include <linux/device.h>
23#include <linux/spinlock.h>
24#include <linux/ioport.h>
25#include <linux/list.h>
26#include <linux/dma-mapping.h>
27#include <linux/mm.h>
28#include <linux/debugfs.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/otg.h>
33#include <linux/ulpi/interface.h>
34
35#include <linux/phy/phy.h>
36
37#define DWC3_MSG_MAX 500
38
39/* Global constants */
40#define DWC3_ZLP_BUF_SIZE 1024 /* size of a superspeed bulk */
41#define DWC3_EP0_BOUNCE_SIZE 512
42#define DWC3_ENDPOINTS_NUM 32
43#define DWC3_XHCI_RESOURCES_NUM 2
44
45#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
46#define DWC3_EVENT_SIZE 4 /* bytes */
47#define DWC3_EVENT_MAX_NUM 64 /* 2 events/endpoint */
48#define DWC3_EVENT_BUFFERS_SIZE (DWC3_EVENT_SIZE * DWC3_EVENT_MAX_NUM)
49#define DWC3_EVENT_TYPE_MASK 0xfe
50
51#define DWC3_EVENT_TYPE_DEV 0
52#define DWC3_EVENT_TYPE_CARKIT 3
53#define DWC3_EVENT_TYPE_I2C 4
54
55#define DWC3_DEVICE_EVENT_DISCONNECT 0
56#define DWC3_DEVICE_EVENT_RESET 1
57#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
58#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
59#define DWC3_DEVICE_EVENT_WAKEUP 4
60#define DWC3_DEVICE_EVENT_HIBER_REQ 5
61#define DWC3_DEVICE_EVENT_EOPF 6
62#define DWC3_DEVICE_EVENT_SOF 7
63#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
64#define DWC3_DEVICE_EVENT_CMD_CMPL 10
65#define DWC3_DEVICE_EVENT_OVERFLOW 11
66
67#define DWC3_GEVNTCOUNT_MASK 0xfffc
68#define DWC3_GSNPSID_MASK 0xffff0000
69#define DWC3_GSNPSREV_MASK 0xffff
70
71/* DWC3 registers memory space boundries */
72#define DWC3_XHCI_REGS_START 0x0
73#define DWC3_XHCI_REGS_END 0x7fff
74#define DWC3_GLOBALS_REGS_START 0xc100
75#define DWC3_GLOBALS_REGS_END 0xc6ff
76#define DWC3_DEVICE_REGS_START 0xc700
77#define DWC3_DEVICE_REGS_END 0xcbff
78#define DWC3_OTG_REGS_START 0xcc00
79#define DWC3_OTG_REGS_END 0xccff
80
81/* Global Registers */
82#define DWC3_GSBUSCFG0 0xc100
83#define DWC3_GSBUSCFG1 0xc104
84#define DWC3_GTXTHRCFG 0xc108
85#define DWC3_GRXTHRCFG 0xc10c
86#define DWC3_GCTL 0xc110
87#define DWC3_GEVTEN 0xc114
88#define DWC3_GSTS 0xc118
89#define DWC3_GSNPSID 0xc120
90#define DWC3_GGPIO 0xc124
91#define DWC3_GUID 0xc128
92#define DWC3_GUCTL 0xc12c
93#define DWC3_GBUSERRADDR0 0xc130
94#define DWC3_GBUSERRADDR1 0xc134
95#define DWC3_GPRTBIMAP0 0xc138
96#define DWC3_GPRTBIMAP1 0xc13c
97#define DWC3_GHWPARAMS0 0xc140
98#define DWC3_GHWPARAMS1 0xc144
99#define DWC3_GHWPARAMS2 0xc148
100#define DWC3_GHWPARAMS3 0xc14c
101#define DWC3_GHWPARAMS4 0xc150
102#define DWC3_GHWPARAMS5 0xc154
103#define DWC3_GHWPARAMS6 0xc158
104#define DWC3_GHWPARAMS7 0xc15c
105#define DWC3_GDBGFIFOSPACE 0xc160
106#define DWC3_GDBGLTSSM 0xc164
107#define DWC3_GPRTBIMAP_HS0 0xc180
108#define DWC3_GPRTBIMAP_HS1 0xc184
109#define DWC3_GPRTBIMAP_FS0 0xc188
110#define DWC3_GPRTBIMAP_FS1 0xc18c
111
112#define DWC3_VER_NUMBER 0xc1a0
113#define DWC3_VER_TYPE 0xc1a4
114
115#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
116#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
117
118#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
119
120#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
121
122#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
123#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
124
125#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
126#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
127#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
128#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
129
130#define DWC3_GHWPARAMS8 0xc600
131#define DWC3_GFLADJ 0xc630
132
133/* Device Registers */
134#define DWC3_DCFG 0xc700
135#define DWC3_DCTL 0xc704
136#define DWC3_DEVTEN 0xc708
137#define DWC3_DSTS 0xc70c
138#define DWC3_DGCMDPAR 0xc710
139#define DWC3_DGCMD 0xc714
140#define DWC3_DALEPENA 0xc720
141#define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
142#define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
143#define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
144#define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
145
146/* OTG Registers */
147#define DWC3_OCFG 0xcc00
148#define DWC3_OCTL 0xcc04
149#define DWC3_OEVT 0xcc08
150#define DWC3_OEVTEN 0xcc0C
151#define DWC3_OSTS 0xcc10
152
153/* Bit fields */
154
155/* Global Configuration Register */
156#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
157#define DWC3_GCTL_U2RSTECN (1 << 16)
158#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
159#define DWC3_GCTL_CLK_BUS (0)
160#define DWC3_GCTL_CLK_PIPE (1)
161#define DWC3_GCTL_CLK_PIPEHALF (2)
162#define DWC3_GCTL_CLK_MASK (3)
163
164#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
165#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
166#define DWC3_GCTL_PRTCAP_HOST 1
167#define DWC3_GCTL_PRTCAP_DEVICE 2
168#define DWC3_GCTL_PRTCAP_OTG 3
169
170#define DWC3_GCTL_CORESOFTRESET (1 << 11)
171#define DWC3_GCTL_SOFITPSYNC (1 << 10)
172#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
173#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
174#define DWC3_GCTL_DISSCRAMBLE (1 << 3)
175#define DWC3_GCTL_U2EXIT_LFPS (1 << 2)
176#define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
177#define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
178
179/* Global USB2 PHY Configuration Register */
180#define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
181#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
182#define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
183#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
184
185/* Global USB2 PHY Vendor Control Register */
186#define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
187#define DWC3_GUSB2PHYACC_BUSY (1 << 23)
188#define DWC3_GUSB2PHYACC_WRITE (1 << 22)
189#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
190#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
191#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
192
193/* Global USB3 PIPE Control Register */
194#define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
195#define DWC3_GUSB3PIPECTL_U2SSINP3OK (1 << 29)
196#define DWC3_GUSB3PIPECTL_REQP1P2P3 (1 << 24)
197#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
198#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
199#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
200#define DWC3_GUSB3PIPECTL_DEPOCHANGE (1 << 18)
201#define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
202#define DWC3_GUSB3PIPECTL_LFPSFILT (1 << 9)
203#define DWC3_GUSB3PIPECTL_RX_DETOPOLL (1 << 8)
204#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
205#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
206
207/* Global TX Fifo Size Register */
208#define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
209#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
210
211/* Global Event Size Registers */
212#define DWC3_GEVNTSIZ_INTMASK (1 << 31)
213#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
214
215/* Global HWPARAMS1 Register */
216#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
217#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
218#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
219#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
220#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
221#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
222
223/* Global HWPARAMS3 Register */
224#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
225#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
226#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
227#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
228#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
229#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
230#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
231#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
232#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
233#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
234#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
235#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
236
237/* Global HWPARAMS4 Register */
238#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
239#define DWC3_MAX_HIBER_SCRATCHBUFS 15
240
241/* Global HWPARAMS6 Register */
242#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
243
244/* Global Frame Length Adjustment Register */
245#define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
246#define DWC3_GFLADJ_30MHZ_MASK 0x3f
247
248/* Device Configuration Register */
249#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
250#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
251
252#define DWC3_DCFG_SPEED_MASK (7 << 0)
253#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
254#define DWC3_DCFG_SUPERSPEED (4 << 0)
255#define DWC3_DCFG_HIGHSPEED (0 << 0)
256#define DWC3_DCFG_FULLSPEED2 (1 << 0)
257#define DWC3_DCFG_LOWSPEED (2 << 0)
258#define DWC3_DCFG_FULLSPEED1 (3 << 0)
259
260#define DWC3_DCFG_LPM_CAP (1 << 22)
261
262/* Device Control Register */
263#define DWC3_DCTL_RUN_STOP (1 << 31)
264#define DWC3_DCTL_CSFTRST (1 << 30)
265#define DWC3_DCTL_LSFTRST (1 << 29)
266
267#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
268#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
269
270#define DWC3_DCTL_APPL1RES (1 << 23)
271
272/* These apply for core versions 1.87a and earlier */
273#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
274#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
275#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
276#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
277#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
278#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
279#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
280
281/* These apply for core versions 1.94a and later */
282#define DWC3_DCTL_LPM_ERRATA_MASK DWC3_DCTL_LPM_ERRATA(0xf)
283#define DWC3_DCTL_LPM_ERRATA(n) ((n) << 20)
284
285#define DWC3_DCTL_KEEP_CONNECT (1 << 19)
286#define DWC3_DCTL_L1_HIBER_EN (1 << 18)
287#define DWC3_DCTL_CRS (1 << 17)
288#define DWC3_DCTL_CSS (1 << 16)
289
290#define DWC3_DCTL_INITU2ENA (1 << 12)
291#define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
292#define DWC3_DCTL_INITU1ENA (1 << 10)
293#define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
294#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
295
296#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
297#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
298
299#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
300#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
301#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
302#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
303#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
304#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
305#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
306
307/* Device Event Enable Register */
308#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
309#define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
310#define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
311#define DWC3_DEVTEN_ERRTICERREN (1 << 9)
312#define DWC3_DEVTEN_SOFEN (1 << 7)
313#define DWC3_DEVTEN_EOPFEN (1 << 6)
314#define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
315#define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
316#define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
317#define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
318#define DWC3_DEVTEN_USBRSTEN (1 << 1)
319#define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
320
321/* Device Status Register */
322#define DWC3_DSTS_DCNRD (1 << 29)
323
324/* This applies for core versions 1.87a and earlier */
325#define DWC3_DSTS_PWRUPREQ (1 << 24)
326
327/* These apply for core versions 1.94a and later */
328#define DWC3_DSTS_RSS (1 << 25)
329#define DWC3_DSTS_SSS (1 << 24)
330
331#define DWC3_DSTS_COREIDLE (1 << 23)
332#define DWC3_DSTS_DEVCTRLHLT (1 << 22)
333
334#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
335#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
336
337#define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
338
339#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
340#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
341
342#define DWC3_DSTS_CONNECTSPD (7 << 0)
343
344#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
345#define DWC3_DSTS_SUPERSPEED (4 << 0)
346#define DWC3_DSTS_HIGHSPEED (0 << 0)
347#define DWC3_DSTS_FULLSPEED2 (1 << 0)
348#define DWC3_DSTS_LOWSPEED (2 << 0)
349#define DWC3_DSTS_FULLSPEED1 (3 << 0)
350
351/* Device Generic Command Register */
352#define DWC3_DGCMD_SET_LMP 0x01
353#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
354#define DWC3_DGCMD_XMIT_FUNCTION 0x03
355
356/* These apply for core versions 1.94a and later */
357#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
358#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
359
360#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
361#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
362#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
363#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
364
365#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
366#define DWC3_DGCMD_CMDACT (1 << 10)
367#define DWC3_DGCMD_CMDIOC (1 << 8)
368
369/* Device Generic Command Parameter Register */
370#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
371#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
372#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
373#define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
374#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
375#define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
376
377/* Device Endpoint Command Register */
378#define DWC3_DEPCMD_PARAM_SHIFT 16
379#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
380#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
381#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
382#define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
383#define DWC3_DEPCMD_CMDACT (1 << 10)
384#define DWC3_DEPCMD_CMDIOC (1 << 8)
385
386#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
387#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
388#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
389#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
390#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
391#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
392/* This applies for core versions 1.90a and earlier */
393#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
394/* This applies for core versions 1.94a and later */
395#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
396#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
397#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
398
399/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
400#define DWC3_DALEPENA_EP(n) (1 << n)
401
402#define DWC3_DEPCMD_TYPE_CONTROL 0
403#define DWC3_DEPCMD_TYPE_ISOC 1
404#define DWC3_DEPCMD_TYPE_BULK 2
405#define DWC3_DEPCMD_TYPE_INTR 3
406
407/* Structures */
408
409struct dwc3_trb;
410
411/**
412 * struct dwc3_event_buffer - Software event buffer representation
413 * @buf: _THE_ buffer
414 * @length: size of this buffer
415 * @lpos: event offset
416 * @count: cache of last read event count register
417 * @flags: flags related to this event buffer
418 * @dma: dma_addr_t
419 * @dwc: pointer to DWC controller
420 */
421struct dwc3_event_buffer {
422 void *buf;
423 unsigned length;
424 unsigned int lpos;
425 unsigned int count;
426 unsigned int flags;
427
428#define DWC3_EVENT_PENDING BIT(0)
429
430 dma_addr_t dma;
431
432 struct dwc3 *dwc;
433};
434
435#define DWC3_EP_FLAG_STALLED (1 << 0)
436#define DWC3_EP_FLAG_WEDGED (1 << 1)
437
438#define DWC3_EP_DIRECTION_TX true
439#define DWC3_EP_DIRECTION_RX false
440
441#define DWC3_TRB_NUM 32
442#define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
443
444/**
445 * struct dwc3_ep - device side endpoint representation
446 * @endpoint: usb endpoint
447 * @request_list: list of requests for this endpoint
448 * @req_queued: list of requests on this ep which have TRBs setup
449 * @trb_pool: array of transaction buffers
450 * @trb_pool_dma: dma address of @trb_pool
451 * @free_slot: next slot which is going to be used
452 * @busy_slot: first slot which is owned by HW
453 * @desc: usb_endpoint_descriptor pointer
454 * @dwc: pointer to DWC controller
455 * @saved_state: ep state saved during hibernation
456 * @flags: endpoint flags (wedged, stalled, ...)
457 * @number: endpoint number (1 - 15)
458 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
459 * @resource_index: Resource transfer index
460 * @interval: the interval on which the ISOC transfer is started
461 * @name: a human readable name e.g. ep1out-bulk
462 * @direction: true for TX, false for RX
463 * @stream_capable: true when streams are enabled
464 */
465struct dwc3_ep {
466 struct usb_ep endpoint;
467 struct list_head request_list;
468 struct list_head req_queued;
469
470 struct dwc3_trb *trb_pool;
471 dma_addr_t trb_pool_dma;
472 u32 free_slot;
473 u32 busy_slot;
474 const struct usb_ss_ep_comp_descriptor *comp_desc;
475 struct dwc3 *dwc;
476
477 u32 saved_state;
478 unsigned flags;
479#define DWC3_EP_ENABLED (1 << 0)
480#define DWC3_EP_STALL (1 << 1)
481#define DWC3_EP_WEDGE (1 << 2)
482#define DWC3_EP_BUSY (1 << 4)
483#define DWC3_EP_PENDING_REQUEST (1 << 5)
484#define DWC3_EP_MISSED_ISOC (1 << 6)
485
486 /* This last one is specific to EP0 */
487#define DWC3_EP0_DIR_IN (1 << 31)
488
489 u8 number;
490 u8 type;
491 u8 resource_index;
492 u32 interval;
493
494 char name[20];
495
496 unsigned direction:1;
497 unsigned stream_capable:1;
498};
499
500enum dwc3_phy {
501 DWC3_PHY_UNKNOWN = 0,
502 DWC3_PHY_USB3,
503 DWC3_PHY_USB2,
504};
505
506enum dwc3_ep0_next {
507 DWC3_EP0_UNKNOWN = 0,
508 DWC3_EP0_COMPLETE,
509 DWC3_EP0_NRDY_DATA,
510 DWC3_EP0_NRDY_STATUS,
511};
512
513enum dwc3_ep0_state {
514 EP0_UNCONNECTED = 0,
515 EP0_SETUP_PHASE,
516 EP0_DATA_PHASE,
517 EP0_STATUS_PHASE,
518};
519
520enum dwc3_link_state {
521 /* In SuperSpeed */
522 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
523 DWC3_LINK_STATE_U1 = 0x01,
524 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
525 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
526 DWC3_LINK_STATE_SS_DIS = 0x04,
527 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
528 DWC3_LINK_STATE_SS_INACT = 0x06,
529 DWC3_LINK_STATE_POLL = 0x07,
530 DWC3_LINK_STATE_RECOV = 0x08,
531 DWC3_LINK_STATE_HRESET = 0x09,
532 DWC3_LINK_STATE_CMPLY = 0x0a,
533 DWC3_LINK_STATE_LPBK = 0x0b,
534 DWC3_LINK_STATE_RESET = 0x0e,
535 DWC3_LINK_STATE_RESUME = 0x0f,
536 DWC3_LINK_STATE_MASK = 0x0f,
537};
538
539/* TRB Length, PCM and Status */
540#define DWC3_TRB_SIZE_MASK (0x00ffffff)
541#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
542#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
543#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
544
545#define DWC3_TRBSTS_OK 0
546#define DWC3_TRBSTS_MISSED_ISOC 1
547#define DWC3_TRBSTS_SETUP_PENDING 2
548#define DWC3_TRB_STS_XFER_IN_PROG 4
549
550/* TRB Control */
551#define DWC3_TRB_CTRL_HWO (1 << 0)
552#define DWC3_TRB_CTRL_LST (1 << 1)
553#define DWC3_TRB_CTRL_CHN (1 << 2)
554#define DWC3_TRB_CTRL_CSP (1 << 3)
555#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
556#define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
557#define DWC3_TRB_CTRL_IOC (1 << 11)
558#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
559
560#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
561#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
562#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
563#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
564#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
565#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
566#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
567#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
568
569/**
570 * struct dwc3_trb - transfer request block (hw format)
571 * @bpl: DW0-3
572 * @bph: DW4-7
573 * @size: DW8-B
574 * @trl: DWC-F
575 */
576struct dwc3_trb {
577 u32 bpl;
578 u32 bph;
579 u32 size;
580 u32 ctrl;
581} __packed;
582
583/**
584 * dwc3_hwparams - copy of HWPARAMS registers
585 * @hwparams0 - GHWPARAMS0
586 * @hwparams1 - GHWPARAMS1
587 * @hwparams2 - GHWPARAMS2
588 * @hwparams3 - GHWPARAMS3
589 * @hwparams4 - GHWPARAMS4
590 * @hwparams5 - GHWPARAMS5
591 * @hwparams6 - GHWPARAMS6
592 * @hwparams7 - GHWPARAMS7
593 * @hwparams8 - GHWPARAMS8
594 */
595struct dwc3_hwparams {
596 u32 hwparams0;
597 u32 hwparams1;
598 u32 hwparams2;
599 u32 hwparams3;
600 u32 hwparams4;
601 u32 hwparams5;
602 u32 hwparams6;
603 u32 hwparams7;
604 u32 hwparams8;
605};
606
607/* HWPARAMS0 */
608#define DWC3_MODE(n) ((n) & 0x7)
609
610#define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
611
612/* HWPARAMS1 */
613#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
614
615/* HWPARAMS3 */
616#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
617#define DWC3_NUM_EPS_MASK (0x3f << 12)
618#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
619 (DWC3_NUM_EPS_MASK)) >> 12)
620#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
621 (DWC3_NUM_IN_EPS_MASK)) >> 18)
622
623/* HWPARAMS7 */
624#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
625
626struct dwc3_request {
627 struct usb_request request;
628 struct list_head list;
629 struct dwc3_ep *dep;
630 u32 start_slot;
631
632 u8 epnum;
633 struct dwc3_trb *trb;
634 dma_addr_t trb_dma;
635
636 unsigned direction:1;
637 unsigned mapped:1;
638 unsigned queued:1;
639};
640
641/*
642 * struct dwc3_scratchpad_array - hibernation scratchpad array
643 * (format defined by hw)
644 */
645struct dwc3_scratchpad_array {
646 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
647};
648
649/**
650 * struct dwc3 - representation of our controller
651 * @ctrl_req: usb control request which is used for ep0
652 * @ep0_trb: trb which is used for the ctrl_req
653 * @ep0_bounce: bounce buffer for ep0
654 * @zlp_buf: used when request->zero is set
655 * @setup_buf: used while precessing STD USB requests
656 * @ctrl_req_addr: dma address of ctrl_req
657 * @ep0_trb: dma address of ep0_trb
658 * @ep0_usb_req: dummy req used while handling STD USB requests
659 * @ep0_bounce_addr: dma address of ep0_bounce
660 * @scratch_addr: dma address of scratchbuf
661 * @lock: for synchronizing
662 * @dev: pointer to our struct device
663 * @xhci: pointer to our xHCI child
664 * @event_buffer_list: a list of event buffers
665 * @gadget: device side representation of the peripheral controller
666 * @gadget_driver: pointer to the gadget driver
667 * @regs: base address for our registers
668 * @regs_size: address space size
669 * @nr_scratch: number of scratch buffers
670 * @num_event_buffers: calculated number of event buffers
671 * @u1u2: only used on revisions <1.83a for workaround
672 * @maximum_speed: maximum speed requested (mainly for testing purposes)
673 * @revision: revision register contents
674 * @dr_mode: requested mode of operation
675 * @usb2_phy: pointer to USB2 PHY
676 * @usb3_phy: pointer to USB3 PHY
677 * @usb2_generic_phy: pointer to USB2 PHY
678 * @usb3_generic_phy: pointer to USB3 PHY
679 * @ulpi: pointer to ulpi interface
680 * @dcfg: saved contents of DCFG register
681 * @gctl: saved contents of GCTL register
682 * @isoch_delay: wValue from Set Isochronous Delay request;
683 * @u2sel: parameter from Set SEL request.
684 * @u2pel: parameter from Set SEL request.
685 * @u1sel: parameter from Set SEL request.
686 * @u1pel: parameter from Set SEL request.
687 * @num_out_eps: number of out endpoints
688 * @num_in_eps: number of in endpoints
689 * @ep0_next_event: hold the next expected event
690 * @ep0state: state of endpoint zero
691 * @link_state: link state
692 * @speed: device speed (super, high, full, low)
693 * @mem: points to start of memory which is used for this struct.
694 * @hwparams: copy of hwparams registers
695 * @root: debugfs root folder pointer
696 * @regset: debugfs pointer to regdump file
697 * @test_mode: true when we're entering a USB test mode
698 * @test_mode_nr: test feature selector
699 * @lpm_nyet_threshold: LPM NYET response threshold
700 * @hird_threshold: HIRD threshold
701 * @hsphy_interface: "utmi" or "ulpi"
702 * @delayed_status: true when gadget driver asks for delayed status
703 * @ep0_bounced: true when we used bounce buffer
704 * @ep0_expect_in: true when we expect a DATA IN transfer
705 * @has_hibernation: true when dwc3 was configured with Hibernation
706 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
707 * there's now way for software to detect this in runtime.
708 * @is_utmi_l1_suspend: the core asserts output signal
709 * 0 - utmi_sleep_n
710 * 1 - utmi_l1_suspend_n
711 * @is_fpga: true when we are using the FPGA board
712 * @needs_fifo_resize: not all users might want fifo resizing, flag it
713 * @pullups_connected: true when Run/Stop bit is set
714 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
715 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
716 * @start_config_issued: true when StartConfig command has been issued
717 * @three_stage_setup: set if we perform a three phase setup
718 * @usb3_lpm_capable: set if hadrware supports Link Power Management
719 * @disable_scramble_quirk: set if we enable the disable scramble quirk
720 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
721 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
722 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
723 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
724 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
725 * @lfps_filter_quirk: set if we enable LFPS filter quirk
726 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
727 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
728 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
729 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
730 * disabling the suspend signal to the PHY.
731 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
732 * @tx_de_emphasis: Tx de-emphasis value
733 * 0 - -6dB de-emphasis
734 * 1 - -3.5dB de-emphasis
735 * 2 - No de-emphasis
736 * 3 - Reserved
737 */
738struct dwc3 {
739 struct usb_ctrlrequest *ctrl_req;
740 struct dwc3_trb *ep0_trb;
741 void *ep0_bounce;
742 void *zlp_buf;
743 void *scratchbuf;
744 u8 *setup_buf;
745 dma_addr_t ctrl_req_addr;
746 dma_addr_t ep0_trb_addr;
747 dma_addr_t ep0_bounce_addr;
748 dma_addr_t scratch_addr;
749 struct dwc3_request ep0_usb_req;
750
751 /* device lock */
752 spinlock_t lock;
753
754 struct device *dev;
755
756 struct platform_device *xhci;
757 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
758
759 struct dwc3_event_buffer **ev_buffs;
760 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
761
762 struct usb_gadget gadget;
763 struct usb_gadget_driver *gadget_driver;
764
765 struct usb_phy *usb2_phy;
766 struct usb_phy *usb3_phy;
767
768 struct phy *usb2_generic_phy;
769 struct phy *usb3_generic_phy;
770
771 struct ulpi *ulpi;
772
773 void __iomem *regs;
774 size_t regs_size;
775
776 enum usb_dr_mode dr_mode;
777
778 /* used for suspend/resume */
779 u32 dcfg;
780 u32 gctl;
781
782 u32 nr_scratch;
783 u32 num_event_buffers;
784 u32 u1u2;
785 u32 maximum_speed;
786
787 /*
788 * All 3.1 IP version constants are greater than the 3.0 IP
789 * version constants. This works for most version checks in
790 * dwc3. However, in the future, this may not apply as
791 * features may be developed on newer versions of the 3.0 IP
792 * that are not in the 3.1 IP.
793 */
794 u32 revision;
795
796#define DWC3_REVISION_173A 0x5533173a
797#define DWC3_REVISION_175A 0x5533175a
798#define DWC3_REVISION_180A 0x5533180a
799#define DWC3_REVISION_183A 0x5533183a
800#define DWC3_REVISION_185A 0x5533185a
801#define DWC3_REVISION_187A 0x5533187a
802#define DWC3_REVISION_188A 0x5533188a
803#define DWC3_REVISION_190A 0x5533190a
804#define DWC3_REVISION_194A 0x5533194a
805#define DWC3_REVISION_200A 0x5533200a
806#define DWC3_REVISION_202A 0x5533202a
807#define DWC3_REVISION_210A 0x5533210a
808#define DWC3_REVISION_220A 0x5533220a
809#define DWC3_REVISION_230A 0x5533230a
810#define DWC3_REVISION_240A 0x5533240a
811#define DWC3_REVISION_250A 0x5533250a
812#define DWC3_REVISION_260A 0x5533260a
813#define DWC3_REVISION_270A 0x5533270a
814#define DWC3_REVISION_280A 0x5533280a
815
816/*
817 * NOTICE: we're using bit 31 as a "is usb 3.1" flag. This is really
818 * just so dwc31 revisions are always larger than dwc3.
819 */
820#define DWC3_REVISION_IS_DWC31 0x80000000
821#define DWC3_USB31_REVISION_110A (0x3131302a | DWC3_REVISION_IS_USB31)
822
823 enum dwc3_ep0_next ep0_next_event;
824 enum dwc3_ep0_state ep0state;
825 enum dwc3_link_state link_state;
826
827 u16 isoch_delay;
828 u16 u2sel;
829 u16 u2pel;
830 u8 u1sel;
831 u8 u1pel;
832
833 u8 speed;
834
835 u8 num_out_eps;
836 u8 num_in_eps;
837
838 void *mem;
839
840 struct dwc3_hwparams hwparams;
841 struct dentry *root;
842 struct debugfs_regset32 *regset;
843
844 u8 test_mode;
845 u8 test_mode_nr;
846 u8 lpm_nyet_threshold;
847 u8 hird_threshold;
848
849 const char *hsphy_interface;
850
851 unsigned delayed_status:1;
852 unsigned ep0_bounced:1;
853 unsigned ep0_expect_in:1;
854 unsigned has_hibernation:1;
855 unsigned has_lpm_erratum:1;
856 unsigned is_utmi_l1_suspend:1;
857 unsigned is_fpga:1;
858 unsigned needs_fifo_resize:1;
859 unsigned pullups_connected:1;
860 unsigned resize_fifos:1;
861 unsigned setup_packet_pending:1;
862 unsigned three_stage_setup:1;
863 unsigned usb3_lpm_capable:1;
864
865 unsigned disable_scramble_quirk:1;
866 unsigned u2exit_lfps_quirk:1;
867 unsigned u2ss_inp3_quirk:1;
868 unsigned req_p1p2p3_quirk:1;
869 unsigned del_p1p2p3_quirk:1;
870 unsigned del_phy_power_chg_quirk:1;
871 unsigned lfps_filter_quirk:1;
872 unsigned rx_detect_poll_quirk:1;
873 unsigned dis_u3_susphy_quirk:1;
874 unsigned dis_u2_susphy_quirk:1;
875 unsigned dis_enblslpm_quirk:1;
876
877 unsigned tx_de_emphasis_quirk:1;
878 unsigned tx_de_emphasis:2;
879};
880
881/* -------------------------------------------------------------------------- */
882
883/* -------------------------------------------------------------------------- */
884
885struct dwc3_event_type {
886 u32 is_devspec:1;
887 u32 type:7;
888 u32 reserved8_31:24;
889} __packed;
890
891#define DWC3_DEPEVT_XFERCOMPLETE 0x01
892#define DWC3_DEPEVT_XFERINPROGRESS 0x02
893#define DWC3_DEPEVT_XFERNOTREADY 0x03
894#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
895#define DWC3_DEPEVT_STREAMEVT 0x06
896#define DWC3_DEPEVT_EPCMDCMPLT 0x07
897
898/**
899 * struct dwc3_event_depvt - Device Endpoint Events
900 * @one_bit: indicates this is an endpoint event (not used)
901 * @endpoint_number: number of the endpoint
902 * @endpoint_event: The event we have:
903 * 0x00 - Reserved
904 * 0x01 - XferComplete
905 * 0x02 - XferInProgress
906 * 0x03 - XferNotReady
907 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
908 * 0x05 - Reserved
909 * 0x06 - StreamEvt
910 * 0x07 - EPCmdCmplt
911 * @reserved11_10: Reserved, don't use.
912 * @status: Indicates the status of the event. Refer to databook for
913 * more information.
914 * @parameters: Parameters of the current event. Refer to databook for
915 * more information.
916 */
917struct dwc3_event_depevt {
918 u32 one_bit:1;
919 u32 endpoint_number:5;
920 u32 endpoint_event:4;
921 u32 reserved11_10:2;
922 u32 status:4;
923
924/* Within XferNotReady */
925#define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
926
927/* Within XferComplete */
928#define DEPEVT_STATUS_BUSERR (1 << 0)
929#define DEPEVT_STATUS_SHORT (1 << 1)
930#define DEPEVT_STATUS_IOC (1 << 2)
931#define DEPEVT_STATUS_LST (1 << 3)
932
933/* Stream event only */
934#define DEPEVT_STREAMEVT_FOUND 1
935#define DEPEVT_STREAMEVT_NOTFOUND 2
936
937/* Control-only Status */
938#define DEPEVT_STATUS_CONTROL_DATA 1
939#define DEPEVT_STATUS_CONTROL_STATUS 2
940
941 u32 parameters:16;
942} __packed;
943
944/**
945 * struct dwc3_event_devt - Device Events
946 * @one_bit: indicates this is a non-endpoint event (not used)
947 * @device_event: indicates it's a device event. Should read as 0x00
948 * @type: indicates the type of device event.
949 * 0 - DisconnEvt
950 * 1 - USBRst
951 * 2 - ConnectDone
952 * 3 - ULStChng
953 * 4 - WkUpEvt
954 * 5 - Reserved
955 * 6 - EOPF
956 * 7 - SOF
957 * 8 - Reserved
958 * 9 - ErrticErr
959 * 10 - CmdCmplt
960 * 11 - EvntOverflow
961 * 12 - VndrDevTstRcved
962 * @reserved15_12: Reserved, not used
963 * @event_info: Information about this event
964 * @reserved31_25: Reserved, not used
965 */
966struct dwc3_event_devt {
967 u32 one_bit:1;
968 u32 device_event:7;
969 u32 type:4;
970 u32 reserved15_12:4;
971 u32 event_info:9;
972 u32 reserved31_25:7;
973} __packed;
974
975/**
976 * struct dwc3_event_gevt - Other Core Events
977 * @one_bit: indicates this is a non-endpoint event (not used)
978 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
979 * @phy_port_number: self-explanatory
980 * @reserved31_12: Reserved, not used.
981 */
982struct dwc3_event_gevt {
983 u32 one_bit:1;
984 u32 device_event:7;
985 u32 phy_port_number:4;
986 u32 reserved31_12:20;
987} __packed;
988
989/**
990 * union dwc3_event - representation of Event Buffer contents
991 * @raw: raw 32-bit event
992 * @type: the type of the event
993 * @depevt: Device Endpoint Event
994 * @devt: Device Event
995 * @gevt: Global Event
996 */
997union dwc3_event {
998 u32 raw;
999 struct dwc3_event_type type;
1000 struct dwc3_event_depevt depevt;
1001 struct dwc3_event_devt devt;
1002 struct dwc3_event_gevt gevt;
1003};
1004
1005/**
1006 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1007 * parameters
1008 * @param2: third parameter
1009 * @param1: second parameter
1010 * @param0: first parameter
1011 */
1012struct dwc3_gadget_ep_cmd_params {
1013 u32 param2;
1014 u32 param1;
1015 u32 param0;
1016};
1017
1018/*
1019 * DWC3 Features to be used as Driver Data
1020 */
1021
1022#define DWC3_HAS_PERIPHERAL BIT(0)
1023#define DWC3_HAS_XHCI BIT(1)
1024#define DWC3_HAS_OTG BIT(3)
1025
1026/* prototypes */
1027void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1028int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
1029
1030/* check whether we are on the DWC_usb31 core */
1031static inline bool dwc3_is_usb31(struct dwc3 *dwc)
1032{
1033 return !!(dwc->revision & DWC3_REVISION_IS_DWC31);
1034}
1035
1036#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1037int dwc3_host_init(struct dwc3 *dwc);
1038void dwc3_host_exit(struct dwc3 *dwc);
1039#else
1040static inline int dwc3_host_init(struct dwc3 *dwc)
1041{ return 0; }
1042static inline void dwc3_host_exit(struct dwc3 *dwc)
1043{ }
1044#endif
1045
1046#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1047int dwc3_gadget_init(struct dwc3 *dwc);
1048void dwc3_gadget_exit(struct dwc3 *dwc);
1049int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1050int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1051int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1052int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1053 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
1054int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param);
1055#else
1056static inline int dwc3_gadget_init(struct dwc3 *dwc)
1057{ return 0; }
1058static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1059{ }
1060static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1061{ return 0; }
1062static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1063{ return 0; }
1064static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1065 enum dwc3_link_state state)
1066{ return 0; }
1067
1068static inline int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
1069 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
1070{ return 0; }
1071static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1072 int cmd, u32 param)
1073{ return 0; }
1074#endif
1075
1076/* power management interface */
1077#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1078int dwc3_gadget_suspend(struct dwc3 *dwc);
1079int dwc3_gadget_resume(struct dwc3 *dwc);
1080#else
1081static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1082{
1083 return 0;
1084}
1085
1086static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1087{
1088 return 0;
1089}
1090#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1091
1092#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1093int dwc3_ulpi_init(struct dwc3 *dwc);
1094void dwc3_ulpi_exit(struct dwc3 *dwc);
1095#else
1096static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1097{ return 0; }
1098static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1099{ }
1100#endif
1101
1102#endif /* __DRIVERS_USB_DWC3_CORE_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * core.h - DesignWare USB3 DRD Core Header
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11#ifndef __DRIVERS_USB_DWC3_CORE_H
12#define __DRIVERS_USB_DWC3_CORE_H
13
14#include <linux/device.h>
15#include <linux/spinlock.h>
16#include <linux/mutex.h>
17#include <linux/ioport.h>
18#include <linux/list.h>
19#include <linux/bitops.h>
20#include <linux/dma-mapping.h>
21#include <linux/mm.h>
22#include <linux/debugfs.h>
23#include <linux/wait.h>
24#include <linux/workqueue.h>
25
26#include <linux/usb/ch9.h>
27#include <linux/usb/gadget.h>
28#include <linux/usb/otg.h>
29#include <linux/usb/role.h>
30#include <linux/ulpi/interface.h>
31
32#include <linux/phy/phy.h>
33
34#include <linux/power_supply.h>
35
36#define DWC3_MSG_MAX 500
37
38/* Global constants */
39#define DWC3_PULL_UP_TIMEOUT 500 /* ms */
40#define DWC3_BOUNCE_SIZE 1024 /* size of a superspeed bulk */
41#define DWC3_EP0_SETUP_SIZE 512
42#define DWC3_ENDPOINTS_NUM 32
43#define DWC3_XHCI_RESOURCES_NUM 2
44#define DWC3_ISOC_MAX_RETRIES 5
45
46#define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */
47#define DWC3_EVENT_BUFFERS_SIZE 4096
48#define DWC3_EVENT_TYPE_MASK 0xfe
49
50#define DWC3_EVENT_TYPE_DEV 0
51#define DWC3_EVENT_TYPE_CARKIT 3
52#define DWC3_EVENT_TYPE_I2C 4
53
54#define DWC3_DEVICE_EVENT_DISCONNECT 0
55#define DWC3_DEVICE_EVENT_RESET 1
56#define DWC3_DEVICE_EVENT_CONNECT_DONE 2
57#define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
58#define DWC3_DEVICE_EVENT_WAKEUP 4
59#define DWC3_DEVICE_EVENT_HIBER_REQ 5
60#define DWC3_DEVICE_EVENT_SUSPEND 6
61#define DWC3_DEVICE_EVENT_SOF 7
62#define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
63#define DWC3_DEVICE_EVENT_CMD_CMPL 10
64#define DWC3_DEVICE_EVENT_OVERFLOW 11
65
66/* Controller's role while using the OTG block */
67#define DWC3_OTG_ROLE_IDLE 0
68#define DWC3_OTG_ROLE_HOST 1
69#define DWC3_OTG_ROLE_DEVICE 2
70
71#define DWC3_GEVNTCOUNT_MASK 0xfffc
72#define DWC3_GEVNTCOUNT_EHB BIT(31)
73#define DWC3_GSNPSID_MASK 0xffff0000
74#define DWC3_GSNPSREV_MASK 0xffff
75#define DWC3_GSNPS_ID(p) (((p) & DWC3_GSNPSID_MASK) >> 16)
76
77/* DWC3 registers memory space boundries */
78#define DWC3_XHCI_REGS_START 0x0
79#define DWC3_XHCI_REGS_END 0x7fff
80#define DWC3_GLOBALS_REGS_START 0xc100
81#define DWC3_GLOBALS_REGS_END 0xc6ff
82#define DWC3_DEVICE_REGS_START 0xc700
83#define DWC3_DEVICE_REGS_END 0xcbff
84#define DWC3_OTG_REGS_START 0xcc00
85#define DWC3_OTG_REGS_END 0xccff
86
87/* Global Registers */
88#define DWC3_GSBUSCFG0 0xc100
89#define DWC3_GSBUSCFG1 0xc104
90#define DWC3_GTXTHRCFG 0xc108
91#define DWC3_GRXTHRCFG 0xc10c
92#define DWC3_GCTL 0xc110
93#define DWC3_GEVTEN 0xc114
94#define DWC3_GSTS 0xc118
95#define DWC3_GUCTL1 0xc11c
96#define DWC3_GSNPSID 0xc120
97#define DWC3_GGPIO 0xc124
98#define DWC3_GUID 0xc128
99#define DWC3_GUCTL 0xc12c
100#define DWC3_GBUSERRADDR0 0xc130
101#define DWC3_GBUSERRADDR1 0xc134
102#define DWC3_GPRTBIMAP0 0xc138
103#define DWC3_GPRTBIMAP1 0xc13c
104#define DWC3_GHWPARAMS0 0xc140
105#define DWC3_GHWPARAMS1 0xc144
106#define DWC3_GHWPARAMS2 0xc148
107#define DWC3_GHWPARAMS3 0xc14c
108#define DWC3_GHWPARAMS4 0xc150
109#define DWC3_GHWPARAMS5 0xc154
110#define DWC3_GHWPARAMS6 0xc158
111#define DWC3_GHWPARAMS7 0xc15c
112#define DWC3_GDBGFIFOSPACE 0xc160
113#define DWC3_GDBGLTSSM 0xc164
114#define DWC3_GDBGBMU 0xc16c
115#define DWC3_GDBGLSPMUX 0xc170
116#define DWC3_GDBGLSP 0xc174
117#define DWC3_GDBGEPINFO0 0xc178
118#define DWC3_GDBGEPINFO1 0xc17c
119#define DWC3_GPRTBIMAP_HS0 0xc180
120#define DWC3_GPRTBIMAP_HS1 0xc184
121#define DWC3_GPRTBIMAP_FS0 0xc188
122#define DWC3_GPRTBIMAP_FS1 0xc18c
123#define DWC3_GUCTL2 0xc19c
124
125#define DWC3_VER_NUMBER 0xc1a0
126#define DWC3_VER_TYPE 0xc1a4
127
128#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04))
129#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04))
130
131#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04))
132
133#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04))
134
135#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04))
136#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04))
137
138#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10))
139#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10))
140#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10))
141#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10))
142
143#define DWC3_GHWPARAMS8 0xc600
144#define DWC3_GUCTL3 0xc60c
145#define DWC3_GFLADJ 0xc630
146#define DWC3_GHWPARAMS9 0xc6e0
147
148/* Device Registers */
149#define DWC3_DCFG 0xc700
150#define DWC3_DCTL 0xc704
151#define DWC3_DEVTEN 0xc708
152#define DWC3_DSTS 0xc70c
153#define DWC3_DGCMDPAR 0xc710
154#define DWC3_DGCMD 0xc714
155#define DWC3_DALEPENA 0xc720
156#define DWC3_DCFG1 0xc740 /* DWC_usb32 only */
157
158#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10))
159#define DWC3_DEPCMDPAR2 0x00
160#define DWC3_DEPCMDPAR1 0x04
161#define DWC3_DEPCMDPAR0 0x08
162#define DWC3_DEPCMD 0x0c
163
164#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4))
165
166/* OTG Registers */
167#define DWC3_OCFG 0xcc00
168#define DWC3_OCTL 0xcc04
169#define DWC3_OEVT 0xcc08
170#define DWC3_OEVTEN 0xcc0C
171#define DWC3_OSTS 0xcc10
172
173/* Bit fields */
174
175/* Global SoC Bus Configuration INCRx Register 0 */
176#define DWC3_GSBUSCFG0_INCR256BRSTENA (1 << 7) /* INCR256 burst */
177#define DWC3_GSBUSCFG0_INCR128BRSTENA (1 << 6) /* INCR128 burst */
178#define DWC3_GSBUSCFG0_INCR64BRSTENA (1 << 5) /* INCR64 burst */
179#define DWC3_GSBUSCFG0_INCR32BRSTENA (1 << 4) /* INCR32 burst */
180#define DWC3_GSBUSCFG0_INCR16BRSTENA (1 << 3) /* INCR16 burst */
181#define DWC3_GSBUSCFG0_INCR8BRSTENA (1 << 2) /* INCR8 burst */
182#define DWC3_GSBUSCFG0_INCR4BRSTENA (1 << 1) /* INCR4 burst */
183#define DWC3_GSBUSCFG0_INCRBRSTENA (1 << 0) /* undefined length enable */
184#define DWC3_GSBUSCFG0_INCRBRST_MASK 0xff
185
186/* Global Debug LSP MUX Select */
187#define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
188#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
189#define DWC3_GDBGLSPMUX_DEVSELECT(n) (((n) & 0xf) << 4)
190#define DWC3_GDBGLSPMUX_EPSELECT(n) ((n) & 0xf)
191
192/* Global Debug Queue/FIFO Space Available Register */
193#define DWC3_GDBGFIFOSPACE_NUM(n) ((n) & 0x1f)
194#define DWC3_GDBGFIFOSPACE_TYPE(n) (((n) << 5) & 0x1e0)
195#define DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(n) (((n) >> 16) & 0xffff)
196
197#define DWC3_TXFIFO 0
198#define DWC3_RXFIFO 1
199#define DWC3_TXREQQ 2
200#define DWC3_RXREQQ 3
201#define DWC3_RXINFOQ 4
202#define DWC3_PSTATQ 5
203#define DWC3_DESCFETCHQ 6
204#define DWC3_EVENTQ 7
205#define DWC3_AUXEVENTQ 8
206
207/* Global RX Threshold Configuration Register */
208#define DWC3_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 19)
209#define DWC3_GRXTHRCFG_RXPKTCNT(n) (((n) & 0xf) << 24)
210#define DWC3_GRXTHRCFG_PKTCNTSEL BIT(29)
211
212/* Global RX Threshold Configuration Register for DWC_usb31 only */
213#define DWC31_GRXTHRCFG_MAXRXBURSTSIZE(n) (((n) & 0x1f) << 16)
214#define DWC31_GRXTHRCFG_RXPKTCNT(n) (((n) & 0x1f) << 21)
215#define DWC31_GRXTHRCFG_PKTCNTSEL BIT(26)
216#define DWC31_RXTHRNUMPKTSEL_HS_PRD BIT(15)
217#define DWC31_RXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
218#define DWC31_RXTHRNUMPKTSEL_PRD BIT(10)
219#define DWC31_RXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
220#define DWC31_MAXRXBURSTSIZE_PRD(n) ((n) & 0x1f)
221
222/* Global TX Threshold Configuration Register for DWC_usb31 only */
223#define DWC31_GTXTHRCFG_MAXTXBURSTSIZE(n) (((n) & 0x1f) << 16)
224#define DWC31_GTXTHRCFG_TXPKTCNT(n) (((n) & 0x1f) << 21)
225#define DWC31_GTXTHRCFG_PKTCNTSEL BIT(26)
226#define DWC31_TXTHRNUMPKTSEL_HS_PRD BIT(15)
227#define DWC31_TXTHRNUMPKT_HS_PRD(n) (((n) & 0x3) << 13)
228#define DWC31_TXTHRNUMPKTSEL_PRD BIT(10)
229#define DWC31_TXTHRNUMPKT_PRD(n) (((n) & 0x1f) << 5)
230#define DWC31_MAXTXBURSTSIZE_PRD(n) ((n) & 0x1f)
231
232/* Global Configuration Register */
233#define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
234#define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19)
235#define DWC3_GCTL_U2RSTECN BIT(16)
236#define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
237#define DWC3_GCTL_CLK_BUS (0)
238#define DWC3_GCTL_CLK_PIPE (1)
239#define DWC3_GCTL_CLK_PIPEHALF (2)
240#define DWC3_GCTL_CLK_MASK (3)
241
242#define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
243#define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
244#define DWC3_GCTL_PRTCAP_HOST 1
245#define DWC3_GCTL_PRTCAP_DEVICE 2
246#define DWC3_GCTL_PRTCAP_OTG 3
247
248#define DWC3_GCTL_CORESOFTRESET BIT(11)
249#define DWC3_GCTL_SOFITPSYNC BIT(10)
250#define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
251#define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
252#define DWC3_GCTL_DISSCRAMBLE BIT(3)
253#define DWC3_GCTL_U2EXIT_LFPS BIT(2)
254#define DWC3_GCTL_GBLHIBERNATIONEN BIT(1)
255#define DWC3_GCTL_DSBLCLKGTNG BIT(0)
256
257/* Global User Control Register */
258#define DWC3_GUCTL_HSTINAUTORETRY BIT(14)
259
260/* Global User Control 1 Register */
261#define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT BIT(31)
262#define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28)
263#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26)
264#define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24)
265#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17)
266#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10)
267
268/* Global Status Register */
269#define DWC3_GSTS_OTG_IP BIT(10)
270#define DWC3_GSTS_BC_IP BIT(9)
271#define DWC3_GSTS_ADP_IP BIT(8)
272#define DWC3_GSTS_HOST_IP BIT(7)
273#define DWC3_GSTS_DEVICE_IP BIT(6)
274#define DWC3_GSTS_CSR_TIMEOUT BIT(5)
275#define DWC3_GSTS_BUS_ERR_ADDR_VLD BIT(4)
276#define DWC3_GSTS_CURMOD(n) ((n) & 0x3)
277#define DWC3_GSTS_CURMOD_DEVICE 0
278#define DWC3_GSTS_CURMOD_HOST 1
279
280/* Global USB2 PHY Configuration Register */
281#define DWC3_GUSB2PHYCFG_PHYSOFTRST BIT(31)
282#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS BIT(30)
283#define DWC3_GUSB2PHYCFG_SUSPHY BIT(6)
284#define DWC3_GUSB2PHYCFG_ULPI_UTMI BIT(4)
285#define DWC3_GUSB2PHYCFG_ENBLSLPM BIT(8)
286#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
287#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
288#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
289#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
290#define USBTRDTIM_UTMI_8_BIT 9
291#define USBTRDTIM_UTMI_16_BIT 5
292#define UTMI_PHYIF_16_BIT 1
293#define UTMI_PHYIF_8_BIT 0
294
295/* Global USB2 PHY Vendor Control Register */
296#define DWC3_GUSB2PHYACC_NEWREGREQ BIT(25)
297#define DWC3_GUSB2PHYACC_DONE BIT(24)
298#define DWC3_GUSB2PHYACC_BUSY BIT(23)
299#define DWC3_GUSB2PHYACC_WRITE BIT(22)
300#define DWC3_GUSB2PHYACC_ADDR(n) (n << 16)
301#define DWC3_GUSB2PHYACC_EXTEND_ADDR(n) (n << 8)
302#define DWC3_GUSB2PHYACC_DATA(n) (n & 0xff)
303
304/* Global USB3 PIPE Control Register */
305#define DWC3_GUSB3PIPECTL_PHYSOFTRST BIT(31)
306#define DWC3_GUSB3PIPECTL_U2SSINP3OK BIT(29)
307#define DWC3_GUSB3PIPECTL_DISRXDETINP3 BIT(28)
308#define DWC3_GUSB3PIPECTL_UX_EXIT_PX BIT(27)
309#define DWC3_GUSB3PIPECTL_REQP1P2P3 BIT(24)
310#define DWC3_GUSB3PIPECTL_DEP1P2P3(n) ((n) << 19)
311#define DWC3_GUSB3PIPECTL_DEP1P2P3_MASK DWC3_GUSB3PIPECTL_DEP1P2P3(7)
312#define DWC3_GUSB3PIPECTL_DEP1P2P3_EN DWC3_GUSB3PIPECTL_DEP1P2P3(1)
313#define DWC3_GUSB3PIPECTL_DEPOCHANGE BIT(18)
314#define DWC3_GUSB3PIPECTL_SUSPHY BIT(17)
315#define DWC3_GUSB3PIPECTL_LFPSFILT BIT(9)
316#define DWC3_GUSB3PIPECTL_RX_DETOPOLL BIT(8)
317#define DWC3_GUSB3PIPECTL_TX_DEEPH_MASK DWC3_GUSB3PIPECTL_TX_DEEPH(3)
318#define DWC3_GUSB3PIPECTL_TX_DEEPH(n) ((n) << 1)
319
320/* Global TX Fifo Size Register */
321#define DWC31_GTXFIFOSIZ_TXFRAMNUM BIT(15) /* DWC_usb31 only */
322#define DWC31_GTXFIFOSIZ_TXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
323#define DWC3_GTXFIFOSIZ_TXFDEP(n) ((n) & 0xffff)
324#define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
325
326/* Global RX Fifo Size Register */
327#define DWC31_GRXFIFOSIZ_RXFDEP(n) ((n) & 0x7fff) /* DWC_usb31 only */
328#define DWC3_GRXFIFOSIZ_RXFDEP(n) ((n) & 0xffff)
329
330/* Global Event Size Registers */
331#define DWC3_GEVNTSIZ_INTMASK BIT(31)
332#define DWC3_GEVNTSIZ_SIZE(n) ((n) & 0xffff)
333
334/* Global HWPARAMS0 Register */
335#define DWC3_GHWPARAMS0_MODE(n) ((n) & 0x3)
336#define DWC3_GHWPARAMS0_MODE_GADGET 0
337#define DWC3_GHWPARAMS0_MODE_HOST 1
338#define DWC3_GHWPARAMS0_MODE_DRD 2
339#define DWC3_GHWPARAMS0_MBUS_TYPE(n) (((n) >> 3) & 0x7)
340#define DWC3_GHWPARAMS0_SBUS_TYPE(n) (((n) >> 6) & 0x3)
341#define DWC3_GHWPARAMS0_MDWIDTH(n) (((n) >> 8) & 0xff)
342#define DWC3_GHWPARAMS0_SDWIDTH(n) (((n) >> 16) & 0xff)
343#define DWC3_GHWPARAMS0_AWIDTH(n) (((n) >> 24) & 0xff)
344
345/* Global HWPARAMS1 Register */
346#define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
347#define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
348#define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
349#define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
350#define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
351#define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
352#define DWC3_GHWPARAMS1_ENDBC BIT(31)
353
354/* Global HWPARAMS3 Register */
355#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3)
356#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0
357#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN1 1
358#define DWC3_GHWPARAMS3_SSPHY_IFC_GEN2 2 /* DWC_usb31 only */
359#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
360#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0
361#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1
362#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2
363#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3
364#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
365#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0
366#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1
367
368/* Global HWPARAMS4 Register */
369#define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
370#define DWC3_MAX_HIBER_SCRATCHBUFS 15
371
372/* Global HWPARAMS6 Register */
373#define DWC3_GHWPARAMS6_BCSUPPORT BIT(14)
374#define DWC3_GHWPARAMS6_OTG3SUPPORT BIT(13)
375#define DWC3_GHWPARAMS6_ADPSUPPORT BIT(12)
376#define DWC3_GHWPARAMS6_HNPSUPPORT BIT(11)
377#define DWC3_GHWPARAMS6_SRPSUPPORT BIT(10)
378#define DWC3_GHWPARAMS6_EN_FPGA BIT(7)
379
380/* DWC_usb32 only */
381#define DWC3_GHWPARAMS6_MDWIDTH(n) ((n) & (0x3 << 8))
382
383/* Global HWPARAMS7 Register */
384#define DWC3_GHWPARAMS7_RAM1_DEPTH(n) ((n) & 0xffff)
385#define DWC3_GHWPARAMS7_RAM2_DEPTH(n) (((n) >> 16) & 0xffff)
386
387/* Global HWPARAMS9 Register */
388#define DWC3_GHWPARAMS9_DEV_TXF_FLUSH_BYPASS BIT(0)
389#define DWC3_GHWPARAMS9_DEV_MST BIT(1)
390
391/* Global Frame Length Adjustment Register */
392#define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7)
393#define DWC3_GFLADJ_30MHZ_MASK 0x3f
394#define DWC3_GFLADJ_REFCLK_FLADJ_MASK GENMASK(21, 8)
395#define DWC3_GFLADJ_REFCLK_LPM_SEL BIT(23)
396#define DWC3_GFLADJ_240MHZDECR GENMASK(30, 24)
397#define DWC3_GFLADJ_240MHZDECR_PLS1 BIT(31)
398
399/* Global User Control Register*/
400#define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000
401#define DWC3_GUCTL_REFCLKPER_SEL 22
402
403/* Global User Control Register 2 */
404#define DWC3_GUCTL2_RST_ACTBITLATER BIT(14)
405
406/* Global User Control Register 3 */
407#define DWC3_GUCTL3_SPLITDISABLE BIT(14)
408
409/* Device Configuration Register */
410#define DWC3_DCFG_NUMLANES(n) (((n) & 0x3) << 30) /* DWC_usb32 only */
411
412#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
413#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
414
415#define DWC3_DCFG_SPEED_MASK (7 << 0)
416#define DWC3_DCFG_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
417#define DWC3_DCFG_SUPERSPEED (4 << 0)
418#define DWC3_DCFG_HIGHSPEED (0 << 0)
419#define DWC3_DCFG_FULLSPEED BIT(0)
420
421#define DWC3_DCFG_NUMP_SHIFT 17
422#define DWC3_DCFG_NUMP(n) (((n) >> DWC3_DCFG_NUMP_SHIFT) & 0x1f)
423#define DWC3_DCFG_NUMP_MASK (0x1f << DWC3_DCFG_NUMP_SHIFT)
424#define DWC3_DCFG_LPM_CAP BIT(22)
425#define DWC3_DCFG_IGNSTRMPP BIT(23)
426
427/* Device Control Register */
428#define DWC3_DCTL_RUN_STOP BIT(31)
429#define DWC3_DCTL_CSFTRST BIT(30)
430#define DWC3_DCTL_LSFTRST BIT(29)
431
432#define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
433#define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
434
435#define DWC3_DCTL_APPL1RES BIT(23)
436
437/* These apply for core versions 1.87a and earlier */
438#define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
439#define DWC3_DCTL_TRGTULST(n) ((n) << 17)
440#define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
441#define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
442#define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
443#define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
444#define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
445
446/* These apply for core versions 1.94a and later */
447#define DWC3_DCTL_NYET_THRES(n) (((n) & 0xf) << 20)
448
449#define DWC3_DCTL_KEEP_CONNECT BIT(19)
450#define DWC3_DCTL_L1_HIBER_EN BIT(18)
451#define DWC3_DCTL_CRS BIT(17)
452#define DWC3_DCTL_CSS BIT(16)
453
454#define DWC3_DCTL_INITU2ENA BIT(12)
455#define DWC3_DCTL_ACCEPTU2ENA BIT(11)
456#define DWC3_DCTL_INITU1ENA BIT(10)
457#define DWC3_DCTL_ACCEPTU1ENA BIT(9)
458#define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
459
460#define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
461#define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
462
463#define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
464#define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
465#define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
466#define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
467#define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
468#define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
469#define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
470
471/* Device Event Enable Register */
472#define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN BIT(12)
473#define DWC3_DEVTEN_EVNTOVERFLOWEN BIT(11)
474#define DWC3_DEVTEN_CMDCMPLTEN BIT(10)
475#define DWC3_DEVTEN_ERRTICERREN BIT(9)
476#define DWC3_DEVTEN_SOFEN BIT(7)
477#define DWC3_DEVTEN_U3L2L1SUSPEN BIT(6)
478#define DWC3_DEVTEN_HIBERNATIONREQEVTEN BIT(5)
479#define DWC3_DEVTEN_WKUPEVTEN BIT(4)
480#define DWC3_DEVTEN_ULSTCNGEN BIT(3)
481#define DWC3_DEVTEN_CONNECTDONEEN BIT(2)
482#define DWC3_DEVTEN_USBRSTEN BIT(1)
483#define DWC3_DEVTEN_DISCONNEVTEN BIT(0)
484
485#define DWC3_DSTS_CONNLANES(n) (((n) >> 30) & 0x3) /* DWC_usb32 only */
486
487/* Device Status Register */
488#define DWC3_DSTS_DCNRD BIT(29)
489
490/* This applies for core versions 1.87a and earlier */
491#define DWC3_DSTS_PWRUPREQ BIT(24)
492
493/* These apply for core versions 1.94a and later */
494#define DWC3_DSTS_RSS BIT(25)
495#define DWC3_DSTS_SSS BIT(24)
496
497#define DWC3_DSTS_COREIDLE BIT(23)
498#define DWC3_DSTS_DEVCTRLHLT BIT(22)
499
500#define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
501#define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
502
503#define DWC3_DSTS_RXFIFOEMPTY BIT(17)
504
505#define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
506#define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
507
508#define DWC3_DSTS_CONNECTSPD (7 << 0)
509
510#define DWC3_DSTS_SUPERSPEED_PLUS (5 << 0) /* DWC_usb31 only */
511#define DWC3_DSTS_SUPERSPEED (4 << 0)
512#define DWC3_DSTS_HIGHSPEED (0 << 0)
513#define DWC3_DSTS_FULLSPEED BIT(0)
514
515/* Device Generic Command Register */
516#define DWC3_DGCMD_SET_LMP 0x01
517#define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
518#define DWC3_DGCMD_XMIT_FUNCTION 0x03
519
520/* These apply for core versions 1.94a and later */
521#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
522#define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
523
524#define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
525#define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
526#define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
527#define DWC3_DGCMD_SET_ENDPOINT_PRIME 0x0d
528#define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
529
530#define DWC3_DGCMD_STATUS(n) (((n) >> 12) & 0x0F)
531#define DWC3_DGCMD_CMDACT BIT(10)
532#define DWC3_DGCMD_CMDIOC BIT(8)
533
534/* Device Generic Command Parameter Register */
535#define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT BIT(0)
536#define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
537#define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
538#define DWC3_DGCMDPAR_TX_FIFO BIT(5)
539#define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
540#define DWC3_DGCMDPAR_LOOPBACK_ENA BIT(0)
541
542/* Device Endpoint Command Register */
543#define DWC3_DEPCMD_PARAM_SHIFT 16
544#define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
545#define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
546#define DWC3_DEPCMD_STATUS(x) (((x) >> 12) & 0x0F)
547#define DWC3_DEPCMD_HIPRI_FORCERM BIT(11)
548#define DWC3_DEPCMD_CLEARPENDIN BIT(11)
549#define DWC3_DEPCMD_CMDACT BIT(10)
550#define DWC3_DEPCMD_CMDIOC BIT(8)
551
552#define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
553#define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
554#define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
555#define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
556#define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
557#define DWC3_DEPCMD_SETSTALL (0x04 << 0)
558/* This applies for core versions 1.90a and earlier */
559#define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
560/* This applies for core versions 1.94a and later */
561#define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
562#define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
563#define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
564
565#define DWC3_DEPCMD_CMD(x) ((x) & 0xf)
566
567/* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
568#define DWC3_DALEPENA_EP(n) BIT(n)
569
570/* DWC_usb32 DCFG1 config */
571#define DWC3_DCFG1_DIS_MST_ENH BIT(1)
572
573#define DWC3_DEPCMD_TYPE_CONTROL 0
574#define DWC3_DEPCMD_TYPE_ISOC 1
575#define DWC3_DEPCMD_TYPE_BULK 2
576#define DWC3_DEPCMD_TYPE_INTR 3
577
578#define DWC3_DEV_IMOD_COUNT_SHIFT 16
579#define DWC3_DEV_IMOD_COUNT_MASK (0xffff << 16)
580#define DWC3_DEV_IMOD_INTERVAL_SHIFT 0
581#define DWC3_DEV_IMOD_INTERVAL_MASK (0xffff << 0)
582
583/* OTG Configuration Register */
584#define DWC3_OCFG_DISPWRCUTTOFF BIT(5)
585#define DWC3_OCFG_HIBDISMASK BIT(4)
586#define DWC3_OCFG_SFTRSTMASK BIT(3)
587#define DWC3_OCFG_OTGVERSION BIT(2)
588#define DWC3_OCFG_HNPCAP BIT(1)
589#define DWC3_OCFG_SRPCAP BIT(0)
590
591/* OTG CTL Register */
592#define DWC3_OCTL_OTG3GOERR BIT(7)
593#define DWC3_OCTL_PERIMODE BIT(6)
594#define DWC3_OCTL_PRTPWRCTL BIT(5)
595#define DWC3_OCTL_HNPREQ BIT(4)
596#define DWC3_OCTL_SESREQ BIT(3)
597#define DWC3_OCTL_TERMSELIDPULSE BIT(2)
598#define DWC3_OCTL_DEVSETHNPEN BIT(1)
599#define DWC3_OCTL_HSTSETHNPEN BIT(0)
600
601/* OTG Event Register */
602#define DWC3_OEVT_DEVICEMODE BIT(31)
603#define DWC3_OEVT_XHCIRUNSTPSET BIT(27)
604#define DWC3_OEVT_DEVRUNSTPSET BIT(26)
605#define DWC3_OEVT_HIBENTRY BIT(25)
606#define DWC3_OEVT_CONIDSTSCHNG BIT(24)
607#define DWC3_OEVT_HRRCONFNOTIF BIT(23)
608#define DWC3_OEVT_HRRINITNOTIF BIT(22)
609#define DWC3_OEVT_ADEVIDLE BIT(21)
610#define DWC3_OEVT_ADEVBHOSTEND BIT(20)
611#define DWC3_OEVT_ADEVHOST BIT(19)
612#define DWC3_OEVT_ADEVHNPCHNG BIT(18)
613#define DWC3_OEVT_ADEVSRPDET BIT(17)
614#define DWC3_OEVT_ADEVSESSENDDET BIT(16)
615#define DWC3_OEVT_BDEVBHOSTEND BIT(11)
616#define DWC3_OEVT_BDEVHNPCHNG BIT(10)
617#define DWC3_OEVT_BDEVSESSVLDDET BIT(9)
618#define DWC3_OEVT_BDEVVBUSCHNG BIT(8)
619#define DWC3_OEVT_BSESSVLD BIT(3)
620#define DWC3_OEVT_HSTNEGSTS BIT(2)
621#define DWC3_OEVT_SESREQSTS BIT(1)
622#define DWC3_OEVT_ERROR BIT(0)
623
624/* OTG Event Enable Register */
625#define DWC3_OEVTEN_XHCIRUNSTPSETEN BIT(27)
626#define DWC3_OEVTEN_DEVRUNSTPSETEN BIT(26)
627#define DWC3_OEVTEN_HIBENTRYEN BIT(25)
628#define DWC3_OEVTEN_CONIDSTSCHNGEN BIT(24)
629#define DWC3_OEVTEN_HRRCONFNOTIFEN BIT(23)
630#define DWC3_OEVTEN_HRRINITNOTIFEN BIT(22)
631#define DWC3_OEVTEN_ADEVIDLEEN BIT(21)
632#define DWC3_OEVTEN_ADEVBHOSTENDEN BIT(20)
633#define DWC3_OEVTEN_ADEVHOSTEN BIT(19)
634#define DWC3_OEVTEN_ADEVHNPCHNGEN BIT(18)
635#define DWC3_OEVTEN_ADEVSRPDETEN BIT(17)
636#define DWC3_OEVTEN_ADEVSESSENDDETEN BIT(16)
637#define DWC3_OEVTEN_BDEVBHOSTENDEN BIT(11)
638#define DWC3_OEVTEN_BDEVHNPCHNGEN BIT(10)
639#define DWC3_OEVTEN_BDEVSESSVLDDETEN BIT(9)
640#define DWC3_OEVTEN_BDEVVBUSCHNGEN BIT(8)
641
642/* OTG Status Register */
643#define DWC3_OSTS_DEVRUNSTP BIT(13)
644#define DWC3_OSTS_XHCIRUNSTP BIT(12)
645#define DWC3_OSTS_PERIPHERALSTATE BIT(4)
646#define DWC3_OSTS_XHCIPRTPOWER BIT(3)
647#define DWC3_OSTS_BSESVLD BIT(2)
648#define DWC3_OSTS_VBUSVLD BIT(1)
649#define DWC3_OSTS_CONIDSTS BIT(0)
650
651/* Structures */
652
653struct dwc3_trb;
654
655/**
656 * struct dwc3_event_buffer - Software event buffer representation
657 * @buf: _THE_ buffer
658 * @cache: The buffer cache used in the threaded interrupt
659 * @length: size of this buffer
660 * @lpos: event offset
661 * @count: cache of last read event count register
662 * @flags: flags related to this event buffer
663 * @dma: dma_addr_t
664 * @dwc: pointer to DWC controller
665 */
666struct dwc3_event_buffer {
667 void *buf;
668 void *cache;
669 unsigned int length;
670 unsigned int lpos;
671 unsigned int count;
672 unsigned int flags;
673
674#define DWC3_EVENT_PENDING BIT(0)
675
676 dma_addr_t dma;
677
678 struct dwc3 *dwc;
679};
680
681#define DWC3_EP_FLAG_STALLED BIT(0)
682#define DWC3_EP_FLAG_WEDGED BIT(1)
683
684#define DWC3_EP_DIRECTION_TX true
685#define DWC3_EP_DIRECTION_RX false
686
687#define DWC3_TRB_NUM 256
688
689/**
690 * struct dwc3_ep - device side endpoint representation
691 * @endpoint: usb endpoint
692 * @cancelled_list: list of cancelled requests for this endpoint
693 * @pending_list: list of pending requests for this endpoint
694 * @started_list: list of started requests on this endpoint
695 * @regs: pointer to first endpoint register
696 * @trb_pool: array of transaction buffers
697 * @trb_pool_dma: dma address of @trb_pool
698 * @trb_enqueue: enqueue 'pointer' into TRB array
699 * @trb_dequeue: dequeue 'pointer' into TRB array
700 * @dwc: pointer to DWC controller
701 * @saved_state: ep state saved during hibernation
702 * @flags: endpoint flags (wedged, stalled, ...)
703 * @number: endpoint number (1 - 15)
704 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
705 * @resource_index: Resource transfer index
706 * @frame_number: set to the frame number we want this transfer to start (ISOC)
707 * @interval: the interval on which the ISOC transfer is started
708 * @name: a human readable name e.g. ep1out-bulk
709 * @direction: true for TX, false for RX
710 * @stream_capable: true when streams are enabled
711 * @combo_num: the test combination BIT[15:14] of the frame number to test
712 * isochronous START TRANSFER command failure workaround
713 * @start_cmd_status: the status of testing START TRANSFER command with
714 * combo_num = 'b00
715 */
716struct dwc3_ep {
717 struct usb_ep endpoint;
718 struct list_head cancelled_list;
719 struct list_head pending_list;
720 struct list_head started_list;
721
722 void __iomem *regs;
723
724 struct dwc3_trb *trb_pool;
725 dma_addr_t trb_pool_dma;
726 struct dwc3 *dwc;
727
728 u32 saved_state;
729 unsigned int flags;
730#define DWC3_EP_ENABLED BIT(0)
731#define DWC3_EP_STALL BIT(1)
732#define DWC3_EP_WEDGE BIT(2)
733#define DWC3_EP_TRANSFER_STARTED BIT(3)
734#define DWC3_EP_END_TRANSFER_PENDING BIT(4)
735#define DWC3_EP_PENDING_REQUEST BIT(5)
736#define DWC3_EP_DELAY_START BIT(6)
737#define DWC3_EP_WAIT_TRANSFER_COMPLETE BIT(7)
738#define DWC3_EP_IGNORE_NEXT_NOSTREAM BIT(8)
739#define DWC3_EP_FORCE_RESTART_STREAM BIT(9)
740#define DWC3_EP_FIRST_STREAM_PRIMED BIT(10)
741#define DWC3_EP_PENDING_CLEAR_STALL BIT(11)
742#define DWC3_EP_TXFIFO_RESIZED BIT(12)
743#define DWC3_EP_DELAY_STOP BIT(13)
744
745 /* This last one is specific to EP0 */
746#define DWC3_EP0_DIR_IN BIT(31)
747
748 /*
749 * IMPORTANT: we *know* we have 256 TRBs in our @trb_pool, so we will
750 * use a u8 type here. If anybody decides to increase number of TRBs to
751 * anything larger than 256 - I can't see why people would want to do
752 * this though - then this type needs to be changed.
753 *
754 * By using u8 types we ensure that our % operator when incrementing
755 * enqueue and dequeue get optimized away by the compiler.
756 */
757 u8 trb_enqueue;
758 u8 trb_dequeue;
759
760 u8 number;
761 u8 type;
762 u8 resource_index;
763 u32 frame_number;
764 u32 interval;
765
766 char name[20];
767
768 unsigned direction:1;
769 unsigned stream_capable:1;
770
771 /* For isochronous START TRANSFER workaround only */
772 u8 combo_num;
773 int start_cmd_status;
774};
775
776enum dwc3_phy {
777 DWC3_PHY_UNKNOWN = 0,
778 DWC3_PHY_USB3,
779 DWC3_PHY_USB2,
780};
781
782enum dwc3_ep0_next {
783 DWC3_EP0_UNKNOWN = 0,
784 DWC3_EP0_COMPLETE,
785 DWC3_EP0_NRDY_DATA,
786 DWC3_EP0_NRDY_STATUS,
787};
788
789enum dwc3_ep0_state {
790 EP0_UNCONNECTED = 0,
791 EP0_SETUP_PHASE,
792 EP0_DATA_PHASE,
793 EP0_STATUS_PHASE,
794};
795
796enum dwc3_link_state {
797 /* In SuperSpeed */
798 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
799 DWC3_LINK_STATE_U1 = 0x01,
800 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
801 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
802 DWC3_LINK_STATE_SS_DIS = 0x04,
803 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
804 DWC3_LINK_STATE_SS_INACT = 0x06,
805 DWC3_LINK_STATE_POLL = 0x07,
806 DWC3_LINK_STATE_RECOV = 0x08,
807 DWC3_LINK_STATE_HRESET = 0x09,
808 DWC3_LINK_STATE_CMPLY = 0x0a,
809 DWC3_LINK_STATE_LPBK = 0x0b,
810 DWC3_LINK_STATE_RESET = 0x0e,
811 DWC3_LINK_STATE_RESUME = 0x0f,
812 DWC3_LINK_STATE_MASK = 0x0f,
813};
814
815/* TRB Length, PCM and Status */
816#define DWC3_TRB_SIZE_MASK (0x00ffffff)
817#define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
818#define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
819#define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
820
821#define DWC3_TRBSTS_OK 0
822#define DWC3_TRBSTS_MISSED_ISOC 1
823#define DWC3_TRBSTS_SETUP_PENDING 2
824#define DWC3_TRB_STS_XFER_IN_PROG 4
825
826/* TRB Control */
827#define DWC3_TRB_CTRL_HWO BIT(0)
828#define DWC3_TRB_CTRL_LST BIT(1)
829#define DWC3_TRB_CTRL_CHN BIT(2)
830#define DWC3_TRB_CTRL_CSP BIT(3)
831#define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
832#define DWC3_TRB_CTRL_ISP_IMI BIT(10)
833#define DWC3_TRB_CTRL_IOC BIT(11)
834#define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
835#define DWC3_TRB_CTRL_GET_SID_SOFN(n) (((n) & (0xffff << 14)) >> 14)
836
837#define DWC3_TRBCTL_TYPE(n) ((n) & (0x3f << 4))
838#define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
839#define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
840#define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
841#define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
842#define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
843#define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
844#define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
845#define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
846
847/**
848 * struct dwc3_trb - transfer request block (hw format)
849 * @bpl: DW0-3
850 * @bph: DW4-7
851 * @size: DW8-B
852 * @ctrl: DWC-F
853 */
854struct dwc3_trb {
855 u32 bpl;
856 u32 bph;
857 u32 size;
858 u32 ctrl;
859} __packed;
860
861/**
862 * struct dwc3_hwparams - copy of HWPARAMS registers
863 * @hwparams0: GHWPARAMS0
864 * @hwparams1: GHWPARAMS1
865 * @hwparams2: GHWPARAMS2
866 * @hwparams3: GHWPARAMS3
867 * @hwparams4: GHWPARAMS4
868 * @hwparams5: GHWPARAMS5
869 * @hwparams6: GHWPARAMS6
870 * @hwparams7: GHWPARAMS7
871 * @hwparams8: GHWPARAMS8
872 * @hwparams9: GHWPARAMS9
873 */
874struct dwc3_hwparams {
875 u32 hwparams0;
876 u32 hwparams1;
877 u32 hwparams2;
878 u32 hwparams3;
879 u32 hwparams4;
880 u32 hwparams5;
881 u32 hwparams6;
882 u32 hwparams7;
883 u32 hwparams8;
884 u32 hwparams9;
885};
886
887/* HWPARAMS0 */
888#define DWC3_MODE(n) ((n) & 0x7)
889
890/* HWPARAMS1 */
891#define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
892
893/* HWPARAMS3 */
894#define DWC3_NUM_IN_EPS_MASK (0x1f << 18)
895#define DWC3_NUM_EPS_MASK (0x3f << 12)
896#define DWC3_NUM_EPS(p) (((p)->hwparams3 & \
897 (DWC3_NUM_EPS_MASK)) >> 12)
898#define DWC3_NUM_IN_EPS(p) (((p)->hwparams3 & \
899 (DWC3_NUM_IN_EPS_MASK)) >> 18)
900
901/* HWPARAMS7 */
902#define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
903
904/* HWPARAMS9 */
905#define DWC3_MST_CAPABLE(p) (!!((p)->hwparams9 & \
906 DWC3_GHWPARAMS9_DEV_MST))
907
908/**
909 * struct dwc3_request - representation of a transfer request
910 * @request: struct usb_request to be transferred
911 * @list: a list_head used for request queueing
912 * @dep: struct dwc3_ep owning this request
913 * @sg: pointer to first incomplete sg
914 * @start_sg: pointer to the sg which should be queued next
915 * @num_pending_sgs: counter to pending sgs
916 * @num_queued_sgs: counter to the number of sgs which already got queued
917 * @remaining: amount of data remaining
918 * @status: internal dwc3 request status tracking
919 * @epnum: endpoint number to which this request refers
920 * @trb: pointer to struct dwc3_trb
921 * @trb_dma: DMA address of @trb
922 * @num_trbs: number of TRBs used by this request
923 * @needs_extra_trb: true when request needs one extra TRB (either due to ZLP
924 * or unaligned OUT)
925 * @direction: IN or OUT direction flag
926 * @mapped: true when request has been dma-mapped
927 */
928struct dwc3_request {
929 struct usb_request request;
930 struct list_head list;
931 struct dwc3_ep *dep;
932 struct scatterlist *sg;
933 struct scatterlist *start_sg;
934
935 unsigned int num_pending_sgs;
936 unsigned int num_queued_sgs;
937 unsigned int remaining;
938
939 unsigned int status;
940#define DWC3_REQUEST_STATUS_QUEUED 0
941#define DWC3_REQUEST_STATUS_STARTED 1
942#define DWC3_REQUEST_STATUS_DISCONNECTED 2
943#define DWC3_REQUEST_STATUS_DEQUEUED 3
944#define DWC3_REQUEST_STATUS_STALLED 4
945#define DWC3_REQUEST_STATUS_COMPLETED 5
946#define DWC3_REQUEST_STATUS_UNKNOWN -1
947
948 u8 epnum;
949 struct dwc3_trb *trb;
950 dma_addr_t trb_dma;
951
952 unsigned int num_trbs;
953
954 unsigned int needs_extra_trb:1;
955 unsigned int direction:1;
956 unsigned int mapped:1;
957};
958
959/*
960 * struct dwc3_scratchpad_array - hibernation scratchpad array
961 * (format defined by hw)
962 */
963struct dwc3_scratchpad_array {
964 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
965};
966
967/**
968 * struct dwc3 - representation of our controller
969 * @drd_work: workqueue used for role swapping
970 * @ep0_trb: trb which is used for the ctrl_req
971 * @bounce: address of bounce buffer
972 * @scratchbuf: address of scratch buffer
973 * @setup_buf: used while precessing STD USB requests
974 * @ep0_trb_addr: dma address of @ep0_trb
975 * @bounce_addr: dma address of @bounce
976 * @ep0_usb_req: dummy req used while handling STD USB requests
977 * @scratch_addr: dma address of scratchbuf
978 * @ep0_in_setup: one control transfer is completed and enter setup phase
979 * @lock: for synchronizing
980 * @mutex: for mode switching
981 * @dev: pointer to our struct device
982 * @sysdev: pointer to the DMA-capable device
983 * @xhci: pointer to our xHCI child
984 * @xhci_resources: struct resources for our @xhci child
985 * @ev_buf: struct dwc3_event_buffer pointer
986 * @eps: endpoint array
987 * @gadget: device side representation of the peripheral controller
988 * @gadget_driver: pointer to the gadget driver
989 * @bus_clk: clock for accessing the registers
990 * @ref_clk: reference clock
991 * @susp_clk: clock used when the SS phy is in low power (S3) state
992 * @reset: reset control
993 * @regs: base address for our registers
994 * @regs_size: address space size
995 * @fladj: frame length adjustment
996 * @ref_clk_per: reference clock period configuration
997 * @irq_gadget: peripheral controller's IRQ number
998 * @otg_irq: IRQ number for OTG IRQs
999 * @current_otg_role: current role of operation while using the OTG block
1000 * @desired_otg_role: desired role of operation while using the OTG block
1001 * @otg_restart_host: flag that OTG controller needs to restart host
1002 * @nr_scratch: number of scratch buffers
1003 * @u1u2: only used on revisions <1.83a for workaround
1004 * @maximum_speed: maximum speed requested (mainly for testing purposes)
1005 * @max_ssp_rate: SuperSpeed Plus maximum signaling rate and lane count
1006 * @gadget_max_speed: maximum gadget speed requested
1007 * @gadget_ssp_rate: Gadget driver's maximum supported SuperSpeed Plus signaling
1008 * rate and lane count.
1009 * @ip: controller's ID
1010 * @revision: controller's version of an IP
1011 * @version_type: VERSIONTYPE register contents, a sub release of a revision
1012 * @dr_mode: requested mode of operation
1013 * @current_dr_role: current role of operation when in dual-role mode
1014 * @desired_dr_role: desired role of operation when in dual-role mode
1015 * @edev: extcon handle
1016 * @edev_nb: extcon notifier
1017 * @hsphy_mode: UTMI phy mode, one of following:
1018 * - USBPHY_INTERFACE_MODE_UTMI
1019 * - USBPHY_INTERFACE_MODE_UTMIW
1020 * @role_sw: usb_role_switch handle
1021 * @role_switch_default_mode: default operation mode of controller while
1022 * usb role is USB_ROLE_NONE.
1023 * @usb_psy: pointer to power supply interface.
1024 * @usb2_phy: pointer to USB2 PHY
1025 * @usb3_phy: pointer to USB3 PHY
1026 * @usb2_generic_phy: pointer to USB2 PHY
1027 * @usb3_generic_phy: pointer to USB3 PHY
1028 * @phys_ready: flag to indicate that PHYs are ready
1029 * @ulpi: pointer to ulpi interface
1030 * @ulpi_ready: flag to indicate that ULPI is initialized
1031 * @u2sel: parameter from Set SEL request.
1032 * @u2pel: parameter from Set SEL request.
1033 * @u1sel: parameter from Set SEL request.
1034 * @u1pel: parameter from Set SEL request.
1035 * @num_eps: number of endpoints
1036 * @ep0_next_event: hold the next expected event
1037 * @ep0state: state of endpoint zero
1038 * @link_state: link state
1039 * @speed: device speed (super, high, full, low)
1040 * @hwparams: copy of hwparams registers
1041 * @regset: debugfs pointer to regdump file
1042 * @dbg_lsp_select: current debug lsp mux register selection
1043 * @test_mode: true when we're entering a USB test mode
1044 * @test_mode_nr: test feature selector
1045 * @lpm_nyet_threshold: LPM NYET response threshold
1046 * @hird_threshold: HIRD threshold
1047 * @rx_thr_num_pkt_prd: periodic ESS receive packet count
1048 * @rx_max_burst_prd: max periodic ESS receive burst size
1049 * @tx_thr_num_pkt_prd: periodic ESS transmit packet count
1050 * @tx_max_burst_prd: max periodic ESS transmit burst size
1051 * @tx_fifo_resize_max_num: max number of fifos allocated during txfifo resize
1052 * @clear_stall_protocol: endpoint number that requires a delayed status phase
1053 * @hsphy_interface: "utmi" or "ulpi"
1054 * @connected: true when we're connected to a host, false otherwise
1055 * @softconnect: true when gadget connect is called, false when disconnect runs
1056 * @delayed_status: true when gadget driver asks for delayed status
1057 * @ep0_bounced: true when we used bounce buffer
1058 * @ep0_expect_in: true when we expect a DATA IN transfer
1059 * @has_hibernation: true when dwc3 was configured with Hibernation
1060 * @sysdev_is_parent: true when dwc3 device has a parent driver
1061 * @has_lpm_erratum: true when core was configured with LPM Erratum. Note that
1062 * there's now way for software to detect this in runtime.
1063 * @is_utmi_l1_suspend: the core asserts output signal
1064 * 0 - utmi_sleep_n
1065 * 1 - utmi_l1_suspend_n
1066 * @is_fpga: true when we are using the FPGA board
1067 * @pending_events: true when we have pending IRQs to be handled
1068 * @do_fifo_resize: true when txfifo resizing is enabled for dwc3 endpoints
1069 * @pullups_connected: true when Run/Stop bit is set
1070 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
1071 * @three_stage_setup: set if we perform a three phase setup
1072 * @dis_start_transfer_quirk: set if start_transfer failure SW workaround is
1073 * not needed for DWC_usb31 version 1.70a-ea06 and below
1074 * @usb3_lpm_capable: set if hadrware supports Link Power Management
1075 * @usb2_lpm_disable: set to disable usb2 lpm for host
1076 * @usb2_gadget_lpm_disable: set to disable usb2 lpm for gadget
1077 * @disable_scramble_quirk: set if we enable the disable scramble quirk
1078 * @u2exit_lfps_quirk: set if we enable u2exit lfps quirk
1079 * @u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk
1080 * @req_p1p2p3_quirk: set if we enable request p1p2p3 quirk
1081 * @del_p1p2p3_quirk: set if we enable delay p1p2p3 quirk
1082 * @del_phy_power_chg_quirk: set if we enable delay phy power change quirk
1083 * @lfps_filter_quirk: set if we enable LFPS filter quirk
1084 * @rx_detect_poll_quirk: set if we enable rx_detect to polling lfps quirk
1085 * @dis_u3_susphy_quirk: set if we disable usb3 suspend phy
1086 * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
1087 * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
1088 * disabling the suspend signal to the PHY.
1089 * @dis_u1_entry_quirk: set if link entering into U1 state needs to be disabled.
1090 * @dis_u2_entry_quirk: set if link entering into U2 state needs to be disabled.
1091 * @dis_rxdet_inp3_quirk: set if we disable Rx.Detect in P3
1092 * @async_callbacks: if set, indicate that async callbacks will be used.
1093 *
1094 * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
1095 * in GUSB2PHYCFG, specify that USB2 PHY doesn't
1096 * provide a free-running PHY clock.
1097 * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
1098 * change quirk.
1099 * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate
1100 * check during HS transmit.
1101 * @resume-hs-terminations: Set if we enable quirk for fixing improper crc
1102 * generation after resume from suspend.
1103 * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed
1104 * instances in park mode.
1105 * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
1106 * @tx_de_emphasis: Tx de-emphasis value
1107 * 0 - -6dB de-emphasis
1108 * 1 - -3.5dB de-emphasis
1109 * 2 - No de-emphasis
1110 * 3 - Reserved
1111 * @dis_metastability_quirk: set to disable metastability quirk.
1112 * @dis_split_quirk: set to disable split boundary.
1113 * @imod_interval: set the interrupt moderation interval in 250ns
1114 * increments or 0 to disable.
1115 * @max_cfg_eps: current max number of IN eps used across all USB configs.
1116 * @last_fifo_depth: last fifo depth used to determine next fifo ram start
1117 * address.
1118 * @num_ep_resized: carries the current number endpoints which have had its tx
1119 * fifo resized.
1120 */
1121struct dwc3 {
1122 struct work_struct drd_work;
1123 struct dwc3_trb *ep0_trb;
1124 void *bounce;
1125 void *scratchbuf;
1126 u8 *setup_buf;
1127 dma_addr_t ep0_trb_addr;
1128 dma_addr_t bounce_addr;
1129 dma_addr_t scratch_addr;
1130 struct dwc3_request ep0_usb_req;
1131 struct completion ep0_in_setup;
1132
1133 /* device lock */
1134 spinlock_t lock;
1135
1136 /* mode switching lock */
1137 struct mutex mutex;
1138
1139 struct device *dev;
1140 struct device *sysdev;
1141
1142 struct platform_device *xhci;
1143 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
1144
1145 struct dwc3_event_buffer *ev_buf;
1146 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
1147
1148 struct usb_gadget *gadget;
1149 struct usb_gadget_driver *gadget_driver;
1150
1151 struct clk *bus_clk;
1152 struct clk *ref_clk;
1153 struct clk *susp_clk;
1154
1155 struct reset_control *reset;
1156
1157 struct usb_phy *usb2_phy;
1158 struct usb_phy *usb3_phy;
1159
1160 struct phy *usb2_generic_phy;
1161 struct phy *usb3_generic_phy;
1162
1163 bool phys_ready;
1164
1165 struct ulpi *ulpi;
1166 bool ulpi_ready;
1167
1168 void __iomem *regs;
1169 size_t regs_size;
1170
1171 enum usb_dr_mode dr_mode;
1172 u32 current_dr_role;
1173 u32 desired_dr_role;
1174 struct extcon_dev *edev;
1175 struct notifier_block edev_nb;
1176 enum usb_phy_interface hsphy_mode;
1177 struct usb_role_switch *role_sw;
1178 enum usb_dr_mode role_switch_default_mode;
1179
1180 struct power_supply *usb_psy;
1181
1182 u32 fladj;
1183 u32 ref_clk_per;
1184 u32 irq_gadget;
1185 u32 otg_irq;
1186 u32 current_otg_role;
1187 u32 desired_otg_role;
1188 bool otg_restart_host;
1189 u32 nr_scratch;
1190 u32 u1u2;
1191 u32 maximum_speed;
1192 u32 gadget_max_speed;
1193 enum usb_ssp_rate max_ssp_rate;
1194 enum usb_ssp_rate gadget_ssp_rate;
1195
1196 u32 ip;
1197
1198#define DWC3_IP 0x5533
1199#define DWC31_IP 0x3331
1200#define DWC32_IP 0x3332
1201
1202 u32 revision;
1203
1204#define DWC3_REVISION_ANY 0x0
1205#define DWC3_REVISION_173A 0x5533173a
1206#define DWC3_REVISION_175A 0x5533175a
1207#define DWC3_REVISION_180A 0x5533180a
1208#define DWC3_REVISION_183A 0x5533183a
1209#define DWC3_REVISION_185A 0x5533185a
1210#define DWC3_REVISION_187A 0x5533187a
1211#define DWC3_REVISION_188A 0x5533188a
1212#define DWC3_REVISION_190A 0x5533190a
1213#define DWC3_REVISION_194A 0x5533194a
1214#define DWC3_REVISION_200A 0x5533200a
1215#define DWC3_REVISION_202A 0x5533202a
1216#define DWC3_REVISION_210A 0x5533210a
1217#define DWC3_REVISION_220A 0x5533220a
1218#define DWC3_REVISION_230A 0x5533230a
1219#define DWC3_REVISION_240A 0x5533240a
1220#define DWC3_REVISION_250A 0x5533250a
1221#define DWC3_REVISION_260A 0x5533260a
1222#define DWC3_REVISION_270A 0x5533270a
1223#define DWC3_REVISION_280A 0x5533280a
1224#define DWC3_REVISION_290A 0x5533290a
1225#define DWC3_REVISION_300A 0x5533300a
1226#define DWC3_REVISION_310A 0x5533310a
1227#define DWC3_REVISION_330A 0x5533330a
1228
1229#define DWC31_REVISION_ANY 0x0
1230#define DWC31_REVISION_110A 0x3131302a
1231#define DWC31_REVISION_120A 0x3132302a
1232#define DWC31_REVISION_160A 0x3136302a
1233#define DWC31_REVISION_170A 0x3137302a
1234#define DWC31_REVISION_180A 0x3138302a
1235#define DWC31_REVISION_190A 0x3139302a
1236
1237#define DWC32_REVISION_ANY 0x0
1238#define DWC32_REVISION_100A 0x3130302a
1239
1240 u32 version_type;
1241
1242#define DWC31_VERSIONTYPE_ANY 0x0
1243#define DWC31_VERSIONTYPE_EA01 0x65613031
1244#define DWC31_VERSIONTYPE_EA02 0x65613032
1245#define DWC31_VERSIONTYPE_EA03 0x65613033
1246#define DWC31_VERSIONTYPE_EA04 0x65613034
1247#define DWC31_VERSIONTYPE_EA05 0x65613035
1248#define DWC31_VERSIONTYPE_EA06 0x65613036
1249
1250 enum dwc3_ep0_next ep0_next_event;
1251 enum dwc3_ep0_state ep0state;
1252 enum dwc3_link_state link_state;
1253
1254 u16 u2sel;
1255 u16 u2pel;
1256 u8 u1sel;
1257 u8 u1pel;
1258
1259 u8 speed;
1260
1261 u8 num_eps;
1262
1263 struct dwc3_hwparams hwparams;
1264 struct debugfs_regset32 *regset;
1265
1266 u32 dbg_lsp_select;
1267
1268 u8 test_mode;
1269 u8 test_mode_nr;
1270 u8 lpm_nyet_threshold;
1271 u8 hird_threshold;
1272 u8 rx_thr_num_pkt_prd;
1273 u8 rx_max_burst_prd;
1274 u8 tx_thr_num_pkt_prd;
1275 u8 tx_max_burst_prd;
1276 u8 tx_fifo_resize_max_num;
1277 u8 clear_stall_protocol;
1278
1279 const char *hsphy_interface;
1280
1281 unsigned connected:1;
1282 unsigned softconnect:1;
1283 unsigned delayed_status:1;
1284 unsigned ep0_bounced:1;
1285 unsigned ep0_expect_in:1;
1286 unsigned has_hibernation:1;
1287 unsigned sysdev_is_parent:1;
1288 unsigned has_lpm_erratum:1;
1289 unsigned is_utmi_l1_suspend:1;
1290 unsigned is_fpga:1;
1291 unsigned pending_events:1;
1292 unsigned do_fifo_resize:1;
1293 unsigned pullups_connected:1;
1294 unsigned setup_packet_pending:1;
1295 unsigned three_stage_setup:1;
1296 unsigned dis_start_transfer_quirk:1;
1297 unsigned usb3_lpm_capable:1;
1298 unsigned usb2_lpm_disable:1;
1299 unsigned usb2_gadget_lpm_disable:1;
1300
1301 unsigned disable_scramble_quirk:1;
1302 unsigned u2exit_lfps_quirk:1;
1303 unsigned u2ss_inp3_quirk:1;
1304 unsigned req_p1p2p3_quirk:1;
1305 unsigned del_p1p2p3_quirk:1;
1306 unsigned del_phy_power_chg_quirk:1;
1307 unsigned lfps_filter_quirk:1;
1308 unsigned rx_detect_poll_quirk:1;
1309 unsigned dis_u3_susphy_quirk:1;
1310 unsigned dis_u2_susphy_quirk:1;
1311 unsigned dis_enblslpm_quirk:1;
1312 unsigned dis_u1_entry_quirk:1;
1313 unsigned dis_u2_entry_quirk:1;
1314 unsigned dis_rxdet_inp3_quirk:1;
1315 unsigned dis_u2_freeclk_exists_quirk:1;
1316 unsigned dis_del_phy_power_chg_quirk:1;
1317 unsigned dis_tx_ipgap_linecheck_quirk:1;
1318 unsigned resume_hs_terminations:1;
1319 unsigned parkmode_disable_ss_quirk:1;
1320 unsigned gfladj_refclk_lpm_sel:1;
1321
1322 unsigned tx_de_emphasis_quirk:1;
1323 unsigned tx_de_emphasis:2;
1324
1325 unsigned dis_metastability_quirk:1;
1326
1327 unsigned dis_split_quirk:1;
1328 unsigned async_callbacks:1;
1329
1330 u16 imod_interval;
1331
1332 int max_cfg_eps;
1333 int last_fifo_depth;
1334 int num_ep_resized;
1335};
1336
1337#define INCRX_BURST_MODE 0
1338#define INCRX_UNDEF_LENGTH_BURST_MODE 1
1339
1340#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
1341
1342/* -------------------------------------------------------------------------- */
1343
1344struct dwc3_event_type {
1345 u32 is_devspec:1;
1346 u32 type:7;
1347 u32 reserved8_31:24;
1348} __packed;
1349
1350#define DWC3_DEPEVT_XFERCOMPLETE 0x01
1351#define DWC3_DEPEVT_XFERINPROGRESS 0x02
1352#define DWC3_DEPEVT_XFERNOTREADY 0x03
1353#define DWC3_DEPEVT_RXTXFIFOEVT 0x04
1354#define DWC3_DEPEVT_STREAMEVT 0x06
1355#define DWC3_DEPEVT_EPCMDCMPLT 0x07
1356
1357/**
1358 * struct dwc3_event_depevt - Device Endpoint Events
1359 * @one_bit: indicates this is an endpoint event (not used)
1360 * @endpoint_number: number of the endpoint
1361 * @endpoint_event: The event we have:
1362 * 0x00 - Reserved
1363 * 0x01 - XferComplete
1364 * 0x02 - XferInProgress
1365 * 0x03 - XferNotReady
1366 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
1367 * 0x05 - Reserved
1368 * 0x06 - StreamEvt
1369 * 0x07 - EPCmdCmplt
1370 * @reserved11_10: Reserved, don't use.
1371 * @status: Indicates the status of the event. Refer to databook for
1372 * more information.
1373 * @parameters: Parameters of the current event. Refer to databook for
1374 * more information.
1375 */
1376struct dwc3_event_depevt {
1377 u32 one_bit:1;
1378 u32 endpoint_number:5;
1379 u32 endpoint_event:4;
1380 u32 reserved11_10:2;
1381 u32 status:4;
1382
1383/* Within XferNotReady */
1384#define DEPEVT_STATUS_TRANSFER_ACTIVE BIT(3)
1385
1386/* Within XferComplete or XferInProgress */
1387#define DEPEVT_STATUS_BUSERR BIT(0)
1388#define DEPEVT_STATUS_SHORT BIT(1)
1389#define DEPEVT_STATUS_IOC BIT(2)
1390#define DEPEVT_STATUS_LST BIT(3) /* XferComplete */
1391#define DEPEVT_STATUS_MISSED_ISOC BIT(3) /* XferInProgress */
1392
1393/* Stream event only */
1394#define DEPEVT_STREAMEVT_FOUND 1
1395#define DEPEVT_STREAMEVT_NOTFOUND 2
1396
1397/* Stream event parameter */
1398#define DEPEVT_STREAM_PRIME 0xfffe
1399#define DEPEVT_STREAM_NOSTREAM 0x0
1400
1401/* Control-only Status */
1402#define DEPEVT_STATUS_CONTROL_DATA 1
1403#define DEPEVT_STATUS_CONTROL_STATUS 2
1404#define DEPEVT_STATUS_CONTROL_PHASE(n) ((n) & 3)
1405
1406/* In response to Start Transfer */
1407#define DEPEVT_TRANSFER_NO_RESOURCE 1
1408#define DEPEVT_TRANSFER_BUS_EXPIRY 2
1409
1410 u32 parameters:16;
1411
1412/* For Command Complete Events */
1413#define DEPEVT_PARAMETER_CMD(n) (((n) & (0xf << 8)) >> 8)
1414} __packed;
1415
1416/**
1417 * struct dwc3_event_devt - Device Events
1418 * @one_bit: indicates this is a non-endpoint event (not used)
1419 * @device_event: indicates it's a device event. Should read as 0x00
1420 * @type: indicates the type of device event.
1421 * 0 - DisconnEvt
1422 * 1 - USBRst
1423 * 2 - ConnectDone
1424 * 3 - ULStChng
1425 * 4 - WkUpEvt
1426 * 5 - Reserved
1427 * 6 - Suspend (EOPF on revisions 2.10a and prior)
1428 * 7 - SOF
1429 * 8 - Reserved
1430 * 9 - ErrticErr
1431 * 10 - CmdCmplt
1432 * 11 - EvntOverflow
1433 * 12 - VndrDevTstRcved
1434 * @reserved15_12: Reserved, not used
1435 * @event_info: Information about this event
1436 * @reserved31_25: Reserved, not used
1437 */
1438struct dwc3_event_devt {
1439 u32 one_bit:1;
1440 u32 device_event:7;
1441 u32 type:4;
1442 u32 reserved15_12:4;
1443 u32 event_info:9;
1444 u32 reserved31_25:7;
1445} __packed;
1446
1447/**
1448 * struct dwc3_event_gevt - Other Core Events
1449 * @one_bit: indicates this is a non-endpoint event (not used)
1450 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
1451 * @phy_port_number: self-explanatory
1452 * @reserved31_12: Reserved, not used.
1453 */
1454struct dwc3_event_gevt {
1455 u32 one_bit:1;
1456 u32 device_event:7;
1457 u32 phy_port_number:4;
1458 u32 reserved31_12:20;
1459} __packed;
1460
1461/**
1462 * union dwc3_event - representation of Event Buffer contents
1463 * @raw: raw 32-bit event
1464 * @type: the type of the event
1465 * @depevt: Device Endpoint Event
1466 * @devt: Device Event
1467 * @gevt: Global Event
1468 */
1469union dwc3_event {
1470 u32 raw;
1471 struct dwc3_event_type type;
1472 struct dwc3_event_depevt depevt;
1473 struct dwc3_event_devt devt;
1474 struct dwc3_event_gevt gevt;
1475};
1476
1477/**
1478 * struct dwc3_gadget_ep_cmd_params - representation of endpoint command
1479 * parameters
1480 * @param2: third parameter
1481 * @param1: second parameter
1482 * @param0: first parameter
1483 */
1484struct dwc3_gadget_ep_cmd_params {
1485 u32 param2;
1486 u32 param1;
1487 u32 param0;
1488};
1489
1490/*
1491 * DWC3 Features to be used as Driver Data
1492 */
1493
1494#define DWC3_HAS_PERIPHERAL BIT(0)
1495#define DWC3_HAS_XHCI BIT(1)
1496#define DWC3_HAS_OTG BIT(3)
1497
1498/* prototypes */
1499void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode);
1500void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
1501u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type);
1502
1503#define DWC3_IP_IS(_ip) \
1504 (dwc->ip == _ip##_IP)
1505
1506#define DWC3_VER_IS(_ip, _ver) \
1507 (DWC3_IP_IS(_ip) && dwc->revision == _ip##_REVISION_##_ver)
1508
1509#define DWC3_VER_IS_PRIOR(_ip, _ver) \
1510 (DWC3_IP_IS(_ip) && dwc->revision < _ip##_REVISION_##_ver)
1511
1512#define DWC3_VER_IS_WITHIN(_ip, _from, _to) \
1513 (DWC3_IP_IS(_ip) && \
1514 dwc->revision >= _ip##_REVISION_##_from && \
1515 (!(_ip##_REVISION_##_to) || \
1516 dwc->revision <= _ip##_REVISION_##_to))
1517
1518#define DWC3_VER_TYPE_IS_WITHIN(_ip, _ver, _from, _to) \
1519 (DWC3_VER_IS(_ip, _ver) && \
1520 dwc->version_type >= _ip##_VERSIONTYPE_##_from && \
1521 (!(_ip##_VERSIONTYPE_##_to) || \
1522 dwc->version_type <= _ip##_VERSIONTYPE_##_to))
1523
1524/**
1525 * dwc3_mdwidth - get MDWIDTH value in bits
1526 * @dwc: pointer to our context structure
1527 *
1528 * Return MDWIDTH configuration value in bits.
1529 */
1530static inline u32 dwc3_mdwidth(struct dwc3 *dwc)
1531{
1532 u32 mdwidth;
1533
1534 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1535 if (DWC3_IP_IS(DWC32))
1536 mdwidth += DWC3_GHWPARAMS6_MDWIDTH(dwc->hwparams.hwparams6);
1537
1538 return mdwidth;
1539}
1540
1541bool dwc3_has_imod(struct dwc3 *dwc);
1542
1543int dwc3_event_buffers_setup(struct dwc3 *dwc);
1544void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
1545
1546int dwc3_core_soft_reset(struct dwc3 *dwc);
1547
1548#if IS_ENABLED(CONFIG_USB_DWC3_HOST) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1549int dwc3_host_init(struct dwc3 *dwc);
1550void dwc3_host_exit(struct dwc3 *dwc);
1551#else
1552static inline int dwc3_host_init(struct dwc3 *dwc)
1553{ return 0; }
1554static inline void dwc3_host_exit(struct dwc3 *dwc)
1555{ }
1556#endif
1557
1558#if IS_ENABLED(CONFIG_USB_DWC3_GADGET) || IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1559int dwc3_gadget_init(struct dwc3 *dwc);
1560void dwc3_gadget_exit(struct dwc3 *dwc);
1561int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
1562int dwc3_gadget_get_link_state(struct dwc3 *dwc);
1563int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
1564int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1565 struct dwc3_gadget_ep_cmd_params *params);
1566int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd,
1567 u32 param);
1568void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc);
1569void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep, int status);
1570#else
1571static inline int dwc3_gadget_init(struct dwc3 *dwc)
1572{ return 0; }
1573static inline void dwc3_gadget_exit(struct dwc3 *dwc)
1574{ }
1575static inline int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
1576{ return 0; }
1577static inline int dwc3_gadget_get_link_state(struct dwc3 *dwc)
1578{ return 0; }
1579static inline int dwc3_gadget_set_link_state(struct dwc3 *dwc,
1580 enum dwc3_link_state state)
1581{ return 0; }
1582
1583static inline int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned int cmd,
1584 struct dwc3_gadget_ep_cmd_params *params)
1585{ return 0; }
1586static inline int dwc3_send_gadget_generic_command(struct dwc3 *dwc,
1587 int cmd, u32 param)
1588{ return 0; }
1589static inline void dwc3_gadget_clear_tx_fifos(struct dwc3 *dwc)
1590{ }
1591#endif
1592
1593#if IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)
1594int dwc3_drd_init(struct dwc3 *dwc);
1595void dwc3_drd_exit(struct dwc3 *dwc);
1596void dwc3_otg_init(struct dwc3 *dwc);
1597void dwc3_otg_exit(struct dwc3 *dwc);
1598void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus);
1599void dwc3_otg_host_init(struct dwc3 *dwc);
1600#else
1601static inline int dwc3_drd_init(struct dwc3 *dwc)
1602{ return 0; }
1603static inline void dwc3_drd_exit(struct dwc3 *dwc)
1604{ }
1605static inline void dwc3_otg_init(struct dwc3 *dwc)
1606{ }
1607static inline void dwc3_otg_exit(struct dwc3 *dwc)
1608{ }
1609static inline void dwc3_otg_update(struct dwc3 *dwc, bool ignore_idstatus)
1610{ }
1611static inline void dwc3_otg_host_init(struct dwc3 *dwc)
1612{ }
1613#endif
1614
1615/* power management interface */
1616#if !IS_ENABLED(CONFIG_USB_DWC3_HOST)
1617int dwc3_gadget_suspend(struct dwc3 *dwc);
1618int dwc3_gadget_resume(struct dwc3 *dwc);
1619void dwc3_gadget_process_pending_events(struct dwc3 *dwc);
1620#else
1621static inline int dwc3_gadget_suspend(struct dwc3 *dwc)
1622{
1623 return 0;
1624}
1625
1626static inline int dwc3_gadget_resume(struct dwc3 *dwc)
1627{
1628 return 0;
1629}
1630
1631static inline void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
1632{
1633}
1634#endif /* !IS_ENABLED(CONFIG_USB_DWC3_HOST) */
1635
1636#if IS_ENABLED(CONFIG_USB_DWC3_ULPI)
1637int dwc3_ulpi_init(struct dwc3 *dwc);
1638void dwc3_ulpi_exit(struct dwc3 *dwc);
1639#else
1640static inline int dwc3_ulpi_init(struct dwc3 *dwc)
1641{ return 0; }
1642static inline void dwc3_ulpi_exit(struct dwc3 *dwc)
1643{ }
1644#endif
1645
1646#endif /* __DRIVERS_USB_DWC3_CORE_H */