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1/*
2 * Freescale STMP37XX/STMP378X Real Time Clock driver
3 *
4 * Copyright (c) 2007 Sigmatel, Inc.
5 * Peter Hartley, <peter.hartley@sigmatel.com>
6 *
7 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
9 * Copyright 2011 Wolfram Sang, Pengutronix e.K.
10 */
11
12/*
13 * The code contained herein is licensed under the GNU General Public
14 * License. You may obtain a copy of the GNU General Public License
15 * Version 2 or later at the following locations:
16 *
17 * http://www.opensource.org/licenses/gpl-license.html
18 * http://www.gnu.org/copyleft/gpl.html
19 */
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/io.h>
23#include <linux/init.h>
24#include <linux/platform_device.h>
25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/rtc.h>
28#include <linux/slab.h>
29#include <linux/of_device.h>
30#include <linux/of.h>
31#include <linux/stmp_device.h>
32#include <linux/stmp3xxx_rtc_wdt.h>
33
34#define STMP3XXX_RTC_CTRL 0x0
35#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
36#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
37#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
38#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
39
40#define STMP3XXX_RTC_STAT 0x10
41#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
42#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
43#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
44#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
45
46#define STMP3XXX_RTC_SECONDS 0x30
47
48#define STMP3XXX_RTC_ALARM 0x40
49
50#define STMP3XXX_RTC_WATCHDOG 0x50
51
52#define STMP3XXX_RTC_PERSISTENT0 0x60
53#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
54#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
55#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
56#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
57#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
58#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
59#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
60
61#define STMP3XXX_RTC_PERSISTENT1 0x70
62/* missing bitmask in headers */
63#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
64
65struct stmp3xxx_rtc_data {
66 struct rtc_device *rtc;
67 void __iomem *io;
68 int irq_alarm;
69};
70
71#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
72/**
73 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
74 * @dev: the parent device of the watchdog (= the RTC)
75 * @timeout: the desired value for the timeout register of the watchdog.
76 * 0 disables the watchdog
77 *
78 * The watchdog needs one register and two bits which are in the RTC domain.
79 * To handle the resource conflict, the RTC driver will create another
80 * platform_device for the watchdog driver as a child of the RTC device.
81 * The watchdog driver is passed the below accessor function via platform_data
82 * to configure the watchdog. Locking is not needed because accessing SET/CLR
83 * registers is atomic.
84 */
85
86static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
87{
88 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
89
90 if (timeout) {
91 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
92 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
93 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
94 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
95 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
96 } else {
97 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
98 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
99 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
100 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
101 }
102}
103
104static struct stmp3xxx_wdt_pdata wdt_pdata = {
105 .wdt_set_timeout = stmp3xxx_wdt_set_timeout,
106};
107
108static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
109{
110 struct platform_device *wdt_pdev =
111 platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
112
113 if (wdt_pdev) {
114 wdt_pdev->dev.parent = &rtc_pdev->dev;
115 wdt_pdev->dev.platform_data = &wdt_pdata;
116 platform_device_add(wdt_pdev);
117 }
118}
119#else
120static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
121{
122}
123#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
124
125static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
126{
127 int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
128 /*
129 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
130 * states:
131 * | The order in which registers are updated is
132 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
133 * | (This list is in bitfield order, from LSB to MSB, as they would
134 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
135 * | register. For example, the Seconds register corresponds to
136 * | STALE_REGS or NEW_REGS containing 0x80.)
137 */
138 do {
139 if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
140 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
141 return 0;
142 udelay(1);
143 } while (--timeout > 0);
144 return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
145 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
146}
147
148/* Time read/write */
149static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
150{
151 int ret;
152 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
153
154 ret = stmp3xxx_wait_time(rtc_data);
155 if (ret)
156 return ret;
157
158 rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
159 return 0;
160}
161
162static int stmp3xxx_rtc_set_mmss(struct device *dev, unsigned long t)
163{
164 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
165
166 writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS);
167 return stmp3xxx_wait_time(rtc_data);
168}
169
170/* interrupt(s) handler */
171static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
172{
173 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
174 u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
175
176 if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
177 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
178 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
179 rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
180 return IRQ_HANDLED;
181 }
182
183 return IRQ_NONE;
184}
185
186static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
187{
188 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
189
190 if (enabled) {
191 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
192 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
193 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
194 STMP_OFFSET_REG_SET);
195 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
196 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
197 } else {
198 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
199 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
200 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
201 STMP_OFFSET_REG_CLR);
202 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
203 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
204 }
205 return 0;
206}
207
208static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
209{
210 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
211
212 rtc_time_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
213 return 0;
214}
215
216static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
217{
218 unsigned long t;
219 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
220
221 rtc_tm_to_time(&alm->time, &t);
222 writel(t, rtc_data->io + STMP3XXX_RTC_ALARM);
223
224 stmp3xxx_alarm_irq_enable(dev, alm->enabled);
225
226 return 0;
227}
228
229static struct rtc_class_ops stmp3xxx_rtc_ops = {
230 .alarm_irq_enable =
231 stmp3xxx_alarm_irq_enable,
232 .read_time = stmp3xxx_rtc_gettime,
233 .set_mmss = stmp3xxx_rtc_set_mmss,
234 .read_alarm = stmp3xxx_rtc_read_alarm,
235 .set_alarm = stmp3xxx_rtc_set_alarm,
236};
237
238static int stmp3xxx_rtc_remove(struct platform_device *pdev)
239{
240 struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
241
242 if (!rtc_data)
243 return 0;
244
245 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
246 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
247
248 return 0;
249}
250
251static int stmp3xxx_rtc_probe(struct platform_device *pdev)
252{
253 struct stmp3xxx_rtc_data *rtc_data;
254 struct resource *r;
255 u32 rtc_stat;
256 u32 pers0_set, pers0_clr;
257 u32 crystalfreq = 0;
258 int err;
259
260 rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
261 if (!rtc_data)
262 return -ENOMEM;
263
264 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
265 if (!r) {
266 dev_err(&pdev->dev, "failed to get resource\n");
267 return -ENXIO;
268 }
269
270 rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
271 if (!rtc_data->io) {
272 dev_err(&pdev->dev, "ioremap failed\n");
273 return -EIO;
274 }
275
276 rtc_data->irq_alarm = platform_get_irq(pdev, 0);
277
278 rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
279 if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
280 dev_err(&pdev->dev, "no device onboard\n");
281 return -ENODEV;
282 }
283
284 platform_set_drvdata(pdev, rtc_data);
285
286 err = stmp_reset_block(rtc_data->io);
287 if (err) {
288 dev_err(&pdev->dev, "stmp_reset_block failed: %d\n", err);
289 return err;
290 }
291
292 /*
293 * Obviously the rtc needs a clock input to be able to run.
294 * This clock can be provided by an external 32k crystal. If that one is
295 * missing XTAL must not be disabled in suspend which consumes a
296 * lot of power. Normally the presence and exact frequency (supported
297 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
298 * proves these fuses are not blown correctly on all machines, so the
299 * frequency can be overridden in the device tree.
300 */
301 if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
302 crystalfreq = 32000;
303 else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
304 crystalfreq = 32768;
305
306 of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
307 &crystalfreq);
308
309 switch (crystalfreq) {
310 case 32000:
311 /* keep 32kHz crystal running in low-power mode */
312 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
313 STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
314 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
315 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
316 break;
317 case 32768:
318 /* keep 32.768kHz crystal running in low-power mode */
319 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
320 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
321 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
322 STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
323 break;
324 default:
325 dev_warn(&pdev->dev,
326 "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
327 /* fall-through */
328 case 0:
329 /* keep XTAL on in low-power mode */
330 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
331 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
332 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
333 }
334
335 writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
336 STMP_OFFSET_REG_SET);
337
338 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
339 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
340 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
341 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
342
343 writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
344 STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
345 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
346
347 rtc_data->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
348 &stmp3xxx_rtc_ops, THIS_MODULE);
349 if (IS_ERR(rtc_data->rtc))
350 return PTR_ERR(rtc_data->rtc);
351
352 err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
353 stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
354 if (err) {
355 dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
356 rtc_data->irq_alarm);
357 return err;
358 }
359
360 stmp3xxx_wdt_register(pdev);
361 return 0;
362}
363
364#ifdef CONFIG_PM_SLEEP
365static int stmp3xxx_rtc_suspend(struct device *dev)
366{
367 return 0;
368}
369
370static int stmp3xxx_rtc_resume(struct device *dev)
371{
372 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
373
374 stmp_reset_block(rtc_data->io);
375 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
376 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
377 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
378 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
379 return 0;
380}
381#endif
382
383static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
384 stmp3xxx_rtc_resume);
385
386static const struct of_device_id rtc_dt_ids[] = {
387 { .compatible = "fsl,stmp3xxx-rtc", },
388 { /* sentinel */ }
389};
390MODULE_DEVICE_TABLE(of, rtc_dt_ids);
391
392static struct platform_driver stmp3xxx_rtcdrv = {
393 .probe = stmp3xxx_rtc_probe,
394 .remove = stmp3xxx_rtc_remove,
395 .driver = {
396 .name = "stmp3xxx-rtc",
397 .pm = &stmp3xxx_rtc_pm_ops,
398 .of_match_table = rtc_dt_ids,
399 },
400};
401
402module_platform_driver(stmp3xxx_rtcdrv);
403
404MODULE_DESCRIPTION("STMP3xxx RTC Driver");
405MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
406 "Wolfram Sang <w.sang@pengutronix.de>");
407MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Freescale STMP37XX/STMP378X Real Time Clock driver
4 *
5 * Copyright (c) 2007 Sigmatel, Inc.
6 * Peter Hartley, <peter.hartley@sigmatel.com>
7 *
8 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
10 * Copyright 2011 Wolfram Sang, Pengutronix e.K.
11 */
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/io.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/interrupt.h>
18#include <linux/delay.h>
19#include <linux/rtc.h>
20#include <linux/slab.h>
21#include <linux/of_device.h>
22#include <linux/of.h>
23#include <linux/stmp_device.h>
24#include <linux/stmp3xxx_rtc_wdt.h>
25
26#define STMP3XXX_RTC_CTRL 0x0
27#define STMP3XXX_RTC_CTRL_ALARM_IRQ_EN 0x00000001
28#define STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
29#define STMP3XXX_RTC_CTRL_ALARM_IRQ 0x00000004
30#define STMP3XXX_RTC_CTRL_WATCHDOGEN 0x00000010
31
32#define STMP3XXX_RTC_STAT 0x10
33#define STMP3XXX_RTC_STAT_STALE_SHIFT 16
34#define STMP3XXX_RTC_STAT_RTC_PRESENT 0x80000000
35#define STMP3XXX_RTC_STAT_XTAL32000_PRESENT 0x10000000
36#define STMP3XXX_RTC_STAT_XTAL32768_PRESENT 0x08000000
37
38#define STMP3XXX_RTC_SECONDS 0x30
39
40#define STMP3XXX_RTC_ALARM 0x40
41
42#define STMP3XXX_RTC_WATCHDOG 0x50
43
44#define STMP3XXX_RTC_PERSISTENT0 0x60
45#define STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE (1 << 0)
46#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1)
47#define STMP3XXX_RTC_PERSISTENT0_ALARM_EN (1 << 2)
48#define STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP (1 << 4)
49#define STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5)
50#define STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ (1 << 6)
51#define STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE (1 << 7)
52
53#define STMP3XXX_RTC_PERSISTENT1 0x70
54/* missing bitmask in headers */
55#define STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER 0x80000000
56
57struct stmp3xxx_rtc_data {
58 struct rtc_device *rtc;
59 void __iomem *io;
60 int irq_alarm;
61};
62
63#if IS_ENABLED(CONFIG_STMP3XXX_RTC_WATCHDOG)
64/**
65 * stmp3xxx_wdt_set_timeout - configure the watchdog inside the STMP3xxx RTC
66 * @dev: the parent device of the watchdog (= the RTC)
67 * @timeout: the desired value for the timeout register of the watchdog.
68 * 0 disables the watchdog
69 *
70 * The watchdog needs one register and two bits which are in the RTC domain.
71 * To handle the resource conflict, the RTC driver will create another
72 * platform_device for the watchdog driver as a child of the RTC device.
73 * The watchdog driver is passed the below accessor function via platform_data
74 * to configure the watchdog. Locking is not needed because accessing SET/CLR
75 * registers is atomic.
76 */
77
78static void stmp3xxx_wdt_set_timeout(struct device *dev, u32 timeout)
79{
80 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
81
82 if (timeout) {
83 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG);
84 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
85 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
86 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
87 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_SET);
88 } else {
89 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN,
90 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
91 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER,
92 rtc_data->io + STMP3XXX_RTC_PERSISTENT1 + STMP_OFFSET_REG_CLR);
93 }
94}
95
96static struct stmp3xxx_wdt_pdata wdt_pdata = {
97 .wdt_set_timeout = stmp3xxx_wdt_set_timeout,
98};
99
100static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
101{
102 int rc = -1;
103 struct platform_device *wdt_pdev =
104 platform_device_alloc("stmp3xxx_rtc_wdt", rtc_pdev->id);
105
106 if (wdt_pdev) {
107 wdt_pdev->dev.parent = &rtc_pdev->dev;
108 wdt_pdev->dev.platform_data = &wdt_pdata;
109 rc = platform_device_add(wdt_pdev);
110 if (rc)
111 platform_device_put(wdt_pdev);
112 }
113
114 if (rc)
115 dev_err(&rtc_pdev->dev,
116 "failed to register stmp3xxx_rtc_wdt\n");
117}
118#else
119static void stmp3xxx_wdt_register(struct platform_device *rtc_pdev)
120{
121}
122#endif /* CONFIG_STMP3XXX_RTC_WATCHDOG */
123
124static int stmp3xxx_wait_time(struct stmp3xxx_rtc_data *rtc_data)
125{
126 int timeout = 5000; /* 3ms according to i.MX28 Ref Manual */
127 /*
128 * The i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
129 * states:
130 * | The order in which registers are updated is
131 * | Persistent 0, 1, 2, 3, 4, 5, Alarm, Seconds.
132 * | (This list is in bitfield order, from LSB to MSB, as they would
133 * | appear in the STALE_REGS and NEW_REGS bitfields of the HW_RTC_STAT
134 * | register. For example, the Seconds register corresponds to
135 * | STALE_REGS or NEW_REGS containing 0x80.)
136 */
137 do {
138 if (!(readl(rtc_data->io + STMP3XXX_RTC_STAT) &
139 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)))
140 return 0;
141 udelay(1);
142 } while (--timeout > 0);
143 return (readl(rtc_data->io + STMP3XXX_RTC_STAT) &
144 (0x80 << STMP3XXX_RTC_STAT_STALE_SHIFT)) ? -ETIME : 0;
145}
146
147/* Time read/write */
148static int stmp3xxx_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
149{
150 int ret;
151 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
152
153 ret = stmp3xxx_wait_time(rtc_data);
154 if (ret)
155 return ret;
156
157 rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_SECONDS), rtc_tm);
158 return 0;
159}
160
161static int stmp3xxx_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
162{
163 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
164
165 writel(rtc_tm_to_time64(rtc_tm), rtc_data->io + STMP3XXX_RTC_SECONDS);
166 return stmp3xxx_wait_time(rtc_data);
167}
168
169/* interrupt(s) handler */
170static irqreturn_t stmp3xxx_rtc_interrupt(int irq, void *dev_id)
171{
172 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev_id);
173 u32 status = readl(rtc_data->io + STMP3XXX_RTC_CTRL);
174
175 if (status & STMP3XXX_RTC_CTRL_ALARM_IRQ) {
176 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ,
177 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
178 rtc_update_irq(rtc_data->rtc, 1, RTC_AF | RTC_IRQF);
179 return IRQ_HANDLED;
180 }
181
182 return IRQ_NONE;
183}
184
185static int stmp3xxx_alarm_irq_enable(struct device *dev, unsigned int enabled)
186{
187 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
188
189 if (enabled) {
190 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
191 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
192 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
193 STMP_OFFSET_REG_SET);
194 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
195 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_SET);
196 } else {
197 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
198 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN,
199 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
200 STMP_OFFSET_REG_CLR);
201 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
202 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
203 }
204 return 0;
205}
206
207static int stmp3xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
208{
209 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
210
211 rtc_time64_to_tm(readl(rtc_data->io + STMP3XXX_RTC_ALARM), &alm->time);
212 return 0;
213}
214
215static int stmp3xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
216{
217 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
218
219 writel(rtc_tm_to_time64(&alm->time), rtc_data->io + STMP3XXX_RTC_ALARM);
220
221 stmp3xxx_alarm_irq_enable(dev, alm->enabled);
222
223 return 0;
224}
225
226static const struct rtc_class_ops stmp3xxx_rtc_ops = {
227 .alarm_irq_enable =
228 stmp3xxx_alarm_irq_enable,
229 .read_time = stmp3xxx_rtc_gettime,
230 .set_time = stmp3xxx_rtc_settime,
231 .read_alarm = stmp3xxx_rtc_read_alarm,
232 .set_alarm = stmp3xxx_rtc_set_alarm,
233};
234
235static int stmp3xxx_rtc_remove(struct platform_device *pdev)
236{
237 struct stmp3xxx_rtc_data *rtc_data = platform_get_drvdata(pdev);
238
239 if (!rtc_data)
240 return 0;
241
242 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
243 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
244
245 return 0;
246}
247
248static int stmp3xxx_rtc_probe(struct platform_device *pdev)
249{
250 struct stmp3xxx_rtc_data *rtc_data;
251 struct resource *r;
252 u32 rtc_stat;
253 u32 pers0_set, pers0_clr;
254 u32 crystalfreq = 0;
255 int err;
256
257 rtc_data = devm_kzalloc(&pdev->dev, sizeof(*rtc_data), GFP_KERNEL);
258 if (!rtc_data)
259 return -ENOMEM;
260
261 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
262 if (!r) {
263 dev_err(&pdev->dev, "failed to get resource\n");
264 return -ENXIO;
265 }
266
267 rtc_data->io = devm_ioremap(&pdev->dev, r->start, resource_size(r));
268 if (!rtc_data->io) {
269 dev_err(&pdev->dev, "ioremap failed\n");
270 return -EIO;
271 }
272
273 rtc_data->irq_alarm = platform_get_irq(pdev, 0);
274
275 rtc_stat = readl(rtc_data->io + STMP3XXX_RTC_STAT);
276 if (!(rtc_stat & STMP3XXX_RTC_STAT_RTC_PRESENT)) {
277 dev_err(&pdev->dev, "no device onboard\n");
278 return -ENODEV;
279 }
280
281 platform_set_drvdata(pdev, rtc_data);
282
283 /*
284 * Resetting the rtc stops the watchdog timer that is potentially
285 * running. So (assuming it is running on purpose) don't reset if the
286 * watchdog is enabled.
287 */
288 if (readl(rtc_data->io + STMP3XXX_RTC_CTRL) &
289 STMP3XXX_RTC_CTRL_WATCHDOGEN) {
290 dev_info(&pdev->dev,
291 "Watchdog is running, skip resetting rtc\n");
292 } else {
293 err = stmp_reset_block(rtc_data->io);
294 if (err) {
295 dev_err(&pdev->dev, "stmp_reset_block failed: %d\n",
296 err);
297 return err;
298 }
299 }
300
301 /*
302 * Obviously the rtc needs a clock input to be able to run.
303 * This clock can be provided by an external 32k crystal. If that one is
304 * missing XTAL must not be disabled in suspend which consumes a
305 * lot of power. Normally the presence and exact frequency (supported
306 * are 32000 Hz and 32768 Hz) is detectable from fuses, but as reality
307 * proves these fuses are not blown correctly on all machines, so the
308 * frequency can be overridden in the device tree.
309 */
310 if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32000_PRESENT)
311 crystalfreq = 32000;
312 else if (rtc_stat & STMP3XXX_RTC_STAT_XTAL32768_PRESENT)
313 crystalfreq = 32768;
314
315 of_property_read_u32(pdev->dev.of_node, "stmp,crystal-freq",
316 &crystalfreq);
317
318 switch (crystalfreq) {
319 case 32000:
320 /* keep 32kHz crystal running in low-power mode */
321 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ |
322 STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
323 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
324 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
325 break;
326 case 32768:
327 /* keep 32.768kHz crystal running in low-power mode */
328 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
329 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
330 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP |
331 STMP3XXX_RTC_PERSISTENT0_XTAL32_FREQ;
332 break;
333 default:
334 dev_warn(&pdev->dev,
335 "invalid crystal-freq specified in device-tree. Assuming no crystal\n");
336 fallthrough;
337 case 0:
338 /* keep XTAL on in low-power mode */
339 pers0_set = STMP3XXX_RTC_PERSISTENT0_XTAL24MHZ_PWRUP;
340 pers0_clr = STMP3XXX_RTC_PERSISTENT0_XTAL32KHZ_PWRUP |
341 STMP3XXX_RTC_PERSISTENT0_CLOCKSOURCE;
342 }
343
344 writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 +
345 STMP_OFFSET_REG_SET);
346
347 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
348 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
349 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE | pers0_clr,
350 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
351
352 writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN |
353 STMP3XXX_RTC_CTRL_ALARM_IRQ_EN,
354 rtc_data->io + STMP3XXX_RTC_CTRL + STMP_OFFSET_REG_CLR);
355
356 rtc_data->rtc = devm_rtc_allocate_device(&pdev->dev);
357 if (IS_ERR(rtc_data->rtc))
358 return PTR_ERR(rtc_data->rtc);
359
360 err = devm_request_irq(&pdev->dev, rtc_data->irq_alarm,
361 stmp3xxx_rtc_interrupt, 0, "RTC alarm", &pdev->dev);
362 if (err) {
363 dev_err(&pdev->dev, "Cannot claim IRQ%d\n",
364 rtc_data->irq_alarm);
365 return err;
366 }
367
368 rtc_data->rtc->ops = &stmp3xxx_rtc_ops;
369 rtc_data->rtc->range_max = U32_MAX;
370
371 err = devm_rtc_register_device(rtc_data->rtc);
372 if (err)
373 return err;
374
375 stmp3xxx_wdt_register(pdev);
376 return 0;
377}
378
379#ifdef CONFIG_PM_SLEEP
380static int stmp3xxx_rtc_suspend(struct device *dev)
381{
382 return 0;
383}
384
385static int stmp3xxx_rtc_resume(struct device *dev)
386{
387 struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
388
389 stmp_reset_block(rtc_data->io);
390 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
391 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
392 STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
393 rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + STMP_OFFSET_REG_CLR);
394 return 0;
395}
396#endif
397
398static SIMPLE_DEV_PM_OPS(stmp3xxx_rtc_pm_ops, stmp3xxx_rtc_suspend,
399 stmp3xxx_rtc_resume);
400
401static const struct of_device_id rtc_dt_ids[] = {
402 { .compatible = "fsl,stmp3xxx-rtc", },
403 { /* sentinel */ }
404};
405MODULE_DEVICE_TABLE(of, rtc_dt_ids);
406
407static struct platform_driver stmp3xxx_rtcdrv = {
408 .probe = stmp3xxx_rtc_probe,
409 .remove = stmp3xxx_rtc_remove,
410 .driver = {
411 .name = "stmp3xxx-rtc",
412 .pm = &stmp3xxx_rtc_pm_ops,
413 .of_match_table = rtc_dt_ids,
414 },
415};
416
417module_platform_driver(stmp3xxx_rtcdrv);
418
419MODULE_DESCRIPTION("STMP3xxx RTC Driver");
420MODULE_AUTHOR("dmitry pervushin <dpervushin@embeddedalley.com> and "
421 "Wolfram Sang <kernel@pengutronix.de>");
422MODULE_LICENSE("GPL");