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1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12#include <linux/of.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/rtc.h>
16#include <linux/platform_device.h>
17#include <linux/pm.h>
18#include <linux/regmap.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21
22/* RTC Register offsets from RTC CTRL REG */
23#define PM8XXX_ALARM_CTRL_OFFSET 0x01
24#define PM8XXX_RTC_WRITE_OFFSET 0x02
25#define PM8XXX_RTC_READ_OFFSET 0x06
26#define PM8XXX_ALARM_RW_OFFSET 0x0A
27
28/* RTC_CTRL register bit fields */
29#define PM8xxx_RTC_ENABLE BIT(7)
30#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
31
32#define NUM_8_BIT_RTC_REGS 0x4
33
34/**
35 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
36 * @ctrl: base address of control register
37 * @write: base address of write register
38 * @read: base address of read register
39 * @alarm_ctrl: base address of alarm control register
40 * @alarm_ctrl2: base address of alarm control2 register
41 * @alarm_rw: base address of alarm read-write register
42 * @alarm_en: alarm enable mask
43 */
44struct pm8xxx_rtc_regs {
45 unsigned int ctrl;
46 unsigned int write;
47 unsigned int read;
48 unsigned int alarm_ctrl;
49 unsigned int alarm_ctrl2;
50 unsigned int alarm_rw;
51 unsigned int alarm_en;
52};
53
54/**
55 * struct pm8xxx_rtc - rtc driver internal structure
56 * @rtc: rtc device for this driver.
57 * @regmap: regmap used to access RTC registers
58 * @allow_set_time: indicates whether writing to the RTC is allowed
59 * @rtc_alarm_irq: rtc alarm irq number.
60 * @ctrl_reg: rtc control register.
61 * @rtc_dev: device structure.
62 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
63 */
64struct pm8xxx_rtc {
65 struct rtc_device *rtc;
66 struct regmap *regmap;
67 bool allow_set_time;
68 int rtc_alarm_irq;
69 const struct pm8xxx_rtc_regs *regs;
70 struct device *rtc_dev;
71 spinlock_t ctrl_reg_lock;
72};
73
74/*
75 * Steps to write the RTC registers.
76 * 1. Disable alarm if enabled.
77 * 2. Write 0x00 to LSB.
78 * 3. Write Byte[1], Byte[2], Byte[3] then Byte[0].
79 * 4. Enable alarm if disabled in step 1.
80 */
81static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
82{
83 int rc, i;
84 unsigned long secs, irq_flags;
85 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0;
86 unsigned int ctrl_reg;
87 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
88 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
89
90 if (!rtc_dd->allow_set_time)
91 return -EACCES;
92
93 rtc_tm_to_time(tm, &secs);
94
95 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
96 value[i] = secs & 0xFF;
97 secs >>= 8;
98 }
99
100 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
101
102 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
103
104 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
105 if (rc)
106 goto rtc_rw_fail;
107
108 if (ctrl_reg & regs->alarm_en) {
109 alarm_enabled = 1;
110 ctrl_reg &= ~regs->alarm_en;
111 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
112 if (rc) {
113 dev_err(dev, "Write to RTC control register failed\n");
114 goto rtc_rw_fail;
115 }
116 }
117
118 /* Write 0 to Byte[0] */
119 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
120 if (rc) {
121 dev_err(dev, "Write to RTC write data register failed\n");
122 goto rtc_rw_fail;
123 }
124
125 /* Write Byte[1], Byte[2], Byte[3] */
126 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
127 &value[1], sizeof(value) - 1);
128 if (rc) {
129 dev_err(dev, "Write to RTC write data register failed\n");
130 goto rtc_rw_fail;
131 }
132
133 /* Write Byte[0] */
134 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
135 if (rc) {
136 dev_err(dev, "Write to RTC write data register failed\n");
137 goto rtc_rw_fail;
138 }
139
140 if (alarm_enabled) {
141 ctrl_reg |= regs->alarm_en;
142 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
143 if (rc) {
144 dev_err(dev, "Write to RTC control register failed\n");
145 goto rtc_rw_fail;
146 }
147 }
148
149rtc_rw_fail:
150 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
151
152 return rc;
153}
154
155static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
156{
157 int rc;
158 u8 value[NUM_8_BIT_RTC_REGS];
159 unsigned long secs;
160 unsigned int reg;
161 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
162 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
163
164 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
165 if (rc) {
166 dev_err(dev, "RTC read data register failed\n");
167 return rc;
168 }
169
170 /*
171 * Read the LSB again and check if there has been a carry over.
172 * If there is, redo the read operation.
173 */
174 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
175 if (rc < 0) {
176 dev_err(dev, "RTC read data register failed\n");
177 return rc;
178 }
179
180 if (unlikely(reg < value[0])) {
181 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
182 value, sizeof(value));
183 if (rc) {
184 dev_err(dev, "RTC read data register failed\n");
185 return rc;
186 }
187 }
188
189 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
190
191 rtc_time_to_tm(secs, tm);
192
193 rc = rtc_valid_tm(tm);
194 if (rc < 0) {
195 dev_err(dev, "Invalid time read from RTC\n");
196 return rc;
197 }
198
199 dev_dbg(dev, "secs = %lu, h:m:s == %d:%d:%d, d/m/y = %d/%d/%d\n",
200 secs, tm->tm_hour, tm->tm_min, tm->tm_sec,
201 tm->tm_mday, tm->tm_mon, tm->tm_year);
202
203 return 0;
204}
205
206static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
207{
208 int rc, i;
209 u8 value[NUM_8_BIT_RTC_REGS];
210 unsigned int ctrl_reg;
211 unsigned long secs, irq_flags;
212 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
213 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
214
215 rtc_tm_to_time(&alarm->time, &secs);
216
217 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
218 value[i] = secs & 0xFF;
219 secs >>= 8;
220 }
221
222 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
223
224 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
225 sizeof(value));
226 if (rc) {
227 dev_err(dev, "Write to RTC ALARM register failed\n");
228 goto rtc_rw_fail;
229 }
230
231 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
232 if (rc)
233 goto rtc_rw_fail;
234
235 if (alarm->enabled)
236 ctrl_reg |= regs->alarm_en;
237 else
238 ctrl_reg &= ~regs->alarm_en;
239
240 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
241 if (rc) {
242 dev_err(dev, "Write to RTC alarm control register failed\n");
243 goto rtc_rw_fail;
244 }
245
246 dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
247 alarm->time.tm_hour, alarm->time.tm_min,
248 alarm->time.tm_sec, alarm->time.tm_mday,
249 alarm->time.tm_mon, alarm->time.tm_year);
250rtc_rw_fail:
251 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
252 return rc;
253}
254
255static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
256{
257 int rc;
258 u8 value[NUM_8_BIT_RTC_REGS];
259 unsigned long secs;
260 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
261 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
262
263 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
264 sizeof(value));
265 if (rc) {
266 dev_err(dev, "RTC alarm time read failed\n");
267 return rc;
268 }
269
270 secs = value[0] | (value[1] << 8) | (value[2] << 16) | (value[3] << 24);
271
272 rtc_time_to_tm(secs, &alarm->time);
273
274 rc = rtc_valid_tm(&alarm->time);
275 if (rc < 0) {
276 dev_err(dev, "Invalid alarm time read from RTC\n");
277 return rc;
278 }
279
280 dev_dbg(dev, "Alarm set for - h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
281 alarm->time.tm_hour, alarm->time.tm_min,
282 alarm->time.tm_sec, alarm->time.tm_mday,
283 alarm->time.tm_mon, alarm->time.tm_year);
284
285 return 0;
286}
287
288static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
289{
290 int rc;
291 unsigned long irq_flags;
292 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
293 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
294 unsigned int ctrl_reg;
295
296 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
297
298 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
299 if (rc)
300 goto rtc_rw_fail;
301
302 if (enable)
303 ctrl_reg |= regs->alarm_en;
304 else
305 ctrl_reg &= ~regs->alarm_en;
306
307 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
308 if (rc) {
309 dev_err(dev, "Write to RTC control register failed\n");
310 goto rtc_rw_fail;
311 }
312
313rtc_rw_fail:
314 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
315 return rc;
316}
317
318static const struct rtc_class_ops pm8xxx_rtc_ops = {
319 .read_time = pm8xxx_rtc_read_time,
320 .set_time = pm8xxx_rtc_set_time,
321 .set_alarm = pm8xxx_rtc_set_alarm,
322 .read_alarm = pm8xxx_rtc_read_alarm,
323 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
324};
325
326static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
327{
328 struct pm8xxx_rtc *rtc_dd = dev_id;
329 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
330 unsigned int ctrl_reg;
331 int rc;
332 unsigned long irq_flags;
333
334 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
335
336 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
337
338 /* Clear the alarm enable bit */
339 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
340 if (rc) {
341 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
342 goto rtc_alarm_handled;
343 }
344
345 ctrl_reg &= ~regs->alarm_en;
346
347 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
348 if (rc) {
349 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
350 dev_err(rtc_dd->rtc_dev,
351 "Write to alarm control register failed\n");
352 goto rtc_alarm_handled;
353 }
354
355 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
356
357 /* Clear RTC alarm register */
358 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
359 if (rc) {
360 dev_err(rtc_dd->rtc_dev,
361 "RTC Alarm control2 register read failed\n");
362 goto rtc_alarm_handled;
363 }
364
365 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
366 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
367 if (rc)
368 dev_err(rtc_dd->rtc_dev,
369 "Write to RTC Alarm control2 register failed\n");
370
371rtc_alarm_handled:
372 return IRQ_HANDLED;
373}
374
375static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
376{
377 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
378 unsigned int ctrl_reg;
379 int rc;
380
381 /* Check if the RTC is on, else turn it on */
382 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
383 if (rc)
384 return rc;
385
386 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
387 ctrl_reg |= PM8xxx_RTC_ENABLE;
388 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
389 if (rc)
390 return rc;
391 }
392
393 return 0;
394}
395
396static const struct pm8xxx_rtc_regs pm8921_regs = {
397 .ctrl = 0x11d,
398 .write = 0x11f,
399 .read = 0x123,
400 .alarm_rw = 0x127,
401 .alarm_ctrl = 0x11d,
402 .alarm_ctrl2 = 0x11e,
403 .alarm_en = BIT(1),
404};
405
406static const struct pm8xxx_rtc_regs pm8058_regs = {
407 .ctrl = 0x1e8,
408 .write = 0x1ea,
409 .read = 0x1ee,
410 .alarm_rw = 0x1f2,
411 .alarm_ctrl = 0x1e8,
412 .alarm_ctrl2 = 0x1e9,
413 .alarm_en = BIT(1),
414};
415
416static const struct pm8xxx_rtc_regs pm8941_regs = {
417 .ctrl = 0x6046,
418 .write = 0x6040,
419 .read = 0x6048,
420 .alarm_rw = 0x6140,
421 .alarm_ctrl = 0x6146,
422 .alarm_ctrl2 = 0x6148,
423 .alarm_en = BIT(7),
424};
425
426/*
427 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
428 */
429static const struct of_device_id pm8xxx_id_table[] = {
430 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
431 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
432 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
433 { },
434};
435MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
436
437static int pm8xxx_rtc_probe(struct platform_device *pdev)
438{
439 int rc;
440 struct pm8xxx_rtc *rtc_dd;
441 const struct of_device_id *match;
442
443 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
444 if (!match)
445 return -ENXIO;
446
447 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
448 if (rtc_dd == NULL)
449 return -ENOMEM;
450
451 /* Initialise spinlock to protect RTC control register */
452 spin_lock_init(&rtc_dd->ctrl_reg_lock);
453
454 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
455 if (!rtc_dd->regmap) {
456 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
457 return -ENXIO;
458 }
459
460 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
461 if (rtc_dd->rtc_alarm_irq < 0) {
462 dev_err(&pdev->dev, "Alarm IRQ resource absent!\n");
463 return -ENXIO;
464 }
465
466 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
467 "allow-set-time");
468
469 rtc_dd->regs = match->data;
470 rtc_dd->rtc_dev = &pdev->dev;
471
472 rc = pm8xxx_rtc_enable(rtc_dd);
473 if (rc)
474 return rc;
475
476 platform_set_drvdata(pdev, rtc_dd);
477
478 device_init_wakeup(&pdev->dev, 1);
479
480 /* Register the RTC device */
481 rtc_dd->rtc = devm_rtc_device_register(&pdev->dev, "pm8xxx_rtc",
482 &pm8xxx_rtc_ops, THIS_MODULE);
483 if (IS_ERR(rtc_dd->rtc)) {
484 dev_err(&pdev->dev, "%s: RTC registration failed (%ld)\n",
485 __func__, PTR_ERR(rtc_dd->rtc));
486 return PTR_ERR(rtc_dd->rtc);
487 }
488
489 /* Request the alarm IRQ */
490 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
491 pm8xxx_alarm_trigger,
492 IRQF_TRIGGER_RISING,
493 "pm8xxx_rtc_alarm", rtc_dd);
494 if (rc < 0) {
495 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
496 return rc;
497 }
498
499 dev_dbg(&pdev->dev, "Probe success !!\n");
500
501 return 0;
502}
503
504#ifdef CONFIG_PM_SLEEP
505static int pm8xxx_rtc_resume(struct device *dev)
506{
507 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
508
509 if (device_may_wakeup(dev))
510 disable_irq_wake(rtc_dd->rtc_alarm_irq);
511
512 return 0;
513}
514
515static int pm8xxx_rtc_suspend(struct device *dev)
516{
517 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
518
519 if (device_may_wakeup(dev))
520 enable_irq_wake(rtc_dd->rtc_alarm_irq);
521
522 return 0;
523}
524#endif
525
526static SIMPLE_DEV_PM_OPS(pm8xxx_rtc_pm_ops,
527 pm8xxx_rtc_suspend,
528 pm8xxx_rtc_resume);
529
530static struct platform_driver pm8xxx_rtc_driver = {
531 .probe = pm8xxx_rtc_probe,
532 .driver = {
533 .name = "rtc-pm8xxx",
534 .pm = &pm8xxx_rtc_pm_ops,
535 .of_match_table = pm8xxx_id_table,
536 },
537};
538
539module_platform_driver(pm8xxx_rtc_driver);
540
541MODULE_ALIAS("platform:rtc-pm8xxx");
542MODULE_DESCRIPTION("PMIC8xxx RTC driver");
543MODULE_LICENSE("GPL v2");
544MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");
1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4#include <linux/of.h>
5#include <linux/module.h>
6#include <linux/init.h>
7#include <linux/rtc.h>
8#include <linux/platform_device.h>
9#include <linux/pm.h>
10#include <linux/pm_wakeirq.h>
11#include <linux/regmap.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14
15/* RTC Register offsets from RTC CTRL REG */
16#define PM8XXX_ALARM_CTRL_OFFSET 0x01
17#define PM8XXX_RTC_WRITE_OFFSET 0x02
18#define PM8XXX_RTC_READ_OFFSET 0x06
19#define PM8XXX_ALARM_RW_OFFSET 0x0A
20
21/* RTC_CTRL register bit fields */
22#define PM8xxx_RTC_ENABLE BIT(7)
23#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
24#define PM8xxx_RTC_ALARM_ENABLE BIT(7)
25
26#define NUM_8_BIT_RTC_REGS 0x4
27
28/**
29 * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
30 * @ctrl: base address of control register
31 * @write: base address of write register
32 * @read: base address of read register
33 * @alarm_ctrl: base address of alarm control register
34 * @alarm_ctrl2: base address of alarm control2 register
35 * @alarm_rw: base address of alarm read-write register
36 * @alarm_en: alarm enable mask
37 */
38struct pm8xxx_rtc_regs {
39 unsigned int ctrl;
40 unsigned int write;
41 unsigned int read;
42 unsigned int alarm_ctrl;
43 unsigned int alarm_ctrl2;
44 unsigned int alarm_rw;
45 unsigned int alarm_en;
46};
47
48/**
49 * struct pm8xxx_rtc - rtc driver internal structure
50 * @rtc: rtc device for this driver.
51 * @regmap: regmap used to access RTC registers
52 * @allow_set_time: indicates whether writing to the RTC is allowed
53 * @rtc_alarm_irq: rtc alarm irq number.
54 * @regs: rtc registers description.
55 * @rtc_dev: device structure.
56 * @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
57 */
58struct pm8xxx_rtc {
59 struct rtc_device *rtc;
60 struct regmap *regmap;
61 bool allow_set_time;
62 int rtc_alarm_irq;
63 const struct pm8xxx_rtc_regs *regs;
64 struct device *rtc_dev;
65 spinlock_t ctrl_reg_lock;
66};
67
68/*
69 * Steps to write the RTC registers.
70 * 1. Disable alarm if enabled.
71 * 2. Disable rtc if enabled.
72 * 3. Write 0x00 to LSB.
73 * 4. Write Byte[1], Byte[2], Byte[3] then Byte[0].
74 * 5. Enable rtc if disabled in step 2.
75 * 6. Enable alarm if disabled in step 1.
76 */
77static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
78{
79 int rc, i;
80 unsigned long secs, irq_flags;
81 u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, rtc_disabled = 0;
82 unsigned int ctrl_reg, rtc_ctrl_reg;
83 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
84 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
85
86 if (!rtc_dd->allow_set_time)
87 return -ENODEV;
88
89 secs = rtc_tm_to_time64(tm);
90
91 dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
92
93 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
94 value[i] = secs & 0xFF;
95 secs >>= 8;
96 }
97
98 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
99
100 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
101 if (rc)
102 goto rtc_rw_fail;
103
104 if (ctrl_reg & regs->alarm_en) {
105 alarm_enabled = 1;
106 ctrl_reg &= ~regs->alarm_en;
107 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
108 if (rc) {
109 dev_err(dev, "Write to RTC Alarm control register failed\n");
110 goto rtc_rw_fail;
111 }
112 }
113
114 /* Disable RTC H/w before writing on RTC register */
115 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &rtc_ctrl_reg);
116 if (rc)
117 goto rtc_rw_fail;
118
119 if (rtc_ctrl_reg & PM8xxx_RTC_ENABLE) {
120 rtc_disabled = 1;
121 rtc_ctrl_reg &= ~PM8xxx_RTC_ENABLE;
122 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
123 if (rc) {
124 dev_err(dev, "Write to RTC control register failed\n");
125 goto rtc_rw_fail;
126 }
127 }
128
129 /* Write 0 to Byte[0] */
130 rc = regmap_write(rtc_dd->regmap, regs->write, 0);
131 if (rc) {
132 dev_err(dev, "Write to RTC write data register failed\n");
133 goto rtc_rw_fail;
134 }
135
136 /* Write Byte[1], Byte[2], Byte[3] */
137 rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
138 &value[1], sizeof(value) - 1);
139 if (rc) {
140 dev_err(dev, "Write to RTC write data register failed\n");
141 goto rtc_rw_fail;
142 }
143
144 /* Write Byte[0] */
145 rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
146 if (rc) {
147 dev_err(dev, "Write to RTC write data register failed\n");
148 goto rtc_rw_fail;
149 }
150
151 /* Enable RTC H/w after writing on RTC register */
152 if (rtc_disabled) {
153 rtc_ctrl_reg |= PM8xxx_RTC_ENABLE;
154 rc = regmap_write(rtc_dd->regmap, regs->ctrl, rtc_ctrl_reg);
155 if (rc) {
156 dev_err(dev, "Write to RTC control register failed\n");
157 goto rtc_rw_fail;
158 }
159 }
160
161 if (alarm_enabled) {
162 ctrl_reg |= regs->alarm_en;
163 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
164 if (rc) {
165 dev_err(dev, "Write to RTC Alarm control register failed\n");
166 goto rtc_rw_fail;
167 }
168 }
169
170rtc_rw_fail:
171 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
172
173 return rc;
174}
175
176static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
177{
178 int rc;
179 u8 value[NUM_8_BIT_RTC_REGS];
180 unsigned long secs;
181 unsigned int reg;
182 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
183 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
184
185 rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
186 if (rc) {
187 dev_err(dev, "RTC read data register failed\n");
188 return rc;
189 }
190
191 /*
192 * Read the LSB again and check if there has been a carry over.
193 * If there is, redo the read operation.
194 */
195 rc = regmap_read(rtc_dd->regmap, regs->read, ®);
196 if (rc < 0) {
197 dev_err(dev, "RTC read data register failed\n");
198 return rc;
199 }
200
201 if (unlikely(reg < value[0])) {
202 rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
203 value, sizeof(value));
204 if (rc) {
205 dev_err(dev, "RTC read data register failed\n");
206 return rc;
207 }
208 }
209
210 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
211 ((unsigned long)value[3] << 24);
212
213 rtc_time64_to_tm(secs, tm);
214
215 dev_dbg(dev, "secs = %lu, h:m:s == %ptRt, y-m-d = %ptRdr\n", secs, tm, tm);
216
217 return 0;
218}
219
220static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
221{
222 int rc, i;
223 u8 value[NUM_8_BIT_RTC_REGS];
224 unsigned int ctrl_reg;
225 unsigned long secs, irq_flags;
226 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
227 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
228
229 secs = rtc_tm_to_time64(&alarm->time);
230
231 for (i = 0; i < NUM_8_BIT_RTC_REGS; i++) {
232 value[i] = secs & 0xFF;
233 secs >>= 8;
234 }
235
236 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
237
238 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
239 sizeof(value));
240 if (rc) {
241 dev_err(dev, "Write to RTC ALARM register failed\n");
242 goto rtc_rw_fail;
243 }
244
245 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
246 if (rc)
247 goto rtc_rw_fail;
248
249 if (alarm->enabled)
250 ctrl_reg |= regs->alarm_en;
251 else
252 ctrl_reg &= ~regs->alarm_en;
253
254 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
255 if (rc) {
256 dev_err(dev, "Write to RTC alarm control register failed\n");
257 goto rtc_rw_fail;
258 }
259
260 dev_dbg(dev, "Alarm Set for h:m:s=%ptRt, y-m-d=%ptRdr\n",
261 &alarm->time, &alarm->time);
262rtc_rw_fail:
263 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
264 return rc;
265}
266
267static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
268{
269 int rc;
270 unsigned int ctrl_reg;
271 u8 value[NUM_8_BIT_RTC_REGS];
272 unsigned long secs;
273 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
274 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
275
276 rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
277 sizeof(value));
278 if (rc) {
279 dev_err(dev, "RTC alarm time read failed\n");
280 return rc;
281 }
282
283 secs = value[0] | (value[1] << 8) | (value[2] << 16) |
284 ((unsigned long)value[3] << 24);
285
286 rtc_time64_to_tm(secs, &alarm->time);
287
288 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
289 if (rc) {
290 dev_err(dev, "Read from RTC alarm control register failed\n");
291 return rc;
292 }
293 alarm->enabled = !!(ctrl_reg & PM8xxx_RTC_ALARM_ENABLE);
294
295 dev_dbg(dev, "Alarm set for - h:m:s=%ptRt, y-m-d=%ptRdr\n",
296 &alarm->time, &alarm->time);
297
298 return 0;
299}
300
301static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
302{
303 int rc;
304 unsigned long irq_flags;
305 struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
306 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
307 unsigned int ctrl_reg;
308 u8 value[NUM_8_BIT_RTC_REGS] = {0};
309
310 spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
311
312 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
313 if (rc)
314 goto rtc_rw_fail;
315
316 if (enable)
317 ctrl_reg |= regs->alarm_en;
318 else
319 ctrl_reg &= ~regs->alarm_en;
320
321 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
322 if (rc) {
323 dev_err(dev, "Write to RTC control register failed\n");
324 goto rtc_rw_fail;
325 }
326
327 /* Clear Alarm register */
328 if (!enable) {
329 rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
330 sizeof(value));
331 if (rc) {
332 dev_err(dev, "Clear RTC ALARM register failed\n");
333 goto rtc_rw_fail;
334 }
335 }
336
337rtc_rw_fail:
338 spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
339 return rc;
340}
341
342static const struct rtc_class_ops pm8xxx_rtc_ops = {
343 .read_time = pm8xxx_rtc_read_time,
344 .set_time = pm8xxx_rtc_set_time,
345 .set_alarm = pm8xxx_rtc_set_alarm,
346 .read_alarm = pm8xxx_rtc_read_alarm,
347 .alarm_irq_enable = pm8xxx_rtc_alarm_irq_enable,
348};
349
350static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
351{
352 struct pm8xxx_rtc *rtc_dd = dev_id;
353 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
354 unsigned int ctrl_reg;
355 int rc;
356
357 rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
358
359 spin_lock(&rtc_dd->ctrl_reg_lock);
360
361 /* Clear the alarm enable bit */
362 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
363 if (rc) {
364 spin_unlock(&rtc_dd->ctrl_reg_lock);
365 goto rtc_alarm_handled;
366 }
367
368 ctrl_reg &= ~regs->alarm_en;
369
370 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
371 if (rc) {
372 spin_unlock(&rtc_dd->ctrl_reg_lock);
373 dev_err(rtc_dd->rtc_dev,
374 "Write to alarm control register failed\n");
375 goto rtc_alarm_handled;
376 }
377
378 spin_unlock(&rtc_dd->ctrl_reg_lock);
379
380 /* Clear RTC alarm register */
381 rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
382 if (rc) {
383 dev_err(rtc_dd->rtc_dev,
384 "RTC Alarm control2 register read failed\n");
385 goto rtc_alarm_handled;
386 }
387
388 ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
389 rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
390 if (rc)
391 dev_err(rtc_dd->rtc_dev,
392 "Write to RTC Alarm control2 register failed\n");
393
394rtc_alarm_handled:
395 return IRQ_HANDLED;
396}
397
398static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
399{
400 const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
401 unsigned int ctrl_reg;
402 int rc;
403
404 /* Check if the RTC is on, else turn it on */
405 rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
406 if (rc)
407 return rc;
408
409 if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
410 ctrl_reg |= PM8xxx_RTC_ENABLE;
411 rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
412 if (rc)
413 return rc;
414 }
415
416 return 0;
417}
418
419static const struct pm8xxx_rtc_regs pm8921_regs = {
420 .ctrl = 0x11d,
421 .write = 0x11f,
422 .read = 0x123,
423 .alarm_rw = 0x127,
424 .alarm_ctrl = 0x11d,
425 .alarm_ctrl2 = 0x11e,
426 .alarm_en = BIT(1),
427};
428
429static const struct pm8xxx_rtc_regs pm8058_regs = {
430 .ctrl = 0x1e8,
431 .write = 0x1ea,
432 .read = 0x1ee,
433 .alarm_rw = 0x1f2,
434 .alarm_ctrl = 0x1e8,
435 .alarm_ctrl2 = 0x1e9,
436 .alarm_en = BIT(1),
437};
438
439static const struct pm8xxx_rtc_regs pm8941_regs = {
440 .ctrl = 0x6046,
441 .write = 0x6040,
442 .read = 0x6048,
443 .alarm_rw = 0x6140,
444 .alarm_ctrl = 0x6146,
445 .alarm_ctrl2 = 0x6148,
446 .alarm_en = BIT(7),
447};
448
449static const struct pm8xxx_rtc_regs pmk8350_regs = {
450 .ctrl = 0x6146,
451 .write = 0x6140,
452 .read = 0x6148,
453 .alarm_rw = 0x6240,
454 .alarm_ctrl = 0x6246,
455 .alarm_ctrl2 = 0x6248,
456 .alarm_en = BIT(7),
457};
458
459/*
460 * Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
461 */
462static const struct of_device_id pm8xxx_id_table[] = {
463 { .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
464 { .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
465 { .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
466 { .compatible = "qcom,pmk8350-rtc", .data = &pmk8350_regs },
467 { },
468};
469MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
470
471static int pm8xxx_rtc_probe(struct platform_device *pdev)
472{
473 int rc;
474 struct pm8xxx_rtc *rtc_dd;
475 const struct of_device_id *match;
476
477 match = of_match_node(pm8xxx_id_table, pdev->dev.of_node);
478 if (!match)
479 return -ENXIO;
480
481 rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
482 if (rtc_dd == NULL)
483 return -ENOMEM;
484
485 /* Initialise spinlock to protect RTC control register */
486 spin_lock_init(&rtc_dd->ctrl_reg_lock);
487
488 rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
489 if (!rtc_dd->regmap) {
490 dev_err(&pdev->dev, "Parent regmap unavailable.\n");
491 return -ENXIO;
492 }
493
494 rtc_dd->rtc_alarm_irq = platform_get_irq(pdev, 0);
495 if (rtc_dd->rtc_alarm_irq < 0)
496 return -ENXIO;
497
498 rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
499 "allow-set-time");
500
501 rtc_dd->regs = match->data;
502 rtc_dd->rtc_dev = &pdev->dev;
503
504 rc = pm8xxx_rtc_enable(rtc_dd);
505 if (rc)
506 return rc;
507
508 platform_set_drvdata(pdev, rtc_dd);
509
510 device_init_wakeup(&pdev->dev, 1);
511
512 /* Register the RTC device */
513 rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
514 if (IS_ERR(rtc_dd->rtc))
515 return PTR_ERR(rtc_dd->rtc);
516
517 rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
518 rtc_dd->rtc->range_max = U32_MAX;
519
520 /* Request the alarm IRQ */
521 rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->rtc_alarm_irq,
522 pm8xxx_alarm_trigger,
523 IRQF_TRIGGER_RISING,
524 "pm8xxx_rtc_alarm", rtc_dd);
525 if (rc < 0) {
526 dev_err(&pdev->dev, "Request IRQ failed (%d)\n", rc);
527 return rc;
528 }
529
530 rc = devm_rtc_register_device(rtc_dd->rtc);
531 if (rc)
532 return rc;
533
534 rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->rtc_alarm_irq);
535 if (rc)
536 return rc;
537
538 return 0;
539}
540
541static int pm8xxx_remove(struct platform_device *pdev)
542{
543 dev_pm_clear_wake_irq(&pdev->dev);
544 return 0;
545}
546
547static struct platform_driver pm8xxx_rtc_driver = {
548 .probe = pm8xxx_rtc_probe,
549 .remove = pm8xxx_remove,
550 .driver = {
551 .name = "rtc-pm8xxx",
552 .of_match_table = pm8xxx_id_table,
553 },
554};
555
556module_platform_driver(pm8xxx_rtc_driver);
557
558MODULE_ALIAS("platform:rtc-pm8xxx");
559MODULE_DESCRIPTION("PMIC8xxx RTC driver");
560MODULE_LICENSE("GPL v2");
561MODULE_AUTHOR("Anirudh Ghayal <aghayal@codeaurora.org>");