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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2017-2018 SiFive
4 * For SiFive's PWM IP block documentation please refer Chapter 14 of
5 * Reference Manual : https://static.dev.sifive.com/FU540-C000-v1.0.pdf
6 *
7 * Limitations:
8 * - When changing both duty cycle and period, we cannot prevent in
9 * software that the output might produce a period with mixed
10 * settings (new period length and old duty cycle).
11 * - The hardware cannot generate a 100% duty cycle.
12 * - The hardware generates only inverted output.
13 */
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/slab.h>
20#include <linux/bitfield.h>
21
22/* Register offsets */
23#define PWM_SIFIVE_PWMCFG 0x0
24#define PWM_SIFIVE_PWMCOUNT 0x8
25#define PWM_SIFIVE_PWMS 0x10
26#define PWM_SIFIVE_PWMCMP(i) (0x20 + 4 * (i))
27
28/* PWMCFG fields */
29#define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0)
30#define PWM_SIFIVE_PWMCFG_STICKY BIT(8)
31#define PWM_SIFIVE_PWMCFG_ZERO_CMP BIT(9)
32#define PWM_SIFIVE_PWMCFG_DEGLITCH BIT(10)
33#define PWM_SIFIVE_PWMCFG_EN_ALWAYS BIT(12)
34#define PWM_SIFIVE_PWMCFG_EN_ONCE BIT(13)
35#define PWM_SIFIVE_PWMCFG_CENTER BIT(16)
36#define PWM_SIFIVE_PWMCFG_GANG BIT(24)
37#define PWM_SIFIVE_PWMCFG_IP BIT(28)
38
39#define PWM_SIFIVE_CMPWIDTH 16
40#define PWM_SIFIVE_DEFAULT_PERIOD 10000000
41
42struct pwm_sifive_ddata {
43 struct pwm_chip chip;
44 struct mutex lock; /* lock to protect user_count and approx_period */
45 struct notifier_block notifier;
46 struct clk *clk;
47 void __iomem *regs;
48 unsigned int real_period;
49 unsigned int approx_period;
50 int user_count;
51};
52
53static inline
54struct pwm_sifive_ddata *pwm_sifive_chip_to_ddata(struct pwm_chip *c)
55{
56 return container_of(c, struct pwm_sifive_ddata, chip);
57}
58
59static int pwm_sifive_request(struct pwm_chip *chip, struct pwm_device *pwm)
60{
61 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
62
63 mutex_lock(&ddata->lock);
64 ddata->user_count++;
65 mutex_unlock(&ddata->lock);
66
67 return 0;
68}
69
70static void pwm_sifive_free(struct pwm_chip *chip, struct pwm_device *pwm)
71{
72 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
73
74 mutex_lock(&ddata->lock);
75 ddata->user_count--;
76 mutex_unlock(&ddata->lock);
77}
78
79/* Called holding ddata->lock */
80static void pwm_sifive_update_clock(struct pwm_sifive_ddata *ddata,
81 unsigned long rate)
82{
83 unsigned long long num;
84 unsigned long scale_pow;
85 int scale;
86 u32 val;
87 /*
88 * The PWM unit is used with pwmzerocmp=0, so the only way to modify the
89 * period length is using pwmscale which provides the number of bits the
90 * counter is shifted before being feed to the comparators. A period
91 * lasts (1 << (PWM_SIFIVE_CMPWIDTH + pwmscale)) clock ticks.
92 * (1 << (PWM_SIFIVE_CMPWIDTH + scale)) * 10^9/rate = period
93 */
94 scale_pow = div64_ul(ddata->approx_period * (u64)rate, NSEC_PER_SEC);
95 scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
96
97 val = PWM_SIFIVE_PWMCFG_EN_ALWAYS |
98 FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
99 writel(val, ddata->regs + PWM_SIFIVE_PWMCFG);
100
101 /* As scale <= 15 the shift operation cannot overflow. */
102 num = (unsigned long long)NSEC_PER_SEC << (PWM_SIFIVE_CMPWIDTH + scale);
103 ddata->real_period = div64_ul(num, rate);
104 dev_dbg(ddata->chip.dev,
105 "New real_period = %u ns\n", ddata->real_period);
106}
107
108static int pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
109 struct pwm_state *state)
110{
111 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
112 u32 duty, val;
113
114 duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
115
116 state->enabled = duty > 0;
117
118 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
119 if (!(val & PWM_SIFIVE_PWMCFG_EN_ALWAYS))
120 state->enabled = false;
121
122 state->period = ddata->real_period;
123 state->duty_cycle =
124 (u64)duty * ddata->real_period >> PWM_SIFIVE_CMPWIDTH;
125 state->polarity = PWM_POLARITY_INVERSED;
126
127 return 0;
128}
129
130static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm,
131 const struct pwm_state *state)
132{
133 struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip);
134 struct pwm_state cur_state;
135 unsigned int duty_cycle;
136 unsigned long long num;
137 bool enabled;
138 int ret = 0;
139 u32 frac;
140
141 if (state->polarity != PWM_POLARITY_INVERSED)
142 return -EINVAL;
143
144 cur_state = pwm->state;
145 enabled = cur_state.enabled;
146
147 duty_cycle = state->duty_cycle;
148 if (!state->enabled)
149 duty_cycle = 0;
150
151 /*
152 * The problem of output producing mixed setting as mentioned at top,
153 * occurs here. To minimize the window for this problem, we are
154 * calculating the register values first and then writing them
155 * consecutively
156 */
157 num = (u64)duty_cycle * (1U << PWM_SIFIVE_CMPWIDTH);
158 frac = DIV64_U64_ROUND_CLOSEST(num, state->period);
159 /* The hardware cannot generate a 100% duty cycle */
160 frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
161
162 mutex_lock(&ddata->lock);
163 if (state->period != ddata->approx_period) {
164 if (ddata->user_count != 1) {
165 mutex_unlock(&ddata->lock);
166 return -EBUSY;
167 }
168 ddata->approx_period = state->period;
169 pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk));
170 }
171 mutex_unlock(&ddata->lock);
172
173 /*
174 * If the PWM is enabled the clk is already on. So only enable it
175 * conditionally to have it on exactly once afterwards independent of
176 * the PWM state.
177 */
178 if (!enabled) {
179 ret = clk_enable(ddata->clk);
180 if (ret) {
181 dev_err(ddata->chip.dev, "Enable clk failed\n");
182 return ret;
183 }
184 }
185
186 writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm));
187
188 if (!state->enabled)
189 clk_disable(ddata->clk);
190
191 return 0;
192}
193
194static const struct pwm_ops pwm_sifive_ops = {
195 .request = pwm_sifive_request,
196 .free = pwm_sifive_free,
197 .get_state = pwm_sifive_get_state,
198 .apply = pwm_sifive_apply,
199 .owner = THIS_MODULE,
200};
201
202static int pwm_sifive_clock_notifier(struct notifier_block *nb,
203 unsigned long event, void *data)
204{
205 struct clk_notifier_data *ndata = data;
206 struct pwm_sifive_ddata *ddata =
207 container_of(nb, struct pwm_sifive_ddata, notifier);
208
209 if (event == POST_RATE_CHANGE) {
210 mutex_lock(&ddata->lock);
211 pwm_sifive_update_clock(ddata, ndata->new_rate);
212 mutex_unlock(&ddata->lock);
213 }
214
215 return NOTIFY_OK;
216}
217
218static int pwm_sifive_probe(struct platform_device *pdev)
219{
220 struct device *dev = &pdev->dev;
221 struct pwm_sifive_ddata *ddata;
222 struct pwm_chip *chip;
223 int ret;
224 u32 val;
225 unsigned int enabled_pwms = 0, enabled_clks = 1;
226
227 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
228 if (!ddata)
229 return -ENOMEM;
230
231 mutex_init(&ddata->lock);
232 chip = &ddata->chip;
233 chip->dev = dev;
234 chip->ops = &pwm_sifive_ops;
235 chip->npwm = 4;
236
237 ddata->regs = devm_platform_ioremap_resource(pdev, 0);
238 if (IS_ERR(ddata->regs))
239 return PTR_ERR(ddata->regs);
240
241 ddata->clk = devm_clk_get(dev, NULL);
242 if (IS_ERR(ddata->clk))
243 return dev_err_probe(dev, PTR_ERR(ddata->clk),
244 "Unable to find controller clock\n");
245
246 ret = clk_prepare_enable(ddata->clk);
247 if (ret) {
248 dev_err(dev, "failed to enable clock for pwm: %d\n", ret);
249 return ret;
250 }
251
252 val = readl(ddata->regs + PWM_SIFIVE_PWMCFG);
253 if (val & PWM_SIFIVE_PWMCFG_EN_ALWAYS) {
254 unsigned int i;
255
256 for (i = 0; i < chip->npwm; ++i) {
257 val = readl(ddata->regs + PWM_SIFIVE_PWMCMP(i));
258 if (val > 0)
259 ++enabled_pwms;
260 }
261 }
262
263 /* The clk should be on once for each running PWM. */
264 if (enabled_pwms) {
265 while (enabled_clks < enabled_pwms) {
266 /* This is not expected to fail as the clk is already on */
267 ret = clk_enable(ddata->clk);
268 if (unlikely(ret)) {
269 dev_err_probe(dev, ret, "Failed to enable clk\n");
270 goto disable_clk;
271 }
272 ++enabled_clks;
273 }
274 } else {
275 clk_disable(ddata->clk);
276 enabled_clks = 0;
277 }
278
279 /* Watch for changes to underlying clock frequency */
280 ddata->notifier.notifier_call = pwm_sifive_clock_notifier;
281 ret = clk_notifier_register(ddata->clk, &ddata->notifier);
282 if (ret) {
283 dev_err(dev, "failed to register clock notifier: %d\n", ret);
284 goto disable_clk;
285 }
286
287 ret = pwmchip_add(chip);
288 if (ret < 0) {
289 dev_err(dev, "cannot register PWM: %d\n", ret);
290 goto unregister_clk;
291 }
292
293 platform_set_drvdata(pdev, ddata);
294 dev_dbg(dev, "SiFive PWM chip registered %d PWMs\n", chip->npwm);
295
296 return 0;
297
298unregister_clk:
299 clk_notifier_unregister(ddata->clk, &ddata->notifier);
300disable_clk:
301 while (enabled_clks) {
302 clk_disable(ddata->clk);
303 --enabled_clks;
304 }
305 clk_unprepare(ddata->clk);
306
307 return ret;
308}
309
310static int pwm_sifive_remove(struct platform_device *dev)
311{
312 struct pwm_sifive_ddata *ddata = platform_get_drvdata(dev);
313 struct pwm_device *pwm;
314 int ch;
315
316 pwmchip_remove(&ddata->chip);
317 clk_notifier_unregister(ddata->clk, &ddata->notifier);
318
319 for (ch = 0; ch < ddata->chip.npwm; ch++) {
320 pwm = &ddata->chip.pwms[ch];
321 if (pwm->state.enabled)
322 clk_disable(ddata->clk);
323 }
324
325 clk_unprepare(ddata->clk);
326
327 return 0;
328}
329
330static const struct of_device_id pwm_sifive_of_match[] = {
331 { .compatible = "sifive,pwm0" },
332 {},
333};
334MODULE_DEVICE_TABLE(of, pwm_sifive_of_match);
335
336static struct platform_driver pwm_sifive_driver = {
337 .probe = pwm_sifive_probe,
338 .remove = pwm_sifive_remove,
339 .driver = {
340 .name = "pwm-sifive",
341 .of_match_table = pwm_sifive_of_match,
342 },
343};
344module_platform_driver(pwm_sifive_driver);
345
346MODULE_DESCRIPTION("SiFive PWM driver");
347MODULE_LICENSE("GPL v2");