Loading...
1/*
2 * Copyright (C) Overkiz SAS 2012
3 *
4 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
5 * License terms: GNU General Public License (GPL) version 2
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/clocksource.h>
11#include <linux/clockchips.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/platform_device.h>
20#include <linux/atmel_tc.h>
21#include <linux/pwm.h>
22#include <linux/of_device.h>
23#include <linux/slab.h>
24
25#define NPWM 6
26
27#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
28 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
29
30#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
31 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
32
33struct atmel_tcb_pwm_device {
34 enum pwm_polarity polarity; /* PWM polarity */
35 unsigned div; /* PWM clock divider */
36 unsigned duty; /* PWM duty expressed in clk cycles */
37 unsigned period; /* PWM period expressed in clk cycles */
38};
39
40struct atmel_tcb_pwm_chip {
41 struct pwm_chip chip;
42 spinlock_t lock;
43 struct atmel_tc *tc;
44 struct atmel_tcb_pwm_device *pwms[NPWM];
45};
46
47static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
48{
49 return container_of(chip, struct atmel_tcb_pwm_chip, chip);
50}
51
52static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
53 struct pwm_device *pwm,
54 enum pwm_polarity polarity)
55{
56 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
57
58 tcbpwm->polarity = polarity;
59
60 return 0;
61}
62
63static int atmel_tcb_pwm_request(struct pwm_chip *chip,
64 struct pwm_device *pwm)
65{
66 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
67 struct atmel_tcb_pwm_device *tcbpwm;
68 struct atmel_tc *tc = tcbpwmc->tc;
69 void __iomem *regs = tc->regs;
70 unsigned group = pwm->hwpwm / 2;
71 unsigned index = pwm->hwpwm % 2;
72 unsigned cmr;
73 int ret;
74
75 tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
76 if (!tcbpwm)
77 return -ENOMEM;
78
79 ret = clk_prepare_enable(tc->clk[group]);
80 if (ret) {
81 devm_kfree(chip->dev, tcbpwm);
82 return ret;
83 }
84
85 pwm_set_chip_data(pwm, tcbpwm);
86 tcbpwm->polarity = PWM_POLARITY_NORMAL;
87 tcbpwm->duty = 0;
88 tcbpwm->period = 0;
89 tcbpwm->div = 0;
90
91 spin_lock(&tcbpwmc->lock);
92 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
93 /*
94 * Get init config from Timer Counter registers if
95 * Timer Counter is already configured as a PWM generator.
96 */
97 if (cmr & ATMEL_TC_WAVE) {
98 if (index == 0)
99 tcbpwm->duty =
100 __raw_readl(regs + ATMEL_TC_REG(group, RA));
101 else
102 tcbpwm->duty =
103 __raw_readl(regs + ATMEL_TC_REG(group, RB));
104
105 tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
106 tcbpwm->period = __raw_readl(regs + ATMEL_TC_REG(group, RC));
107 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
108 ATMEL_TC_BCMR_MASK);
109 } else
110 cmr = 0;
111
112 cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
113 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
114 spin_unlock(&tcbpwmc->lock);
115
116 tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
117
118 return 0;
119}
120
121static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
122{
123 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
124 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
125 struct atmel_tc *tc = tcbpwmc->tc;
126
127 clk_disable_unprepare(tc->clk[pwm->hwpwm / 2]);
128 tcbpwmc->pwms[pwm->hwpwm] = NULL;
129 devm_kfree(chip->dev, tcbpwm);
130}
131
132static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
133{
134 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
135 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
136 struct atmel_tc *tc = tcbpwmc->tc;
137 void __iomem *regs = tc->regs;
138 unsigned group = pwm->hwpwm / 2;
139 unsigned index = pwm->hwpwm % 2;
140 unsigned cmr;
141 enum pwm_polarity polarity = tcbpwm->polarity;
142
143 /*
144 * If duty is 0 the timer will be stopped and we have to
145 * configure the output correctly on software trigger:
146 * - set output to high if PWM_POLARITY_INVERSED
147 * - set output to low if PWM_POLARITY_NORMAL
148 *
149 * This is why we're reverting polarity in this case.
150 */
151 if (tcbpwm->duty == 0)
152 polarity = !polarity;
153
154 spin_lock(&tcbpwmc->lock);
155 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
156
157 /* flush old setting and set the new one */
158 if (index == 0) {
159 cmr &= ~ATMEL_TC_ACMR_MASK;
160 if (polarity == PWM_POLARITY_INVERSED)
161 cmr |= ATMEL_TC_ASWTRG_CLEAR;
162 else
163 cmr |= ATMEL_TC_ASWTRG_SET;
164 } else {
165 cmr &= ~ATMEL_TC_BCMR_MASK;
166 if (polarity == PWM_POLARITY_INVERSED)
167 cmr |= ATMEL_TC_BSWTRG_CLEAR;
168 else
169 cmr |= ATMEL_TC_BSWTRG_SET;
170 }
171
172 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
173
174 /*
175 * Use software trigger to apply the new setting.
176 * If both PWM devices in this group are disabled we stop the clock.
177 */
178 if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC)))
179 __raw_writel(ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS,
180 regs + ATMEL_TC_REG(group, CCR));
181 else
182 __raw_writel(ATMEL_TC_SWTRG, regs +
183 ATMEL_TC_REG(group, CCR));
184
185 spin_unlock(&tcbpwmc->lock);
186}
187
188static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
189{
190 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
191 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
192 struct atmel_tc *tc = tcbpwmc->tc;
193 void __iomem *regs = tc->regs;
194 unsigned group = pwm->hwpwm / 2;
195 unsigned index = pwm->hwpwm % 2;
196 u32 cmr;
197 enum pwm_polarity polarity = tcbpwm->polarity;
198
199 /*
200 * If duty is 0 the timer will be stopped and we have to
201 * configure the output correctly on software trigger:
202 * - set output to high if PWM_POLARITY_INVERSED
203 * - set output to low if PWM_POLARITY_NORMAL
204 *
205 * This is why we're reverting polarity in this case.
206 */
207 if (tcbpwm->duty == 0)
208 polarity = !polarity;
209
210 spin_lock(&tcbpwmc->lock);
211 cmr = __raw_readl(regs + ATMEL_TC_REG(group, CMR));
212
213 /* flush old setting and set the new one */
214 cmr &= ~ATMEL_TC_TCCLKS;
215
216 if (index == 0) {
217 cmr &= ~ATMEL_TC_ACMR_MASK;
218
219 /* Set CMR flags according to given polarity */
220 if (polarity == PWM_POLARITY_INVERSED)
221 cmr |= ATMEL_TC_ASWTRG_CLEAR;
222 else
223 cmr |= ATMEL_TC_ASWTRG_SET;
224 } else {
225 cmr &= ~ATMEL_TC_BCMR_MASK;
226 if (polarity == PWM_POLARITY_INVERSED)
227 cmr |= ATMEL_TC_BSWTRG_CLEAR;
228 else
229 cmr |= ATMEL_TC_BSWTRG_SET;
230 }
231
232 /*
233 * If duty is 0 or equal to period there's no need to register
234 * a specific action on RA/RB and RC compare.
235 * The output will be configured on software trigger and keep
236 * this config till next config call.
237 */
238 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
239 if (index == 0) {
240 if (polarity == PWM_POLARITY_INVERSED)
241 cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
242 else
243 cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
244 } else {
245 if (polarity == PWM_POLARITY_INVERSED)
246 cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
247 else
248 cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
249 }
250 }
251
252 cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
253
254 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR));
255
256 if (index == 0)
257 __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA));
258 else
259 __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB));
260
261 __raw_writel(tcbpwm->period, regs + ATMEL_TC_REG(group, RC));
262
263 /* Use software trigger to apply the new setting */
264 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
265 regs + ATMEL_TC_REG(group, CCR));
266 spin_unlock(&tcbpwmc->lock);
267 return 0;
268}
269
270static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
271 int duty_ns, int period_ns)
272{
273 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
274 struct atmel_tcb_pwm_device *tcbpwm = pwm_get_chip_data(pwm);
275 unsigned group = pwm->hwpwm / 2;
276 unsigned index = pwm->hwpwm % 2;
277 struct atmel_tcb_pwm_device *atcbpwm = NULL;
278 struct atmel_tc *tc = tcbpwmc->tc;
279 int i;
280 int slowclk = 0;
281 unsigned period;
282 unsigned duty;
283 unsigned rate = clk_get_rate(tc->clk[group]);
284 unsigned long long min;
285 unsigned long long max;
286
287 /*
288 * Find best clk divisor:
289 * the smallest divisor which can fulfill the period_ns requirements.
290 */
291 for (i = 0; i < 5; ++i) {
292 if (atmel_tc_divisors[i] == 0) {
293 slowclk = i;
294 continue;
295 }
296 min = div_u64((u64)NSEC_PER_SEC * atmel_tc_divisors[i], rate);
297 max = min << tc->tcb_config->counter_width;
298 if (max >= period_ns)
299 break;
300 }
301
302 /*
303 * If none of the divisor are small enough to represent period_ns
304 * take slow clock (32KHz).
305 */
306 if (i == 5) {
307 i = slowclk;
308 rate = clk_get_rate(tc->slow_clk);
309 min = div_u64(NSEC_PER_SEC, rate);
310 max = min << tc->tcb_config->counter_width;
311
312 /* If period is too big return ERANGE error */
313 if (max < period_ns)
314 return -ERANGE;
315 }
316
317 duty = div_u64(duty_ns, min);
318 period = div_u64(period_ns, min);
319
320 if (index == 0)
321 atcbpwm = tcbpwmc->pwms[pwm->hwpwm + 1];
322 else
323 atcbpwm = tcbpwmc->pwms[pwm->hwpwm - 1];
324
325 /*
326 * PWM devices provided by TCB driver are grouped by 2:
327 * - group 0: PWM 0 & 1
328 * - group 1: PWM 2 & 3
329 * - group 2: PWM 4 & 5
330 *
331 * PWM devices in a given group must be configured with the
332 * same period_ns.
333 *
334 * We're checking the period value of the second PWM device
335 * in this group before applying the new config.
336 */
337 if ((atcbpwm && atcbpwm->duty > 0 &&
338 atcbpwm->duty != atcbpwm->period) &&
339 (atcbpwm->div != i || atcbpwm->period != period)) {
340 dev_err(chip->dev,
341 "failed to configure period_ns: PWM group already configured with a different value\n");
342 return -EINVAL;
343 }
344
345 tcbpwm->period = period;
346 tcbpwm->div = i;
347 tcbpwm->duty = duty;
348
349 /* If the PWM is enabled, call enable to apply the new conf */
350 if (pwm_is_enabled(pwm))
351 atmel_tcb_pwm_enable(chip, pwm);
352
353 return 0;
354}
355
356static const struct pwm_ops atmel_tcb_pwm_ops = {
357 .request = atmel_tcb_pwm_request,
358 .free = atmel_tcb_pwm_free,
359 .config = atmel_tcb_pwm_config,
360 .set_polarity = atmel_tcb_pwm_set_polarity,
361 .enable = atmel_tcb_pwm_enable,
362 .disable = atmel_tcb_pwm_disable,
363 .owner = THIS_MODULE,
364};
365
366static int atmel_tcb_pwm_probe(struct platform_device *pdev)
367{
368 struct atmel_tcb_pwm_chip *tcbpwm;
369 struct device_node *np = pdev->dev.of_node;
370 struct atmel_tc *tc;
371 int err;
372 int tcblock;
373
374 err = of_property_read_u32(np, "tc-block", &tcblock);
375 if (err < 0) {
376 dev_err(&pdev->dev,
377 "failed to get Timer Counter Block number from device tree (error: %d)\n",
378 err);
379 return err;
380 }
381
382 tc = atmel_tc_alloc(tcblock);
383 if (tc == NULL) {
384 dev_err(&pdev->dev, "failed to allocate Timer Counter Block\n");
385 return -ENOMEM;
386 }
387
388 tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
389 if (tcbpwm == NULL) {
390 err = -ENOMEM;
391 dev_err(&pdev->dev, "failed to allocate memory\n");
392 goto err_free_tc;
393 }
394
395 tcbpwm->chip.dev = &pdev->dev;
396 tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
397 tcbpwm->chip.of_xlate = of_pwm_xlate_with_flags;
398 tcbpwm->chip.of_pwm_n_cells = 3;
399 tcbpwm->chip.base = -1;
400 tcbpwm->chip.npwm = NPWM;
401 tcbpwm->tc = tc;
402
403 err = clk_prepare_enable(tc->slow_clk);
404 if (err)
405 goto err_free_tc;
406
407 spin_lock_init(&tcbpwm->lock);
408
409 err = pwmchip_add(&tcbpwm->chip);
410 if (err < 0)
411 goto err_disable_clk;
412
413 platform_set_drvdata(pdev, tcbpwm);
414
415 return 0;
416
417err_disable_clk:
418 clk_disable_unprepare(tcbpwm->tc->slow_clk);
419
420err_free_tc:
421 atmel_tc_free(tc);
422
423 return err;
424}
425
426static int atmel_tcb_pwm_remove(struct platform_device *pdev)
427{
428 struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
429 int err;
430
431 clk_disable_unprepare(tcbpwm->tc->slow_clk);
432
433 err = pwmchip_remove(&tcbpwm->chip);
434 if (err < 0)
435 return err;
436
437 atmel_tc_free(tcbpwm->tc);
438
439 return 0;
440}
441
442static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
443 { .compatible = "atmel,tcb-pwm", },
444 { /* sentinel */ }
445};
446MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
447
448static struct platform_driver atmel_tcb_pwm_driver = {
449 .driver = {
450 .name = "atmel-tcb-pwm",
451 .of_match_table = atmel_tcb_pwm_dt_ids,
452 },
453 .probe = atmel_tcb_pwm_probe,
454 .remove = atmel_tcb_pwm_remove,
455};
456module_platform_driver(atmel_tcb_pwm_driver);
457
458MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
459MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
460MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) Overkiz SAS 2012
4 *
5 * Author: Boris BREZILLON <b.brezillon@overkiz.com>
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/clocksource.h>
11#include <linux/clockchips.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/mfd/syscon.h>
20#include <linux/platform_device.h>
21#include <linux/pwm.h>
22#include <linux/of_device.h>
23#include <linux/of_irq.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26#include <soc/at91/atmel_tcb.h>
27
28#define NPWM 2
29
30#define ATMEL_TC_ACMR_MASK (ATMEL_TC_ACPA | ATMEL_TC_ACPC | \
31 ATMEL_TC_AEEVT | ATMEL_TC_ASWTRG)
32
33#define ATMEL_TC_BCMR_MASK (ATMEL_TC_BCPB | ATMEL_TC_BCPC | \
34 ATMEL_TC_BEEVT | ATMEL_TC_BSWTRG)
35
36struct atmel_tcb_pwm_device {
37 enum pwm_polarity polarity; /* PWM polarity */
38 unsigned div; /* PWM clock divider */
39 unsigned duty; /* PWM duty expressed in clk cycles */
40 unsigned period; /* PWM period expressed in clk cycles */
41};
42
43struct atmel_tcb_channel {
44 u32 enabled;
45 u32 cmr;
46 u32 ra;
47 u32 rb;
48 u32 rc;
49};
50
51struct atmel_tcb_pwm_chip {
52 struct pwm_chip chip;
53 spinlock_t lock;
54 u8 channel;
55 u8 width;
56 struct regmap *regmap;
57 struct clk *clk;
58 struct clk *gclk;
59 struct clk *slow_clk;
60 struct atmel_tcb_pwm_device *pwms[NPWM];
61 struct atmel_tcb_channel bkup;
62};
63
64static const u8 atmel_tcb_divisors[] = { 2, 8, 32, 128, 0, };
65
66static inline struct atmel_tcb_pwm_chip *to_tcb_chip(struct pwm_chip *chip)
67{
68 return container_of(chip, struct atmel_tcb_pwm_chip, chip);
69}
70
71static int atmel_tcb_pwm_set_polarity(struct pwm_chip *chip,
72 struct pwm_device *pwm,
73 enum pwm_polarity polarity)
74{
75 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
76 struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
77
78 tcbpwm->polarity = polarity;
79
80 return 0;
81}
82
83static int atmel_tcb_pwm_request(struct pwm_chip *chip,
84 struct pwm_device *pwm)
85{
86 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
87 struct atmel_tcb_pwm_device *tcbpwm;
88 unsigned cmr;
89 int ret;
90
91 tcbpwm = devm_kzalloc(chip->dev, sizeof(*tcbpwm), GFP_KERNEL);
92 if (!tcbpwm)
93 return -ENOMEM;
94
95 ret = clk_prepare_enable(tcbpwmc->clk);
96 if (ret) {
97 devm_kfree(chip->dev, tcbpwm);
98 return ret;
99 }
100
101 tcbpwm->polarity = PWM_POLARITY_NORMAL;
102 tcbpwm->duty = 0;
103 tcbpwm->period = 0;
104 tcbpwm->div = 0;
105
106 spin_lock(&tcbpwmc->lock);
107 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
108 /*
109 * Get init config from Timer Counter registers if
110 * Timer Counter is already configured as a PWM generator.
111 */
112 if (cmr & ATMEL_TC_WAVE) {
113 if (pwm->hwpwm == 0)
114 regmap_read(tcbpwmc->regmap,
115 ATMEL_TC_REG(tcbpwmc->channel, RA),
116 &tcbpwm->duty);
117 else
118 regmap_read(tcbpwmc->regmap,
119 ATMEL_TC_REG(tcbpwmc->channel, RB),
120 &tcbpwm->duty);
121
122 tcbpwm->div = cmr & ATMEL_TC_TCCLKS;
123 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
124 &tcbpwm->period);
125 cmr &= (ATMEL_TC_TCCLKS | ATMEL_TC_ACMR_MASK |
126 ATMEL_TC_BCMR_MASK);
127 } else
128 cmr = 0;
129
130 cmr |= ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO | ATMEL_TC_EEVT_XC0;
131 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
132 spin_unlock(&tcbpwmc->lock);
133
134 tcbpwmc->pwms[pwm->hwpwm] = tcbpwm;
135
136 return 0;
137}
138
139static void atmel_tcb_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
140{
141 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
142 struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
143
144 clk_disable_unprepare(tcbpwmc->clk);
145 tcbpwmc->pwms[pwm->hwpwm] = NULL;
146 devm_kfree(chip->dev, tcbpwm);
147}
148
149static void atmel_tcb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
150{
151 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
152 struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
153 unsigned cmr;
154 enum pwm_polarity polarity = tcbpwm->polarity;
155
156 /*
157 * If duty is 0 the timer will be stopped and we have to
158 * configure the output correctly on software trigger:
159 * - set output to high if PWM_POLARITY_INVERSED
160 * - set output to low if PWM_POLARITY_NORMAL
161 *
162 * This is why we're reverting polarity in this case.
163 */
164 if (tcbpwm->duty == 0)
165 polarity = !polarity;
166
167 spin_lock(&tcbpwmc->lock);
168 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
169
170 /* flush old setting and set the new one */
171 if (pwm->hwpwm == 0) {
172 cmr &= ~ATMEL_TC_ACMR_MASK;
173 if (polarity == PWM_POLARITY_INVERSED)
174 cmr |= ATMEL_TC_ASWTRG_CLEAR;
175 else
176 cmr |= ATMEL_TC_ASWTRG_SET;
177 } else {
178 cmr &= ~ATMEL_TC_BCMR_MASK;
179 if (polarity == PWM_POLARITY_INVERSED)
180 cmr |= ATMEL_TC_BSWTRG_CLEAR;
181 else
182 cmr |= ATMEL_TC_BSWTRG_SET;
183 }
184
185 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
186
187 /*
188 * Use software trigger to apply the new setting.
189 * If both PWM devices in this group are disabled we stop the clock.
190 */
191 if (!(cmr & (ATMEL_TC_ACPC | ATMEL_TC_BCPC))) {
192 regmap_write(tcbpwmc->regmap,
193 ATMEL_TC_REG(tcbpwmc->channel, CCR),
194 ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS);
195 tcbpwmc->bkup.enabled = 1;
196 } else {
197 regmap_write(tcbpwmc->regmap,
198 ATMEL_TC_REG(tcbpwmc->channel, CCR),
199 ATMEL_TC_SWTRG);
200 tcbpwmc->bkup.enabled = 0;
201 }
202
203 spin_unlock(&tcbpwmc->lock);
204}
205
206static int atmel_tcb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
207{
208 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
209 struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
210 u32 cmr;
211 enum pwm_polarity polarity = tcbpwm->polarity;
212
213 /*
214 * If duty is 0 the timer will be stopped and we have to
215 * configure the output correctly on software trigger:
216 * - set output to high if PWM_POLARITY_INVERSED
217 * - set output to low if PWM_POLARITY_NORMAL
218 *
219 * This is why we're reverting polarity in this case.
220 */
221 if (tcbpwm->duty == 0)
222 polarity = !polarity;
223
224 spin_lock(&tcbpwmc->lock);
225 regmap_read(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), &cmr);
226
227 /* flush old setting and set the new one */
228 cmr &= ~ATMEL_TC_TCCLKS;
229
230 if (pwm->hwpwm == 0) {
231 cmr &= ~ATMEL_TC_ACMR_MASK;
232
233 /* Set CMR flags according to given polarity */
234 if (polarity == PWM_POLARITY_INVERSED)
235 cmr |= ATMEL_TC_ASWTRG_CLEAR;
236 else
237 cmr |= ATMEL_TC_ASWTRG_SET;
238 } else {
239 cmr &= ~ATMEL_TC_BCMR_MASK;
240 if (polarity == PWM_POLARITY_INVERSED)
241 cmr |= ATMEL_TC_BSWTRG_CLEAR;
242 else
243 cmr |= ATMEL_TC_BSWTRG_SET;
244 }
245
246 /*
247 * If duty is 0 or equal to period there's no need to register
248 * a specific action on RA/RB and RC compare.
249 * The output will be configured on software trigger and keep
250 * this config till next config call.
251 */
252 if (tcbpwm->duty != tcbpwm->period && tcbpwm->duty > 0) {
253 if (pwm->hwpwm == 0) {
254 if (polarity == PWM_POLARITY_INVERSED)
255 cmr |= ATMEL_TC_ACPA_SET | ATMEL_TC_ACPC_CLEAR;
256 else
257 cmr |= ATMEL_TC_ACPA_CLEAR | ATMEL_TC_ACPC_SET;
258 } else {
259 if (polarity == PWM_POLARITY_INVERSED)
260 cmr |= ATMEL_TC_BCPB_SET | ATMEL_TC_BCPC_CLEAR;
261 else
262 cmr |= ATMEL_TC_BCPB_CLEAR | ATMEL_TC_BCPC_SET;
263 }
264 }
265
266 cmr |= (tcbpwm->div & ATMEL_TC_TCCLKS);
267
268 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CMR), cmr);
269
270 if (pwm->hwpwm == 0)
271 regmap_write(tcbpwmc->regmap,
272 ATMEL_TC_REG(tcbpwmc->channel, RA),
273 tcbpwm->duty);
274 else
275 regmap_write(tcbpwmc->regmap,
276 ATMEL_TC_REG(tcbpwmc->channel, RB),
277 tcbpwm->duty);
278
279 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, RC),
280 tcbpwm->period);
281
282 /* Use software trigger to apply the new setting */
283 regmap_write(tcbpwmc->regmap, ATMEL_TC_REG(tcbpwmc->channel, CCR),
284 ATMEL_TC_SWTRG | ATMEL_TC_CLKEN);
285 tcbpwmc->bkup.enabled = 1;
286 spin_unlock(&tcbpwmc->lock);
287 return 0;
288}
289
290static int atmel_tcb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
291 int duty_ns, int period_ns)
292{
293 struct atmel_tcb_pwm_chip *tcbpwmc = to_tcb_chip(chip);
294 struct atmel_tcb_pwm_device *tcbpwm = tcbpwmc->pwms[pwm->hwpwm];
295 struct atmel_tcb_pwm_device *atcbpwm = NULL;
296 int i = 0;
297 int slowclk = 0;
298 unsigned period;
299 unsigned duty;
300 unsigned rate = clk_get_rate(tcbpwmc->clk);
301 unsigned long long min;
302 unsigned long long max;
303
304 /*
305 * Find best clk divisor:
306 * the smallest divisor which can fulfill the period_ns requirements.
307 * If there is a gclk, the first divisor is actually the gclk selector
308 */
309 if (tcbpwmc->gclk)
310 i = 1;
311 for (; i < ARRAY_SIZE(atmel_tcb_divisors); ++i) {
312 if (atmel_tcb_divisors[i] == 0) {
313 slowclk = i;
314 continue;
315 }
316 min = div_u64((u64)NSEC_PER_SEC * atmel_tcb_divisors[i], rate);
317 max = min << tcbpwmc->width;
318 if (max >= period_ns)
319 break;
320 }
321
322 /*
323 * If none of the divisor are small enough to represent period_ns
324 * take slow clock (32KHz).
325 */
326 if (i == ARRAY_SIZE(atmel_tcb_divisors)) {
327 i = slowclk;
328 rate = clk_get_rate(tcbpwmc->slow_clk);
329 min = div_u64(NSEC_PER_SEC, rate);
330 max = min << tcbpwmc->width;
331
332 /* If period is too big return ERANGE error */
333 if (max < period_ns)
334 return -ERANGE;
335 }
336
337 duty = div_u64(duty_ns, min);
338 period = div_u64(period_ns, min);
339
340 if (pwm->hwpwm == 0)
341 atcbpwm = tcbpwmc->pwms[1];
342 else
343 atcbpwm = tcbpwmc->pwms[0];
344
345 /*
346 * PWM devices provided by the TCB driver are grouped by 2.
347 * PWM devices in a given group must be configured with the
348 * same period_ns.
349 *
350 * We're checking the period value of the second PWM device
351 * in this group before applying the new config.
352 */
353 if ((atcbpwm && atcbpwm->duty > 0 &&
354 atcbpwm->duty != atcbpwm->period) &&
355 (atcbpwm->div != i || atcbpwm->period != period)) {
356 dev_err(chip->dev,
357 "failed to configure period_ns: PWM group already configured with a different value\n");
358 return -EINVAL;
359 }
360
361 tcbpwm->period = period;
362 tcbpwm->div = i;
363 tcbpwm->duty = duty;
364
365 return 0;
366}
367
368static int atmel_tcb_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
369 const struct pwm_state *state)
370{
371 int duty_cycle, period;
372 int ret;
373
374 /* This function only sets a flag in driver data */
375 atmel_tcb_pwm_set_polarity(chip, pwm, state->polarity);
376
377 if (!state->enabled) {
378 atmel_tcb_pwm_disable(chip, pwm);
379 return 0;
380 }
381
382 period = state->period < INT_MAX ? state->period : INT_MAX;
383 duty_cycle = state->duty_cycle < INT_MAX ? state->duty_cycle : INT_MAX;
384
385 ret = atmel_tcb_pwm_config(chip, pwm, duty_cycle, period);
386 if (ret)
387 return ret;
388
389 return atmel_tcb_pwm_enable(chip, pwm);
390}
391
392static const struct pwm_ops atmel_tcb_pwm_ops = {
393 .request = atmel_tcb_pwm_request,
394 .free = atmel_tcb_pwm_free,
395 .apply = atmel_tcb_pwm_apply,
396 .owner = THIS_MODULE,
397};
398
399static struct atmel_tcb_config tcb_rm9200_config = {
400 .counter_width = 16,
401};
402
403static struct atmel_tcb_config tcb_sam9x5_config = {
404 .counter_width = 32,
405};
406
407static struct atmel_tcb_config tcb_sama5d2_config = {
408 .counter_width = 32,
409 .has_gclk = 1,
410};
411
412static const struct of_device_id atmel_tcb_of_match[] = {
413 { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
414 { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
415 { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
416 { /* sentinel */ }
417};
418
419static int atmel_tcb_pwm_probe(struct platform_device *pdev)
420{
421 const struct of_device_id *match;
422 struct atmel_tcb_pwm_chip *tcbpwm;
423 const struct atmel_tcb_config *config;
424 struct device_node *np = pdev->dev.of_node;
425 struct regmap *regmap;
426 struct clk *clk, *gclk = NULL;
427 struct clk *slow_clk;
428 char clk_name[] = "t0_clk";
429 int err;
430 int channel;
431
432 err = of_property_read_u32(np, "reg", &channel);
433 if (err < 0) {
434 dev_err(&pdev->dev,
435 "failed to get Timer Counter Block channel from device tree (error: %d)\n",
436 err);
437 return err;
438 }
439
440 regmap = syscon_node_to_regmap(np->parent);
441 if (IS_ERR(regmap))
442 return PTR_ERR(regmap);
443
444 slow_clk = of_clk_get_by_name(np->parent, "slow_clk");
445 if (IS_ERR(slow_clk))
446 return PTR_ERR(slow_clk);
447
448 clk_name[1] += channel;
449 clk = of_clk_get_by_name(np->parent, clk_name);
450 if (IS_ERR(clk))
451 clk = of_clk_get_by_name(np->parent, "t0_clk");
452 if (IS_ERR(clk))
453 return PTR_ERR(clk);
454
455 match = of_match_node(atmel_tcb_of_match, np->parent);
456 config = match->data;
457
458 if (config->has_gclk) {
459 gclk = of_clk_get_by_name(np->parent, "gclk");
460 if (IS_ERR(gclk))
461 return PTR_ERR(gclk);
462 }
463
464 tcbpwm = devm_kzalloc(&pdev->dev, sizeof(*tcbpwm), GFP_KERNEL);
465 if (tcbpwm == NULL) {
466 err = -ENOMEM;
467 goto err_slow_clk;
468 }
469
470 tcbpwm->chip.dev = &pdev->dev;
471 tcbpwm->chip.ops = &atmel_tcb_pwm_ops;
472 tcbpwm->chip.npwm = NPWM;
473 tcbpwm->channel = channel;
474 tcbpwm->regmap = regmap;
475 tcbpwm->clk = clk;
476 tcbpwm->gclk = gclk;
477 tcbpwm->slow_clk = slow_clk;
478 tcbpwm->width = config->counter_width;
479
480 err = clk_prepare_enable(slow_clk);
481 if (err)
482 goto err_slow_clk;
483
484 spin_lock_init(&tcbpwm->lock);
485
486 err = pwmchip_add(&tcbpwm->chip);
487 if (err < 0)
488 goto err_disable_clk;
489
490 platform_set_drvdata(pdev, tcbpwm);
491
492 return 0;
493
494err_disable_clk:
495 clk_disable_unprepare(tcbpwm->slow_clk);
496
497err_slow_clk:
498 clk_put(slow_clk);
499
500 return err;
501}
502
503static int atmel_tcb_pwm_remove(struct platform_device *pdev)
504{
505 struct atmel_tcb_pwm_chip *tcbpwm = platform_get_drvdata(pdev);
506
507 pwmchip_remove(&tcbpwm->chip);
508
509 clk_disable_unprepare(tcbpwm->slow_clk);
510 clk_put(tcbpwm->slow_clk);
511 clk_put(tcbpwm->clk);
512
513 return 0;
514}
515
516static const struct of_device_id atmel_tcb_pwm_dt_ids[] = {
517 { .compatible = "atmel,tcb-pwm", },
518 { /* sentinel */ }
519};
520MODULE_DEVICE_TABLE(of, atmel_tcb_pwm_dt_ids);
521
522#ifdef CONFIG_PM_SLEEP
523static int atmel_tcb_pwm_suspend(struct device *dev)
524{
525 struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
526 struct atmel_tcb_channel *chan = &tcbpwm->bkup;
527 unsigned int channel = tcbpwm->channel;
528
529 regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), &chan->cmr);
530 regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), &chan->ra);
531 regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), &chan->rb);
532 regmap_read(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), &chan->rc);
533
534 return 0;
535}
536
537static int atmel_tcb_pwm_resume(struct device *dev)
538{
539 struct atmel_tcb_pwm_chip *tcbpwm = dev_get_drvdata(dev);
540 struct atmel_tcb_channel *chan = &tcbpwm->bkup;
541 unsigned int channel = tcbpwm->channel;
542
543 regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, CMR), chan->cmr);
544 regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RA), chan->ra);
545 regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RB), chan->rb);
546 regmap_write(tcbpwm->regmap, ATMEL_TC_REG(channel, RC), chan->rc);
547
548 if (chan->enabled)
549 regmap_write(tcbpwm->regmap,
550 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,
551 ATMEL_TC_REG(channel, CCR));
552
553 return 0;
554}
555#endif
556
557static SIMPLE_DEV_PM_OPS(atmel_tcb_pwm_pm_ops, atmel_tcb_pwm_suspend,
558 atmel_tcb_pwm_resume);
559
560static struct platform_driver atmel_tcb_pwm_driver = {
561 .driver = {
562 .name = "atmel-tcb-pwm",
563 .of_match_table = atmel_tcb_pwm_dt_ids,
564 .pm = &atmel_tcb_pwm_pm_ops,
565 },
566 .probe = atmel_tcb_pwm_probe,
567 .remove = atmel_tcb_pwm_remove,
568};
569module_platform_driver(atmel_tcb_pwm_driver);
570
571MODULE_AUTHOR("Boris BREZILLON <b.brezillon@overkiz.com>");
572MODULE_DESCRIPTION("Atmel Timer Counter Pulse Width Modulation Driver");
573MODULE_LICENSE("GPL v2");