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1/*
2 * intel_scu_ipc.c: Driver for the Intel SCU IPC mechanism
3 *
4 * (C) Copyright 2008-2010,2015 Intel Corporation
5 * Author: Sreedhara DS (sreedhara.ds@intel.com)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
10 * of the License.
11 *
12 * SCU running in ARC processor communicates with other entity running in IA
13 * core through IPC mechanism which in turn messaging between IA core ad SCU.
14 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
15 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
16 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
17 * along with other APIs.
18 */
19#include <linux/delay.h>
20#include <linux/errno.h>
21#include <linux/init.h>
22#include <linux/device.h>
23#include <linux/pm.h>
24#include <linux/pci.h>
25#include <linux/interrupt.h>
26#include <linux/sfi.h>
27#include <asm/intel-mid.h>
28#include <asm/intel_scu_ipc.h>
29
30/* IPC defines the following message types */
31#define IPCMSG_WATCHDOG_TIMER 0xF8 /* Set Kernel Watchdog Threshold */
32#define IPCMSG_BATTERY 0xEF /* Coulomb Counter Accumulator */
33#define IPCMSG_FW_UPDATE 0xFE /* Firmware update */
34#define IPCMSG_PCNTRL 0xFF /* Power controller unit read/write */
35#define IPCMSG_FW_REVISION 0xF4 /* Get firmware revision */
36
37/* Command id associated with message IPCMSG_PCNTRL */
38#define IPC_CMD_PCNTRL_W 0 /* Register write */
39#define IPC_CMD_PCNTRL_R 1 /* Register read */
40#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
41
42/*
43 * IPC register summary
44 *
45 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
46 * To read or write information to the SCU, driver writes to IPC-1 memory
47 * mapped registers. The following is the IPC mechanism
48 *
49 * 1. IA core cDMI interface claims this transaction and converts it to a
50 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
51 *
52 * 2. South Complex cDMI block receives this message and writes it to
53 * the IPC-1 register block, causing an interrupt to the SCU
54 *
55 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
56 * message handler is called within firmware.
57 */
58
59#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
60#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
61#define IPC_IOC 0x100 /* IPC command register IOC bit */
62
63#define PCI_DEVICE_ID_LINCROFT 0x082a
64#define PCI_DEVICE_ID_PENWELL 0x080e
65#define PCI_DEVICE_ID_CLOVERVIEW 0x08ea
66#define PCI_DEVICE_ID_TANGIER 0x11a0
67
68/* intel scu ipc driver data */
69struct intel_scu_ipc_pdata_t {
70 u32 i2c_base;
71 u32 i2c_len;
72 u8 irq_mode;
73};
74
75static struct intel_scu_ipc_pdata_t intel_scu_ipc_lincroft_pdata = {
76 .i2c_base = 0xff12b000,
77 .i2c_len = 0x10,
78 .irq_mode = 0,
79};
80
81/* Penwell and Cloverview */
82static struct intel_scu_ipc_pdata_t intel_scu_ipc_penwell_pdata = {
83 .i2c_base = 0xff12b000,
84 .i2c_len = 0x10,
85 .irq_mode = 1,
86};
87
88static struct intel_scu_ipc_pdata_t intel_scu_ipc_tangier_pdata = {
89 .i2c_base = 0xff00d000,
90 .i2c_len = 0x10,
91 .irq_mode = 0,
92};
93
94struct intel_scu_ipc_dev {
95 struct device *dev;
96 void __iomem *ipc_base;
97 void __iomem *i2c_base;
98 struct completion cmd_complete;
99 u8 irq_mode;
100};
101
102static struct intel_scu_ipc_dev ipcdev; /* Only one for now */
103
104/*
105 * IPC Read Buffer (Read Only):
106 * 16 byte buffer for receiving data from SCU, if IPC command
107 * processing results in response data
108 */
109#define IPC_READ_BUFFER 0x90
110
111#define IPC_I2C_CNTRL_ADDR 0
112#define I2C_DATA_ADDR 0x04
113
114static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
115
116/*
117 * Send ipc command
118 * Command Register (Write Only):
119 * A write to this register results in an interrupt to the SCU core processor
120 * Format:
121 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
122 */
123static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
124{
125 if (scu->irq_mode) {
126 reinit_completion(&scu->cmd_complete);
127 writel(cmd | IPC_IOC, scu->ipc_base);
128 }
129 writel(cmd, scu->ipc_base);
130}
131
132/*
133 * Write ipc data
134 * IPC Write Buffer (Write Only):
135 * 16-byte buffer for sending data associated with IPC command to
136 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
137 */
138static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
139{
140 writel(data, scu->ipc_base + 0x80 + offset);
141}
142
143/*
144 * Status Register (Read Only):
145 * Driver will read this register to get the ready/busy status of the IPC
146 * block and error status of the IPC command that was just processed by SCU
147 * Format:
148 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
149 */
150static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
151{
152 return __raw_readl(scu->ipc_base + 0x04);
153}
154
155/* Read ipc byte data */
156static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
157{
158 return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
159}
160
161/* Read ipc u32 data */
162static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
163{
164 return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
165}
166
167/* Wait till scu status is busy */
168static inline int busy_loop(struct intel_scu_ipc_dev *scu)
169{
170 u32 status = ipc_read_status(scu);
171 u32 loop_count = 100000;
172
173 /* break if scu doesn't reset busy bit after huge retry */
174 while ((status & BIT(0)) && --loop_count) {
175 udelay(1); /* scu processing time is in few u secods */
176 status = ipc_read_status(scu);
177 }
178
179 if (status & BIT(0)) {
180 dev_err(scu->dev, "IPC timed out");
181 return -ETIMEDOUT;
182 }
183
184 if (status & BIT(1))
185 return -EIO;
186
187 return 0;
188}
189
190/* Wait till ipc ioc interrupt is received or timeout in 3 HZ */
191static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
192{
193 int status;
194
195 if (!wait_for_completion_timeout(&scu->cmd_complete, 3 * HZ)) {
196 dev_err(scu->dev, "IPC timed out\n");
197 return -ETIMEDOUT;
198 }
199
200 status = ipc_read_status(scu);
201 if (status & BIT(1))
202 return -EIO;
203
204 return 0;
205}
206
207static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
208{
209 return scu->irq_mode ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
210}
211
212/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
213static int pwr_reg_rdwr(u16 *addr, u8 *data, u32 count, u32 op, u32 id)
214{
215 struct intel_scu_ipc_dev *scu = &ipcdev;
216 int nc;
217 u32 offset = 0;
218 int err;
219 u8 cbuf[IPC_WWBUF_SIZE];
220 u32 *wbuf = (u32 *)&cbuf;
221
222 memset(cbuf, 0, sizeof(cbuf));
223
224 mutex_lock(&ipclock);
225
226 if (scu->dev == NULL) {
227 mutex_unlock(&ipclock);
228 return -ENODEV;
229 }
230
231 for (nc = 0; nc < count; nc++, offset += 2) {
232 cbuf[offset] = addr[nc];
233 cbuf[offset + 1] = addr[nc] >> 8;
234 }
235
236 if (id == IPC_CMD_PCNTRL_R) {
237 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
238 ipc_data_writel(scu, wbuf[nc], offset);
239 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
240 } else if (id == IPC_CMD_PCNTRL_W) {
241 for (nc = 0; nc < count; nc++, offset += 1)
242 cbuf[offset] = data[nc];
243 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
244 ipc_data_writel(scu, wbuf[nc], offset);
245 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
246 } else if (id == IPC_CMD_PCNTRL_M) {
247 cbuf[offset] = data[0];
248 cbuf[offset + 1] = data[1];
249 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
250 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
251 }
252
253 err = intel_scu_ipc_check_status(scu);
254 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
255 /* Workaround: values are read as 0 without memcpy_fromio */
256 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
257 for (nc = 0; nc < count; nc++)
258 data[nc] = ipc_data_readb(scu, nc);
259 }
260 mutex_unlock(&ipclock);
261 return err;
262}
263
264/**
265 * intel_scu_ipc_ioread8 - read a word via the SCU
266 * @addr: register on SCU
267 * @data: return pointer for read byte
268 *
269 * Read a single register. Returns 0 on success or an error code. All
270 * locking between SCU accesses is handled for the caller.
271 *
272 * This function may sleep.
273 */
274int intel_scu_ipc_ioread8(u16 addr, u8 *data)
275{
276 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
277}
278EXPORT_SYMBOL(intel_scu_ipc_ioread8);
279
280/**
281 * intel_scu_ipc_ioread16 - read a word via the SCU
282 * @addr: register on SCU
283 * @data: return pointer for read word
284 *
285 * Read a register pair. Returns 0 on success or an error code. All
286 * locking between SCU accesses is handled for the caller.
287 *
288 * This function may sleep.
289 */
290int intel_scu_ipc_ioread16(u16 addr, u16 *data)
291{
292 u16 x[2] = {addr, addr + 1};
293 return pwr_reg_rdwr(x, (u8 *)data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
294}
295EXPORT_SYMBOL(intel_scu_ipc_ioread16);
296
297/**
298 * intel_scu_ipc_ioread32 - read a dword via the SCU
299 * @addr: register on SCU
300 * @data: return pointer for read dword
301 *
302 * Read four registers. Returns 0 on success or an error code. All
303 * locking between SCU accesses is handled for the caller.
304 *
305 * This function may sleep.
306 */
307int intel_scu_ipc_ioread32(u16 addr, u32 *data)
308{
309 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
310 return pwr_reg_rdwr(x, (u8 *)data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
311}
312EXPORT_SYMBOL(intel_scu_ipc_ioread32);
313
314/**
315 * intel_scu_ipc_iowrite8 - write a byte via the SCU
316 * @addr: register on SCU
317 * @data: byte to write
318 *
319 * Write a single register. Returns 0 on success or an error code. All
320 * locking between SCU accesses is handled for the caller.
321 *
322 * This function may sleep.
323 */
324int intel_scu_ipc_iowrite8(u16 addr, u8 data)
325{
326 return pwr_reg_rdwr(&addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
327}
328EXPORT_SYMBOL(intel_scu_ipc_iowrite8);
329
330/**
331 * intel_scu_ipc_iowrite16 - write a word via the SCU
332 * @addr: register on SCU
333 * @data: word to write
334 *
335 * Write two registers. Returns 0 on success or an error code. All
336 * locking between SCU accesses is handled for the caller.
337 *
338 * This function may sleep.
339 */
340int intel_scu_ipc_iowrite16(u16 addr, u16 data)
341{
342 u16 x[2] = {addr, addr + 1};
343 return pwr_reg_rdwr(x, (u8 *)&data, 2, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
344}
345EXPORT_SYMBOL(intel_scu_ipc_iowrite16);
346
347/**
348 * intel_scu_ipc_iowrite32 - write a dword via the SCU
349 * @addr: register on SCU
350 * @data: dword to write
351 *
352 * Write four registers. Returns 0 on success or an error code. All
353 * locking between SCU accesses is handled for the caller.
354 *
355 * This function may sleep.
356 */
357int intel_scu_ipc_iowrite32(u16 addr, u32 data)
358{
359 u16 x[4] = {addr, addr + 1, addr + 2, addr + 3};
360 return pwr_reg_rdwr(x, (u8 *)&data, 4, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
361}
362EXPORT_SYMBOL(intel_scu_ipc_iowrite32);
363
364/**
365 * intel_scu_ipc_readvv - read a set of registers
366 * @addr: register list
367 * @data: bytes to return
368 * @len: length of array
369 *
370 * Read registers. Returns 0 on success or an error code. All
371 * locking between SCU accesses is handled for the caller.
372 *
373 * The largest array length permitted by the hardware is 5 items.
374 *
375 * This function may sleep.
376 */
377int intel_scu_ipc_readv(u16 *addr, u8 *data, int len)
378{
379 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
380}
381EXPORT_SYMBOL(intel_scu_ipc_readv);
382
383/**
384 * intel_scu_ipc_writev - write a set of registers
385 * @addr: register list
386 * @data: bytes to write
387 * @len: length of array
388 *
389 * Write registers. Returns 0 on success or an error code. All
390 * locking between SCU accesses is handled for the caller.
391 *
392 * The largest array length permitted by the hardware is 5 items.
393 *
394 * This function may sleep.
395 *
396 */
397int intel_scu_ipc_writev(u16 *addr, u8 *data, int len)
398{
399 return pwr_reg_rdwr(addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
400}
401EXPORT_SYMBOL(intel_scu_ipc_writev);
402
403/**
404 * intel_scu_ipc_update_register - r/m/w a register
405 * @addr: register address
406 * @bits: bits to update
407 * @mask: mask of bits to update
408 *
409 * Read-modify-write power control unit register. The first data argument
410 * must be register value and second is mask value
411 * mask is a bitmap that indicates which bits to update.
412 * 0 = masked. Don't modify this bit, 1 = modify this bit.
413 * returns 0 on success or an error code.
414 *
415 * This function may sleep. Locking between SCU accesses is handled
416 * for the caller.
417 */
418int intel_scu_ipc_update_register(u16 addr, u8 bits, u8 mask)
419{
420 u8 data[2] = { bits, mask };
421 return pwr_reg_rdwr(&addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
422}
423EXPORT_SYMBOL(intel_scu_ipc_update_register);
424
425/**
426 * intel_scu_ipc_simple_command - send a simple command
427 * @cmd: command
428 * @sub: sub type
429 *
430 * Issue a simple command to the SCU. Do not use this interface if
431 * you must then access data as any data values may be overwritten
432 * by another SCU access by the time this function returns.
433 *
434 * This function may sleep. Locking for SCU accesses is handled for
435 * the caller.
436 */
437int intel_scu_ipc_simple_command(int cmd, int sub)
438{
439 struct intel_scu_ipc_dev *scu = &ipcdev;
440 int err;
441
442 mutex_lock(&ipclock);
443 if (scu->dev == NULL) {
444 mutex_unlock(&ipclock);
445 return -ENODEV;
446 }
447 ipc_command(scu, sub << 12 | cmd);
448 err = intel_scu_ipc_check_status(scu);
449 mutex_unlock(&ipclock);
450 return err;
451}
452EXPORT_SYMBOL(intel_scu_ipc_simple_command);
453
454/**
455 * intel_scu_ipc_command - command with data
456 * @cmd: command
457 * @sub: sub type
458 * @in: input data
459 * @inlen: input length in dwords
460 * @out: output data
461 * @outlein: output length in dwords
462 *
463 * Issue a command to the SCU which involves data transfers. Do the
464 * data copies under the lock but leave it for the caller to interpret
465 */
466int intel_scu_ipc_command(int cmd, int sub, u32 *in, int inlen,
467 u32 *out, int outlen)
468{
469 struct intel_scu_ipc_dev *scu = &ipcdev;
470 int i, err;
471
472 mutex_lock(&ipclock);
473 if (scu->dev == NULL) {
474 mutex_unlock(&ipclock);
475 return -ENODEV;
476 }
477
478 for (i = 0; i < inlen; i++)
479 ipc_data_writel(scu, *in++, 4 * i);
480
481 ipc_command(scu, (inlen << 16) | (sub << 12) | cmd);
482 err = intel_scu_ipc_check_status(scu);
483
484 if (!err) {
485 for (i = 0; i < outlen; i++)
486 *out++ = ipc_data_readl(scu, 4 * i);
487 }
488
489 mutex_unlock(&ipclock);
490 return err;
491}
492EXPORT_SYMBOL(intel_scu_ipc_command);
493
494/* I2C commands */
495#define IPC_I2C_WRITE 1 /* I2C Write command */
496#define IPC_I2C_READ 2 /* I2C Read command */
497
498/**
499 * intel_scu_ipc_i2c_cntrl - I2C read/write operations
500 * @addr: I2C address + command bits
501 * @data: data to read/write
502 *
503 * Perform an an I2C read/write operation via the SCU. All locking is
504 * handled for the caller. This function may sleep.
505 *
506 * Returns an error code or 0 on success.
507 *
508 * This has to be in the IPC driver for the locking.
509 */
510int intel_scu_ipc_i2c_cntrl(u32 addr, u32 *data)
511{
512 struct intel_scu_ipc_dev *scu = &ipcdev;
513 u32 cmd = 0;
514
515 mutex_lock(&ipclock);
516 if (scu->dev == NULL) {
517 mutex_unlock(&ipclock);
518 return -ENODEV;
519 }
520 cmd = (addr >> 24) & 0xFF;
521 if (cmd == IPC_I2C_READ) {
522 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
523 /* Write not getting updated without delay */
524 mdelay(1);
525 *data = readl(scu->i2c_base + I2C_DATA_ADDR);
526 } else if (cmd == IPC_I2C_WRITE) {
527 writel(*data, scu->i2c_base + I2C_DATA_ADDR);
528 mdelay(1);
529 writel(addr, scu->i2c_base + IPC_I2C_CNTRL_ADDR);
530 } else {
531 dev_err(scu->dev,
532 "intel_scu_ipc: I2C INVALID_CMD = 0x%x\n", cmd);
533
534 mutex_unlock(&ipclock);
535 return -EIO;
536 }
537 mutex_unlock(&ipclock);
538 return 0;
539}
540EXPORT_SYMBOL(intel_scu_ipc_i2c_cntrl);
541
542/*
543 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
544 * When ioc bit is set to 1, caller api must wait for interrupt handler called
545 * which in turn unlocks the caller api. Currently this is not used
546 *
547 * This is edge triggered so we need take no action to clear anything
548 */
549static irqreturn_t ioc(int irq, void *dev_id)
550{
551 struct intel_scu_ipc_dev *scu = dev_id;
552
553 if (scu->irq_mode)
554 complete(&scu->cmd_complete);
555
556 return IRQ_HANDLED;
557}
558
559/**
560 * ipc_probe - probe an Intel SCU IPC
561 * @pdev: the PCI device matching
562 * @id: entry in the match table
563 *
564 * Enable and install an intel SCU IPC. This appears in the PCI space
565 * but uses some hard coded addresses as well.
566 */
567static int ipc_probe(struct pci_dev *pdev, const struct pci_device_id *id)
568{
569 int platform; /* Platform type */
570 int err;
571 struct intel_scu_ipc_dev *scu = &ipcdev;
572 struct intel_scu_ipc_pdata_t *pdata;
573
574 platform = intel_mid_identify_cpu();
575 if (platform == 0)
576 return -ENODEV;
577
578 if (scu->dev) /* We support only one SCU */
579 return -EBUSY;
580
581 pdata = (struct intel_scu_ipc_pdata_t *)id->driver_data;
582
583 scu->dev = &pdev->dev;
584 scu->irq_mode = pdata->irq_mode;
585
586 err = pcim_enable_device(pdev);
587 if (err)
588 return err;
589
590 err = pcim_iomap_regions(pdev, 1 << 0, pci_name(pdev));
591 if (err)
592 return err;
593
594 init_completion(&scu->cmd_complete);
595
596 err = devm_request_irq(&pdev->dev, pdev->irq, ioc, 0, "intel_scu_ipc",
597 scu);
598 if (err)
599 return err;
600
601 scu->ipc_base = pcim_iomap_table(pdev)[0];
602
603 scu->i2c_base = ioremap_nocache(pdata->i2c_base, pdata->i2c_len);
604 if (!scu->i2c_base)
605 return -ENOMEM;
606
607 intel_scu_devices_create();
608
609 pci_set_drvdata(pdev, scu);
610 return 0;
611}
612
613static const struct pci_device_id pci_ids[] = {
614 {
615 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_LINCROFT),
616 (kernel_ulong_t)&intel_scu_ipc_lincroft_pdata,
617 }, {
618 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL),
619 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
620 }, {
621 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CLOVERVIEW),
622 (kernel_ulong_t)&intel_scu_ipc_penwell_pdata,
623 }, {
624 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER),
625 (kernel_ulong_t)&intel_scu_ipc_tangier_pdata,
626 }, {
627 0,
628 }
629};
630
631static struct pci_driver ipc_driver = {
632 .driver = {
633 .suppress_bind_attrs = true,
634 },
635 .name = "intel_scu_ipc",
636 .id_table = pci_ids,
637 .probe = ipc_probe,
638};
639builtin_pci_driver(ipc_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the Intel SCU IPC mechanism
4 *
5 * (C) Copyright 2008-2010,2015 Intel Corporation
6 * Author: Sreedhara DS (sreedhara.ds@intel.com)
7 *
8 * SCU running in ARC processor communicates with other entity running in IA
9 * core through IPC mechanism which in turn messaging between IA core ad SCU.
10 * SCU has two IPC mechanism IPC-1 and IPC-2. IPC-1 is used between IA32 and
11 * SCU where IPC-2 is used between P-Unit and SCU. This driver delas with
12 * IPC-1 Driver provides an API for power control unit registers (e.g. MSIC)
13 * along with other APIs.
14 */
15
16#include <linux/delay.h>
17#include <linux/device.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24
25#include <asm/intel_scu_ipc.h>
26
27/* IPC defines the following message types */
28#define IPCMSG_PCNTRL 0xff /* Power controller unit read/write */
29
30/* Command id associated with message IPCMSG_PCNTRL */
31#define IPC_CMD_PCNTRL_W 0 /* Register write */
32#define IPC_CMD_PCNTRL_R 1 /* Register read */
33#define IPC_CMD_PCNTRL_M 2 /* Register read-modify-write */
34
35/*
36 * IPC register summary
37 *
38 * IPC register blocks are memory mapped at fixed address of PCI BAR 0.
39 * To read or write information to the SCU, driver writes to IPC-1 memory
40 * mapped registers. The following is the IPC mechanism
41 *
42 * 1. IA core cDMI interface claims this transaction and converts it to a
43 * Transaction Layer Packet (TLP) message which is sent across the cDMI.
44 *
45 * 2. South Complex cDMI block receives this message and writes it to
46 * the IPC-1 register block, causing an interrupt to the SCU
47 *
48 * 3. SCU firmware decodes this interrupt and IPC message and the appropriate
49 * message handler is called within firmware.
50 */
51
52#define IPC_WWBUF_SIZE 20 /* IPC Write buffer Size */
53#define IPC_RWBUF_SIZE 20 /* IPC Read buffer Size */
54#define IPC_IOC 0x100 /* IPC command register IOC bit */
55
56struct intel_scu_ipc_dev {
57 struct device dev;
58 struct resource mem;
59 struct module *owner;
60 int irq;
61 void __iomem *ipc_base;
62 struct completion cmd_complete;
63};
64
65#define IPC_STATUS 0x04
66#define IPC_STATUS_IRQ BIT(2)
67#define IPC_STATUS_ERR BIT(1)
68#define IPC_STATUS_BUSY BIT(0)
69
70/*
71 * IPC Write/Read Buffers:
72 * 16 byte buffer for sending and receiving data to and from SCU.
73 */
74#define IPC_WRITE_BUFFER 0x80
75#define IPC_READ_BUFFER 0x90
76
77/* Timeout in jiffies */
78#define IPC_TIMEOUT (10 * HZ)
79
80static struct intel_scu_ipc_dev *ipcdev; /* Only one for now */
81static DEFINE_MUTEX(ipclock); /* lock used to prevent multiple call to SCU */
82
83static struct class intel_scu_ipc_class = {
84 .name = "intel_scu_ipc",
85 .owner = THIS_MODULE,
86};
87
88/**
89 * intel_scu_ipc_dev_get() - Get SCU IPC instance
90 *
91 * The recommended new API takes SCU IPC instance as parameter and this
92 * function can be called by driver to get the instance. This also makes
93 * sure the driver providing the IPC functionality cannot be unloaded
94 * while the caller has the instance.
95 *
96 * Call intel_scu_ipc_dev_put() to release the instance.
97 *
98 * Returns %NULL if SCU IPC is not currently available.
99 */
100struct intel_scu_ipc_dev *intel_scu_ipc_dev_get(void)
101{
102 struct intel_scu_ipc_dev *scu = NULL;
103
104 mutex_lock(&ipclock);
105 if (ipcdev) {
106 get_device(&ipcdev->dev);
107 /*
108 * Prevent the IPC provider from being unloaded while it
109 * is being used.
110 */
111 if (!try_module_get(ipcdev->owner))
112 put_device(&ipcdev->dev);
113 else
114 scu = ipcdev;
115 }
116
117 mutex_unlock(&ipclock);
118 return scu;
119}
120EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_get);
121
122/**
123 * intel_scu_ipc_dev_put() - Put SCU IPC instance
124 * @scu: SCU IPC instance
125 *
126 * This function releases the SCU IPC instance retrieved from
127 * intel_scu_ipc_dev_get() and allows the driver providing IPC to be
128 * unloaded.
129 */
130void intel_scu_ipc_dev_put(struct intel_scu_ipc_dev *scu)
131{
132 if (scu) {
133 module_put(scu->owner);
134 put_device(&scu->dev);
135 }
136}
137EXPORT_SYMBOL_GPL(intel_scu_ipc_dev_put);
138
139struct intel_scu_ipc_devres {
140 struct intel_scu_ipc_dev *scu;
141};
142
143static void devm_intel_scu_ipc_dev_release(struct device *dev, void *res)
144{
145 struct intel_scu_ipc_devres *dr = res;
146 struct intel_scu_ipc_dev *scu = dr->scu;
147
148 intel_scu_ipc_dev_put(scu);
149}
150
151/**
152 * devm_intel_scu_ipc_dev_get() - Allocate managed SCU IPC device
153 * @dev: Device requesting the SCU IPC device
154 *
155 * The recommended new API takes SCU IPC instance as parameter and this
156 * function can be called by driver to get the instance. This also makes
157 * sure the driver providing the IPC functionality cannot be unloaded
158 * while the caller has the instance.
159 *
160 * Returns %NULL if SCU IPC is not currently available.
161 */
162struct intel_scu_ipc_dev *devm_intel_scu_ipc_dev_get(struct device *dev)
163{
164 struct intel_scu_ipc_devres *dr;
165 struct intel_scu_ipc_dev *scu;
166
167 dr = devres_alloc(devm_intel_scu_ipc_dev_release, sizeof(*dr), GFP_KERNEL);
168 if (!dr)
169 return NULL;
170
171 scu = intel_scu_ipc_dev_get();
172 if (!scu) {
173 devres_free(dr);
174 return NULL;
175 }
176
177 dr->scu = scu;
178 devres_add(dev, dr);
179
180 return scu;
181}
182EXPORT_SYMBOL_GPL(devm_intel_scu_ipc_dev_get);
183
184/*
185 * Send ipc command
186 * Command Register (Write Only):
187 * A write to this register results in an interrupt to the SCU core processor
188 * Format:
189 * |rfu2(8) | size(8) | command id(4) | rfu1(3) | ioc(1) | command(8)|
190 */
191static inline void ipc_command(struct intel_scu_ipc_dev *scu, u32 cmd)
192{
193 reinit_completion(&scu->cmd_complete);
194 writel(cmd | IPC_IOC, scu->ipc_base);
195}
196
197/*
198 * Write ipc data
199 * IPC Write Buffer (Write Only):
200 * 16-byte buffer for sending data associated with IPC command to
201 * SCU. Size of the data is specified in the IPC_COMMAND_REG register
202 */
203static inline void ipc_data_writel(struct intel_scu_ipc_dev *scu, u32 data, u32 offset)
204{
205 writel(data, scu->ipc_base + IPC_WRITE_BUFFER + offset);
206}
207
208/*
209 * Status Register (Read Only):
210 * Driver will read this register to get the ready/busy status of the IPC
211 * block and error status of the IPC command that was just processed by SCU
212 * Format:
213 * |rfu3(8)|error code(8)|initiator id(8)|cmd id(4)|rfu1(2)|error(1)|busy(1)|
214 */
215static inline u8 ipc_read_status(struct intel_scu_ipc_dev *scu)
216{
217 return __raw_readl(scu->ipc_base + IPC_STATUS);
218}
219
220/* Read ipc byte data */
221static inline u8 ipc_data_readb(struct intel_scu_ipc_dev *scu, u32 offset)
222{
223 return readb(scu->ipc_base + IPC_READ_BUFFER + offset);
224}
225
226/* Read ipc u32 data */
227static inline u32 ipc_data_readl(struct intel_scu_ipc_dev *scu, u32 offset)
228{
229 return readl(scu->ipc_base + IPC_READ_BUFFER + offset);
230}
231
232/* Wait till scu status is busy */
233static inline int busy_loop(struct intel_scu_ipc_dev *scu)
234{
235 unsigned long end = jiffies + IPC_TIMEOUT;
236
237 do {
238 u32 status;
239
240 status = ipc_read_status(scu);
241 if (!(status & IPC_STATUS_BUSY))
242 return (status & IPC_STATUS_ERR) ? -EIO : 0;
243
244 usleep_range(50, 100);
245 } while (time_before(jiffies, end));
246
247 return -ETIMEDOUT;
248}
249
250/* Wait till ipc ioc interrupt is received or timeout in 10 HZ */
251static inline int ipc_wait_for_interrupt(struct intel_scu_ipc_dev *scu)
252{
253 int status;
254
255 if (!wait_for_completion_timeout(&scu->cmd_complete, IPC_TIMEOUT))
256 return -ETIMEDOUT;
257
258 status = ipc_read_status(scu);
259 if (status & IPC_STATUS_ERR)
260 return -EIO;
261
262 return 0;
263}
264
265static int intel_scu_ipc_check_status(struct intel_scu_ipc_dev *scu)
266{
267 return scu->irq > 0 ? ipc_wait_for_interrupt(scu) : busy_loop(scu);
268}
269
270/* Read/Write power control(PMIC in Langwell, MSIC in PenWell) registers */
271static int pwr_reg_rdwr(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
272 u32 count, u32 op, u32 id)
273{
274 int nc;
275 u32 offset = 0;
276 int err;
277 u8 cbuf[IPC_WWBUF_SIZE];
278 u32 *wbuf = (u32 *)&cbuf;
279
280 memset(cbuf, 0, sizeof(cbuf));
281
282 mutex_lock(&ipclock);
283 if (!scu)
284 scu = ipcdev;
285 if (!scu) {
286 mutex_unlock(&ipclock);
287 return -ENODEV;
288 }
289
290 for (nc = 0; nc < count; nc++, offset += 2) {
291 cbuf[offset] = addr[nc];
292 cbuf[offset + 1] = addr[nc] >> 8;
293 }
294
295 if (id == IPC_CMD_PCNTRL_R) {
296 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
297 ipc_data_writel(scu, wbuf[nc], offset);
298 ipc_command(scu, (count * 2) << 16 | id << 12 | 0 << 8 | op);
299 } else if (id == IPC_CMD_PCNTRL_W) {
300 for (nc = 0; nc < count; nc++, offset += 1)
301 cbuf[offset] = data[nc];
302 for (nc = 0, offset = 0; nc < count; nc++, offset += 4)
303 ipc_data_writel(scu, wbuf[nc], offset);
304 ipc_command(scu, (count * 3) << 16 | id << 12 | 0 << 8 | op);
305 } else if (id == IPC_CMD_PCNTRL_M) {
306 cbuf[offset] = data[0];
307 cbuf[offset + 1] = data[1];
308 ipc_data_writel(scu, wbuf[0], 0); /* Write wbuff */
309 ipc_command(scu, 4 << 16 | id << 12 | 0 << 8 | op);
310 }
311
312 err = intel_scu_ipc_check_status(scu);
313 if (!err && id == IPC_CMD_PCNTRL_R) { /* Read rbuf */
314 /* Workaround: values are read as 0 without memcpy_fromio */
315 memcpy_fromio(cbuf, scu->ipc_base + 0x90, 16);
316 for (nc = 0; nc < count; nc++)
317 data[nc] = ipc_data_readb(scu, nc);
318 }
319 mutex_unlock(&ipclock);
320 return err;
321}
322
323/**
324 * intel_scu_ipc_dev_ioread8() - Read a byte via the SCU
325 * @scu: Optional SCU IPC instance
326 * @addr: Register on SCU
327 * @data: Return pointer for read byte
328 *
329 * Read a single register. Returns %0 on success or an error code. All
330 * locking between SCU accesses is handled for the caller.
331 *
332 * This function may sleep.
333 */
334int intel_scu_ipc_dev_ioread8(struct intel_scu_ipc_dev *scu, u16 addr, u8 *data)
335{
336 return pwr_reg_rdwr(scu, &addr, data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
337}
338EXPORT_SYMBOL(intel_scu_ipc_dev_ioread8);
339
340/**
341 * intel_scu_ipc_dev_iowrite8() - Write a byte via the SCU
342 * @scu: Optional SCU IPC instance
343 * @addr: Register on SCU
344 * @data: Byte to write
345 *
346 * Write a single register. Returns %0 on success or an error code. All
347 * locking between SCU accesses is handled for the caller.
348 *
349 * This function may sleep.
350 */
351int intel_scu_ipc_dev_iowrite8(struct intel_scu_ipc_dev *scu, u16 addr, u8 data)
352{
353 return pwr_reg_rdwr(scu, &addr, &data, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
354}
355EXPORT_SYMBOL(intel_scu_ipc_dev_iowrite8);
356
357/**
358 * intel_scu_ipc_dev_readv() - Read a set of registers
359 * @scu: Optional SCU IPC instance
360 * @addr: Register list
361 * @data: Bytes to return
362 * @len: Length of array
363 *
364 * Read registers. Returns %0 on success or an error code. All locking
365 * between SCU accesses is handled for the caller.
366 *
367 * The largest array length permitted by the hardware is 5 items.
368 *
369 * This function may sleep.
370 */
371int intel_scu_ipc_dev_readv(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
372 size_t len)
373{
374 return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_R);
375}
376EXPORT_SYMBOL(intel_scu_ipc_dev_readv);
377
378/**
379 * intel_scu_ipc_dev_writev() - Write a set of registers
380 * @scu: Optional SCU IPC instance
381 * @addr: Register list
382 * @data: Bytes to write
383 * @len: Length of array
384 *
385 * Write registers. Returns %0 on success or an error code. All locking
386 * between SCU accesses is handled for the caller.
387 *
388 * The largest array length permitted by the hardware is 5 items.
389 *
390 * This function may sleep.
391 */
392int intel_scu_ipc_dev_writev(struct intel_scu_ipc_dev *scu, u16 *addr, u8 *data,
393 size_t len)
394{
395 return pwr_reg_rdwr(scu, addr, data, len, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_W);
396}
397EXPORT_SYMBOL(intel_scu_ipc_dev_writev);
398
399/**
400 * intel_scu_ipc_dev_update() - Update a register
401 * @scu: Optional SCU IPC instance
402 * @addr: Register address
403 * @data: Bits to update
404 * @mask: Mask of bits to update
405 *
406 * Read-modify-write power control unit register. The first data argument
407 * must be register value and second is mask value mask is a bitmap that
408 * indicates which bits to update. %0 = masked. Don't modify this bit, %1 =
409 * modify this bit. returns %0 on success or an error code.
410 *
411 * This function may sleep. Locking between SCU accesses is handled
412 * for the caller.
413 */
414int intel_scu_ipc_dev_update(struct intel_scu_ipc_dev *scu, u16 addr, u8 data,
415 u8 mask)
416{
417 u8 tmp[2] = { data, mask };
418 return pwr_reg_rdwr(scu, &addr, tmp, 1, IPCMSG_PCNTRL, IPC_CMD_PCNTRL_M);
419}
420EXPORT_SYMBOL(intel_scu_ipc_dev_update);
421
422/**
423 * intel_scu_ipc_dev_simple_command() - Send a simple command
424 * @scu: Optional SCU IPC instance
425 * @cmd: Command
426 * @sub: Sub type
427 *
428 * Issue a simple command to the SCU. Do not use this interface if you must
429 * then access data as any data values may be overwritten by another SCU
430 * access by the time this function returns.
431 *
432 * This function may sleep. Locking for SCU accesses is handled for the
433 * caller.
434 */
435int intel_scu_ipc_dev_simple_command(struct intel_scu_ipc_dev *scu, int cmd,
436 int sub)
437{
438 u32 cmdval;
439 int err;
440
441 mutex_lock(&ipclock);
442 if (!scu)
443 scu = ipcdev;
444 if (!scu) {
445 mutex_unlock(&ipclock);
446 return -ENODEV;
447 }
448 scu = ipcdev;
449 cmdval = sub << 12 | cmd;
450 ipc_command(scu, cmdval);
451 err = intel_scu_ipc_check_status(scu);
452 mutex_unlock(&ipclock);
453 if (err)
454 dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
455 return err;
456}
457EXPORT_SYMBOL(intel_scu_ipc_dev_simple_command);
458
459/**
460 * intel_scu_ipc_dev_command_with_size() - Command with data
461 * @scu: Optional SCU IPC instance
462 * @cmd: Command
463 * @sub: Sub type
464 * @in: Input data
465 * @inlen: Input length in bytes
466 * @size: Input size written to the IPC command register in whatever
467 * units (dword, byte) the particular firmware requires. Normally
468 * should be the same as @inlen.
469 * @out: Output data
470 * @outlen: Output length in bytes
471 *
472 * Issue a command to the SCU which involves data transfers. Do the
473 * data copies under the lock but leave it for the caller to interpret.
474 */
475int intel_scu_ipc_dev_command_with_size(struct intel_scu_ipc_dev *scu, int cmd,
476 int sub, const void *in, size_t inlen,
477 size_t size, void *out, size_t outlen)
478{
479 size_t outbuflen = DIV_ROUND_UP(outlen, sizeof(u32));
480 size_t inbuflen = DIV_ROUND_UP(inlen, sizeof(u32));
481 u32 cmdval, inbuf[4] = {};
482 int i, err;
483
484 if (inbuflen > 4 || outbuflen > 4)
485 return -EINVAL;
486
487 mutex_lock(&ipclock);
488 if (!scu)
489 scu = ipcdev;
490 if (!scu) {
491 mutex_unlock(&ipclock);
492 return -ENODEV;
493 }
494
495 memcpy(inbuf, in, inlen);
496 for (i = 0; i < inbuflen; i++)
497 ipc_data_writel(scu, inbuf[i], 4 * i);
498
499 cmdval = (size << 16) | (sub << 12) | cmd;
500 ipc_command(scu, cmdval);
501 err = intel_scu_ipc_check_status(scu);
502
503 if (!err) {
504 u32 outbuf[4] = {};
505
506 for (i = 0; i < outbuflen; i++)
507 outbuf[i] = ipc_data_readl(scu, 4 * i);
508
509 memcpy(out, outbuf, outlen);
510 }
511
512 mutex_unlock(&ipclock);
513 if (err)
514 dev_err(&scu->dev, "IPC command %#x failed with %d\n", cmdval, err);
515 return err;
516}
517EXPORT_SYMBOL(intel_scu_ipc_dev_command_with_size);
518
519/*
520 * Interrupt handler gets called when ioc bit of IPC_COMMAND_REG set to 1
521 * When ioc bit is set to 1, caller api must wait for interrupt handler called
522 * which in turn unlocks the caller api. Currently this is not used
523 *
524 * This is edge triggered so we need take no action to clear anything
525 */
526static irqreturn_t ioc(int irq, void *dev_id)
527{
528 struct intel_scu_ipc_dev *scu = dev_id;
529 int status = ipc_read_status(scu);
530
531 writel(status | IPC_STATUS_IRQ, scu->ipc_base + IPC_STATUS);
532 complete(&scu->cmd_complete);
533
534 return IRQ_HANDLED;
535}
536
537static void intel_scu_ipc_release(struct device *dev)
538{
539 struct intel_scu_ipc_dev *scu;
540
541 scu = container_of(dev, struct intel_scu_ipc_dev, dev);
542 if (scu->irq > 0)
543 free_irq(scu->irq, scu);
544 iounmap(scu->ipc_base);
545 release_mem_region(scu->mem.start, resource_size(&scu->mem));
546 kfree(scu);
547}
548
549/**
550 * __intel_scu_ipc_register() - Register SCU IPC device
551 * @parent: Parent device
552 * @scu_data: Data used to configure SCU IPC
553 * @owner: Module registering the SCU IPC device
554 *
555 * Call this function to register SCU IPC mechanism under @parent.
556 * Returns pointer to the new SCU IPC device or ERR_PTR() in case of
557 * failure. The caller may use the returned instance if it needs to do
558 * SCU IPC calls itself.
559 */
560struct intel_scu_ipc_dev *
561__intel_scu_ipc_register(struct device *parent,
562 const struct intel_scu_ipc_data *scu_data,
563 struct module *owner)
564{
565 int err;
566 struct intel_scu_ipc_dev *scu;
567 void __iomem *ipc_base;
568
569 mutex_lock(&ipclock);
570 /* We support only one IPC */
571 if (ipcdev) {
572 err = -EBUSY;
573 goto err_unlock;
574 }
575
576 scu = kzalloc(sizeof(*scu), GFP_KERNEL);
577 if (!scu) {
578 err = -ENOMEM;
579 goto err_unlock;
580 }
581
582 scu->owner = owner;
583 scu->dev.parent = parent;
584 scu->dev.class = &intel_scu_ipc_class;
585 scu->dev.release = intel_scu_ipc_release;
586
587 if (!request_mem_region(scu_data->mem.start, resource_size(&scu_data->mem),
588 "intel_scu_ipc")) {
589 err = -EBUSY;
590 goto err_free;
591 }
592
593 ipc_base = ioremap(scu_data->mem.start, resource_size(&scu_data->mem));
594 if (!ipc_base) {
595 err = -ENOMEM;
596 goto err_release;
597 }
598
599 scu->ipc_base = ipc_base;
600 scu->mem = scu_data->mem;
601 scu->irq = scu_data->irq;
602 init_completion(&scu->cmd_complete);
603
604 if (scu->irq > 0) {
605 err = request_irq(scu->irq, ioc, 0, "intel_scu_ipc", scu);
606 if (err)
607 goto err_unmap;
608 }
609
610 /*
611 * After this point intel_scu_ipc_release() takes care of
612 * releasing the SCU IPC resources once refcount drops to zero.
613 */
614 dev_set_name(&scu->dev, "intel_scu_ipc");
615 err = device_register(&scu->dev);
616 if (err) {
617 put_device(&scu->dev);
618 goto err_unlock;
619 }
620
621 /* Assign device at last */
622 ipcdev = scu;
623 mutex_unlock(&ipclock);
624
625 return scu;
626
627err_unmap:
628 iounmap(ipc_base);
629err_release:
630 release_mem_region(scu_data->mem.start, resource_size(&scu_data->mem));
631err_free:
632 kfree(scu);
633err_unlock:
634 mutex_unlock(&ipclock);
635
636 return ERR_PTR(err);
637}
638EXPORT_SYMBOL_GPL(__intel_scu_ipc_register);
639
640/**
641 * intel_scu_ipc_unregister() - Unregister SCU IPC
642 * @scu: SCU IPC handle
643 *
644 * This unregisters the SCU IPC device and releases the acquired
645 * resources once the refcount goes to zero.
646 */
647void intel_scu_ipc_unregister(struct intel_scu_ipc_dev *scu)
648{
649 mutex_lock(&ipclock);
650 if (!WARN_ON(!ipcdev)) {
651 ipcdev = NULL;
652 device_unregister(&scu->dev);
653 }
654 mutex_unlock(&ipclock);
655}
656EXPORT_SYMBOL_GPL(intel_scu_ipc_unregister);
657
658static void devm_intel_scu_ipc_unregister(struct device *dev, void *res)
659{
660 struct intel_scu_ipc_devres *dr = res;
661 struct intel_scu_ipc_dev *scu = dr->scu;
662
663 intel_scu_ipc_unregister(scu);
664}
665
666/**
667 * __devm_intel_scu_ipc_register() - Register managed SCU IPC device
668 * @parent: Parent device
669 * @scu_data: Data used to configure SCU IPC
670 * @owner: Module registering the SCU IPC device
671 *
672 * Call this function to register managed SCU IPC mechanism under
673 * @parent. Returns pointer to the new SCU IPC device or ERR_PTR() in
674 * case of failure. The caller may use the returned instance if it needs
675 * to do SCU IPC calls itself.
676 */
677struct intel_scu_ipc_dev *
678__devm_intel_scu_ipc_register(struct device *parent,
679 const struct intel_scu_ipc_data *scu_data,
680 struct module *owner)
681{
682 struct intel_scu_ipc_devres *dr;
683 struct intel_scu_ipc_dev *scu;
684
685 dr = devres_alloc(devm_intel_scu_ipc_unregister, sizeof(*dr), GFP_KERNEL);
686 if (!dr)
687 return NULL;
688
689 scu = __intel_scu_ipc_register(parent, scu_data, owner);
690 if (IS_ERR(scu)) {
691 devres_free(dr);
692 return scu;
693 }
694
695 dr->scu = scu;
696 devres_add(parent, dr);
697
698 return scu;
699}
700EXPORT_SYMBOL_GPL(__devm_intel_scu_ipc_register);
701
702static int __init intel_scu_ipc_init(void)
703{
704 return class_register(&intel_scu_ipc_class);
705}
706subsys_initcall(intel_scu_ipc_init);
707
708static void __exit intel_scu_ipc_exit(void)
709{
710 class_unregister(&intel_scu_ipc_class);
711}
712module_exit(intel_scu_ipc_exit);