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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * AMD SoC Power Management Controller Driver
4 *
5 * Copyright (c) 2020, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/acpi.h>
14#include <linux/bitfield.h>
15#include <linux/bits.h>
16#include <linux/debugfs.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/iopoll.h>
20#include <linux/limits.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/platform_device.h>
24#include <linux/rtc.h>
25#include <linux/serio.h>
26#include <linux/suspend.h>
27#include <linux/seq_file.h>
28#include <linux/uaccess.h>
29
30/* SMU communication registers */
31#define AMD_PMC_REGISTER_MESSAGE 0x538
32#define AMD_PMC_REGISTER_RESPONSE 0x980
33#define AMD_PMC_REGISTER_ARGUMENT 0x9BC
34
35/* PMC Scratch Registers */
36#define AMD_PMC_SCRATCH_REG_CZN 0x94
37#define AMD_PMC_SCRATCH_REG_YC 0xD14
38
39/* STB Registers */
40#define AMD_PMC_STB_INDEX_ADDRESS 0xF8
41#define AMD_PMC_STB_INDEX_DATA 0xFC
42#define AMD_PMC_STB_PMI_0 0x03E30600
43#define AMD_PMC_STB_S2IDLE_PREPARE 0xC6000001
44#define AMD_PMC_STB_S2IDLE_RESTORE 0xC6000002
45#define AMD_PMC_STB_S2IDLE_CHECK 0xC6000003
46
47/* STB S2D(Spill to DRAM) has different message port offset */
48#define STB_SPILL_TO_DRAM 0xBE
49#define AMD_S2D_REGISTER_MESSAGE 0xA20
50#define AMD_S2D_REGISTER_RESPONSE 0xA80
51#define AMD_S2D_REGISTER_ARGUMENT 0xA88
52
53/* STB Spill to DRAM Parameters */
54#define S2D_TELEMETRY_BYTES_MAX 0x100000
55#define S2D_TELEMETRY_DRAMBYTES_MAX 0x1000000
56
57/* Base address of SMU for mapping physical address to virtual address */
58#define AMD_PMC_SMU_INDEX_ADDRESS 0xB8
59#define AMD_PMC_SMU_INDEX_DATA 0xBC
60#define AMD_PMC_MAPPING_SIZE 0x01000
61#define AMD_PMC_BASE_ADDR_OFFSET 0x10000
62#define AMD_PMC_BASE_ADDR_LO 0x13B102E8
63#define AMD_PMC_BASE_ADDR_HI 0x13B102EC
64#define AMD_PMC_BASE_ADDR_LO_MASK GENMASK(15, 0)
65#define AMD_PMC_BASE_ADDR_HI_MASK GENMASK(31, 20)
66
67/* SMU Response Codes */
68#define AMD_PMC_RESULT_OK 0x01
69#define AMD_PMC_RESULT_CMD_REJECT_BUSY 0xFC
70#define AMD_PMC_RESULT_CMD_REJECT_PREREQ 0xFD
71#define AMD_PMC_RESULT_CMD_UNKNOWN 0xFE
72#define AMD_PMC_RESULT_FAILED 0xFF
73
74/* FCH SSC Registers */
75#define FCH_S0I3_ENTRY_TIME_L_OFFSET 0x30
76#define FCH_S0I3_ENTRY_TIME_H_OFFSET 0x34
77#define FCH_S0I3_EXIT_TIME_L_OFFSET 0x38
78#define FCH_S0I3_EXIT_TIME_H_OFFSET 0x3C
79#define FCH_SSC_MAPPING_SIZE 0x800
80#define FCH_BASE_PHY_ADDR_LOW 0xFED81100
81#define FCH_BASE_PHY_ADDR_HIGH 0x00000000
82
83/* SMU Message Definations */
84#define SMU_MSG_GETSMUVERSION 0x02
85#define SMU_MSG_LOG_GETDRAM_ADDR_HI 0x04
86#define SMU_MSG_LOG_GETDRAM_ADDR_LO 0x05
87#define SMU_MSG_LOG_START 0x06
88#define SMU_MSG_LOG_RESET 0x07
89#define SMU_MSG_LOG_DUMP_DATA 0x08
90#define SMU_MSG_GET_SUP_CONSTRAINTS 0x09
91/* List of supported CPU ids */
92#define AMD_CPU_ID_RV 0x15D0
93#define AMD_CPU_ID_RN 0x1630
94#define AMD_CPU_ID_PCO AMD_CPU_ID_RV
95#define AMD_CPU_ID_CZN AMD_CPU_ID_RN
96#define AMD_CPU_ID_YC 0x14B5
97#define AMD_CPU_ID_CB 0x14D8
98#define AMD_CPU_ID_PS 0x14E8
99
100#define PMC_MSG_DELAY_MIN_US 50
101#define RESPONSE_REGISTER_LOOP_MAX 20000
102
103#define SOC_SUBSYSTEM_IP_MAX 12
104#define DELAY_MIN_US 2000
105#define DELAY_MAX_US 3000
106#define FIFO_SIZE 4096
107enum amd_pmc_def {
108 MSG_TEST = 0x01,
109 MSG_OS_HINT_PCO,
110 MSG_OS_HINT_RN,
111};
112
113enum s2d_arg {
114 S2D_TELEMETRY_SIZE = 0x01,
115 S2D_PHYS_ADDR_LOW,
116 S2D_PHYS_ADDR_HIGH,
117};
118
119struct amd_pmc_bit_map {
120 const char *name;
121 u32 bit_mask;
122};
123
124static const struct amd_pmc_bit_map soc15_ip_blk[] = {
125 {"DISPLAY", BIT(0)},
126 {"CPU", BIT(1)},
127 {"GFX", BIT(2)},
128 {"VDD", BIT(3)},
129 {"ACP", BIT(4)},
130 {"VCN", BIT(5)},
131 {"ISP", BIT(6)},
132 {"NBIO", BIT(7)},
133 {"DF", BIT(8)},
134 {"USB0", BIT(9)},
135 {"USB1", BIT(10)},
136 {"LAPIC", BIT(11)},
137 {}
138};
139
140struct amd_pmc_dev {
141 void __iomem *regbase;
142 void __iomem *smu_virt_addr;
143 void __iomem *stb_virt_addr;
144 void __iomem *fch_virt_addr;
145 bool msg_port;
146 u32 base_addr;
147 u32 cpu_id;
148 u32 active_ips;
149/* SMU version information */
150 u8 smu_program;
151 u8 major;
152 u8 minor;
153 u8 rev;
154 struct device *dev;
155 struct pci_dev *rdev;
156 struct mutex lock; /* generic mutex lock */
157 struct dentry *dbgfs_dir;
158};
159
160static bool enable_stb;
161module_param(enable_stb, bool, 0644);
162MODULE_PARM_DESC(enable_stb, "Enable the STB debug mechanism");
163
164static bool disable_workarounds;
165module_param(disable_workarounds, bool, 0644);
166MODULE_PARM_DESC(disable_workarounds, "Disable workarounds for platform bugs");
167
168static struct amd_pmc_dev pmc;
169static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret);
170static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf);
171#ifdef CONFIG_SUSPEND
172static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data);
173#endif
174
175static inline u32 amd_pmc_reg_read(struct amd_pmc_dev *dev, int reg_offset)
176{
177 return ioread32(dev->regbase + reg_offset);
178}
179
180static inline void amd_pmc_reg_write(struct amd_pmc_dev *dev, int reg_offset, u32 val)
181{
182 iowrite32(val, dev->regbase + reg_offset);
183}
184
185struct smu_metrics {
186 u32 table_version;
187 u32 hint_count;
188 u32 s0i3_last_entry_status;
189 u32 timein_s0i2;
190 u64 timeentering_s0i3_lastcapture;
191 u64 timeentering_s0i3_totaltime;
192 u64 timeto_resume_to_os_lastcapture;
193 u64 timeto_resume_to_os_totaltime;
194 u64 timein_s0i3_lastcapture;
195 u64 timein_s0i3_totaltime;
196 u64 timein_swdrips_lastcapture;
197 u64 timein_swdrips_totaltime;
198 u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
199 u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
200} __packed;
201
202static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
203{
204 struct amd_pmc_dev *dev = filp->f_inode->i_private;
205 u32 size = FIFO_SIZE * sizeof(u32);
206 u32 *buf;
207 int rc;
208
209 buf = kzalloc(size, GFP_KERNEL);
210 if (!buf)
211 return -ENOMEM;
212
213 rc = amd_pmc_read_stb(dev, buf);
214 if (rc) {
215 kfree(buf);
216 return rc;
217 }
218
219 filp->private_data = buf;
220 return rc;
221}
222
223static ssize_t amd_pmc_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
224 loff_t *pos)
225{
226 if (!filp->private_data)
227 return -EINVAL;
228
229 return simple_read_from_buffer(buf, size, pos, filp->private_data,
230 FIFO_SIZE * sizeof(u32));
231}
232
233static int amd_pmc_stb_debugfs_release(struct inode *inode, struct file *filp)
234{
235 kfree(filp->private_data);
236 return 0;
237}
238
239static const struct file_operations amd_pmc_stb_debugfs_fops = {
240 .owner = THIS_MODULE,
241 .open = amd_pmc_stb_debugfs_open,
242 .read = amd_pmc_stb_debugfs_read,
243 .release = amd_pmc_stb_debugfs_release,
244};
245
246static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
247{
248 struct amd_pmc_dev *dev = filp->f_inode->i_private;
249 u32 *buf;
250
251 buf = kzalloc(S2D_TELEMETRY_BYTES_MAX, GFP_KERNEL);
252 if (!buf)
253 return -ENOMEM;
254
255 memcpy_fromio(buf, dev->stb_virt_addr, S2D_TELEMETRY_BYTES_MAX);
256 filp->private_data = buf;
257
258 return 0;
259}
260
261static ssize_t amd_pmc_stb_debugfs_read_v2(struct file *filp, char __user *buf, size_t size,
262 loff_t *pos)
263{
264 if (!filp->private_data)
265 return -EINVAL;
266
267 return simple_read_from_buffer(buf, size, pos, filp->private_data,
268 S2D_TELEMETRY_BYTES_MAX);
269}
270
271static int amd_pmc_stb_debugfs_release_v2(struct inode *inode, struct file *filp)
272{
273 kfree(filp->private_data);
274 return 0;
275}
276
277static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
278 .owner = THIS_MODULE,
279 .open = amd_pmc_stb_debugfs_open_v2,
280 .read = amd_pmc_stb_debugfs_read_v2,
281 .release = amd_pmc_stb_debugfs_release_v2,
282};
283
284static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
285{
286 if (dev->cpu_id == AMD_CPU_ID_PCO) {
287 dev_warn_once(dev->dev, "SMU debugging info not supported on this platform\n");
288 return -EINVAL;
289 }
290
291 /* Get Active devices list from SMU */
292 if (!dev->active_ips)
293 amd_pmc_send_cmd(dev, 0, &dev->active_ips, SMU_MSG_GET_SUP_CONSTRAINTS, 1);
294
295 /* Get dram address */
296 if (!dev->smu_virt_addr) {
297 u32 phys_addr_low, phys_addr_hi;
298 u64 smu_phys_addr;
299
300 amd_pmc_send_cmd(dev, 0, &phys_addr_low, SMU_MSG_LOG_GETDRAM_ADDR_LO, 1);
301 amd_pmc_send_cmd(dev, 0, &phys_addr_hi, SMU_MSG_LOG_GETDRAM_ADDR_HI, 1);
302 smu_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
303
304 dev->smu_virt_addr = devm_ioremap(dev->dev, smu_phys_addr,
305 sizeof(struct smu_metrics));
306 if (!dev->smu_virt_addr)
307 return -ENOMEM;
308 }
309
310 /* Start the logging */
311 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_RESET, 0);
312 amd_pmc_send_cmd(dev, 0, NULL, SMU_MSG_LOG_START, 0);
313
314 return 0;
315}
316
317static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev,
318 struct seq_file *s)
319{
320 u32 val;
321
322 switch (pdev->cpu_id) {
323 case AMD_CPU_ID_CZN:
324 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_CZN);
325 break;
326 case AMD_CPU_ID_YC:
327 case AMD_CPU_ID_CB:
328 case AMD_CPU_ID_PS:
329 val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC);
330 break;
331 default:
332 return -EINVAL;
333 }
334
335 if (dev)
336 dev_dbg(pdev->dev, "SMU idlemask s0i3: 0x%x\n", val);
337
338 if (s)
339 seq_printf(s, "SMU idlemask : 0x%x\n", val);
340
341 return 0;
342}
343
344static int get_metrics_table(struct amd_pmc_dev *pdev, struct smu_metrics *table)
345{
346 if (!pdev->smu_virt_addr) {
347 int ret = amd_pmc_setup_smu_logging(pdev);
348
349 if (ret)
350 return ret;
351 }
352
353 if (pdev->cpu_id == AMD_CPU_ID_PCO)
354 return -ENODEV;
355 memcpy_fromio(table, pdev->smu_virt_addr, sizeof(struct smu_metrics));
356 return 0;
357}
358
359#ifdef CONFIG_SUSPEND
360static void amd_pmc_validate_deepest(struct amd_pmc_dev *pdev)
361{
362 struct smu_metrics table;
363
364 if (get_metrics_table(pdev, &table))
365 return;
366
367 if (!table.s0i3_last_entry_status)
368 dev_warn(pdev->dev, "Last suspend didn't reach deepest state\n");
369 else
370 dev_dbg(pdev->dev, "Last suspend in deepest state for %lluus\n",
371 table.timein_s0i3_lastcapture);
372}
373#endif
374
375static int amd_pmc_get_smu_version(struct amd_pmc_dev *dev)
376{
377 int rc;
378 u32 val;
379
380 rc = amd_pmc_send_cmd(dev, 0, &val, SMU_MSG_GETSMUVERSION, 1);
381 if (rc)
382 return rc;
383
384 dev->smu_program = (val >> 24) & GENMASK(7, 0);
385 dev->major = (val >> 16) & GENMASK(7, 0);
386 dev->minor = (val >> 8) & GENMASK(7, 0);
387 dev->rev = (val >> 0) & GENMASK(7, 0);
388
389 dev_dbg(dev->dev, "SMU program %u version is %u.%u.%u\n",
390 dev->smu_program, dev->major, dev->minor, dev->rev);
391
392 return 0;
393}
394
395static ssize_t smu_fw_version_show(struct device *d, struct device_attribute *attr,
396 char *buf)
397{
398 struct amd_pmc_dev *dev = dev_get_drvdata(d);
399
400 if (!dev->major) {
401 int rc = amd_pmc_get_smu_version(dev);
402
403 if (rc)
404 return rc;
405 }
406 return sysfs_emit(buf, "%u.%u.%u\n", dev->major, dev->minor, dev->rev);
407}
408
409static ssize_t smu_program_show(struct device *d, struct device_attribute *attr,
410 char *buf)
411{
412 struct amd_pmc_dev *dev = dev_get_drvdata(d);
413
414 if (!dev->major) {
415 int rc = amd_pmc_get_smu_version(dev);
416
417 if (rc)
418 return rc;
419 }
420 return sysfs_emit(buf, "%u\n", dev->smu_program);
421}
422
423static DEVICE_ATTR_RO(smu_fw_version);
424static DEVICE_ATTR_RO(smu_program);
425
426static struct attribute *pmc_attrs[] = {
427 &dev_attr_smu_fw_version.attr,
428 &dev_attr_smu_program.attr,
429 NULL,
430};
431ATTRIBUTE_GROUPS(pmc);
432
433static int smu_fw_info_show(struct seq_file *s, void *unused)
434{
435 struct amd_pmc_dev *dev = s->private;
436 struct smu_metrics table;
437 int idx;
438
439 if (get_metrics_table(dev, &table))
440 return -EINVAL;
441
442 seq_puts(s, "\n=== SMU Statistics ===\n");
443 seq_printf(s, "Table Version: %d\n", table.table_version);
444 seq_printf(s, "Hint Count: %d\n", table.hint_count);
445 seq_printf(s, "Last S0i3 Status: %s\n", table.s0i3_last_entry_status ? "Success" :
446 "Unknown/Fail");
447 seq_printf(s, "Time (in us) to S0i3: %lld\n", table.timeentering_s0i3_lastcapture);
448 seq_printf(s, "Time (in us) in S0i3: %lld\n", table.timein_s0i3_lastcapture);
449 seq_printf(s, "Time (in us) to resume from S0i3: %lld\n",
450 table.timeto_resume_to_os_lastcapture);
451
452 seq_puts(s, "\n=== Active time (in us) ===\n");
453 for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
454 if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
455 seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
456 table.timecondition_notmet_lastcapture[idx]);
457 }
458
459 return 0;
460}
461DEFINE_SHOW_ATTRIBUTE(smu_fw_info);
462
463static int s0ix_stats_show(struct seq_file *s, void *unused)
464{
465 struct amd_pmc_dev *dev = s->private;
466 u64 entry_time, exit_time, residency;
467
468 /* Use FCH registers to get the S0ix stats */
469 if (!dev->fch_virt_addr) {
470 u32 base_addr_lo = FCH_BASE_PHY_ADDR_LOW;
471 u32 base_addr_hi = FCH_BASE_PHY_ADDR_HIGH;
472 u64 fch_phys_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
473
474 dev->fch_virt_addr = devm_ioremap(dev->dev, fch_phys_addr, FCH_SSC_MAPPING_SIZE);
475 if (!dev->fch_virt_addr)
476 return -ENOMEM;
477 }
478
479 entry_time = ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_H_OFFSET);
480 entry_time = entry_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_ENTRY_TIME_L_OFFSET);
481
482 exit_time = ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_H_OFFSET);
483 exit_time = exit_time << 32 | ioread32(dev->fch_virt_addr + FCH_S0I3_EXIT_TIME_L_OFFSET);
484
485 /* It's in 48MHz. We need to convert it */
486 residency = exit_time - entry_time;
487 do_div(residency, 48);
488
489 seq_puts(s, "=== S0ix statistics ===\n");
490 seq_printf(s, "S0ix Entry Time: %lld\n", entry_time);
491 seq_printf(s, "S0ix Exit Time: %lld\n", exit_time);
492 seq_printf(s, "Residency Time: %lld\n", residency);
493
494 return 0;
495}
496DEFINE_SHOW_ATTRIBUTE(s0ix_stats);
497
498static int amd_pmc_idlemask_show(struct seq_file *s, void *unused)
499{
500 struct amd_pmc_dev *dev = s->private;
501 int rc;
502
503 /* we haven't yet read SMU version */
504 if (!dev->major) {
505 rc = amd_pmc_get_smu_version(dev);
506 if (rc)
507 return rc;
508 }
509
510 if (dev->major > 56 || (dev->major >= 55 && dev->minor >= 37)) {
511 rc = amd_pmc_idlemask_read(dev, NULL, s);
512 if (rc)
513 return rc;
514 } else {
515 seq_puts(s, "Unsupported SMU version for Idlemask\n");
516 }
517
518 return 0;
519}
520DEFINE_SHOW_ATTRIBUTE(amd_pmc_idlemask);
521
522static void amd_pmc_dbgfs_unregister(struct amd_pmc_dev *dev)
523{
524 debugfs_remove_recursive(dev->dbgfs_dir);
525}
526
527static void amd_pmc_dbgfs_register(struct amd_pmc_dev *dev)
528{
529 dev->dbgfs_dir = debugfs_create_dir("amd_pmc", NULL);
530 debugfs_create_file("smu_fw_info", 0644, dev->dbgfs_dir, dev,
531 &smu_fw_info_fops);
532 debugfs_create_file("s0ix_stats", 0644, dev->dbgfs_dir, dev,
533 &s0ix_stats_fops);
534 debugfs_create_file("amd_pmc_idlemask", 0644, dev->dbgfs_dir, dev,
535 &amd_pmc_idlemask_fops);
536 /* Enable STB only when the module_param is set */
537 if (enable_stb) {
538 if (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB ||
539 dev->cpu_id == AMD_CPU_ID_PS)
540 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
541 &amd_pmc_stb_debugfs_fops_v2);
542 else
543 debugfs_create_file("stb_read", 0644, dev->dbgfs_dir, dev,
544 &amd_pmc_stb_debugfs_fops);
545 }
546}
547
548static void amd_pmc_dump_registers(struct amd_pmc_dev *dev)
549{
550 u32 value, message, argument, response;
551
552 if (dev->msg_port) {
553 message = AMD_S2D_REGISTER_MESSAGE;
554 argument = AMD_S2D_REGISTER_ARGUMENT;
555 response = AMD_S2D_REGISTER_RESPONSE;
556 } else {
557 message = AMD_PMC_REGISTER_MESSAGE;
558 argument = AMD_PMC_REGISTER_ARGUMENT;
559 response = AMD_PMC_REGISTER_RESPONSE;
560 }
561
562 value = amd_pmc_reg_read(dev, response);
563 dev_dbg(dev->dev, "AMD_PMC_REGISTER_RESPONSE:%x\n", value);
564
565 value = amd_pmc_reg_read(dev, argument);
566 dev_dbg(dev->dev, "AMD_PMC_REGISTER_ARGUMENT:%x\n", value);
567
568 value = amd_pmc_reg_read(dev, message);
569 dev_dbg(dev->dev, "AMD_PMC_REGISTER_MESSAGE:%x\n", value);
570}
571
572static int amd_pmc_send_cmd(struct amd_pmc_dev *dev, u32 arg, u32 *data, u8 msg, bool ret)
573{
574 int rc;
575 u32 val, message, argument, response;
576
577 mutex_lock(&dev->lock);
578
579 if (dev->msg_port) {
580 message = AMD_S2D_REGISTER_MESSAGE;
581 argument = AMD_S2D_REGISTER_ARGUMENT;
582 response = AMD_S2D_REGISTER_RESPONSE;
583 } else {
584 message = AMD_PMC_REGISTER_MESSAGE;
585 argument = AMD_PMC_REGISTER_ARGUMENT;
586 response = AMD_PMC_REGISTER_RESPONSE;
587 }
588
589 /* Wait until we get a valid response */
590 rc = readx_poll_timeout(ioread32, dev->regbase + response,
591 val, val != 0, PMC_MSG_DELAY_MIN_US,
592 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
593 if (rc) {
594 dev_err(dev->dev, "failed to talk to SMU\n");
595 goto out_unlock;
596 }
597
598 /* Write zero to response register */
599 amd_pmc_reg_write(dev, response, 0);
600
601 /* Write argument into response register */
602 amd_pmc_reg_write(dev, argument, arg);
603
604 /* Write message ID to message ID register */
605 amd_pmc_reg_write(dev, message, msg);
606
607 /* Wait until we get a valid response */
608 rc = readx_poll_timeout(ioread32, dev->regbase + response,
609 val, val != 0, PMC_MSG_DELAY_MIN_US,
610 PMC_MSG_DELAY_MIN_US * RESPONSE_REGISTER_LOOP_MAX);
611 if (rc) {
612 dev_err(dev->dev, "SMU response timed out\n");
613 goto out_unlock;
614 }
615
616 switch (val) {
617 case AMD_PMC_RESULT_OK:
618 if (ret) {
619 /* PMFW may take longer time to return back the data */
620 usleep_range(DELAY_MIN_US, 10 * DELAY_MAX_US);
621 *data = amd_pmc_reg_read(dev, argument);
622 }
623 break;
624 case AMD_PMC_RESULT_CMD_REJECT_BUSY:
625 dev_err(dev->dev, "SMU not ready. err: 0x%x\n", val);
626 rc = -EBUSY;
627 goto out_unlock;
628 case AMD_PMC_RESULT_CMD_UNKNOWN:
629 dev_err(dev->dev, "SMU cmd unknown. err: 0x%x\n", val);
630 rc = -EINVAL;
631 goto out_unlock;
632 case AMD_PMC_RESULT_CMD_REJECT_PREREQ:
633 case AMD_PMC_RESULT_FAILED:
634 default:
635 dev_err(dev->dev, "SMU cmd failed. err: 0x%x\n", val);
636 rc = -EIO;
637 goto out_unlock;
638 }
639
640out_unlock:
641 mutex_unlock(&dev->lock);
642 amd_pmc_dump_registers(dev);
643 return rc;
644}
645
646#ifdef CONFIG_SUSPEND
647static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev)
648{
649 switch (dev->cpu_id) {
650 case AMD_CPU_ID_PCO:
651 return MSG_OS_HINT_PCO;
652 case AMD_CPU_ID_RN:
653 case AMD_CPU_ID_YC:
654 case AMD_CPU_ID_CB:
655 case AMD_CPU_ID_PS:
656 return MSG_OS_HINT_RN;
657 }
658 return -EINVAL;
659}
660
661static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev)
662{
663 struct device *d;
664 int rc;
665
666 if (!pdev->major) {
667 rc = amd_pmc_get_smu_version(pdev);
668 if (rc)
669 return rc;
670 }
671
672 if (pdev->major > 64 || (pdev->major == 64 && pdev->minor > 65))
673 return 0;
674
675 d = bus_find_device_by_name(&serio_bus, NULL, "serio0");
676 if (!d)
677 return 0;
678 if (device_may_wakeup(d)) {
679 dev_info_once(d, "Disabling IRQ1 wakeup source to avoid platform firmware bug\n");
680 disable_irq_wake(1);
681 device_set_wakeup_enable(d, false);
682 }
683 put_device(d);
684
685 return 0;
686}
687
688static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg)
689{
690 struct rtc_device *rtc_device;
691 time64_t then, now, duration;
692 struct rtc_wkalrm alarm;
693 struct rtc_time tm;
694 int rc;
695
696 /* we haven't yet read SMU version */
697 if (!pdev->major) {
698 rc = amd_pmc_get_smu_version(pdev);
699 if (rc)
700 return rc;
701 }
702
703 if (pdev->major < 64 || (pdev->major == 64 && pdev->minor < 53))
704 return 0;
705
706 rtc_device = rtc_class_open("rtc0");
707 if (!rtc_device)
708 return 0;
709 rc = rtc_read_alarm(rtc_device, &alarm);
710 if (rc)
711 return rc;
712 if (!alarm.enabled) {
713 dev_dbg(pdev->dev, "alarm not enabled\n");
714 return 0;
715 }
716 rc = rtc_read_time(rtc_device, &tm);
717 if (rc)
718 return rc;
719 then = rtc_tm_to_time64(&alarm.time);
720 now = rtc_tm_to_time64(&tm);
721 duration = then-now;
722
723 /* in the past */
724 if (then < now)
725 return 0;
726
727 /* will be stored in upper 16 bits of s0i3 hint argument,
728 * so timer wakeup from s0i3 is limited to ~18 hours or less
729 */
730 if (duration <= 4 || duration > U16_MAX)
731 return -EINVAL;
732
733 *arg |= (duration << 16);
734 rc = rtc_alarm_irq_enable(rtc_device, 0);
735 dev_dbg(pdev->dev, "wakeup timer programmed for %lld seconds\n", duration);
736
737 return rc;
738}
739
740static void amd_pmc_s2idle_prepare(void)
741{
742 struct amd_pmc_dev *pdev = &pmc;
743 int rc;
744 u8 msg;
745 u32 arg = 1;
746
747 /* Reset and Start SMU logging - to monitor the s0i3 stats */
748 amd_pmc_setup_smu_logging(pdev);
749
750 /* Activate CZN specific platform bug workarounds */
751 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
752 rc = amd_pmc_verify_czn_rtc(pdev, &arg);
753 if (rc) {
754 dev_err(pdev->dev, "failed to set RTC: %d\n", rc);
755 return;
756 }
757 }
758
759 msg = amd_pmc_get_os_hint(pdev);
760 rc = amd_pmc_send_cmd(pdev, arg, NULL, msg, 0);
761 if (rc) {
762 dev_err(pdev->dev, "suspend failed: %d\n", rc);
763 return;
764 }
765
766 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_PREPARE);
767 if (rc)
768 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
769}
770
771static void amd_pmc_s2idle_check(void)
772{
773 struct amd_pmc_dev *pdev = &pmc;
774 struct smu_metrics table;
775 int rc;
776
777 /* CZN: Ensure that future s0i3 entry attempts at least 10ms passed */
778 if (pdev->cpu_id == AMD_CPU_ID_CZN && !get_metrics_table(pdev, &table) &&
779 table.s0i3_last_entry_status)
780 usleep_range(10000, 20000);
781
782 /* Dump the IdleMask before we add to the STB */
783 amd_pmc_idlemask_read(pdev, pdev->dev, NULL);
784
785 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_CHECK);
786 if (rc)
787 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
788}
789
790static void amd_pmc_s2idle_restore(void)
791{
792 struct amd_pmc_dev *pdev = &pmc;
793 int rc;
794 u8 msg;
795
796 msg = amd_pmc_get_os_hint(pdev);
797 rc = amd_pmc_send_cmd(pdev, 0, NULL, msg, 0);
798 if (rc)
799 dev_err(pdev->dev, "resume failed: %d\n", rc);
800
801 /* Let SMU know that we are looking for stats */
802 amd_pmc_send_cmd(pdev, 0, NULL, SMU_MSG_LOG_DUMP_DATA, 0);
803
804 rc = amd_pmc_write_stb(pdev, AMD_PMC_STB_S2IDLE_RESTORE);
805 if (rc)
806 dev_err(pdev->dev, "error writing to STB: %d\n", rc);
807
808 /* Notify on failed entry */
809 amd_pmc_validate_deepest(pdev);
810}
811
812static struct acpi_s2idle_dev_ops amd_pmc_s2idle_dev_ops = {
813 .prepare = amd_pmc_s2idle_prepare,
814 .check = amd_pmc_s2idle_check,
815 .restore = amd_pmc_s2idle_restore,
816};
817
818static int __maybe_unused amd_pmc_suspend_handler(struct device *dev)
819{
820 struct amd_pmc_dev *pdev = dev_get_drvdata(dev);
821
822 if (pdev->cpu_id == AMD_CPU_ID_CZN && !disable_workarounds) {
823 int rc = amd_pmc_czn_wa_irq1(pdev);
824
825 if (rc) {
826 dev_err(pdev->dev, "failed to adjust keyboard wakeup: %d\n", rc);
827 return rc;
828 }
829 }
830
831 return 0;
832}
833
834static SIMPLE_DEV_PM_OPS(amd_pmc_pm, amd_pmc_suspend_handler, NULL);
835
836#endif
837
838static const struct pci_device_id pmc_pci_ids[] = {
839 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PS) },
840 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CB) },
841 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_YC) },
842 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_CZN) },
843 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RN) },
844 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_PCO) },
845 { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) },
846 { }
847};
848
849static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
850{
851 u32 phys_addr_low, phys_addr_hi;
852 u64 stb_phys_addr;
853 u32 size = 0;
854
855 /* Spill to DRAM feature uses separate SMU message port */
856 dev->msg_port = 1;
857
858 amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, 1);
859 if (size != S2D_TELEMETRY_BYTES_MAX)
860 return -EIO;
861
862 /* Get STB DRAM address */
863 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, 1);
864 amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, 1);
865
866 stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
867
868 /* Clear msg_port for other SMU operation */
869 dev->msg_port = 0;
870
871 dev->stb_virt_addr = devm_ioremap(dev->dev, stb_phys_addr, S2D_TELEMETRY_DRAMBYTES_MAX);
872 if (!dev->stb_virt_addr)
873 return -ENOMEM;
874
875 return 0;
876}
877
878#ifdef CONFIG_SUSPEND
879static int amd_pmc_write_stb(struct amd_pmc_dev *dev, u32 data)
880{
881 int err;
882
883 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
884 if (err) {
885 dev_err(dev->dev, "failed to write addr in stb: 0x%X\n",
886 AMD_PMC_STB_INDEX_ADDRESS);
887 return pcibios_err_to_errno(err);
888 }
889
890 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, data);
891 if (err) {
892 dev_err(dev->dev, "failed to write data in stb: 0x%X\n",
893 AMD_PMC_STB_INDEX_DATA);
894 return pcibios_err_to_errno(err);
895 }
896
897 return 0;
898}
899#endif
900
901static int amd_pmc_read_stb(struct amd_pmc_dev *dev, u32 *buf)
902{
903 int i, err;
904
905 err = pci_write_config_dword(dev->rdev, AMD_PMC_STB_INDEX_ADDRESS, AMD_PMC_STB_PMI_0);
906 if (err) {
907 dev_err(dev->dev, "error writing addr to stb: 0x%X\n",
908 AMD_PMC_STB_INDEX_ADDRESS);
909 return pcibios_err_to_errno(err);
910 }
911
912 for (i = 0; i < FIFO_SIZE; i++) {
913 err = pci_read_config_dword(dev->rdev, AMD_PMC_STB_INDEX_DATA, buf++);
914 if (err) {
915 dev_err(dev->dev, "error reading data from stb: 0x%X\n",
916 AMD_PMC_STB_INDEX_DATA);
917 return pcibios_err_to_errno(err);
918 }
919 }
920
921 return 0;
922}
923
924static int amd_pmc_probe(struct platform_device *pdev)
925{
926 struct amd_pmc_dev *dev = &pmc;
927 struct pci_dev *rdev;
928 u32 base_addr_lo, base_addr_hi;
929 u64 base_addr;
930 int err;
931 u32 val;
932
933 dev->dev = &pdev->dev;
934
935 rdev = pci_get_domain_bus_and_slot(0, 0, PCI_DEVFN(0, 0));
936 if (!rdev || !pci_match_id(pmc_pci_ids, rdev)) {
937 err = -ENODEV;
938 goto err_pci_dev_put;
939 }
940
941 dev->cpu_id = rdev->device;
942 dev->rdev = rdev;
943 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_LO);
944 if (err) {
945 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
946 err = pcibios_err_to_errno(err);
947 goto err_pci_dev_put;
948 }
949
950 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
951 if (err) {
952 err = pcibios_err_to_errno(err);
953 goto err_pci_dev_put;
954 }
955
956 base_addr_lo = val & AMD_PMC_BASE_ADDR_HI_MASK;
957
958 err = pci_write_config_dword(rdev, AMD_PMC_SMU_INDEX_ADDRESS, AMD_PMC_BASE_ADDR_HI);
959 if (err) {
960 dev_err(dev->dev, "error writing to 0x%x\n", AMD_PMC_SMU_INDEX_ADDRESS);
961 err = pcibios_err_to_errno(err);
962 goto err_pci_dev_put;
963 }
964
965 err = pci_read_config_dword(rdev, AMD_PMC_SMU_INDEX_DATA, &val);
966 if (err) {
967 err = pcibios_err_to_errno(err);
968 goto err_pci_dev_put;
969 }
970
971 base_addr_hi = val & AMD_PMC_BASE_ADDR_LO_MASK;
972 base_addr = ((u64)base_addr_hi << 32 | base_addr_lo);
973
974 dev->regbase = devm_ioremap(dev->dev, base_addr + AMD_PMC_BASE_ADDR_OFFSET,
975 AMD_PMC_MAPPING_SIZE);
976 if (!dev->regbase) {
977 err = -ENOMEM;
978 goto err_pci_dev_put;
979 }
980
981 mutex_init(&dev->lock);
982
983 if (enable_stb && (dev->cpu_id == AMD_CPU_ID_YC || dev->cpu_id == AMD_CPU_ID_CB)) {
984 err = amd_pmc_s2d_init(dev);
985 if (err)
986 goto err_pci_dev_put;
987 }
988
989 platform_set_drvdata(pdev, dev);
990#ifdef CONFIG_SUSPEND
991 err = acpi_register_lps0_dev(&amd_pmc_s2idle_dev_ops);
992 if (err)
993 dev_warn(dev->dev, "failed to register LPS0 sleep handler, expect increased power consumption\n");
994#endif
995
996 amd_pmc_dbgfs_register(dev);
997 return 0;
998
999err_pci_dev_put:
1000 pci_dev_put(rdev);
1001 return err;
1002}
1003
1004static int amd_pmc_remove(struct platform_device *pdev)
1005{
1006 struct amd_pmc_dev *dev = platform_get_drvdata(pdev);
1007
1008#ifdef CONFIG_SUSPEND
1009 acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops);
1010#endif
1011 amd_pmc_dbgfs_unregister(dev);
1012 pci_dev_put(dev->rdev);
1013 mutex_destroy(&dev->lock);
1014 return 0;
1015}
1016
1017static const struct acpi_device_id amd_pmc_acpi_ids[] = {
1018 {"AMDI0005", 0},
1019 {"AMDI0006", 0},
1020 {"AMDI0007", 0},
1021 {"AMDI0008", 0},
1022 {"AMDI0009", 0},
1023 {"AMD0004", 0},
1024 {"AMD0005", 0},
1025 { }
1026};
1027MODULE_DEVICE_TABLE(acpi, amd_pmc_acpi_ids);
1028
1029static struct platform_driver amd_pmc_driver = {
1030 .driver = {
1031 .name = "amd_pmc",
1032 .acpi_match_table = amd_pmc_acpi_ids,
1033 .dev_groups = pmc_groups,
1034#ifdef CONFIG_SUSPEND
1035 .pm = &amd_pmc_pm,
1036#endif
1037 },
1038 .probe = amd_pmc_probe,
1039 .remove = amd_pmc_remove,
1040};
1041module_platform_driver(amd_pmc_driver);
1042
1043MODULE_LICENSE("GPL v2");
1044MODULE_DESCRIPTION("AMD PMC Driver");