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1/*******************************************************************************
2 STMMAC Common Header File
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
25#ifndef __COMMON_H__
26#define __COMMON_H__
27
28#include <linux/etherdevice.h>
29#include <linux/netdevice.h>
30#include <linux/stmmac.h>
31#include <linux/phy.h>
32#include <linux/module.h>
33#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
34#define STMMAC_VLAN_TAG_USED
35#include <linux/if_vlan.h>
36#endif
37
38#include "descs.h"
39#include "mmc.h"
40
41/* Synopsys Core versions */
42#define DWMAC_CORE_3_40 0x34
43#define DWMAC_CORE_3_50 0x35
44
45#define DMA_TX_SIZE 512
46#define DMA_RX_SIZE 512
47#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
48
49#undef FRAME_FILTER_DEBUG
50/* #define FRAME_FILTER_DEBUG */
51
52/* Extra statistic and debug information exposed by ethtool */
53struct stmmac_extra_stats {
54 /* Transmit errors */
55 unsigned long tx_underflow ____cacheline_aligned;
56 unsigned long tx_carrier;
57 unsigned long tx_losscarrier;
58 unsigned long vlan_tag;
59 unsigned long tx_deferred;
60 unsigned long tx_vlan;
61 unsigned long tx_jabber;
62 unsigned long tx_frame_flushed;
63 unsigned long tx_payload_error;
64 unsigned long tx_ip_header_error;
65 /* Receive errors */
66 unsigned long rx_desc;
67 unsigned long sa_filter_fail;
68 unsigned long overflow_error;
69 unsigned long ipc_csum_error;
70 unsigned long rx_collision;
71 unsigned long rx_crc;
72 unsigned long dribbling_bit;
73 unsigned long rx_length;
74 unsigned long rx_mii;
75 unsigned long rx_multicast;
76 unsigned long rx_gmac_overflow;
77 unsigned long rx_watchdog;
78 unsigned long da_rx_filter_fail;
79 unsigned long sa_rx_filter_fail;
80 unsigned long rx_missed_cntr;
81 unsigned long rx_overflow_cntr;
82 unsigned long rx_vlan;
83 /* Tx/Rx IRQ error info */
84 unsigned long tx_undeflow_irq;
85 unsigned long tx_process_stopped_irq;
86 unsigned long tx_jabber_irq;
87 unsigned long rx_overflow_irq;
88 unsigned long rx_buf_unav_irq;
89 unsigned long rx_process_stopped_irq;
90 unsigned long rx_watchdog_irq;
91 unsigned long tx_early_irq;
92 unsigned long fatal_bus_error_irq;
93 /* Tx/Rx IRQ Events */
94 unsigned long rx_early_irq;
95 unsigned long threshold;
96 unsigned long tx_pkt_n;
97 unsigned long rx_pkt_n;
98 unsigned long normal_irq_n;
99 unsigned long rx_normal_irq_n;
100 unsigned long napi_poll;
101 unsigned long tx_normal_irq_n;
102 unsigned long tx_clean;
103 unsigned long tx_set_ic_bit;
104 unsigned long irq_receive_pmt_irq_n;
105 /* MMC info */
106 unsigned long mmc_tx_irq_n;
107 unsigned long mmc_rx_irq_n;
108 unsigned long mmc_rx_csum_offload_irq_n;
109 /* EEE */
110 unsigned long irq_tx_path_in_lpi_mode_n;
111 unsigned long irq_tx_path_exit_lpi_mode_n;
112 unsigned long irq_rx_path_in_lpi_mode_n;
113 unsigned long irq_rx_path_exit_lpi_mode_n;
114 unsigned long phy_eee_wakeup_error_n;
115 /* Extended RDES status */
116 unsigned long ip_hdr_err;
117 unsigned long ip_payload_err;
118 unsigned long ip_csum_bypassed;
119 unsigned long ipv4_pkt_rcvd;
120 unsigned long ipv6_pkt_rcvd;
121 unsigned long rx_msg_type_ext_no_ptp;
122 unsigned long rx_msg_type_sync;
123 unsigned long rx_msg_type_follow_up;
124 unsigned long rx_msg_type_delay_req;
125 unsigned long rx_msg_type_delay_resp;
126 unsigned long rx_msg_type_pdelay_req;
127 unsigned long rx_msg_type_pdelay_resp;
128 unsigned long rx_msg_type_pdelay_follow_up;
129 unsigned long ptp_frame_type;
130 unsigned long ptp_ver;
131 unsigned long timestamp_dropped;
132 unsigned long av_pkt_rcvd;
133 unsigned long av_tagged_pkt_rcvd;
134 unsigned long vlan_tag_priority_val;
135 unsigned long l3_filter_match;
136 unsigned long l4_filter_match;
137 unsigned long l3_l4_filter_no_match;
138 /* PCS */
139 unsigned long irq_pcs_ane_n;
140 unsigned long irq_pcs_link_n;
141 unsigned long irq_rgmii_n;
142 unsigned long pcs_link;
143 unsigned long pcs_duplex;
144 unsigned long pcs_speed;
145 /* debug register */
146 unsigned long mtl_tx_status_fifo_full;
147 unsigned long mtl_tx_fifo_not_empty;
148 unsigned long mmtl_fifo_ctrl;
149 unsigned long mtl_tx_fifo_read_ctrl_write;
150 unsigned long mtl_tx_fifo_read_ctrl_wait;
151 unsigned long mtl_tx_fifo_read_ctrl_read;
152 unsigned long mtl_tx_fifo_read_ctrl_idle;
153 unsigned long mac_tx_in_pause;
154 unsigned long mac_tx_frame_ctrl_xfer;
155 unsigned long mac_tx_frame_ctrl_idle;
156 unsigned long mac_tx_frame_ctrl_wait;
157 unsigned long mac_tx_frame_ctrl_pause;
158 unsigned long mac_gmii_tx_proto_engine;
159 unsigned long mtl_rx_fifo_fill_level_full;
160 unsigned long mtl_rx_fifo_fill_above_thresh;
161 unsigned long mtl_rx_fifo_fill_below_thresh;
162 unsigned long mtl_rx_fifo_fill_level_empty;
163 unsigned long mtl_rx_fifo_read_ctrl_flush;
164 unsigned long mtl_rx_fifo_read_ctrl_read_data;
165 unsigned long mtl_rx_fifo_read_ctrl_status;
166 unsigned long mtl_rx_fifo_read_ctrl_idle;
167 unsigned long mtl_rx_fifo_ctrl_active;
168 unsigned long mac_rx_frame_ctrl_fifo;
169 unsigned long mac_gmii_rx_proto_engine;
170};
171
172/* CSR Frequency Access Defines*/
173#define CSR_F_35M 35000000
174#define CSR_F_60M 60000000
175#define CSR_F_100M 100000000
176#define CSR_F_150M 150000000
177#define CSR_F_250M 250000000
178#define CSR_F_300M 300000000
179
180#define MAC_CSR_H_FRQ_MASK 0x20
181
182#define HASH_TABLE_SIZE 64
183#define PAUSE_TIME 0xffff
184
185/* Flow Control defines */
186#define FLOW_OFF 0
187#define FLOW_RX 1
188#define FLOW_TX 2
189#define FLOW_AUTO (FLOW_TX | FLOW_RX)
190
191/* PCS defines */
192#define STMMAC_PCS_RGMII (1 << 0)
193#define STMMAC_PCS_SGMII (1 << 1)
194#define STMMAC_PCS_TBI (1 << 2)
195#define STMMAC_PCS_RTBI (1 << 3)
196
197#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
198
199/* DAM HW feature register fields */
200#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
201#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
202#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
203#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
204#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
205#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
206#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
207#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
208#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
209#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
210#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
211#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
212#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
213#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
214#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
215#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
216#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
217#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
218#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
219#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
220#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
221#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
222#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
223/* Timestamping with Internal System Time */
224#define DMA_HW_FEAT_INTTSEN 0x02000000
225#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
226#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
227#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
228#define DEFAULT_DMA_PBL 8
229
230/* Max/Min RI Watchdog Timer count value */
231#define MAX_DMA_RIWT 0xff
232#define MIN_DMA_RIWT 0x20
233/* Tx coalesce parameters */
234#define STMMAC_COAL_TX_TIMER 40000
235#define STMMAC_MAX_COAL_TX_TICK 100000
236#define STMMAC_TX_MAX_FRAMES 256
237#define STMMAC_TX_FRAMES 64
238
239/* Rx IPC status */
240enum rx_frame_status {
241 good_frame = 0x0,
242 discard_frame = 0x1,
243 csum_none = 0x2,
244 llc_snap = 0x4,
245 dma_own = 0x8,
246};
247
248/* Tx status */
249enum tx_frame_status {
250 tx_done = 0x0,
251 tx_not_ls = 0x1,
252 tx_err = 0x2,
253 tx_dma_own = 0x4,
254};
255
256enum dma_irq_status {
257 tx_hard_error = 0x1,
258 tx_hard_error_bump_tc = 0x2,
259 handle_rx = 0x4,
260 handle_tx = 0x8,
261};
262
263/* EEE and LPI defines */
264#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
265#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
266#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
267#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
268
269#define CORE_PCS_ANE_COMPLETE (1 << 5)
270#define CORE_PCS_LINK_STATUS (1 << 6)
271#define CORE_RGMII_IRQ (1 << 7)
272
273/* Physical Coding Sublayer */
274struct rgmii_adv {
275 unsigned int pause;
276 unsigned int duplex;
277 unsigned int lp_pause;
278 unsigned int lp_duplex;
279};
280
281#define STMMAC_PCS_PAUSE 1
282#define STMMAC_PCS_ASYM_PAUSE 2
283
284/* DMA HW capabilities */
285struct dma_features {
286 unsigned int mbps_10_100;
287 unsigned int mbps_1000;
288 unsigned int half_duplex;
289 unsigned int hash_filter;
290 unsigned int multi_addr;
291 unsigned int pcs;
292 unsigned int sma_mdio;
293 unsigned int pmt_remote_wake_up;
294 unsigned int pmt_magic_frame;
295 unsigned int rmon;
296 /* IEEE 1588-2002 */
297 unsigned int time_stamp;
298 /* IEEE 1588-2008 */
299 unsigned int atime_stamp;
300 /* 802.3az - Energy-Efficient Ethernet (EEE) */
301 unsigned int eee;
302 unsigned int av;
303 /* TX and RX csum */
304 unsigned int tx_coe;
305 unsigned int rx_coe_type1;
306 unsigned int rx_coe_type2;
307 unsigned int rxfifo_over_2048;
308 /* TX and RX number of channels */
309 unsigned int number_rx_channel;
310 unsigned int number_tx_channel;
311 /* Alternate (enhanced) DESC mode */
312 unsigned int enh_desc;
313};
314
315/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
316#define BUF_SIZE_16KiB 16384
317#define BUF_SIZE_8KiB 8192
318#define BUF_SIZE_4KiB 4096
319#define BUF_SIZE_2KiB 2048
320
321/* Power Down and WOL */
322#define PMT_NOT_SUPPORTED 0
323#define PMT_SUPPORTED 1
324
325/* Common MAC defines */
326#define MAC_CTRL_REG 0x00000000 /* MAC Control */
327#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
328#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
329
330/* Default LPI timers */
331#define STMMAC_DEFAULT_LIT_LS 0x3E8
332#define STMMAC_DEFAULT_TWT_LS 0x1E
333
334#define STMMAC_CHAIN_MODE 0x1
335#define STMMAC_RING_MODE 0x2
336
337#define JUMBO_LEN 9000
338
339/* Descriptors helpers */
340struct stmmac_desc_ops {
341 /* DMA RX descriptor ring initialization */
342 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
343 int end);
344 /* DMA TX descriptor ring initialization */
345 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
346
347 /* Invoked by the xmit function to prepare the tx descriptor */
348 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
349 bool csum_flag, int mode, bool tx_own,
350 bool ls);
351 /* Set/get the owner of the descriptor */
352 void (*set_tx_owner) (struct dma_desc *p);
353 int (*get_tx_owner) (struct dma_desc *p);
354 /* Clean the tx descriptor as soon as the tx irq is received */
355 void (*release_tx_desc) (struct dma_desc *p, int mode);
356 /* Clear interrupt on tx frame completion. When this bit is
357 * set an interrupt happens as soon as the frame is transmitted */
358 void (*set_tx_ic)(struct dma_desc *p);
359 /* Last tx segment reports the transmit status */
360 int (*get_tx_ls) (struct dma_desc *p);
361 /* Return the transmit status looking at the TDES1 */
362 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
363 struct dma_desc *p, void __iomem *ioaddr);
364 /* Get the buffer size from the descriptor */
365 int (*get_tx_len) (struct dma_desc *p);
366 /* Handle extra events on specific interrupts hw dependent */
367 void (*set_rx_owner) (struct dma_desc *p);
368 /* Get the receive frame size */
369 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
370 /* Return the reception status looking at the RDES1 */
371 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
372 struct dma_desc *p);
373 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
374 struct dma_extended_desc *p);
375 /* Set tx timestamp enable bit */
376 void (*enable_tx_timestamp) (struct dma_desc *p);
377 /* get tx timestamp status */
378 int (*get_tx_timestamp_status) (struct dma_desc *p);
379 /* get timestamp value */
380 u64(*get_timestamp) (void *desc, u32 ats);
381 /* get rx timestamp status */
382 int (*get_rx_timestamp_status) (void *desc, u32 ats);
383};
384
385extern const struct stmmac_desc_ops enh_desc_ops;
386extern const struct stmmac_desc_ops ndesc_ops;
387
388/* Specific DMA helpers */
389struct stmmac_dma_ops {
390 /* DMA core initialization */
391 int (*reset)(void __iomem *ioaddr);
392 void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb,
393 int aal, u32 dma_tx, u32 dma_rx, int atds);
394 /* Configure the AXI Bus Mode Register */
395 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
396 /* Dump DMA registers */
397 void (*dump_regs) (void __iomem *ioaddr);
398 /* Set tx/rx threshold in the csr6 register
399 * An invalid value enables the store-and-forward mode */
400 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
401 int rxfifosz);
402 /* To track extra statistic (if supported) */
403 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
404 void __iomem *ioaddr);
405 void (*enable_dma_transmission) (void __iomem *ioaddr);
406 void (*enable_dma_irq) (void __iomem *ioaddr);
407 void (*disable_dma_irq) (void __iomem *ioaddr);
408 void (*start_tx) (void __iomem *ioaddr);
409 void (*stop_tx) (void __iomem *ioaddr);
410 void (*start_rx) (void __iomem *ioaddr);
411 void (*stop_rx) (void __iomem *ioaddr);
412 int (*dma_interrupt) (void __iomem *ioaddr,
413 struct stmmac_extra_stats *x);
414 /* If supported then get the optional core features */
415 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
416 /* Program the HW RX Watchdog */
417 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
418};
419
420struct mac_device_info;
421
422/* Helpers to program the MAC core */
423struct stmmac_ops {
424 /* MAC core initialization */
425 void (*core_init)(struct mac_device_info *hw, int mtu);
426 /* Enable and verify that the IPC module is supported */
427 int (*rx_ipc)(struct mac_device_info *hw);
428 /* Dump MAC registers */
429 void (*dump_regs)(struct mac_device_info *hw);
430 /* Handle extra events on specific interrupts hw dependent */
431 int (*host_irq_status)(struct mac_device_info *hw,
432 struct stmmac_extra_stats *x);
433 /* Multicast filter setting */
434 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
435 /* Flow control setting */
436 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
437 unsigned int fc, unsigned int pause_time);
438 /* Set power management mode (e.g. magic frame) */
439 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
440 /* Set/Get Unicast MAC addresses */
441 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
442 unsigned int reg_n);
443 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
444 unsigned int reg_n);
445 void (*set_eee_mode)(struct mac_device_info *hw);
446 void (*reset_eee_mode)(struct mac_device_info *hw);
447 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
448 void (*set_eee_pls)(struct mac_device_info *hw, int link);
449 void (*ctrl_ane)(struct mac_device_info *hw, bool restart);
450 void (*get_adv)(struct mac_device_info *hw, struct rgmii_adv *adv);
451 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x);
452};
453
454/* PTP and HW Timer helpers */
455struct stmmac_hwtimestamp {
456 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
457 u32 (*config_sub_second_increment) (void __iomem *ioaddr, u32 clk_rate);
458 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
459 int (*config_addend) (void __iomem *ioaddr, u32 addend);
460 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
461 int add_sub);
462 u64(*get_systime) (void __iomem *ioaddr);
463};
464
465extern const struct stmmac_hwtimestamp stmmac_ptp;
466
467struct mac_link {
468 int port;
469 int duplex;
470 int speed;
471};
472
473struct mii_regs {
474 unsigned int addr; /* MII Address */
475 unsigned int data; /* MII Data */
476};
477
478/* Helpers to manage the descriptors for chain and ring modes */
479struct stmmac_mode_ops {
480 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
481 unsigned int extend_desc);
482 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
483 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
484 int (*set_16kib_bfsize)(int mtu);
485 void (*init_desc3)(struct dma_desc *p);
486 void (*refill_desc3) (void *priv, struct dma_desc *p);
487 void (*clean_desc3) (void *priv, struct dma_desc *p);
488};
489
490struct mac_device_info {
491 const struct stmmac_ops *mac;
492 const struct stmmac_desc_ops *desc;
493 const struct stmmac_dma_ops *dma;
494 const struct stmmac_mode_ops *mode;
495 const struct stmmac_hwtimestamp *ptp;
496 struct mii_regs mii; /* MII register Addresses */
497 struct mac_link link;
498 unsigned int synopsys_uid;
499 void __iomem *pcsr; /* vpointer to device CSRs */
500 int multicast_filter_bins;
501 int unicast_filter_entries;
502 int mcast_bits_log2;
503 unsigned int rx_csum;
504};
505
506struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
507 int perfect_uc_entries);
508struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
509
510void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
511 unsigned int high, unsigned int low);
512void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
513 unsigned int high, unsigned int low);
514
515void stmmac_set_mac(void __iomem *ioaddr, bool enable);
516
517void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
518extern const struct stmmac_mode_ops ring_mode_ops;
519extern const struct stmmac_mode_ops chain_mode_ops;
520
521#endif /* __COMMON_H__ */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*******************************************************************************
3 STMMAC Common Header File
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9*******************************************************************************/
10
11#ifndef __COMMON_H__
12#define __COMMON_H__
13
14#include <linux/etherdevice.h>
15#include <linux/netdevice.h>
16#include <linux/stmmac.h>
17#include <linux/phy.h>
18#include <linux/pcs/pcs-xpcs.h>
19#include <linux/module.h>
20#if IS_ENABLED(CONFIG_VLAN_8021Q)
21#define STMMAC_VLAN_TAG_USED
22#include <linux/if_vlan.h>
23#endif
24
25#include "descs.h"
26#include "hwif.h"
27#include "mmc.h"
28
29/* Synopsys Core versions */
30#define DWMAC_CORE_3_40 0x34
31#define DWMAC_CORE_3_50 0x35
32#define DWMAC_CORE_4_00 0x40
33#define DWMAC_CORE_4_10 0x41
34#define DWMAC_CORE_5_00 0x50
35#define DWMAC_CORE_5_10 0x51
36#define DWMAC_CORE_5_20 0x52
37#define DWXGMAC_CORE_2_10 0x21
38#define DWXLGMAC_CORE_2_00 0x20
39
40/* Device ID */
41#define DWXGMAC_ID 0x76
42#define DWXLGMAC_ID 0x27
43
44#define STMMAC_CHAN0 0 /* Always supported and default for all chips */
45
46/* TX and RX Descriptor Length, these need to be power of two.
47 * TX descriptor length less than 64 may cause transmit queue timed out error.
48 * RX descriptor length less than 64 may cause inconsistent Rx chain error.
49 */
50#define DMA_MIN_TX_SIZE 64
51#define DMA_MAX_TX_SIZE 1024
52#define DMA_DEFAULT_TX_SIZE 512
53#define DMA_MIN_RX_SIZE 64
54#define DMA_MAX_RX_SIZE 1024
55#define DMA_DEFAULT_RX_SIZE 512
56#define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
57
58#undef FRAME_FILTER_DEBUG
59/* #define FRAME_FILTER_DEBUG */
60
61struct stmmac_txq_stats {
62 unsigned long tx_pkt_n;
63 unsigned long tx_normal_irq_n;
64};
65
66struct stmmac_rxq_stats {
67 unsigned long rx_pkt_n;
68 unsigned long rx_normal_irq_n;
69};
70
71/* Extra statistic and debug information exposed by ethtool */
72struct stmmac_extra_stats {
73 /* Transmit errors */
74 unsigned long tx_underflow ____cacheline_aligned;
75 unsigned long tx_carrier;
76 unsigned long tx_losscarrier;
77 unsigned long vlan_tag;
78 unsigned long tx_deferred;
79 unsigned long tx_vlan;
80 unsigned long tx_jabber;
81 unsigned long tx_frame_flushed;
82 unsigned long tx_payload_error;
83 unsigned long tx_ip_header_error;
84 /* Receive errors */
85 unsigned long rx_desc;
86 unsigned long sa_filter_fail;
87 unsigned long overflow_error;
88 unsigned long ipc_csum_error;
89 unsigned long rx_collision;
90 unsigned long rx_crc_errors;
91 unsigned long dribbling_bit;
92 unsigned long rx_length;
93 unsigned long rx_mii;
94 unsigned long rx_multicast;
95 unsigned long rx_gmac_overflow;
96 unsigned long rx_watchdog;
97 unsigned long da_rx_filter_fail;
98 unsigned long sa_rx_filter_fail;
99 unsigned long rx_missed_cntr;
100 unsigned long rx_overflow_cntr;
101 unsigned long rx_vlan;
102 unsigned long rx_split_hdr_pkt_n;
103 /* Tx/Rx IRQ error info */
104 unsigned long tx_undeflow_irq;
105 unsigned long tx_process_stopped_irq;
106 unsigned long tx_jabber_irq;
107 unsigned long rx_overflow_irq;
108 unsigned long rx_buf_unav_irq;
109 unsigned long rx_process_stopped_irq;
110 unsigned long rx_watchdog_irq;
111 unsigned long tx_early_irq;
112 unsigned long fatal_bus_error_irq;
113 /* Tx/Rx IRQ Events */
114 unsigned long rx_early_irq;
115 unsigned long threshold;
116 unsigned long tx_pkt_n;
117 unsigned long rx_pkt_n;
118 unsigned long normal_irq_n;
119 unsigned long rx_normal_irq_n;
120 unsigned long napi_poll;
121 unsigned long tx_normal_irq_n;
122 unsigned long tx_clean;
123 unsigned long tx_set_ic_bit;
124 unsigned long irq_receive_pmt_irq_n;
125 /* MMC info */
126 unsigned long mmc_tx_irq_n;
127 unsigned long mmc_rx_irq_n;
128 unsigned long mmc_rx_csum_offload_irq_n;
129 /* EEE */
130 unsigned long irq_tx_path_in_lpi_mode_n;
131 unsigned long irq_tx_path_exit_lpi_mode_n;
132 unsigned long irq_rx_path_in_lpi_mode_n;
133 unsigned long irq_rx_path_exit_lpi_mode_n;
134 unsigned long phy_eee_wakeup_error_n;
135 /* Extended RDES status */
136 unsigned long ip_hdr_err;
137 unsigned long ip_payload_err;
138 unsigned long ip_csum_bypassed;
139 unsigned long ipv4_pkt_rcvd;
140 unsigned long ipv6_pkt_rcvd;
141 unsigned long no_ptp_rx_msg_type_ext;
142 unsigned long ptp_rx_msg_type_sync;
143 unsigned long ptp_rx_msg_type_follow_up;
144 unsigned long ptp_rx_msg_type_delay_req;
145 unsigned long ptp_rx_msg_type_delay_resp;
146 unsigned long ptp_rx_msg_type_pdelay_req;
147 unsigned long ptp_rx_msg_type_pdelay_resp;
148 unsigned long ptp_rx_msg_type_pdelay_follow_up;
149 unsigned long ptp_rx_msg_type_announce;
150 unsigned long ptp_rx_msg_type_management;
151 unsigned long ptp_rx_msg_pkt_reserved_type;
152 unsigned long ptp_frame_type;
153 unsigned long ptp_ver;
154 unsigned long timestamp_dropped;
155 unsigned long av_pkt_rcvd;
156 unsigned long av_tagged_pkt_rcvd;
157 unsigned long vlan_tag_priority_val;
158 unsigned long l3_filter_match;
159 unsigned long l4_filter_match;
160 unsigned long l3_l4_filter_no_match;
161 /* PCS */
162 unsigned long irq_pcs_ane_n;
163 unsigned long irq_pcs_link_n;
164 unsigned long irq_rgmii_n;
165 unsigned long pcs_link;
166 unsigned long pcs_duplex;
167 unsigned long pcs_speed;
168 /* debug register */
169 unsigned long mtl_tx_status_fifo_full;
170 unsigned long mtl_tx_fifo_not_empty;
171 unsigned long mmtl_fifo_ctrl;
172 unsigned long mtl_tx_fifo_read_ctrl_write;
173 unsigned long mtl_tx_fifo_read_ctrl_wait;
174 unsigned long mtl_tx_fifo_read_ctrl_read;
175 unsigned long mtl_tx_fifo_read_ctrl_idle;
176 unsigned long mac_tx_in_pause;
177 unsigned long mac_tx_frame_ctrl_xfer;
178 unsigned long mac_tx_frame_ctrl_idle;
179 unsigned long mac_tx_frame_ctrl_wait;
180 unsigned long mac_tx_frame_ctrl_pause;
181 unsigned long mac_gmii_tx_proto_engine;
182 unsigned long mtl_rx_fifo_fill_level_full;
183 unsigned long mtl_rx_fifo_fill_above_thresh;
184 unsigned long mtl_rx_fifo_fill_below_thresh;
185 unsigned long mtl_rx_fifo_fill_level_empty;
186 unsigned long mtl_rx_fifo_read_ctrl_flush;
187 unsigned long mtl_rx_fifo_read_ctrl_read_data;
188 unsigned long mtl_rx_fifo_read_ctrl_status;
189 unsigned long mtl_rx_fifo_read_ctrl_idle;
190 unsigned long mtl_rx_fifo_ctrl_active;
191 unsigned long mac_rx_frame_ctrl_fifo;
192 unsigned long mac_gmii_rx_proto_engine;
193 /* TSO */
194 unsigned long tx_tso_frames;
195 unsigned long tx_tso_nfrags;
196 /* EST */
197 unsigned long mtl_est_cgce;
198 unsigned long mtl_est_hlbs;
199 unsigned long mtl_est_hlbf;
200 unsigned long mtl_est_btre;
201 unsigned long mtl_est_btrlm;
202 /* per queue statistics */
203 struct stmmac_txq_stats txq_stats[MTL_MAX_TX_QUEUES];
204 struct stmmac_rxq_stats rxq_stats[MTL_MAX_RX_QUEUES];
205};
206
207/* Safety Feature statistics exposed by ethtool */
208struct stmmac_safety_stats {
209 unsigned long mac_errors[32];
210 unsigned long mtl_errors[32];
211 unsigned long dma_errors[32];
212};
213
214/* Number of fields in Safety Stats */
215#define STMMAC_SAFETY_FEAT_SIZE \
216 (sizeof(struct stmmac_safety_stats) / sizeof(unsigned long))
217
218/* CSR Frequency Access Defines*/
219#define CSR_F_35M 35000000
220#define CSR_F_60M 60000000
221#define CSR_F_100M 100000000
222#define CSR_F_150M 150000000
223#define CSR_F_250M 250000000
224#define CSR_F_300M 300000000
225
226#define MAC_CSR_H_FRQ_MASK 0x20
227
228#define HASH_TABLE_SIZE 64
229#define PAUSE_TIME 0xffff
230
231/* Flow Control defines */
232#define FLOW_OFF 0
233#define FLOW_RX 1
234#define FLOW_TX 2
235#define FLOW_AUTO (FLOW_TX | FLOW_RX)
236
237/* PCS defines */
238#define STMMAC_PCS_RGMII (1 << 0)
239#define STMMAC_PCS_SGMII (1 << 1)
240#define STMMAC_PCS_TBI (1 << 2)
241#define STMMAC_PCS_RTBI (1 << 3)
242
243#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
244
245/* DAM HW feature register fields */
246#define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
247#define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
248#define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
249#define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
250#define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
251#define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
252#define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
253#define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
254#define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
255#define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
256#define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
257#define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
258#define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
259#define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
260#define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
261#define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
262#define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
263#define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
264#define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
265#define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
266#define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
267#define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
268#define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
269/* Timestamping with Internal System Time */
270#define DMA_HW_FEAT_INTTSEN 0x02000000
271#define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
272#define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
273#define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
274#define DEFAULT_DMA_PBL 8
275
276/* MSI defines */
277#define STMMAC_MSI_VEC_MAX 32
278
279/* PCS status and mask defines */
280#define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
281#define PCS_LINK_IRQ BIT(1) /* PCS Link */
282#define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
283
284/* Max/Min RI Watchdog Timer count value */
285#define MAX_DMA_RIWT 0xff
286#define MIN_DMA_RIWT 0x10
287#define DEF_DMA_RIWT 0xa0
288/* Tx coalesce parameters */
289#define STMMAC_COAL_TX_TIMER 1000
290#define STMMAC_MAX_COAL_TX_TICK 100000
291#define STMMAC_TX_MAX_FRAMES 256
292#define STMMAC_TX_FRAMES 25
293#define STMMAC_RX_FRAMES 0
294
295/* Packets types */
296enum packets_types {
297 PACKET_AVCPQ = 0x1, /* AV Untagged Control packets */
298 PACKET_PTPQ = 0x2, /* PTP Packets */
299 PACKET_DCBCPQ = 0x3, /* DCB Control Packets */
300 PACKET_UPQ = 0x4, /* Untagged Packets */
301 PACKET_MCBCQ = 0x5, /* Multicast & Broadcast Packets */
302};
303
304/* Rx IPC status */
305enum rx_frame_status {
306 good_frame = 0x0,
307 discard_frame = 0x1,
308 csum_none = 0x2,
309 llc_snap = 0x4,
310 dma_own = 0x8,
311 rx_not_ls = 0x10,
312};
313
314/* Tx status */
315enum tx_frame_status {
316 tx_done = 0x0,
317 tx_not_ls = 0x1,
318 tx_err = 0x2,
319 tx_dma_own = 0x4,
320 tx_err_bump_tc = 0x8,
321};
322
323enum dma_irq_status {
324 tx_hard_error = 0x1,
325 tx_hard_error_bump_tc = 0x2,
326 handle_rx = 0x4,
327 handle_tx = 0x8,
328};
329
330enum dma_irq_dir {
331 DMA_DIR_RX = 0x1,
332 DMA_DIR_TX = 0x2,
333 DMA_DIR_RXTX = 0x3,
334};
335
336enum request_irq_err {
337 REQ_IRQ_ERR_ALL,
338 REQ_IRQ_ERR_TX,
339 REQ_IRQ_ERR_RX,
340 REQ_IRQ_ERR_SFTY_UE,
341 REQ_IRQ_ERR_SFTY_CE,
342 REQ_IRQ_ERR_LPI,
343 REQ_IRQ_ERR_WOL,
344 REQ_IRQ_ERR_MAC,
345 REQ_IRQ_ERR_NO,
346};
347
348/* EEE and LPI defines */
349#define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
350#define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
351#define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
352#define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
353
354/* FPE defines */
355#define FPE_EVENT_UNKNOWN 0
356#define FPE_EVENT_TRSP BIT(0)
357#define FPE_EVENT_TVER BIT(1)
358#define FPE_EVENT_RRSP BIT(2)
359#define FPE_EVENT_RVER BIT(3)
360
361#define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
362
363/* Physical Coding Sublayer */
364struct rgmii_adv {
365 unsigned int pause;
366 unsigned int duplex;
367 unsigned int lp_pause;
368 unsigned int lp_duplex;
369};
370
371#define STMMAC_PCS_PAUSE 1
372#define STMMAC_PCS_ASYM_PAUSE 2
373
374/* DMA HW capabilities */
375struct dma_features {
376 unsigned int mbps_10_100;
377 unsigned int mbps_1000;
378 unsigned int half_duplex;
379 unsigned int hash_filter;
380 unsigned int multi_addr;
381 unsigned int pcs;
382 unsigned int sma_mdio;
383 unsigned int pmt_remote_wake_up;
384 unsigned int pmt_magic_frame;
385 unsigned int rmon;
386 /* IEEE 1588-2002 */
387 unsigned int time_stamp;
388 /* IEEE 1588-2008 */
389 unsigned int atime_stamp;
390 /* 802.3az - Energy-Efficient Ethernet (EEE) */
391 unsigned int eee;
392 unsigned int av;
393 unsigned int hash_tb_sz;
394 unsigned int tsoen;
395 /* TX and RX csum */
396 unsigned int tx_coe;
397 unsigned int rx_coe;
398 unsigned int rx_coe_type1;
399 unsigned int rx_coe_type2;
400 unsigned int rxfifo_over_2048;
401 /* TX and RX number of channels */
402 unsigned int number_rx_channel;
403 unsigned int number_tx_channel;
404 /* TX and RX number of queues */
405 unsigned int number_rx_queues;
406 unsigned int number_tx_queues;
407 /* PPS output */
408 unsigned int pps_out_num;
409 /* Alternate (enhanced) DESC mode */
410 unsigned int enh_desc;
411 /* TX and RX FIFO sizes */
412 unsigned int tx_fifo_size;
413 unsigned int rx_fifo_size;
414 /* Automotive Safety Package */
415 unsigned int asp;
416 /* RX Parser */
417 unsigned int frpsel;
418 unsigned int frpbs;
419 unsigned int frpes;
420 unsigned int addr64;
421 unsigned int rssen;
422 unsigned int vlhash;
423 unsigned int sphen;
424 unsigned int vlins;
425 unsigned int dvlan;
426 unsigned int l3l4fnum;
427 unsigned int arpoffsel;
428 /* TSN Features */
429 unsigned int estwid;
430 unsigned int estdep;
431 unsigned int estsel;
432 unsigned int fpesel;
433 unsigned int tbssel;
434 /* Numbers of Auxiliary Snapshot Inputs */
435 unsigned int aux_snapshot_n;
436};
437
438/* RX Buffer size must be multiple of 4/8/16 bytes */
439#define BUF_SIZE_16KiB 16368
440#define BUF_SIZE_8KiB 8188
441#define BUF_SIZE_4KiB 4096
442#define BUF_SIZE_2KiB 2048
443
444/* Power Down and WOL */
445#define PMT_NOT_SUPPORTED 0
446#define PMT_SUPPORTED 1
447
448/* Common MAC defines */
449#define MAC_CTRL_REG 0x00000000 /* MAC Control */
450#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
451#define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
452
453/* Default LPI timers */
454#define STMMAC_DEFAULT_LIT_LS 0x3E8
455#define STMMAC_DEFAULT_TWT_LS 0x1E
456#define STMMAC_ET_MAX 0xFFFFF
457
458#define STMMAC_CHAIN_MODE 0x1
459#define STMMAC_RING_MODE 0x2
460
461#define JUMBO_LEN 9000
462
463/* Receive Side Scaling */
464#define STMMAC_RSS_HASH_KEY_SIZE 40
465#define STMMAC_RSS_MAX_TABLE_SIZE 256
466
467/* VLAN */
468#define STMMAC_VLAN_NONE 0x0
469#define STMMAC_VLAN_REMOVE 0x1
470#define STMMAC_VLAN_INSERT 0x2
471#define STMMAC_VLAN_REPLACE 0x3
472
473extern const struct stmmac_desc_ops enh_desc_ops;
474extern const struct stmmac_desc_ops ndesc_ops;
475
476struct mac_device_info;
477
478extern const struct stmmac_hwtimestamp stmmac_ptp;
479extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
480
481struct mac_link {
482 u32 speed_mask;
483 u32 speed10;
484 u32 speed100;
485 u32 speed1000;
486 u32 speed2500;
487 u32 duplex;
488 struct {
489 u32 speed2500;
490 u32 speed5000;
491 u32 speed10000;
492 } xgmii;
493 struct {
494 u32 speed25000;
495 u32 speed40000;
496 u32 speed50000;
497 u32 speed100000;
498 } xlgmii;
499};
500
501struct mii_regs {
502 unsigned int addr; /* MII Address */
503 unsigned int data; /* MII Data */
504 unsigned int addr_shift; /* MII address shift */
505 unsigned int reg_shift; /* MII reg shift */
506 unsigned int addr_mask; /* MII address mask */
507 unsigned int reg_mask; /* MII reg mask */
508 unsigned int clk_csr_shift;
509 unsigned int clk_csr_mask;
510};
511
512struct mac_device_info {
513 const struct stmmac_ops *mac;
514 const struct stmmac_desc_ops *desc;
515 const struct stmmac_dma_ops *dma;
516 const struct stmmac_mode_ops *mode;
517 const struct stmmac_hwtimestamp *ptp;
518 const struct stmmac_tc_ops *tc;
519 const struct stmmac_mmc_ops *mmc;
520 struct dw_xpcs *xpcs;
521 struct mii_regs mii; /* MII register Addresses */
522 struct mac_link link;
523 void __iomem *pcsr; /* vpointer to device CSRs */
524 unsigned int multicast_filter_bins;
525 unsigned int unicast_filter_entries;
526 unsigned int mcast_bits_log2;
527 unsigned int rx_csum;
528 unsigned int pcs;
529 unsigned int pmt;
530 unsigned int ps;
531 unsigned int xlgmac;
532 unsigned int num_vlan;
533 u32 vlan_filter[32];
534 unsigned int promisc;
535 bool vlan_fail_q_en;
536 u8 vlan_fail_q;
537};
538
539struct stmmac_rx_routing {
540 u32 reg_mask;
541 u32 reg_shift;
542};
543
544int dwmac100_setup(struct stmmac_priv *priv);
545int dwmac1000_setup(struct stmmac_priv *priv);
546int dwmac4_setup(struct stmmac_priv *priv);
547int dwxgmac2_setup(struct stmmac_priv *priv);
548int dwxlgmac2_setup(struct stmmac_priv *priv);
549
550void stmmac_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
551 unsigned int high, unsigned int low);
552void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
553 unsigned int high, unsigned int low);
554void stmmac_set_mac(void __iomem *ioaddr, bool enable);
555
556void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, const u8 addr[6],
557 unsigned int high, unsigned int low);
558void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
559 unsigned int high, unsigned int low);
560void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
561
562void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
563
564extern const struct stmmac_mode_ops ring_mode_ops;
565extern const struct stmmac_mode_ops chain_mode_ops;
566extern const struct stmmac_desc_ops dwmac4_desc_ops;
567
568#endif /* __COMMON_H__ */