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1/* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580
2 *
3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/pci.h>
21#include <linux/ptp_classify.h>
22
23#include "igb.h"
24
25#define INCVALUE_MASK 0x7fffffff
26#define ISGN 0x80000000
27
28/* The 82580 timesync updates the system timer every 8ns by 8ns,
29 * and this update value cannot be reprogrammed.
30 *
31 * Neither the 82576 nor the 82580 offer registers wide enough to hold
32 * nanoseconds time values for very long. For the 82580, SYSTIM always
33 * counts nanoseconds, but the upper 24 bits are not available. The
34 * frequency is adjusted by changing the 32 bit fractional nanoseconds
35 * register, TIMINCA.
36 *
37 * For the 82576, the SYSTIM register time unit is affect by the
38 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
39 * field are needed to provide the nominal 16 nanosecond period,
40 * leaving 19 bits for fractional nanoseconds.
41 *
42 * We scale the NIC clock cycle by a large factor so that relatively
43 * small clock corrections can be added or subtracted at each clock
44 * tick. The drawbacks of a large factor are a) that the clock
45 * register overflows more quickly (not such a big deal) and b) that
46 * the increment per tick has to fit into 24 bits. As a result we
47 * need to use a shift of 19 so we can fit a value of 16 into the
48 * TIMINCA register.
49 *
50 *
51 * SYSTIMH SYSTIML
52 * +--------------+ +---+---+------+
53 * 82576 | 32 | | 8 | 5 | 19 |
54 * +--------------+ +---+---+------+
55 * \________ 45 bits _______/ fract
56 *
57 * +----------+---+ +--------------+
58 * 82580 | 24 | 8 | | 32 |
59 * +----------+---+ +--------------+
60 * reserved \______ 40 bits _____/
61 *
62 *
63 * The 45 bit 82576 SYSTIM overflows every
64 * 2^45 * 10^-9 / 3600 = 9.77 hours.
65 *
66 * The 40 bit 82580 SYSTIM overflows every
67 * 2^40 * 10^-9 / 60 = 18.3 minutes.
68 */
69
70#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
71#define IGB_PTP_TX_TIMEOUT (HZ * 15)
72#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
73#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
74#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
75#define IGB_NBITS_82580 40
76
77static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
78
79/* SYSTIM read access for the 82576 */
80static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
81{
82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
83 struct e1000_hw *hw = &igb->hw;
84 u64 val;
85 u32 lo, hi;
86
87 lo = rd32(E1000_SYSTIML);
88 hi = rd32(E1000_SYSTIMH);
89
90 val = ((u64) hi) << 32;
91 val |= lo;
92
93 return val;
94}
95
96/* SYSTIM read access for the 82580 */
97static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
98{
99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
100 struct e1000_hw *hw = &igb->hw;
101 u32 lo, hi;
102 u64 val;
103
104 /* The timestamp latches on lowest register read. For the 82580
105 * the lowest register is SYSTIMR instead of SYSTIML. However we only
106 * need to provide nanosecond resolution, so we just ignore it.
107 */
108 rd32(E1000_SYSTIMR);
109 lo = rd32(E1000_SYSTIML);
110 hi = rd32(E1000_SYSTIMH);
111
112 val = ((u64) hi) << 32;
113 val |= lo;
114
115 return val;
116}
117
118/* SYSTIM read access for I210/I211 */
119static void igb_ptp_read_i210(struct igb_adapter *adapter,
120 struct timespec64 *ts)
121{
122 struct e1000_hw *hw = &adapter->hw;
123 u32 sec, nsec;
124
125 /* The timestamp latches on lowest register read. For I210/I211, the
126 * lowest register is SYSTIMR. Since we only need to provide nanosecond
127 * resolution, we can ignore it.
128 */
129 rd32(E1000_SYSTIMR);
130 nsec = rd32(E1000_SYSTIML);
131 sec = rd32(E1000_SYSTIMH);
132
133 ts->tv_sec = sec;
134 ts->tv_nsec = nsec;
135}
136
137static void igb_ptp_write_i210(struct igb_adapter *adapter,
138 const struct timespec64 *ts)
139{
140 struct e1000_hw *hw = &adapter->hw;
141
142 /* Writing the SYSTIMR register is not necessary as it only provides
143 * sub-nanosecond resolution.
144 */
145 wr32(E1000_SYSTIML, ts->tv_nsec);
146 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
147}
148
149/**
150 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
151 * @adapter: board private structure
152 * @hwtstamps: timestamp structure to update
153 * @systim: unsigned 64bit system time value.
154 *
155 * We need to convert the system time value stored in the RX/TXSTMP registers
156 * into a hwtstamp which can be used by the upper level timestamping functions.
157 *
158 * The 'tmreg_lock' spinlock is used to protect the consistency of the
159 * system time value. This is needed because reading the 64 bit time
160 * value involves reading two (or three) 32 bit registers. The first
161 * read latches the value. Ditto for writing.
162 *
163 * In addition, here have extended the system time with an overflow
164 * counter in software.
165 **/
166static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
167 struct skb_shared_hwtstamps *hwtstamps,
168 u64 systim)
169{
170 unsigned long flags;
171 u64 ns;
172
173 switch (adapter->hw.mac.type) {
174 case e1000_82576:
175 case e1000_82580:
176 case e1000_i354:
177 case e1000_i350:
178 spin_lock_irqsave(&adapter->tmreg_lock, flags);
179
180 ns = timecounter_cyc2time(&adapter->tc, systim);
181
182 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
183
184 memset(hwtstamps, 0, sizeof(*hwtstamps));
185 hwtstamps->hwtstamp = ns_to_ktime(ns);
186 break;
187 case e1000_i210:
188 case e1000_i211:
189 memset(hwtstamps, 0, sizeof(*hwtstamps));
190 /* Upper 32 bits contain s, lower 32 bits contain ns. */
191 hwtstamps->hwtstamp = ktime_set(systim >> 32,
192 systim & 0xFFFFFFFF);
193 break;
194 default:
195 break;
196 }
197}
198
199/* PTP clock operations */
200static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
201{
202 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
203 ptp_caps);
204 struct e1000_hw *hw = &igb->hw;
205 int neg_adj = 0;
206 u64 rate;
207 u32 incvalue;
208
209 if (ppb < 0) {
210 neg_adj = 1;
211 ppb = -ppb;
212 }
213 rate = ppb;
214 rate <<= 14;
215 rate = div_u64(rate, 1953125);
216
217 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
218
219 if (neg_adj)
220 incvalue -= rate;
221 else
222 incvalue += rate;
223
224 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
225
226 return 0;
227}
228
229static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
230{
231 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
232 ptp_caps);
233 struct e1000_hw *hw = &igb->hw;
234 int neg_adj = 0;
235 u64 rate;
236 u32 inca;
237
238 if (ppb < 0) {
239 neg_adj = 1;
240 ppb = -ppb;
241 }
242 rate = ppb;
243 rate <<= 26;
244 rate = div_u64(rate, 1953125);
245
246 inca = rate & INCVALUE_MASK;
247 if (neg_adj)
248 inca |= ISGN;
249
250 wr32(E1000_TIMINCA, inca);
251
252 return 0;
253}
254
255static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
256{
257 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
258 ptp_caps);
259 unsigned long flags;
260
261 spin_lock_irqsave(&igb->tmreg_lock, flags);
262 timecounter_adjtime(&igb->tc, delta);
263 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
264
265 return 0;
266}
267
268static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
269{
270 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
271 ptp_caps);
272 unsigned long flags;
273 struct timespec64 now, then = ns_to_timespec64(delta);
274
275 spin_lock_irqsave(&igb->tmreg_lock, flags);
276
277 igb_ptp_read_i210(igb, &now);
278 now = timespec64_add(now, then);
279 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
280
281 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
282
283 return 0;
284}
285
286static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
287 struct timespec64 *ts)
288{
289 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
290 ptp_caps);
291 unsigned long flags;
292 u64 ns;
293
294 spin_lock_irqsave(&igb->tmreg_lock, flags);
295
296 ns = timecounter_read(&igb->tc);
297
298 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
299
300 *ts = ns_to_timespec64(ns);
301
302 return 0;
303}
304
305static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
306 struct timespec64 *ts)
307{
308 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
309 ptp_caps);
310 unsigned long flags;
311
312 spin_lock_irqsave(&igb->tmreg_lock, flags);
313
314 igb_ptp_read_i210(igb, ts);
315
316 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
317
318 return 0;
319}
320
321static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
322 const struct timespec64 *ts)
323{
324 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
325 ptp_caps);
326 unsigned long flags;
327 u64 ns;
328
329 ns = timespec64_to_ns(ts);
330
331 spin_lock_irqsave(&igb->tmreg_lock, flags);
332
333 timecounter_init(&igb->tc, &igb->cc, ns);
334
335 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
336
337 return 0;
338}
339
340static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
341 const struct timespec64 *ts)
342{
343 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
344 ptp_caps);
345 unsigned long flags;
346
347 spin_lock_irqsave(&igb->tmreg_lock, flags);
348
349 igb_ptp_write_i210(igb, ts);
350
351 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
352
353 return 0;
354}
355
356static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
357{
358 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
359 static const u32 mask[IGB_N_SDP] = {
360 E1000_CTRL_SDP0_DIR,
361 E1000_CTRL_SDP1_DIR,
362 E1000_CTRL_EXT_SDP2_DIR,
363 E1000_CTRL_EXT_SDP3_DIR,
364 };
365
366 if (input)
367 *ptr &= ~mask[pin];
368 else
369 *ptr |= mask[pin];
370}
371
372static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
373{
374 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
375 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
376 };
377 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
378 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
379 };
380 static const u32 ts_sdp_en[IGB_N_SDP] = {
381 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
382 };
383 struct e1000_hw *hw = &igb->hw;
384 u32 ctrl, ctrl_ext, tssdp = 0;
385
386 ctrl = rd32(E1000_CTRL);
387 ctrl_ext = rd32(E1000_CTRL_EXT);
388 tssdp = rd32(E1000_TSSDP);
389
390 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
391
392 /* Make sure this pin is not enabled as an output. */
393 tssdp &= ~ts_sdp_en[pin];
394
395 if (chan == 1) {
396 tssdp &= ~AUX1_SEL_SDP3;
397 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
398 } else {
399 tssdp &= ~AUX0_SEL_SDP3;
400 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
401 }
402
403 wr32(E1000_TSSDP, tssdp);
404 wr32(E1000_CTRL, ctrl);
405 wr32(E1000_CTRL_EXT, ctrl_ext);
406}
407
408static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
409{
410 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
411 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
412 };
413 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
414 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
415 };
416 static const u32 ts_sdp_en[IGB_N_SDP] = {
417 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
418 };
419 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
420 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
421 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
422 };
423 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
424 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
425 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
426 };
427 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
428 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
429 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
430 };
431 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
432 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
433 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
434 };
435 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
436 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
437 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
438 };
439 struct e1000_hw *hw = &igb->hw;
440 u32 ctrl, ctrl_ext, tssdp = 0;
441
442 ctrl = rd32(E1000_CTRL);
443 ctrl_ext = rd32(E1000_CTRL_EXT);
444 tssdp = rd32(E1000_TSSDP);
445
446 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
447
448 /* Make sure this pin is not enabled as an input. */
449 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
450 tssdp &= ~AUX0_TS_SDP_EN;
451
452 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
453 tssdp &= ~AUX1_TS_SDP_EN;
454
455 tssdp &= ~ts_sdp_sel_clr[pin];
456 if (freq) {
457 if (chan == 1)
458 tssdp |= ts_sdp_sel_fc1[pin];
459 else
460 tssdp |= ts_sdp_sel_fc0[pin];
461 } else {
462 if (chan == 1)
463 tssdp |= ts_sdp_sel_tt1[pin];
464 else
465 tssdp |= ts_sdp_sel_tt0[pin];
466 }
467 tssdp |= ts_sdp_en[pin];
468
469 wr32(E1000_TSSDP, tssdp);
470 wr32(E1000_CTRL, ctrl);
471 wr32(E1000_CTRL_EXT, ctrl_ext);
472}
473
474static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
475 struct ptp_clock_request *rq, int on)
476{
477 struct igb_adapter *igb =
478 container_of(ptp, struct igb_adapter, ptp_caps);
479 struct e1000_hw *hw = &igb->hw;
480 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
481 unsigned long flags;
482 struct timespec64 ts;
483 int use_freq = 0, pin = -1;
484 s64 ns;
485
486 switch (rq->type) {
487 case PTP_CLK_REQ_EXTTS:
488 if (on) {
489 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
490 rq->extts.index);
491 if (pin < 0)
492 return -EBUSY;
493 }
494 if (rq->extts.index == 1) {
495 tsauxc_mask = TSAUXC_EN_TS1;
496 tsim_mask = TSINTR_AUTT1;
497 } else {
498 tsauxc_mask = TSAUXC_EN_TS0;
499 tsim_mask = TSINTR_AUTT0;
500 }
501 spin_lock_irqsave(&igb->tmreg_lock, flags);
502 tsauxc = rd32(E1000_TSAUXC);
503 tsim = rd32(E1000_TSIM);
504 if (on) {
505 igb_pin_extts(igb, rq->extts.index, pin);
506 tsauxc |= tsauxc_mask;
507 tsim |= tsim_mask;
508 } else {
509 tsauxc &= ~tsauxc_mask;
510 tsim &= ~tsim_mask;
511 }
512 wr32(E1000_TSAUXC, tsauxc);
513 wr32(E1000_TSIM, tsim);
514 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
515 return 0;
516
517 case PTP_CLK_REQ_PEROUT:
518 if (on) {
519 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
520 rq->perout.index);
521 if (pin < 0)
522 return -EBUSY;
523 }
524 ts.tv_sec = rq->perout.period.sec;
525 ts.tv_nsec = rq->perout.period.nsec;
526 ns = timespec64_to_ns(&ts);
527 ns = ns >> 1;
528 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
529 (ns == 250000000LL) || (ns == 500000000LL))) {
530 if (ns < 8LL)
531 return -EINVAL;
532 use_freq = 1;
533 }
534 ts = ns_to_timespec64(ns);
535 if (rq->perout.index == 1) {
536 if (use_freq) {
537 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
538 tsim_mask = 0;
539 } else {
540 tsauxc_mask = TSAUXC_EN_TT1;
541 tsim_mask = TSINTR_TT1;
542 }
543 trgttiml = E1000_TRGTTIML1;
544 trgttimh = E1000_TRGTTIMH1;
545 freqout = E1000_FREQOUT1;
546 } else {
547 if (use_freq) {
548 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
549 tsim_mask = 0;
550 } else {
551 tsauxc_mask = TSAUXC_EN_TT0;
552 tsim_mask = TSINTR_TT0;
553 }
554 trgttiml = E1000_TRGTTIML0;
555 trgttimh = E1000_TRGTTIMH0;
556 freqout = E1000_FREQOUT0;
557 }
558 spin_lock_irqsave(&igb->tmreg_lock, flags);
559 tsauxc = rd32(E1000_TSAUXC);
560 tsim = rd32(E1000_TSIM);
561 if (rq->perout.index == 1) {
562 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
563 tsim &= ~TSINTR_TT1;
564 } else {
565 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
566 tsim &= ~TSINTR_TT0;
567 }
568 if (on) {
569 int i = rq->perout.index;
570 igb_pin_perout(igb, i, pin, use_freq);
571 igb->perout[i].start.tv_sec = rq->perout.start.sec;
572 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
573 igb->perout[i].period.tv_sec = ts.tv_sec;
574 igb->perout[i].period.tv_nsec = ts.tv_nsec;
575 wr32(trgttimh, rq->perout.start.sec);
576 wr32(trgttiml, rq->perout.start.nsec);
577 if (use_freq)
578 wr32(freqout, ns);
579 tsauxc |= tsauxc_mask;
580 tsim |= tsim_mask;
581 }
582 wr32(E1000_TSAUXC, tsauxc);
583 wr32(E1000_TSIM, tsim);
584 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
585 return 0;
586
587 case PTP_CLK_REQ_PPS:
588 spin_lock_irqsave(&igb->tmreg_lock, flags);
589 tsim = rd32(E1000_TSIM);
590 if (on)
591 tsim |= TSINTR_SYS_WRAP;
592 else
593 tsim &= ~TSINTR_SYS_WRAP;
594 wr32(E1000_TSIM, tsim);
595 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
596 return 0;
597 }
598
599 return -EOPNOTSUPP;
600}
601
602static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
603 struct ptp_clock_request *rq, int on)
604{
605 return -EOPNOTSUPP;
606}
607
608static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
609 enum ptp_pin_function func, unsigned int chan)
610{
611 switch (func) {
612 case PTP_PF_NONE:
613 case PTP_PF_EXTTS:
614 case PTP_PF_PEROUT:
615 break;
616 case PTP_PF_PHYSYNC:
617 return -1;
618 }
619 return 0;
620}
621
622/**
623 * igb_ptp_tx_work
624 * @work: pointer to work struct
625 *
626 * This work function polls the TSYNCTXCTL valid bit to determine when a
627 * timestamp has been taken for the current stored skb.
628 **/
629static void igb_ptp_tx_work(struct work_struct *work)
630{
631 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
632 ptp_tx_work);
633 struct e1000_hw *hw = &adapter->hw;
634 u32 tsynctxctl;
635
636 if (!adapter->ptp_tx_skb)
637 return;
638
639 if (time_is_before_jiffies(adapter->ptp_tx_start +
640 IGB_PTP_TX_TIMEOUT)) {
641 dev_kfree_skb_any(adapter->ptp_tx_skb);
642 adapter->ptp_tx_skb = NULL;
643 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
644 adapter->tx_hwtstamp_timeouts++;
645 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
646 return;
647 }
648
649 tsynctxctl = rd32(E1000_TSYNCTXCTL);
650 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
651 igb_ptp_tx_hwtstamp(adapter);
652 else
653 /* reschedule to check later */
654 schedule_work(&adapter->ptp_tx_work);
655}
656
657static void igb_ptp_overflow_check(struct work_struct *work)
658{
659 struct igb_adapter *igb =
660 container_of(work, struct igb_adapter, ptp_overflow_work.work);
661 struct timespec64 ts;
662
663 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
664
665 pr_debug("igb overflow check at %lld.%09lu\n",
666 (long long) ts.tv_sec, ts.tv_nsec);
667
668 schedule_delayed_work(&igb->ptp_overflow_work,
669 IGB_SYSTIM_OVERFLOW_PERIOD);
670}
671
672/**
673 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
674 * @adapter: private network adapter structure
675 *
676 * This watchdog task is scheduled to detect error case where hardware has
677 * dropped an Rx packet that was timestamped when the ring is full. The
678 * particular error is rare but leaves the device in a state unable to timestamp
679 * any future packets.
680 **/
681void igb_ptp_rx_hang(struct igb_adapter *adapter)
682{
683 struct e1000_hw *hw = &adapter->hw;
684 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
685 unsigned long rx_event;
686
687 if (hw->mac.type != e1000_82576)
688 return;
689
690 /* If we don't have a valid timestamp in the registers, just update the
691 * timeout counter and exit
692 */
693 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
694 adapter->last_rx_ptp_check = jiffies;
695 return;
696 }
697
698 /* Determine the most recent watchdog or rx_timestamp event */
699 rx_event = adapter->last_rx_ptp_check;
700 if (time_after(adapter->last_rx_timestamp, rx_event))
701 rx_event = adapter->last_rx_timestamp;
702
703 /* Only need to read the high RXSTMP register to clear the lock */
704 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
705 rd32(E1000_RXSTMPH);
706 adapter->last_rx_ptp_check = jiffies;
707 adapter->rx_hwtstamp_cleared++;
708 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
709 }
710}
711
712/**
713 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
714 * @adapter: Board private structure.
715 *
716 * If we were asked to do hardware stamping and such a time stamp is
717 * available, then it must have been for this skb here because we only
718 * allow only one such packet into the queue.
719 **/
720static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
721{
722 struct e1000_hw *hw = &adapter->hw;
723 struct skb_shared_hwtstamps shhwtstamps;
724 u64 regval;
725
726 regval = rd32(E1000_TXSTMPL);
727 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
728
729 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
730 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
731 dev_kfree_skb_any(adapter->ptp_tx_skb);
732 adapter->ptp_tx_skb = NULL;
733 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
734}
735
736/**
737 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
738 * @q_vector: Pointer to interrupt specific structure
739 * @va: Pointer to address containing Rx buffer
740 * @skb: Buffer containing timestamp and packet
741 *
742 * This function is meant to retrieve a timestamp from the first buffer of an
743 * incoming frame. The value is stored in little endian format starting on
744 * byte 8.
745 **/
746void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
747 unsigned char *va,
748 struct sk_buff *skb)
749{
750 __le64 *regval = (__le64 *)va;
751
752 /* The timestamp is recorded in little endian format.
753 * DWORD: 0 1 2 3
754 * Field: Reserved Reserved SYSTIML SYSTIMH
755 */
756 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
757 le64_to_cpu(regval[1]));
758}
759
760/**
761 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
762 * @q_vector: Pointer to interrupt specific structure
763 * @skb: Buffer containing timestamp and packet
764 *
765 * This function is meant to retrieve a timestamp from the internal registers
766 * of the adapter and store it in the skb.
767 **/
768void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
769 struct sk_buff *skb)
770{
771 struct igb_adapter *adapter = q_vector->adapter;
772 struct e1000_hw *hw = &adapter->hw;
773 u64 regval;
774
775 /* If this bit is set, then the RX registers contain the time stamp. No
776 * other packet will be time stamped until we read these registers, so
777 * read the registers to make them available again. Because only one
778 * packet can be time stamped at a time, we know that the register
779 * values must belong to this one here and therefore we don't need to
780 * compare any of the additional attributes stored for it.
781 *
782 * If nothing went wrong, then it should have a shared tx_flags that we
783 * can turn into a skb_shared_hwtstamps.
784 */
785 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
786 return;
787
788 regval = rd32(E1000_RXSTMPL);
789 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
790
791 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
792
793 /* Update the last_rx_timestamp timer in order to enable watchdog check
794 * for error case of latched timestamp on a dropped packet.
795 */
796 adapter->last_rx_timestamp = jiffies;
797}
798
799/**
800 * igb_ptp_get_ts_config - get hardware time stamping config
801 * @netdev:
802 * @ifreq:
803 *
804 * Get the hwtstamp_config settings to return to the user. Rather than attempt
805 * to deconstruct the settings from the registers, just return a shadow copy
806 * of the last known settings.
807 **/
808int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
809{
810 struct igb_adapter *adapter = netdev_priv(netdev);
811 struct hwtstamp_config *config = &adapter->tstamp_config;
812
813 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
814 -EFAULT : 0;
815}
816
817/**
818 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
819 * @adapter: networking device structure
820 * @config: hwtstamp configuration
821 *
822 * Outgoing time stamping can be enabled and disabled. Play nice and
823 * disable it when requested, although it shouldn't case any overhead
824 * when no packet needs it. At most one packet in the queue may be
825 * marked for time stamping, otherwise it would be impossible to tell
826 * for sure to which packet the hardware time stamp belongs.
827 *
828 * Incoming time stamping has to be configured via the hardware
829 * filters. Not all combinations are supported, in particular event
830 * type has to be specified. Matching the kind of event packet is
831 * not supported, with the exception of "all V2 events regardless of
832 * level 2 or 4".
833 */
834static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
835 struct hwtstamp_config *config)
836{
837 struct e1000_hw *hw = &adapter->hw;
838 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
839 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
840 u32 tsync_rx_cfg = 0;
841 bool is_l4 = false;
842 bool is_l2 = false;
843 u32 regval;
844
845 /* reserved for future extensions */
846 if (config->flags)
847 return -EINVAL;
848
849 switch (config->tx_type) {
850 case HWTSTAMP_TX_OFF:
851 tsync_tx_ctl = 0;
852 case HWTSTAMP_TX_ON:
853 break;
854 default:
855 return -ERANGE;
856 }
857
858 switch (config->rx_filter) {
859 case HWTSTAMP_FILTER_NONE:
860 tsync_rx_ctl = 0;
861 break;
862 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
863 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
864 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
865 is_l4 = true;
866 break;
867 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
868 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
869 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
870 is_l4 = true;
871 break;
872 case HWTSTAMP_FILTER_PTP_V2_EVENT:
873 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
874 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
875 case HWTSTAMP_FILTER_PTP_V2_SYNC:
876 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
877 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
878 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
879 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
880 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
881 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
882 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
883 is_l2 = true;
884 is_l4 = true;
885 break;
886 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
887 case HWTSTAMP_FILTER_ALL:
888 /* 82576 cannot timestamp all packets, which it needs to do to
889 * support both V1 Sync and Delay_Req messages
890 */
891 if (hw->mac.type != e1000_82576) {
892 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
893 config->rx_filter = HWTSTAMP_FILTER_ALL;
894 break;
895 }
896 /* fall through */
897 default:
898 config->rx_filter = HWTSTAMP_FILTER_NONE;
899 return -ERANGE;
900 }
901
902 if (hw->mac.type == e1000_82575) {
903 if (tsync_rx_ctl | tsync_tx_ctl)
904 return -EINVAL;
905 return 0;
906 }
907
908 /* Per-packet timestamping only works if all packets are
909 * timestamped, so enable timestamping in all packets as
910 * long as one Rx filter was configured.
911 */
912 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
913 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
914 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
915 config->rx_filter = HWTSTAMP_FILTER_ALL;
916 is_l2 = true;
917 is_l4 = true;
918
919 if ((hw->mac.type == e1000_i210) ||
920 (hw->mac.type == e1000_i211)) {
921 regval = rd32(E1000_RXPBS);
922 regval |= E1000_RXPBS_CFG_TS_EN;
923 wr32(E1000_RXPBS, regval);
924 }
925 }
926
927 /* enable/disable TX */
928 regval = rd32(E1000_TSYNCTXCTL);
929 regval &= ~E1000_TSYNCTXCTL_ENABLED;
930 regval |= tsync_tx_ctl;
931 wr32(E1000_TSYNCTXCTL, regval);
932
933 /* enable/disable RX */
934 regval = rd32(E1000_TSYNCRXCTL);
935 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
936 regval |= tsync_rx_ctl;
937 wr32(E1000_TSYNCRXCTL, regval);
938
939 /* define which PTP packets are time stamped */
940 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
941
942 /* define ethertype filter for timestamped packets */
943 if (is_l2)
944 wr32(E1000_ETQF(3),
945 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
946 E1000_ETQF_1588 | /* enable timestamping */
947 ETH_P_1588)); /* 1588 eth protocol type */
948 else
949 wr32(E1000_ETQF(3), 0);
950
951 /* L4 Queue Filter[3]: filter by destination port and protocol */
952 if (is_l4) {
953 u32 ftqf = (IPPROTO_UDP /* UDP */
954 | E1000_FTQF_VF_BP /* VF not compared */
955 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
956 | E1000_FTQF_MASK); /* mask all inputs */
957 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
958
959 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
960 wr32(E1000_IMIREXT(3),
961 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
962 if (hw->mac.type == e1000_82576) {
963 /* enable source port check */
964 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
965 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
966 }
967 wr32(E1000_FTQF(3), ftqf);
968 } else {
969 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
970 }
971 wrfl();
972
973 /* clear TX/RX time stamp registers, just to be sure */
974 regval = rd32(E1000_TXSTMPL);
975 regval = rd32(E1000_TXSTMPH);
976 regval = rd32(E1000_RXSTMPL);
977 regval = rd32(E1000_RXSTMPH);
978
979 return 0;
980}
981
982/**
983 * igb_ptp_set_ts_config - set hardware time stamping config
984 * @netdev:
985 * @ifreq:
986 *
987 **/
988int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
989{
990 struct igb_adapter *adapter = netdev_priv(netdev);
991 struct hwtstamp_config config;
992 int err;
993
994 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
995 return -EFAULT;
996
997 err = igb_ptp_set_timestamp_mode(adapter, &config);
998 if (err)
999 return err;
1000
1001 /* save these settings for future reference */
1002 memcpy(&adapter->tstamp_config, &config,
1003 sizeof(adapter->tstamp_config));
1004
1005 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1006 -EFAULT : 0;
1007}
1008
1009void igb_ptp_init(struct igb_adapter *adapter)
1010{
1011 struct e1000_hw *hw = &adapter->hw;
1012 struct net_device *netdev = adapter->netdev;
1013 int i;
1014
1015 switch (hw->mac.type) {
1016 case e1000_82576:
1017 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1018 adapter->ptp_caps.owner = THIS_MODULE;
1019 adapter->ptp_caps.max_adj = 999999881;
1020 adapter->ptp_caps.n_ext_ts = 0;
1021 adapter->ptp_caps.pps = 0;
1022 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1023 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1024 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1025 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1026 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1027 adapter->cc.read = igb_ptp_read_82576;
1028 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1029 adapter->cc.mult = 1;
1030 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1031 /* Dial the nominal frequency. */
1032 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1033 break;
1034 case e1000_82580:
1035 case e1000_i354:
1036 case e1000_i350:
1037 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1038 adapter->ptp_caps.owner = THIS_MODULE;
1039 adapter->ptp_caps.max_adj = 62499999;
1040 adapter->ptp_caps.n_ext_ts = 0;
1041 adapter->ptp_caps.pps = 0;
1042 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1043 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1044 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1045 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1046 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1047 adapter->cc.read = igb_ptp_read_82580;
1048 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1049 adapter->cc.mult = 1;
1050 adapter->cc.shift = 0;
1051 /* Enable the timer functions by clearing bit 31. */
1052 wr32(E1000_TSAUXC, 0x0);
1053 break;
1054 case e1000_i210:
1055 case e1000_i211:
1056 for (i = 0; i < IGB_N_SDP; i++) {
1057 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1058
1059 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1060 ppd->index = i;
1061 ppd->func = PTP_PF_NONE;
1062 }
1063 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1064 adapter->ptp_caps.owner = THIS_MODULE;
1065 adapter->ptp_caps.max_adj = 62499999;
1066 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1067 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1068 adapter->ptp_caps.n_pins = IGB_N_SDP;
1069 adapter->ptp_caps.pps = 1;
1070 adapter->ptp_caps.pin_config = adapter->sdp_config;
1071 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1072 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1073 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1074 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1075 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1076 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1077 /* Enable the timer functions by clearing bit 31. */
1078 wr32(E1000_TSAUXC, 0x0);
1079 break;
1080 default:
1081 adapter->ptp_clock = NULL;
1082 return;
1083 }
1084
1085 wrfl();
1086
1087 spin_lock_init(&adapter->tmreg_lock);
1088 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1089
1090 /* Initialize the clock and overflow work for devices that need it. */
1091 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1092 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1093
1094 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
1095 } else {
1096 timecounter_init(&adapter->tc, &adapter->cc,
1097 ktime_to_ns(ktime_get_real()));
1098
1099 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1100 igb_ptp_overflow_check);
1101
1102 schedule_delayed_work(&adapter->ptp_overflow_work,
1103 IGB_SYSTIM_OVERFLOW_PERIOD);
1104 }
1105
1106 /* Initialize the time sync interrupts for devices that support it. */
1107 if (hw->mac.type >= e1000_82580) {
1108 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1109 wr32(E1000_IMS, E1000_IMS_TS);
1110 }
1111
1112 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1113 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1114
1115 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1116 &adapter->pdev->dev);
1117 if (IS_ERR(adapter->ptp_clock)) {
1118 adapter->ptp_clock = NULL;
1119 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1120 } else {
1121 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1122 adapter->netdev->name);
1123 adapter->flags |= IGB_FLAG_PTP;
1124 }
1125}
1126
1127/**
1128 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1129 * @adapter: Board private structure.
1130 *
1131 * This function stops the PTP support and cancels the delayed work.
1132 **/
1133void igb_ptp_stop(struct igb_adapter *adapter)
1134{
1135 switch (adapter->hw.mac.type) {
1136 case e1000_82576:
1137 case e1000_82580:
1138 case e1000_i354:
1139 case e1000_i350:
1140 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1141 break;
1142 case e1000_i210:
1143 case e1000_i211:
1144 /* No delayed work to cancel. */
1145 break;
1146 default:
1147 return;
1148 }
1149
1150 cancel_work_sync(&adapter->ptp_tx_work);
1151 if (adapter->ptp_tx_skb) {
1152 dev_kfree_skb_any(adapter->ptp_tx_skb);
1153 adapter->ptp_tx_skb = NULL;
1154 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1155 }
1156
1157 if (adapter->ptp_clock) {
1158 ptp_clock_unregister(adapter->ptp_clock);
1159 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1160 adapter->netdev->name);
1161 adapter->flags &= ~IGB_FLAG_PTP;
1162 }
1163}
1164
1165/**
1166 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1167 * @adapter: Board private structure.
1168 *
1169 * This function handles the reset work required to re-enable the PTP device.
1170 **/
1171void igb_ptp_reset(struct igb_adapter *adapter)
1172{
1173 struct e1000_hw *hw = &adapter->hw;
1174 unsigned long flags;
1175
1176 if (!(adapter->flags & IGB_FLAG_PTP))
1177 return;
1178
1179 /* reset the tstamp_config */
1180 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1181
1182 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1183
1184 switch (adapter->hw.mac.type) {
1185 case e1000_82576:
1186 /* Dial the nominal frequency. */
1187 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1188 break;
1189 case e1000_82580:
1190 case e1000_i354:
1191 case e1000_i350:
1192 case e1000_i210:
1193 case e1000_i211:
1194 wr32(E1000_TSAUXC, 0x0);
1195 wr32(E1000_TSSDP, 0x0);
1196 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1197 wr32(E1000_IMS, E1000_IMS_TS);
1198 break;
1199 default:
1200 /* No work to do. */
1201 goto out;
1202 }
1203
1204 /* Re-initialize the timer. */
1205 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1206 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1207
1208 igb_ptp_write_i210(adapter, &ts);
1209 } else {
1210 timecounter_init(&adapter->tc, &adapter->cc,
1211 ktime_to_ns(ktime_get_real()));
1212 }
1213out:
1214 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1215}
1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */
3
4#include <linux/module.h>
5#include <linux/device.h>
6#include <linux/pci.h>
7#include <linux/ptp_classify.h>
8
9#include "igb.h"
10
11#define INCVALUE_MASK 0x7fffffff
12#define ISGN 0x80000000
13
14/* The 82580 timesync updates the system timer every 8ns by 8ns,
15 * and this update value cannot be reprogrammed.
16 *
17 * Neither the 82576 nor the 82580 offer registers wide enough to hold
18 * nanoseconds time values for very long. For the 82580, SYSTIM always
19 * counts nanoseconds, but the upper 24 bits are not available. The
20 * frequency is adjusted by changing the 32 bit fractional nanoseconds
21 * register, TIMINCA.
22 *
23 * For the 82576, the SYSTIM register time unit is affect by the
24 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
25 * field are needed to provide the nominal 16 nanosecond period,
26 * leaving 19 bits for fractional nanoseconds.
27 *
28 * We scale the NIC clock cycle by a large factor so that relatively
29 * small clock corrections can be added or subtracted at each clock
30 * tick. The drawbacks of a large factor are a) that the clock
31 * register overflows more quickly (not such a big deal) and b) that
32 * the increment per tick has to fit into 24 bits. As a result we
33 * need to use a shift of 19 so we can fit a value of 16 into the
34 * TIMINCA register.
35 *
36 *
37 * SYSTIMH SYSTIML
38 * +--------------+ +---+---+------+
39 * 82576 | 32 | | 8 | 5 | 19 |
40 * +--------------+ +---+---+------+
41 * \________ 45 bits _______/ fract
42 *
43 * +----------+---+ +--------------+
44 * 82580 | 24 | 8 | | 32 |
45 * +----------+---+ +--------------+
46 * reserved \______ 40 bits _____/
47 *
48 *
49 * The 45 bit 82576 SYSTIM overflows every
50 * 2^45 * 10^-9 / 3600 = 9.77 hours.
51 *
52 * The 40 bit 82580 SYSTIM overflows every
53 * 2^40 * 10^-9 / 60 = 18.3 minutes.
54 *
55 * SYSTIM is converted to real time using a timecounter. As
56 * timecounter_cyc2time() allows old timestamps, the timecounter needs
57 * to be updated at least once per half of the SYSTIM interval.
58 * Scheduling of delayed work is not very accurate, and also the NIC
59 * clock can be adjusted to run up to 6% faster and the system clock
60 * up to 10% slower, so we aim for 6 minutes to be sure the actual
61 * interval in the NIC time is shorter than 9.16 minutes.
62 */
63
64#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 6)
65#define IGB_PTP_TX_TIMEOUT (HZ * 15)
66#define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
67#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
68#define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
69#define IGB_NBITS_82580 40
70
71static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
72static void igb_ptp_sdp_init(struct igb_adapter *adapter);
73
74/* SYSTIM read access for the 82576 */
75static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
76{
77 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
78 struct e1000_hw *hw = &igb->hw;
79 u64 val;
80 u32 lo, hi;
81
82 lo = rd32(E1000_SYSTIML);
83 hi = rd32(E1000_SYSTIMH);
84
85 val = ((u64) hi) << 32;
86 val |= lo;
87
88 return val;
89}
90
91/* SYSTIM read access for the 82580 */
92static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
93{
94 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
95 struct e1000_hw *hw = &igb->hw;
96 u32 lo, hi;
97 u64 val;
98
99 /* The timestamp latches on lowest register read. For the 82580
100 * the lowest register is SYSTIMR instead of SYSTIML. However we only
101 * need to provide nanosecond resolution, so we just ignore it.
102 */
103 rd32(E1000_SYSTIMR);
104 lo = rd32(E1000_SYSTIML);
105 hi = rd32(E1000_SYSTIMH);
106
107 val = ((u64) hi) << 32;
108 val |= lo;
109
110 return val;
111}
112
113/* SYSTIM read access for I210/I211 */
114static void igb_ptp_read_i210(struct igb_adapter *adapter,
115 struct timespec64 *ts)
116{
117 struct e1000_hw *hw = &adapter->hw;
118 u32 sec, nsec;
119
120 /* The timestamp latches on lowest register read. For I210/I211, the
121 * lowest register is SYSTIMR. Since we only need to provide nanosecond
122 * resolution, we can ignore it.
123 */
124 rd32(E1000_SYSTIMR);
125 nsec = rd32(E1000_SYSTIML);
126 sec = rd32(E1000_SYSTIMH);
127
128 ts->tv_sec = sec;
129 ts->tv_nsec = nsec;
130}
131
132static void igb_ptp_write_i210(struct igb_adapter *adapter,
133 const struct timespec64 *ts)
134{
135 struct e1000_hw *hw = &adapter->hw;
136
137 /* Writing the SYSTIMR register is not necessary as it only provides
138 * sub-nanosecond resolution.
139 */
140 wr32(E1000_SYSTIML, ts->tv_nsec);
141 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
142}
143
144/**
145 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
146 * @adapter: board private structure
147 * @hwtstamps: timestamp structure to update
148 * @systim: unsigned 64bit system time value.
149 *
150 * We need to convert the system time value stored in the RX/TXSTMP registers
151 * into a hwtstamp which can be used by the upper level timestamping functions.
152 *
153 * The 'tmreg_lock' spinlock is used to protect the consistency of the
154 * system time value. This is needed because reading the 64 bit time
155 * value involves reading two (or three) 32 bit registers. The first
156 * read latches the value. Ditto for writing.
157 *
158 * In addition, here have extended the system time with an overflow
159 * counter in software.
160 **/
161static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
162 struct skb_shared_hwtstamps *hwtstamps,
163 u64 systim)
164{
165 unsigned long flags;
166 u64 ns;
167
168 memset(hwtstamps, 0, sizeof(*hwtstamps));
169
170 switch (adapter->hw.mac.type) {
171 case e1000_82576:
172 case e1000_82580:
173 case e1000_i354:
174 case e1000_i350:
175 spin_lock_irqsave(&adapter->tmreg_lock, flags);
176 ns = timecounter_cyc2time(&adapter->tc, systim);
177 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
178
179 hwtstamps->hwtstamp = ns_to_ktime(ns);
180 break;
181 case e1000_i210:
182 case e1000_i211:
183 /* Upper 32 bits contain s, lower 32 bits contain ns. */
184 hwtstamps->hwtstamp = ktime_set(systim >> 32,
185 systim & 0xFFFFFFFF);
186 break;
187 default:
188 break;
189 }
190}
191
192/* PTP clock operations */
193static int igb_ptp_adjfine_82576(struct ptp_clock_info *ptp, long scaled_ppm)
194{
195 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
196 ptp_caps);
197 struct e1000_hw *hw = &igb->hw;
198 u64 incvalue;
199
200 incvalue = adjust_by_scaled_ppm(INCVALUE_82576, scaled_ppm);
201
202 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
203
204 return 0;
205}
206
207static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
208{
209 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
210 ptp_caps);
211 struct e1000_hw *hw = &igb->hw;
212 int neg_adj = 0;
213 u64 rate;
214 u32 inca;
215
216 if (scaled_ppm < 0) {
217 neg_adj = 1;
218 scaled_ppm = -scaled_ppm;
219 }
220 rate = scaled_ppm;
221 rate <<= 13;
222 rate = div_u64(rate, 15625);
223
224 inca = rate & INCVALUE_MASK;
225 if (neg_adj)
226 inca |= ISGN;
227
228 wr32(E1000_TIMINCA, inca);
229
230 return 0;
231}
232
233static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
234{
235 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
236 ptp_caps);
237 unsigned long flags;
238
239 spin_lock_irqsave(&igb->tmreg_lock, flags);
240 timecounter_adjtime(&igb->tc, delta);
241 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
242
243 return 0;
244}
245
246static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
247{
248 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
249 ptp_caps);
250 unsigned long flags;
251 struct timespec64 now, then = ns_to_timespec64(delta);
252
253 spin_lock_irqsave(&igb->tmreg_lock, flags);
254
255 igb_ptp_read_i210(igb, &now);
256 now = timespec64_add(now, then);
257 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
258
259 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
260
261 return 0;
262}
263
264static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp,
265 struct timespec64 *ts,
266 struct ptp_system_timestamp *sts)
267{
268 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
269 ptp_caps);
270 struct e1000_hw *hw = &igb->hw;
271 unsigned long flags;
272 u32 lo, hi;
273 u64 ns;
274
275 spin_lock_irqsave(&igb->tmreg_lock, flags);
276
277 ptp_read_system_prets(sts);
278 lo = rd32(E1000_SYSTIML);
279 ptp_read_system_postts(sts);
280 hi = rd32(E1000_SYSTIMH);
281
282 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo);
283
284 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
285
286 *ts = ns_to_timespec64(ns);
287
288 return 0;
289}
290
291static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp,
292 struct timespec64 *ts,
293 struct ptp_system_timestamp *sts)
294{
295 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
296 ptp_caps);
297 struct e1000_hw *hw = &igb->hw;
298 unsigned long flags;
299 u32 lo, hi;
300 u64 ns;
301
302 spin_lock_irqsave(&igb->tmreg_lock, flags);
303
304 ptp_read_system_prets(sts);
305 rd32(E1000_SYSTIMR);
306 ptp_read_system_postts(sts);
307 lo = rd32(E1000_SYSTIML);
308 hi = rd32(E1000_SYSTIMH);
309
310 ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo);
311
312 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
313
314 *ts = ns_to_timespec64(ns);
315
316 return 0;
317}
318
319static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp,
320 struct timespec64 *ts,
321 struct ptp_system_timestamp *sts)
322{
323 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
324 ptp_caps);
325 struct e1000_hw *hw = &igb->hw;
326 unsigned long flags;
327
328 spin_lock_irqsave(&igb->tmreg_lock, flags);
329
330 ptp_read_system_prets(sts);
331 rd32(E1000_SYSTIMR);
332 ptp_read_system_postts(sts);
333 ts->tv_nsec = rd32(E1000_SYSTIML);
334 ts->tv_sec = rd32(E1000_SYSTIMH);
335
336 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
337
338 return 0;
339}
340
341static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
342 const struct timespec64 *ts)
343{
344 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
345 ptp_caps);
346 unsigned long flags;
347 u64 ns;
348
349 ns = timespec64_to_ns(ts);
350
351 spin_lock_irqsave(&igb->tmreg_lock, flags);
352
353 timecounter_init(&igb->tc, &igb->cc, ns);
354
355 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
356
357 return 0;
358}
359
360static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
361 const struct timespec64 *ts)
362{
363 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
364 ptp_caps);
365 unsigned long flags;
366
367 spin_lock_irqsave(&igb->tmreg_lock, flags);
368
369 igb_ptp_write_i210(igb, ts);
370
371 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
372
373 return 0;
374}
375
376static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
377{
378 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
379 static const u32 mask[IGB_N_SDP] = {
380 E1000_CTRL_SDP0_DIR,
381 E1000_CTRL_SDP1_DIR,
382 E1000_CTRL_EXT_SDP2_DIR,
383 E1000_CTRL_EXT_SDP3_DIR,
384 };
385
386 if (input)
387 *ptr &= ~mask[pin];
388 else
389 *ptr |= mask[pin];
390}
391
392static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
393{
394 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
395 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
396 };
397 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
398 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
399 };
400 static const u32 ts_sdp_en[IGB_N_SDP] = {
401 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
402 };
403 struct e1000_hw *hw = &igb->hw;
404 u32 ctrl, ctrl_ext, tssdp = 0;
405
406 ctrl = rd32(E1000_CTRL);
407 ctrl_ext = rd32(E1000_CTRL_EXT);
408 tssdp = rd32(E1000_TSSDP);
409
410 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
411
412 /* Make sure this pin is not enabled as an output. */
413 tssdp &= ~ts_sdp_en[pin];
414
415 if (chan == 1) {
416 tssdp &= ~AUX1_SEL_SDP3;
417 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
418 } else {
419 tssdp &= ~AUX0_SEL_SDP3;
420 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
421 }
422
423 wr32(E1000_TSSDP, tssdp);
424 wr32(E1000_CTRL, ctrl);
425 wr32(E1000_CTRL_EXT, ctrl_ext);
426}
427
428static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
429{
430 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
431 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
432 };
433 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
434 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
435 };
436 static const u32 ts_sdp_en[IGB_N_SDP] = {
437 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
438 };
439 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
440 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
441 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
442 };
443 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
444 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
445 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
446 };
447 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
448 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
449 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
450 };
451 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
452 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
453 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
454 };
455 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
456 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
457 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
458 };
459 struct e1000_hw *hw = &igb->hw;
460 u32 ctrl, ctrl_ext, tssdp = 0;
461
462 ctrl = rd32(E1000_CTRL);
463 ctrl_ext = rd32(E1000_CTRL_EXT);
464 tssdp = rd32(E1000_TSSDP);
465
466 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
467
468 /* Make sure this pin is not enabled as an input. */
469 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
470 tssdp &= ~AUX0_TS_SDP_EN;
471
472 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
473 tssdp &= ~AUX1_TS_SDP_EN;
474
475 tssdp &= ~ts_sdp_sel_clr[pin];
476 if (freq) {
477 if (chan == 1)
478 tssdp |= ts_sdp_sel_fc1[pin];
479 else
480 tssdp |= ts_sdp_sel_fc0[pin];
481 } else {
482 if (chan == 1)
483 tssdp |= ts_sdp_sel_tt1[pin];
484 else
485 tssdp |= ts_sdp_sel_tt0[pin];
486 }
487 tssdp |= ts_sdp_en[pin];
488
489 wr32(E1000_TSSDP, tssdp);
490 wr32(E1000_CTRL, ctrl);
491 wr32(E1000_CTRL_EXT, ctrl_ext);
492}
493
494static int igb_ptp_feature_enable_82580(struct ptp_clock_info *ptp,
495 struct ptp_clock_request *rq, int on)
496{
497 struct igb_adapter *igb =
498 container_of(ptp, struct igb_adapter, ptp_caps);
499 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, systiml,
500 systimh, level_mask, level, rem;
501 struct e1000_hw *hw = &igb->hw;
502 struct timespec64 ts, start;
503 unsigned long flags;
504 u64 systim, now;
505 int pin = -1;
506 s64 ns;
507
508 switch (rq->type) {
509 case PTP_CLK_REQ_EXTTS:
510 /* Reject requests with unsupported flags */
511 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
512 PTP_RISING_EDGE |
513 PTP_FALLING_EDGE |
514 PTP_STRICT_FLAGS))
515 return -EOPNOTSUPP;
516
517 if (on) {
518 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
519 rq->extts.index);
520 if (pin < 0)
521 return -EBUSY;
522 }
523 if (rq->extts.index == 1) {
524 tsauxc_mask = TSAUXC_EN_TS1;
525 tsim_mask = TSINTR_AUTT1;
526 } else {
527 tsauxc_mask = TSAUXC_EN_TS0;
528 tsim_mask = TSINTR_AUTT0;
529 }
530 spin_lock_irqsave(&igb->tmreg_lock, flags);
531 tsauxc = rd32(E1000_TSAUXC);
532 tsim = rd32(E1000_TSIM);
533 if (on) {
534 igb_pin_extts(igb, rq->extts.index, pin);
535 tsauxc |= tsauxc_mask;
536 tsim |= tsim_mask;
537 } else {
538 tsauxc &= ~tsauxc_mask;
539 tsim &= ~tsim_mask;
540 }
541 wr32(E1000_TSAUXC, tsauxc);
542 wr32(E1000_TSIM, tsim);
543 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
544 return 0;
545
546 case PTP_CLK_REQ_PEROUT:
547 /* Reject requests with unsupported flags */
548 if (rq->perout.flags)
549 return -EOPNOTSUPP;
550
551 if (on) {
552 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
553 rq->perout.index);
554 if (pin < 0)
555 return -EBUSY;
556 }
557 ts.tv_sec = rq->perout.period.sec;
558 ts.tv_nsec = rq->perout.period.nsec;
559 ns = timespec64_to_ns(&ts);
560 ns = ns >> 1;
561 if (on && ns < 8LL)
562 return -EINVAL;
563 ts = ns_to_timespec64(ns);
564 if (rq->perout.index == 1) {
565 tsauxc_mask = TSAUXC_EN_TT1;
566 tsim_mask = TSINTR_TT1;
567 trgttiml = E1000_TRGTTIML1;
568 trgttimh = E1000_TRGTTIMH1;
569 } else {
570 tsauxc_mask = TSAUXC_EN_TT0;
571 tsim_mask = TSINTR_TT0;
572 trgttiml = E1000_TRGTTIML0;
573 trgttimh = E1000_TRGTTIMH0;
574 }
575 spin_lock_irqsave(&igb->tmreg_lock, flags);
576 tsauxc = rd32(E1000_TSAUXC);
577 tsim = rd32(E1000_TSIM);
578 if (rq->perout.index == 1) {
579 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
580 tsim &= ~TSINTR_TT1;
581 } else {
582 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
583 tsim &= ~TSINTR_TT0;
584 }
585 if (on) {
586 int i = rq->perout.index;
587
588 /* read systim registers in sequence */
589 rd32(E1000_SYSTIMR);
590 systiml = rd32(E1000_SYSTIML);
591 systimh = rd32(E1000_SYSTIMH);
592 systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml);
593 now = timecounter_cyc2time(&igb->tc, systim);
594
595 if (pin < 2) {
596 level_mask = (i == 1) ? 0x80000 : 0x40000;
597 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0;
598 } else {
599 level_mask = (i == 1) ? 0x80 : 0x40;
600 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0;
601 }
602
603 div_u64_rem(now, ns, &rem);
604 systim = systim + (ns - rem);
605
606 /* synchronize pin level with rising/falling edges */
607 div_u64_rem(now, ns << 1, &rem);
608 if (rem < ns) {
609 /* first half of period */
610 if (level == 0) {
611 /* output is already low, skip this period */
612 systim += ns;
613 }
614 } else {
615 /* second half of period */
616 if (level == 1) {
617 /* output is already high, skip this period */
618 systim += ns;
619 }
620 }
621
622 start = ns_to_timespec64(systim + (ns - rem));
623 igb_pin_perout(igb, i, pin, 0);
624 igb->perout[i].start.tv_sec = start.tv_sec;
625 igb->perout[i].start.tv_nsec = start.tv_nsec;
626 igb->perout[i].period.tv_sec = ts.tv_sec;
627 igb->perout[i].period.tv_nsec = ts.tv_nsec;
628
629 wr32(trgttiml, (u32)systim);
630 wr32(trgttimh, ((u32)(systim >> 32)) & 0xFF);
631 tsauxc |= tsauxc_mask;
632 tsim |= tsim_mask;
633 }
634 wr32(E1000_TSAUXC, tsauxc);
635 wr32(E1000_TSIM, tsim);
636 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
637 return 0;
638
639 case PTP_CLK_REQ_PPS:
640 return -EOPNOTSUPP;
641 }
642
643 return -EOPNOTSUPP;
644}
645
646static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
647 struct ptp_clock_request *rq, int on)
648{
649 struct igb_adapter *igb =
650 container_of(ptp, struct igb_adapter, ptp_caps);
651 struct e1000_hw *hw = &igb->hw;
652 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
653 unsigned long flags;
654 struct timespec64 ts;
655 int use_freq = 0, pin = -1;
656 s64 ns;
657
658 switch (rq->type) {
659 case PTP_CLK_REQ_EXTTS:
660 /* Reject requests with unsupported flags */
661 if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
662 PTP_RISING_EDGE |
663 PTP_FALLING_EDGE |
664 PTP_STRICT_FLAGS))
665 return -EOPNOTSUPP;
666
667 /* Reject requests failing to enable both edges. */
668 if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
669 (rq->extts.flags & PTP_ENABLE_FEATURE) &&
670 (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
671 return -EOPNOTSUPP;
672
673 if (on) {
674 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
675 rq->extts.index);
676 if (pin < 0)
677 return -EBUSY;
678 }
679 if (rq->extts.index == 1) {
680 tsauxc_mask = TSAUXC_EN_TS1;
681 tsim_mask = TSINTR_AUTT1;
682 } else {
683 tsauxc_mask = TSAUXC_EN_TS0;
684 tsim_mask = TSINTR_AUTT0;
685 }
686 spin_lock_irqsave(&igb->tmreg_lock, flags);
687 tsauxc = rd32(E1000_TSAUXC);
688 tsim = rd32(E1000_TSIM);
689 if (on) {
690 igb_pin_extts(igb, rq->extts.index, pin);
691 tsauxc |= tsauxc_mask;
692 tsim |= tsim_mask;
693 } else {
694 tsauxc &= ~tsauxc_mask;
695 tsim &= ~tsim_mask;
696 }
697 wr32(E1000_TSAUXC, tsauxc);
698 wr32(E1000_TSIM, tsim);
699 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
700 return 0;
701
702 case PTP_CLK_REQ_PEROUT:
703 /* Reject requests with unsupported flags */
704 if (rq->perout.flags)
705 return -EOPNOTSUPP;
706
707 if (on) {
708 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
709 rq->perout.index);
710 if (pin < 0)
711 return -EBUSY;
712 }
713 ts.tv_sec = rq->perout.period.sec;
714 ts.tv_nsec = rq->perout.period.nsec;
715 ns = timespec64_to_ns(&ts);
716 ns = ns >> 1;
717 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
718 (ns == 250000000LL) || (ns == 500000000LL))) {
719 if (ns < 8LL)
720 return -EINVAL;
721 use_freq = 1;
722 }
723 ts = ns_to_timespec64(ns);
724 if (rq->perout.index == 1) {
725 if (use_freq) {
726 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
727 tsim_mask = 0;
728 } else {
729 tsauxc_mask = TSAUXC_EN_TT1;
730 tsim_mask = TSINTR_TT1;
731 }
732 trgttiml = E1000_TRGTTIML1;
733 trgttimh = E1000_TRGTTIMH1;
734 freqout = E1000_FREQOUT1;
735 } else {
736 if (use_freq) {
737 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
738 tsim_mask = 0;
739 } else {
740 tsauxc_mask = TSAUXC_EN_TT0;
741 tsim_mask = TSINTR_TT0;
742 }
743 trgttiml = E1000_TRGTTIML0;
744 trgttimh = E1000_TRGTTIMH0;
745 freqout = E1000_FREQOUT0;
746 }
747 spin_lock_irqsave(&igb->tmreg_lock, flags);
748 tsauxc = rd32(E1000_TSAUXC);
749 tsim = rd32(E1000_TSIM);
750 if (rq->perout.index == 1) {
751 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
752 tsim &= ~TSINTR_TT1;
753 } else {
754 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
755 tsim &= ~TSINTR_TT0;
756 }
757 if (on) {
758 int i = rq->perout.index;
759 igb_pin_perout(igb, i, pin, use_freq);
760 igb->perout[i].start.tv_sec = rq->perout.start.sec;
761 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
762 igb->perout[i].period.tv_sec = ts.tv_sec;
763 igb->perout[i].period.tv_nsec = ts.tv_nsec;
764 wr32(trgttimh, rq->perout.start.sec);
765 wr32(trgttiml, rq->perout.start.nsec);
766 if (use_freq)
767 wr32(freqout, ns);
768 tsauxc |= tsauxc_mask;
769 tsim |= tsim_mask;
770 }
771 wr32(E1000_TSAUXC, tsauxc);
772 wr32(E1000_TSIM, tsim);
773 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
774 return 0;
775
776 case PTP_CLK_REQ_PPS:
777 spin_lock_irqsave(&igb->tmreg_lock, flags);
778 tsim = rd32(E1000_TSIM);
779 if (on)
780 tsim |= TSINTR_SYS_WRAP;
781 else
782 tsim &= ~TSINTR_SYS_WRAP;
783 igb->pps_sys_wrap_on = !!on;
784 wr32(E1000_TSIM, tsim);
785 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
786 return 0;
787 }
788
789 return -EOPNOTSUPP;
790}
791
792static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
793 struct ptp_clock_request *rq, int on)
794{
795 return -EOPNOTSUPP;
796}
797
798static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
799 enum ptp_pin_function func, unsigned int chan)
800{
801 switch (func) {
802 case PTP_PF_NONE:
803 case PTP_PF_EXTTS:
804 case PTP_PF_PEROUT:
805 break;
806 case PTP_PF_PHYSYNC:
807 return -1;
808 }
809 return 0;
810}
811
812/**
813 * igb_ptp_tx_work
814 * @work: pointer to work struct
815 *
816 * This work function polls the TSYNCTXCTL valid bit to determine when a
817 * timestamp has been taken for the current stored skb.
818 **/
819static void igb_ptp_tx_work(struct work_struct *work)
820{
821 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
822 ptp_tx_work);
823 struct e1000_hw *hw = &adapter->hw;
824 u32 tsynctxctl;
825
826 if (!adapter->ptp_tx_skb)
827 return;
828
829 if (time_is_before_jiffies(adapter->ptp_tx_start +
830 IGB_PTP_TX_TIMEOUT)) {
831 dev_kfree_skb_any(adapter->ptp_tx_skb);
832 adapter->ptp_tx_skb = NULL;
833 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
834 adapter->tx_hwtstamp_timeouts++;
835 /* Clear the tx valid bit in TSYNCTXCTL register to enable
836 * interrupt
837 */
838 rd32(E1000_TXSTMPH);
839 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
840 return;
841 }
842
843 tsynctxctl = rd32(E1000_TSYNCTXCTL);
844 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
845 igb_ptp_tx_hwtstamp(adapter);
846 else
847 /* reschedule to check later */
848 schedule_work(&adapter->ptp_tx_work);
849}
850
851static void igb_ptp_overflow_check(struct work_struct *work)
852{
853 struct igb_adapter *igb =
854 container_of(work, struct igb_adapter, ptp_overflow_work.work);
855 struct timespec64 ts;
856 u64 ns;
857
858 /* Update the timecounter */
859 ns = timecounter_read(&igb->tc);
860
861 ts = ns_to_timespec64(ns);
862 pr_debug("igb overflow check at %lld.%09lu\n",
863 (long long) ts.tv_sec, ts.tv_nsec);
864
865 schedule_delayed_work(&igb->ptp_overflow_work,
866 IGB_SYSTIM_OVERFLOW_PERIOD);
867}
868
869/**
870 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
871 * @adapter: private network adapter structure
872 *
873 * This watchdog task is scheduled to detect error case where hardware has
874 * dropped an Rx packet that was timestamped when the ring is full. The
875 * particular error is rare but leaves the device in a state unable to timestamp
876 * any future packets.
877 **/
878void igb_ptp_rx_hang(struct igb_adapter *adapter)
879{
880 struct e1000_hw *hw = &adapter->hw;
881 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
882 unsigned long rx_event;
883
884 /* Other hardware uses per-packet timestamps */
885 if (hw->mac.type != e1000_82576)
886 return;
887
888 /* If we don't have a valid timestamp in the registers, just update the
889 * timeout counter and exit
890 */
891 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
892 adapter->last_rx_ptp_check = jiffies;
893 return;
894 }
895
896 /* Determine the most recent watchdog or rx_timestamp event */
897 rx_event = adapter->last_rx_ptp_check;
898 if (time_after(adapter->last_rx_timestamp, rx_event))
899 rx_event = adapter->last_rx_timestamp;
900
901 /* Only need to read the high RXSTMP register to clear the lock */
902 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
903 rd32(E1000_RXSTMPH);
904 adapter->last_rx_ptp_check = jiffies;
905 adapter->rx_hwtstamp_cleared++;
906 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
907 }
908}
909
910/**
911 * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
912 * @adapter: private network adapter structure
913 */
914void igb_ptp_tx_hang(struct igb_adapter *adapter)
915{
916 struct e1000_hw *hw = &adapter->hw;
917 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
918 IGB_PTP_TX_TIMEOUT);
919
920 if (!adapter->ptp_tx_skb)
921 return;
922
923 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
924 return;
925
926 /* If we haven't received a timestamp within the timeout, it is
927 * reasonable to assume that it will never occur, so we can unlock the
928 * timestamp bit when this occurs.
929 */
930 if (timeout) {
931 cancel_work_sync(&adapter->ptp_tx_work);
932 dev_kfree_skb_any(adapter->ptp_tx_skb);
933 adapter->ptp_tx_skb = NULL;
934 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
935 adapter->tx_hwtstamp_timeouts++;
936 /* Clear the tx valid bit in TSYNCTXCTL register to enable
937 * interrupt
938 */
939 rd32(E1000_TXSTMPH);
940 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
941 }
942}
943
944/**
945 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
946 * @adapter: Board private structure.
947 *
948 * If we were asked to do hardware stamping and such a time stamp is
949 * available, then it must have been for this skb here because we only
950 * allow only one such packet into the queue.
951 **/
952static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
953{
954 struct sk_buff *skb = adapter->ptp_tx_skb;
955 struct e1000_hw *hw = &adapter->hw;
956 struct skb_shared_hwtstamps shhwtstamps;
957 u64 regval;
958 int adjust = 0;
959
960 regval = rd32(E1000_TXSTMPL);
961 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
962
963 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
964 /* adjust timestamp for the TX latency based on link speed */
965 if (adapter->hw.mac.type == e1000_i210) {
966 switch (adapter->link_speed) {
967 case SPEED_10:
968 adjust = IGB_I210_TX_LATENCY_10;
969 break;
970 case SPEED_100:
971 adjust = IGB_I210_TX_LATENCY_100;
972 break;
973 case SPEED_1000:
974 adjust = IGB_I210_TX_LATENCY_1000;
975 break;
976 }
977 }
978
979 shhwtstamps.hwtstamp =
980 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
981
982 /* Clear the lock early before calling skb_tstamp_tx so that
983 * applications are not woken up before the lock bit is clear. We use
984 * a copy of the skb pointer to ensure other threads can't change it
985 * while we're notifying the stack.
986 */
987 adapter->ptp_tx_skb = NULL;
988 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
989
990 /* Notify the stack and free the skb after we've unlocked */
991 skb_tstamp_tx(skb, &shhwtstamps);
992 dev_kfree_skb_any(skb);
993}
994
995/**
996 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
997 * @q_vector: Pointer to interrupt specific structure
998 * @va: Pointer to address containing Rx buffer
999 * @timestamp: Pointer where timestamp will be stored
1000 *
1001 * This function is meant to retrieve a timestamp from the first buffer of an
1002 * incoming frame. The value is stored in little endian format starting on
1003 * byte 8
1004 *
1005 * Returns: The timestamp header length or 0 if not available
1006 **/
1007int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
1008 ktime_t *timestamp)
1009{
1010 struct igb_adapter *adapter = q_vector->adapter;
1011 struct skb_shared_hwtstamps ts;
1012 __le64 *regval = (__le64 *)va;
1013 int adjust = 0;
1014
1015 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1016 return 0;
1017
1018 /* The timestamp is recorded in little endian format.
1019 * DWORD: 0 1 2 3
1020 * Field: Reserved Reserved SYSTIML SYSTIMH
1021 */
1022
1023 /* check reserved dwords are zero, be/le doesn't matter for zero */
1024 if (regval[0])
1025 return 0;
1026
1027 igb_ptp_systim_to_hwtstamp(adapter, &ts, le64_to_cpu(regval[1]));
1028
1029 /* adjust timestamp for the RX latency based on link speed */
1030 if (adapter->hw.mac.type == e1000_i210) {
1031 switch (adapter->link_speed) {
1032 case SPEED_10:
1033 adjust = IGB_I210_RX_LATENCY_10;
1034 break;
1035 case SPEED_100:
1036 adjust = IGB_I210_RX_LATENCY_100;
1037 break;
1038 case SPEED_1000:
1039 adjust = IGB_I210_RX_LATENCY_1000;
1040 break;
1041 }
1042 }
1043
1044 *timestamp = ktime_sub_ns(ts.hwtstamp, adjust);
1045
1046 return IGB_TS_HDR_LEN;
1047}
1048
1049/**
1050 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
1051 * @q_vector: Pointer to interrupt specific structure
1052 * @skb: Buffer containing timestamp and packet
1053 *
1054 * This function is meant to retrieve a timestamp from the internal registers
1055 * of the adapter and store it in the skb.
1056 **/
1057void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
1058{
1059 struct igb_adapter *adapter = q_vector->adapter;
1060 struct e1000_hw *hw = &adapter->hw;
1061 int adjust = 0;
1062 u64 regval;
1063
1064 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1065 return;
1066
1067 /* If this bit is set, then the RX registers contain the time stamp. No
1068 * other packet will be time stamped until we read these registers, so
1069 * read the registers to make them available again. Because only one
1070 * packet can be time stamped at a time, we know that the register
1071 * values must belong to this one here and therefore we don't need to
1072 * compare any of the additional attributes stored for it.
1073 *
1074 * If nothing went wrong, then it should have a shared tx_flags that we
1075 * can turn into a skb_shared_hwtstamps.
1076 */
1077 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
1078 return;
1079
1080 regval = rd32(E1000_RXSTMPL);
1081 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
1082
1083 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
1084
1085 /* adjust timestamp for the RX latency based on link speed */
1086 if (adapter->hw.mac.type == e1000_i210) {
1087 switch (adapter->link_speed) {
1088 case SPEED_10:
1089 adjust = IGB_I210_RX_LATENCY_10;
1090 break;
1091 case SPEED_100:
1092 adjust = IGB_I210_RX_LATENCY_100;
1093 break;
1094 case SPEED_1000:
1095 adjust = IGB_I210_RX_LATENCY_1000;
1096 break;
1097 }
1098 }
1099 skb_hwtstamps(skb)->hwtstamp =
1100 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
1101
1102 /* Update the last_rx_timestamp timer in order to enable watchdog check
1103 * for error case of latched timestamp on a dropped packet.
1104 */
1105 adapter->last_rx_timestamp = jiffies;
1106}
1107
1108/**
1109 * igb_ptp_get_ts_config - get hardware time stamping config
1110 * @netdev: netdev struct
1111 * @ifr: interface struct
1112 *
1113 * Get the hwtstamp_config settings to return to the user. Rather than attempt
1114 * to deconstruct the settings from the registers, just return a shadow copy
1115 * of the last known settings.
1116 **/
1117int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
1118{
1119 struct igb_adapter *adapter = netdev_priv(netdev);
1120 struct hwtstamp_config *config = &adapter->tstamp_config;
1121
1122 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
1123 -EFAULT : 0;
1124}
1125
1126/**
1127 * igb_ptp_set_timestamp_mode - setup hardware for timestamping
1128 * @adapter: networking device structure
1129 * @config: hwtstamp configuration
1130 *
1131 * Outgoing time stamping can be enabled and disabled. Play nice and
1132 * disable it when requested, although it shouldn't case any overhead
1133 * when no packet needs it. At most one packet in the queue may be
1134 * marked for time stamping, otherwise it would be impossible to tell
1135 * for sure to which packet the hardware time stamp belongs.
1136 *
1137 * Incoming time stamping has to be configured via the hardware
1138 * filters. Not all combinations are supported, in particular event
1139 * type has to be specified. Matching the kind of event packet is
1140 * not supported, with the exception of "all V2 events regardless of
1141 * level 2 or 4".
1142 */
1143static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
1144 struct hwtstamp_config *config)
1145{
1146 struct e1000_hw *hw = &adapter->hw;
1147 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
1148 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1149 u32 tsync_rx_cfg = 0;
1150 bool is_l4 = false;
1151 bool is_l2 = false;
1152 u32 regval;
1153
1154 switch (config->tx_type) {
1155 case HWTSTAMP_TX_OFF:
1156 tsync_tx_ctl = 0;
1157 break;
1158 case HWTSTAMP_TX_ON:
1159 break;
1160 default:
1161 return -ERANGE;
1162 }
1163
1164 switch (config->rx_filter) {
1165 case HWTSTAMP_FILTER_NONE:
1166 tsync_rx_ctl = 0;
1167 break;
1168 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1169 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
1170 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
1171 is_l4 = true;
1172 break;
1173 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1174 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
1175 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
1176 is_l4 = true;
1177 break;
1178 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1179 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1180 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1181 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1182 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1183 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1184 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1185 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1186 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1187 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
1188 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1189 is_l2 = true;
1190 is_l4 = true;
1191 break;
1192 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1193 case HWTSTAMP_FILTER_NTP_ALL:
1194 case HWTSTAMP_FILTER_ALL:
1195 /* 82576 cannot timestamp all packets, which it needs to do to
1196 * support both V1 Sync and Delay_Req messages
1197 */
1198 if (hw->mac.type != e1000_82576) {
1199 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1200 config->rx_filter = HWTSTAMP_FILTER_ALL;
1201 break;
1202 }
1203 fallthrough;
1204 default:
1205 config->rx_filter = HWTSTAMP_FILTER_NONE;
1206 return -ERANGE;
1207 }
1208
1209 if (hw->mac.type == e1000_82575) {
1210 if (tsync_rx_ctl | tsync_tx_ctl)
1211 return -EINVAL;
1212 return 0;
1213 }
1214
1215 /* Per-packet timestamping only works if all packets are
1216 * timestamped, so enable timestamping in all packets as
1217 * long as one Rx filter was configured.
1218 */
1219 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1220 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1221 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1222 config->rx_filter = HWTSTAMP_FILTER_ALL;
1223 is_l2 = true;
1224 is_l4 = true;
1225
1226 if ((hw->mac.type == e1000_i210) ||
1227 (hw->mac.type == e1000_i211)) {
1228 regval = rd32(E1000_RXPBS);
1229 regval |= E1000_RXPBS_CFG_TS_EN;
1230 wr32(E1000_RXPBS, regval);
1231 }
1232 }
1233
1234 /* enable/disable TX */
1235 regval = rd32(E1000_TSYNCTXCTL);
1236 regval &= ~E1000_TSYNCTXCTL_ENABLED;
1237 regval |= tsync_tx_ctl;
1238 wr32(E1000_TSYNCTXCTL, regval);
1239
1240 /* enable/disable RX */
1241 regval = rd32(E1000_TSYNCRXCTL);
1242 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1243 regval |= tsync_rx_ctl;
1244 wr32(E1000_TSYNCRXCTL, regval);
1245
1246 /* define which PTP packets are time stamped */
1247 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1248
1249 /* define ethertype filter for timestamped packets */
1250 if (is_l2)
1251 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1252 (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1253 E1000_ETQF_1588 | /* enable timestamping */
1254 ETH_P_1588)); /* 1588 eth protocol type */
1255 else
1256 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1257
1258 /* L4 Queue Filter[3]: filter by destination port and protocol */
1259 if (is_l4) {
1260 u32 ftqf = (IPPROTO_UDP /* UDP */
1261 | E1000_FTQF_VF_BP /* VF not compared */
1262 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1263 | E1000_FTQF_MASK); /* mask all inputs */
1264 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1265
1266 wr32(E1000_IMIR(3), (__force unsigned int)htons(PTP_EV_PORT));
1267 wr32(E1000_IMIREXT(3),
1268 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1269 if (hw->mac.type == e1000_82576) {
1270 /* enable source port check */
1271 wr32(E1000_SPQF(3), (__force unsigned int)htons(PTP_EV_PORT));
1272 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1273 }
1274 wr32(E1000_FTQF(3), ftqf);
1275 } else {
1276 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1277 }
1278 wrfl();
1279
1280 /* clear TX/RX time stamp registers, just to be sure */
1281 regval = rd32(E1000_TXSTMPL);
1282 regval = rd32(E1000_TXSTMPH);
1283 regval = rd32(E1000_RXSTMPL);
1284 regval = rd32(E1000_RXSTMPH);
1285
1286 return 0;
1287}
1288
1289/**
1290 * igb_ptp_set_ts_config - set hardware time stamping config
1291 * @netdev: netdev struct
1292 * @ifr: interface struct
1293 *
1294 **/
1295int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1296{
1297 struct igb_adapter *adapter = netdev_priv(netdev);
1298 struct hwtstamp_config config;
1299 int err;
1300
1301 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1302 return -EFAULT;
1303
1304 err = igb_ptp_set_timestamp_mode(adapter, &config);
1305 if (err)
1306 return err;
1307
1308 /* save these settings for future reference */
1309 memcpy(&adapter->tstamp_config, &config,
1310 sizeof(adapter->tstamp_config));
1311
1312 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1313 -EFAULT : 0;
1314}
1315
1316/**
1317 * igb_ptp_init - Initialize PTP functionality
1318 * @adapter: Board private structure
1319 *
1320 * This function is called at device probe to initialize the PTP
1321 * functionality.
1322 */
1323void igb_ptp_init(struct igb_adapter *adapter)
1324{
1325 struct e1000_hw *hw = &adapter->hw;
1326 struct net_device *netdev = adapter->netdev;
1327
1328 switch (hw->mac.type) {
1329 case e1000_82576:
1330 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1331 adapter->ptp_caps.owner = THIS_MODULE;
1332 adapter->ptp_caps.max_adj = 999999881;
1333 adapter->ptp_caps.n_ext_ts = 0;
1334 adapter->ptp_caps.pps = 0;
1335 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82576;
1336 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1337 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576;
1338 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1339 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1340 adapter->cc.read = igb_ptp_read_82576;
1341 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1342 adapter->cc.mult = 1;
1343 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1344 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1345 break;
1346 case e1000_82580:
1347 case e1000_i354:
1348 case e1000_i350:
1349 igb_ptp_sdp_init(adapter);
1350 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1351 adapter->ptp_caps.owner = THIS_MODULE;
1352 adapter->ptp_caps.max_adj = 62499999;
1353 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1354 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1355 adapter->ptp_caps.n_pins = IGB_N_SDP;
1356 adapter->ptp_caps.pps = 0;
1357 adapter->ptp_caps.pin_config = adapter->sdp_config;
1358 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1359 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1360 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580;
1361 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1362 adapter->ptp_caps.enable = igb_ptp_feature_enable_82580;
1363 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1364 adapter->cc.read = igb_ptp_read_82580;
1365 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1366 adapter->cc.mult = 1;
1367 adapter->cc.shift = 0;
1368 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1369 break;
1370 case e1000_i210:
1371 case e1000_i211:
1372 igb_ptp_sdp_init(adapter);
1373 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1374 adapter->ptp_caps.owner = THIS_MODULE;
1375 adapter->ptp_caps.max_adj = 62499999;
1376 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1377 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1378 adapter->ptp_caps.n_pins = IGB_N_SDP;
1379 adapter->ptp_caps.pps = 1;
1380 adapter->ptp_caps.pin_config = adapter->sdp_config;
1381 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1382 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1383 adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210;
1384 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1385 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1386 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1387 break;
1388 default:
1389 adapter->ptp_clock = NULL;
1390 return;
1391 }
1392
1393 spin_lock_init(&adapter->tmreg_lock);
1394 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1395
1396 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1397 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1398 igb_ptp_overflow_check);
1399
1400 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1401 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1402
1403 igb_ptp_reset(adapter);
1404
1405 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1406 &adapter->pdev->dev);
1407 if (IS_ERR(adapter->ptp_clock)) {
1408 adapter->ptp_clock = NULL;
1409 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1410 } else if (adapter->ptp_clock) {
1411 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1412 adapter->netdev->name);
1413 adapter->ptp_flags |= IGB_PTP_ENABLED;
1414 }
1415}
1416
1417/**
1418 * igb_ptp_sdp_init - utility function which inits the SDP config structs
1419 * @adapter: Board private structure.
1420 **/
1421void igb_ptp_sdp_init(struct igb_adapter *adapter)
1422{
1423 int i;
1424
1425 for (i = 0; i < IGB_N_SDP; i++) {
1426 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1427
1428 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1429 ppd->index = i;
1430 ppd->func = PTP_PF_NONE;
1431 }
1432}
1433
1434/**
1435 * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1436 * @adapter: Board private structure
1437 *
1438 * This function stops the overflow check work and PTP Tx timestamp work, and
1439 * will prepare the device for OS suspend.
1440 */
1441void igb_ptp_suspend(struct igb_adapter *adapter)
1442{
1443 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1444 return;
1445
1446 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1447 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1448
1449 cancel_work_sync(&adapter->ptp_tx_work);
1450 if (adapter->ptp_tx_skb) {
1451 dev_kfree_skb_any(adapter->ptp_tx_skb);
1452 adapter->ptp_tx_skb = NULL;
1453 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1454 }
1455}
1456
1457/**
1458 * igb_ptp_stop - Disable PTP device and stop the overflow check.
1459 * @adapter: Board private structure.
1460 *
1461 * This function stops the PTP support and cancels the delayed work.
1462 **/
1463void igb_ptp_stop(struct igb_adapter *adapter)
1464{
1465 igb_ptp_suspend(adapter);
1466
1467 if (adapter->ptp_clock) {
1468 ptp_clock_unregister(adapter->ptp_clock);
1469 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1470 adapter->netdev->name);
1471 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1472 }
1473}
1474
1475/**
1476 * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1477 * @adapter: Board private structure.
1478 *
1479 * This function handles the reset work required to re-enable the PTP device.
1480 **/
1481void igb_ptp_reset(struct igb_adapter *adapter)
1482{
1483 struct e1000_hw *hw = &adapter->hw;
1484 unsigned long flags;
1485
1486 /* reset the tstamp_config */
1487 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1488
1489 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1490
1491 switch (adapter->hw.mac.type) {
1492 case e1000_82576:
1493 /* Dial the nominal frequency. */
1494 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1495 break;
1496 case e1000_82580:
1497 case e1000_i354:
1498 case e1000_i350:
1499 case e1000_i210:
1500 case e1000_i211:
1501 wr32(E1000_TSAUXC, 0x0);
1502 wr32(E1000_TSSDP, 0x0);
1503 wr32(E1000_TSIM,
1504 TSYNC_INTERRUPTS |
1505 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1506 wr32(E1000_IMS, E1000_IMS_TS);
1507 break;
1508 default:
1509 /* No work to do. */
1510 goto out;
1511 }
1512
1513 /* Re-initialize the timer. */
1514 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1515 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1516
1517 igb_ptp_write_i210(adapter, &ts);
1518 } else {
1519 timecounter_init(&adapter->tc, &adapter->cc,
1520 ktime_to_ns(ktime_get_real()));
1521 }
1522out:
1523 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1524
1525 wrfl();
1526
1527 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1528 schedule_delayed_work(&adapter->ptp_overflow_work,
1529 IGB_SYSTIM_OVERFLOW_PERIOD);
1530}