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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 */
9#include <linux/bitmap.h>
10#include <linux/clocksource.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14#include <linux/irqchip.h>
15#include <linux/irqchip/mips-gic.h>
16#include <linux/of_address.h>
17#include <linux/sched.h>
18#include <linux/smp.h>
19
20#include <asm/mips-cm.h>
21#include <asm/setup.h>
22#include <asm/traps.h>
23
24#include <dt-bindings/interrupt-controller/mips-gic.h>
25
26unsigned int gic_present;
27
28struct gic_pcpu_mask {
29 DECLARE_BITMAP(pcpu_mask, GIC_MAX_INTRS);
30};
31
32struct gic_irq_spec {
33 enum {
34 GIC_DEVICE,
35 GIC_IPI
36 } type;
37
38 union {
39 struct cpumask *ipimask;
40 unsigned int hwirq;
41 };
42};
43
44static unsigned long __gic_base_addr;
45
46static void __iomem *gic_base;
47static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
48static DEFINE_SPINLOCK(gic_lock);
49static struct irq_domain *gic_irq_domain;
50static struct irq_domain *gic_dev_domain;
51static struct irq_domain *gic_ipi_domain;
52static int gic_shared_intrs;
53static int gic_vpes;
54static unsigned int gic_cpu_pin;
55static unsigned int timer_cpu_pin;
56static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
57DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
58
59static void __gic_irq_dispatch(void);
60
61static inline u32 gic_read32(unsigned int reg)
62{
63 return __raw_readl(gic_base + reg);
64}
65
66static inline u64 gic_read64(unsigned int reg)
67{
68 return __raw_readq(gic_base + reg);
69}
70
71static inline unsigned long gic_read(unsigned int reg)
72{
73 if (!mips_cm_is64)
74 return gic_read32(reg);
75 else
76 return gic_read64(reg);
77}
78
79static inline void gic_write32(unsigned int reg, u32 val)
80{
81 return __raw_writel(val, gic_base + reg);
82}
83
84static inline void gic_write64(unsigned int reg, u64 val)
85{
86 return __raw_writeq(val, gic_base + reg);
87}
88
89static inline void gic_write(unsigned int reg, unsigned long val)
90{
91 if (!mips_cm_is64)
92 return gic_write32(reg, (u32)val);
93 else
94 return gic_write64(reg, (u64)val);
95}
96
97static inline void gic_update_bits(unsigned int reg, unsigned long mask,
98 unsigned long val)
99{
100 unsigned long regval;
101
102 regval = gic_read(reg);
103 regval &= ~mask;
104 regval |= val;
105 gic_write(reg, regval);
106}
107
108static inline void gic_reset_mask(unsigned int intr)
109{
110 gic_write(GIC_REG(SHARED, GIC_SH_RMASK) + GIC_INTR_OFS(intr),
111 1ul << GIC_INTR_BIT(intr));
112}
113
114static inline void gic_set_mask(unsigned int intr)
115{
116 gic_write(GIC_REG(SHARED, GIC_SH_SMASK) + GIC_INTR_OFS(intr),
117 1ul << GIC_INTR_BIT(intr));
118}
119
120static inline void gic_set_polarity(unsigned int intr, unsigned int pol)
121{
122 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_POLARITY) +
123 GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
124 (unsigned long)pol << GIC_INTR_BIT(intr));
125}
126
127static inline void gic_set_trigger(unsigned int intr, unsigned int trig)
128{
129 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
130 GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
131 (unsigned long)trig << GIC_INTR_BIT(intr));
132}
133
134static inline void gic_set_dual_edge(unsigned int intr, unsigned int dual)
135{
136 gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_DUAL) + GIC_INTR_OFS(intr),
137 1ul << GIC_INTR_BIT(intr),
138 (unsigned long)dual << GIC_INTR_BIT(intr));
139}
140
141static inline void gic_map_to_pin(unsigned int intr, unsigned int pin)
142{
143 gic_write32(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_PIN_BASE) +
144 GIC_SH_MAP_TO_PIN(intr), GIC_MAP_TO_PIN_MSK | pin);
145}
146
147static inline void gic_map_to_vpe(unsigned int intr, unsigned int vpe)
148{
149 gic_write(GIC_REG(SHARED, GIC_SH_INTR_MAP_TO_VPE_BASE) +
150 GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe),
151 GIC_SH_MAP_TO_VPE_REG_BIT(vpe));
152}
153
154#ifdef CONFIG_CLKSRC_MIPS_GIC
155cycle_t gic_read_count(void)
156{
157 unsigned int hi, hi2, lo;
158
159 if (mips_cm_is64)
160 return (cycle_t)gic_read(GIC_REG(SHARED, GIC_SH_COUNTER));
161
162 do {
163 hi = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
164 lo = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_31_00));
165 hi2 = gic_read32(GIC_REG(SHARED, GIC_SH_COUNTER_63_32));
166 } while (hi2 != hi);
167
168 return (((cycle_t) hi) << 32) + lo;
169}
170
171unsigned int gic_get_count_width(void)
172{
173 unsigned int bits, config;
174
175 config = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
176 bits = 32 + 4 * ((config & GIC_SH_CONFIG_COUNTBITS_MSK) >>
177 GIC_SH_CONFIG_COUNTBITS_SHF);
178
179 return bits;
180}
181
182void gic_write_compare(cycle_t cnt)
183{
184 if (mips_cm_is64) {
185 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE), cnt);
186 } else {
187 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
188 (int)(cnt >> 32));
189 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
190 (int)(cnt & 0xffffffff));
191 }
192}
193
194void gic_write_cpu_compare(cycle_t cnt, int cpu)
195{
196 unsigned long flags;
197
198 local_irq_save(flags);
199
200 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), cpu);
201
202 if (mips_cm_is64) {
203 gic_write(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE), cnt);
204 } else {
205 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_HI),
206 (int)(cnt >> 32));
207 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_LO),
208 (int)(cnt & 0xffffffff));
209 }
210
211 local_irq_restore(flags);
212}
213
214cycle_t gic_read_compare(void)
215{
216 unsigned int hi, lo;
217
218 if (mips_cm_is64)
219 return (cycle_t)gic_read(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE));
220
221 hi = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI));
222 lo = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO));
223
224 return (((cycle_t) hi) << 32) + lo;
225}
226
227void gic_start_count(void)
228{
229 u32 gicconfig;
230
231 /* Start the counter */
232 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
233 gicconfig &= ~(1 << GIC_SH_CONFIG_COUNTSTOP_SHF);
234 gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
235}
236
237void gic_stop_count(void)
238{
239 u32 gicconfig;
240
241 /* Stop the counter */
242 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
243 gicconfig |= 1 << GIC_SH_CONFIG_COUNTSTOP_SHF;
244 gic_write(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
245}
246
247#endif
248
249static bool gic_local_irq_is_routable(int intr)
250{
251 u32 vpe_ctl;
252
253 /* All local interrupts are routable in EIC mode. */
254 if (cpu_has_veic)
255 return true;
256
257 vpe_ctl = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_CTL));
258 switch (intr) {
259 case GIC_LOCAL_INT_TIMER:
260 return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
261 case GIC_LOCAL_INT_PERFCTR:
262 return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
263 case GIC_LOCAL_INT_FDC:
264 return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
265 case GIC_LOCAL_INT_SWINT0:
266 case GIC_LOCAL_INT_SWINT1:
267 return vpe_ctl & GIC_VPE_CTL_SWINT_RTBL_MSK;
268 default:
269 return true;
270 }
271}
272
273static void gic_bind_eic_interrupt(int irq, int set)
274{
275 /* Convert irq vector # to hw int # */
276 irq -= GIC_PIN_TO_VEC_OFFSET;
277
278 /* Set irq to use shadow set */
279 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_EIC_SHADOW_SET_BASE) +
280 GIC_VPE_EIC_SS(irq), set);
281}
282
283static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
284{
285 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
286
287 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_SET(hwirq));
288}
289
290int gic_get_c0_compare_int(void)
291{
292 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
293 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
294 return irq_create_mapping(gic_irq_domain,
295 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
296}
297
298int gic_get_c0_perfcount_int(void)
299{
300 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
301 /* Is the performance counter shared with the timer? */
302 if (cp0_perfcount_irq < 0)
303 return -1;
304 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
305 }
306 return irq_create_mapping(gic_irq_domain,
307 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
308}
309
310int gic_get_c0_fdc_int(void)
311{
312 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
313 /* Is the FDC IRQ even present? */
314 if (cp0_fdc_irq < 0)
315 return -1;
316 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
317 }
318
319 return irq_create_mapping(gic_irq_domain,
320 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
321}
322
323int gic_get_usm_range(struct resource *gic_usm_res)
324{
325 if (!gic_present)
326 return -1;
327
328 gic_usm_res->start = __gic_base_addr + USM_VISIBLE_SECTION_OFS;
329 gic_usm_res->end = gic_usm_res->start + (USM_VISIBLE_SECTION_SIZE - 1);
330
331 return 0;
332}
333
334static void gic_handle_shared_int(bool chained)
335{
336 unsigned int i, intr, virq, gic_reg_step = mips_cm_is64 ? 8 : 4;
337 unsigned long *pcpu_mask;
338 unsigned long pending_reg, intrmask_reg;
339 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
340 DECLARE_BITMAP(intrmask, GIC_MAX_INTRS);
341
342 /* Get per-cpu bitmaps */
343 pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
344
345 pending_reg = GIC_REG(SHARED, GIC_SH_PEND);
346 intrmask_reg = GIC_REG(SHARED, GIC_SH_MASK);
347
348 for (i = 0; i < BITS_TO_LONGS(gic_shared_intrs); i++) {
349 pending[i] = gic_read(pending_reg);
350 intrmask[i] = gic_read(intrmask_reg);
351 pending_reg += gic_reg_step;
352 intrmask_reg += gic_reg_step;
353
354 if (!config_enabled(CONFIG_64BIT) || mips_cm_is64)
355 continue;
356
357 pending[i] |= (u64)gic_read(pending_reg) << 32;
358 intrmask[i] |= (u64)gic_read(intrmask_reg) << 32;
359 pending_reg += gic_reg_step;
360 intrmask_reg += gic_reg_step;
361 }
362
363 bitmap_and(pending, pending, intrmask, gic_shared_intrs);
364 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
365
366 intr = find_first_bit(pending, gic_shared_intrs);
367 while (intr != gic_shared_intrs) {
368 virq = irq_linear_revmap(gic_irq_domain,
369 GIC_SHARED_TO_HWIRQ(intr));
370 if (chained)
371 generic_handle_irq(virq);
372 else
373 do_IRQ(virq);
374
375 /* go to next pending bit */
376 bitmap_clear(pending, intr, 1);
377 intr = find_first_bit(pending, gic_shared_intrs);
378 }
379}
380
381static void gic_mask_irq(struct irq_data *d)
382{
383 gic_reset_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
384}
385
386static void gic_unmask_irq(struct irq_data *d)
387{
388 gic_set_mask(GIC_HWIRQ_TO_SHARED(d->hwirq));
389}
390
391static void gic_ack_irq(struct irq_data *d)
392{
393 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
394
395 gic_write(GIC_REG(SHARED, GIC_SH_WEDGE), GIC_SH_WEDGE_CLR(irq));
396}
397
398static int gic_set_type(struct irq_data *d, unsigned int type)
399{
400 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
401 unsigned long flags;
402 bool is_edge;
403
404 spin_lock_irqsave(&gic_lock, flags);
405 switch (type & IRQ_TYPE_SENSE_MASK) {
406 case IRQ_TYPE_EDGE_FALLING:
407 gic_set_polarity(irq, GIC_POL_NEG);
408 gic_set_trigger(irq, GIC_TRIG_EDGE);
409 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
410 is_edge = true;
411 break;
412 case IRQ_TYPE_EDGE_RISING:
413 gic_set_polarity(irq, GIC_POL_POS);
414 gic_set_trigger(irq, GIC_TRIG_EDGE);
415 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
416 is_edge = true;
417 break;
418 case IRQ_TYPE_EDGE_BOTH:
419 /* polarity is irrelevant in this case */
420 gic_set_trigger(irq, GIC_TRIG_EDGE);
421 gic_set_dual_edge(irq, GIC_TRIG_DUAL_ENABLE);
422 is_edge = true;
423 break;
424 case IRQ_TYPE_LEVEL_LOW:
425 gic_set_polarity(irq, GIC_POL_NEG);
426 gic_set_trigger(irq, GIC_TRIG_LEVEL);
427 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
428 is_edge = false;
429 break;
430 case IRQ_TYPE_LEVEL_HIGH:
431 default:
432 gic_set_polarity(irq, GIC_POL_POS);
433 gic_set_trigger(irq, GIC_TRIG_LEVEL);
434 gic_set_dual_edge(irq, GIC_TRIG_DUAL_DISABLE);
435 is_edge = false;
436 break;
437 }
438
439 if (is_edge)
440 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
441 handle_edge_irq, NULL);
442 else
443 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
444 handle_level_irq, NULL);
445 spin_unlock_irqrestore(&gic_lock, flags);
446
447 return 0;
448}
449
450#ifdef CONFIG_SMP
451static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
452 bool force)
453{
454 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
455 cpumask_t tmp = CPU_MASK_NONE;
456 unsigned long flags;
457 int i;
458
459 cpumask_and(&tmp, cpumask, cpu_online_mask);
460 if (cpumask_empty(&tmp))
461 return -EINVAL;
462
463 /* Assumption : cpumask refers to a single CPU */
464 spin_lock_irqsave(&gic_lock, flags);
465
466 /* Re-route this IRQ */
467 gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp)));
468
469 /* Update the pcpu_masks */
470 for (i = 0; i < min(gic_vpes, NR_CPUS); i++)
471 clear_bit(irq, pcpu_masks[i].pcpu_mask);
472 set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask);
473
474 cpumask_copy(irq_data_get_affinity_mask(d), cpumask);
475 spin_unlock_irqrestore(&gic_lock, flags);
476
477 return IRQ_SET_MASK_OK_NOCOPY;
478}
479#endif
480
481static struct irq_chip gic_level_irq_controller = {
482 .name = "MIPS GIC",
483 .irq_mask = gic_mask_irq,
484 .irq_unmask = gic_unmask_irq,
485 .irq_set_type = gic_set_type,
486#ifdef CONFIG_SMP
487 .irq_set_affinity = gic_set_affinity,
488#endif
489};
490
491static struct irq_chip gic_edge_irq_controller = {
492 .name = "MIPS GIC",
493 .irq_ack = gic_ack_irq,
494 .irq_mask = gic_mask_irq,
495 .irq_unmask = gic_unmask_irq,
496 .irq_set_type = gic_set_type,
497#ifdef CONFIG_SMP
498 .irq_set_affinity = gic_set_affinity,
499#endif
500 .ipi_send_single = gic_send_ipi,
501};
502
503static void gic_handle_local_int(bool chained)
504{
505 unsigned long pending, masked;
506 unsigned int intr, virq;
507
508 pending = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_PEND));
509 masked = gic_read32(GIC_REG(VPE_LOCAL, GIC_VPE_MASK));
510
511 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
512
513 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
514 while (intr != GIC_NUM_LOCAL_INTRS) {
515 virq = irq_linear_revmap(gic_irq_domain,
516 GIC_LOCAL_TO_HWIRQ(intr));
517 if (chained)
518 generic_handle_irq(virq);
519 else
520 do_IRQ(virq);
521
522 /* go to next pending bit */
523 bitmap_clear(&pending, intr, 1);
524 intr = find_first_bit(&pending, GIC_NUM_LOCAL_INTRS);
525 }
526}
527
528static void gic_mask_local_irq(struct irq_data *d)
529{
530 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
531
532 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_RMASK), 1 << intr);
533}
534
535static void gic_unmask_local_irq(struct irq_data *d)
536{
537 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
538
539 gic_write32(GIC_REG(VPE_LOCAL, GIC_VPE_SMASK), 1 << intr);
540}
541
542static struct irq_chip gic_local_irq_controller = {
543 .name = "MIPS GIC Local",
544 .irq_mask = gic_mask_local_irq,
545 .irq_unmask = gic_unmask_local_irq,
546};
547
548static void gic_mask_local_irq_all_vpes(struct irq_data *d)
549{
550 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
551 int i;
552 unsigned long flags;
553
554 spin_lock_irqsave(&gic_lock, flags);
555 for (i = 0; i < gic_vpes; i++) {
556 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
557 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << intr);
558 }
559 spin_unlock_irqrestore(&gic_lock, flags);
560}
561
562static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
563{
564 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
565 int i;
566 unsigned long flags;
567
568 spin_lock_irqsave(&gic_lock, flags);
569 for (i = 0; i < gic_vpes; i++) {
570 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
571 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SMASK), 1 << intr);
572 }
573 spin_unlock_irqrestore(&gic_lock, flags);
574}
575
576static struct irq_chip gic_all_vpes_local_irq_controller = {
577 .name = "MIPS GIC Local",
578 .irq_mask = gic_mask_local_irq_all_vpes,
579 .irq_unmask = gic_unmask_local_irq_all_vpes,
580};
581
582static void __gic_irq_dispatch(void)
583{
584 gic_handle_local_int(false);
585 gic_handle_shared_int(false);
586}
587
588static void gic_irq_dispatch(struct irq_desc *desc)
589{
590 gic_handle_local_int(true);
591 gic_handle_shared_int(true);
592}
593
594static void __init gic_basic_init(void)
595{
596 unsigned int i;
597
598 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
599
600 /* Setup defaults */
601 for (i = 0; i < gic_shared_intrs; i++) {
602 gic_set_polarity(i, GIC_POL_POS);
603 gic_set_trigger(i, GIC_TRIG_LEVEL);
604 gic_reset_mask(i);
605 }
606
607 for (i = 0; i < gic_vpes; i++) {
608 unsigned int j;
609
610 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
611 for (j = 0; j < GIC_NUM_LOCAL_INTRS; j++) {
612 if (!gic_local_irq_is_routable(j))
613 continue;
614 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_RMASK), 1 << j);
615 }
616 }
617}
618
619static int gic_local_irq_domain_map(struct irq_domain *d, unsigned int virq,
620 irq_hw_number_t hw)
621{
622 int intr = GIC_HWIRQ_TO_LOCAL(hw);
623 int ret = 0;
624 int i;
625 unsigned long flags;
626
627 if (!gic_local_irq_is_routable(intr))
628 return -EPERM;
629
630 /*
631 * HACK: These are all really percpu interrupts, but the rest
632 * of the MIPS kernel code does not use the percpu IRQ API for
633 * the CP0 timer and performance counter interrupts.
634 */
635 switch (intr) {
636 case GIC_LOCAL_INT_TIMER:
637 case GIC_LOCAL_INT_PERFCTR:
638 case GIC_LOCAL_INT_FDC:
639 irq_set_chip_and_handler(virq,
640 &gic_all_vpes_local_irq_controller,
641 handle_percpu_irq);
642 break;
643 default:
644 irq_set_chip_and_handler(virq,
645 &gic_local_irq_controller,
646 handle_percpu_devid_irq);
647 irq_set_percpu_devid(virq);
648 break;
649 }
650
651 spin_lock_irqsave(&gic_lock, flags);
652 for (i = 0; i < gic_vpes; i++) {
653 u32 val = GIC_MAP_TO_PIN_MSK | gic_cpu_pin;
654
655 gic_write(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
656
657 switch (intr) {
658 case GIC_LOCAL_INT_WD:
659 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_WD_MAP), val);
660 break;
661 case GIC_LOCAL_INT_COMPARE:
662 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_COMPARE_MAP),
663 val);
664 break;
665 case GIC_LOCAL_INT_TIMER:
666 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
667 val = GIC_MAP_TO_PIN_MSK | timer_cpu_pin;
668 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
669 val);
670 break;
671 case GIC_LOCAL_INT_PERFCTR:
672 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
673 val);
674 break;
675 case GIC_LOCAL_INT_SWINT0:
676 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT0_MAP),
677 val);
678 break;
679 case GIC_LOCAL_INT_SWINT1:
680 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_SWINT1_MAP),
681 val);
682 break;
683 case GIC_LOCAL_INT_FDC:
684 gic_write32(GIC_REG(VPE_OTHER, GIC_VPE_FDC_MAP), val);
685 break;
686 default:
687 pr_err("Invalid local IRQ %d\n", intr);
688 ret = -EINVAL;
689 break;
690 }
691 }
692 spin_unlock_irqrestore(&gic_lock, flags);
693
694 return ret;
695}
696
697static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
698 irq_hw_number_t hw, unsigned int vpe)
699{
700 int intr = GIC_HWIRQ_TO_SHARED(hw);
701 unsigned long flags;
702 int i;
703
704 irq_set_chip_and_handler(virq, &gic_level_irq_controller,
705 handle_level_irq);
706
707 spin_lock_irqsave(&gic_lock, flags);
708 gic_map_to_pin(intr, gic_cpu_pin);
709 gic_map_to_vpe(intr, vpe);
710 for (i = 0; i < min(gic_vpes, NR_CPUS); i++)
711 clear_bit(intr, pcpu_masks[i].pcpu_mask);
712 set_bit(intr, pcpu_masks[vpe].pcpu_mask);
713 spin_unlock_irqrestore(&gic_lock, flags);
714
715 return 0;
716}
717
718static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
719 irq_hw_number_t hw)
720{
721 if (GIC_HWIRQ_TO_LOCAL(hw) < GIC_NUM_LOCAL_INTRS)
722 return gic_local_irq_domain_map(d, virq, hw);
723 return gic_shared_irq_domain_map(d, virq, hw, 0);
724}
725
726static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
727 unsigned int nr_irqs, void *arg)
728{
729 struct gic_irq_spec *spec = arg;
730 irq_hw_number_t hwirq, base_hwirq;
731 int cpu, ret, i;
732
733 if (spec->type == GIC_DEVICE) {
734 /* verify that it doesn't conflict with an IPI irq */
735 if (test_bit(spec->hwirq, ipi_resrv))
736 return -EBUSY;
737 } else {
738 base_hwirq = find_first_bit(ipi_resrv, gic_shared_intrs);
739 if (base_hwirq == gic_shared_intrs) {
740 return -ENOMEM;
741 }
742
743 /* check that we have enough space */
744 for (i = base_hwirq; i < nr_irqs; i++) {
745 if (!test_bit(i, ipi_resrv))
746 return -EBUSY;
747 }
748 bitmap_clear(ipi_resrv, base_hwirq, nr_irqs);
749
750 /* map the hwirq for each cpu consecutively */
751 i = 0;
752 for_each_cpu(cpu, spec->ipimask) {
753 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
754
755 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
756 &gic_edge_irq_controller,
757 NULL);
758 if (ret)
759 goto error;
760
761 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
762 if (ret)
763 goto error;
764
765 i++;
766 }
767
768 /*
769 * tell the parent about the base hwirq we allocated so it can
770 * set its own domain data
771 */
772 spec->hwirq = base_hwirq;
773 }
774
775 return 0;
776error:
777 bitmap_set(ipi_resrv, base_hwirq, nr_irqs);
778 return ret;
779}
780
781void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
782 unsigned int nr_irqs)
783{
784 irq_hw_number_t base_hwirq;
785 struct irq_data *data;
786
787 data = irq_get_irq_data(virq);
788 if (!data)
789 return;
790
791 base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
792 bitmap_set(ipi_resrv, base_hwirq, nr_irqs);
793}
794
795int gic_irq_domain_match(struct irq_domain *d, struct device_node *node,
796 enum irq_domain_bus_token bus_token)
797{
798 /* this domain should'nt be accessed directly */
799 return 0;
800}
801
802static const struct irq_domain_ops gic_irq_domain_ops = {
803 .map = gic_irq_domain_map,
804 .alloc = gic_irq_domain_alloc,
805 .free = gic_irq_domain_free,
806 .match = gic_irq_domain_match,
807};
808
809static int gic_dev_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
810 const u32 *intspec, unsigned int intsize,
811 irq_hw_number_t *out_hwirq,
812 unsigned int *out_type)
813{
814 if (intsize != 3)
815 return -EINVAL;
816
817 if (intspec[0] == GIC_SHARED)
818 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
819 else if (intspec[0] == GIC_LOCAL)
820 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
821 else
822 return -EINVAL;
823 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
824
825 return 0;
826}
827
828static int gic_dev_domain_alloc(struct irq_domain *d, unsigned int virq,
829 unsigned int nr_irqs, void *arg)
830{
831 struct irq_fwspec *fwspec = arg;
832 struct gic_irq_spec spec = {
833 .type = GIC_DEVICE,
834 .hwirq = fwspec->param[1],
835 };
836 int i, ret;
837 bool is_shared = fwspec->param[0] == GIC_SHARED;
838
839 if (is_shared) {
840 ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &spec);
841 if (ret)
842 return ret;
843 }
844
845 for (i = 0; i < nr_irqs; i++) {
846 irq_hw_number_t hwirq;
847
848 if (is_shared)
849 hwirq = GIC_SHARED_TO_HWIRQ(spec.hwirq + i);
850 else
851 hwirq = GIC_LOCAL_TO_HWIRQ(spec.hwirq + i);
852
853 ret = irq_domain_set_hwirq_and_chip(d, virq + i,
854 hwirq,
855 &gic_level_irq_controller,
856 NULL);
857 if (ret)
858 return ret;
859 }
860
861 return 0;
862}
863
864void gic_dev_domain_free(struct irq_domain *d, unsigned int virq,
865 unsigned int nr_irqs)
866{
867 /* no real allocation is done for dev irqs, so no need to free anything */
868 return;
869}
870
871static struct irq_domain_ops gic_dev_domain_ops = {
872 .xlate = gic_dev_domain_xlate,
873 .alloc = gic_dev_domain_alloc,
874 .free = gic_dev_domain_free,
875};
876
877static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
878 const u32 *intspec, unsigned int intsize,
879 irq_hw_number_t *out_hwirq,
880 unsigned int *out_type)
881{
882 /*
883 * There's nothing to translate here. hwirq is dynamically allocated and
884 * the irq type is always edge triggered.
885 * */
886 *out_hwirq = 0;
887 *out_type = IRQ_TYPE_EDGE_RISING;
888
889 return 0;
890}
891
892static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
893 unsigned int nr_irqs, void *arg)
894{
895 struct cpumask *ipimask = arg;
896 struct gic_irq_spec spec = {
897 .type = GIC_IPI,
898 .ipimask = ipimask
899 };
900 int ret, i;
901
902 ret = irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &spec);
903 if (ret)
904 return ret;
905
906 /* the parent should have set spec.hwirq to the base_hwirq it allocated */
907 for (i = 0; i < nr_irqs; i++) {
908 ret = irq_domain_set_hwirq_and_chip(d, virq + i,
909 GIC_SHARED_TO_HWIRQ(spec.hwirq + i),
910 &gic_edge_irq_controller,
911 NULL);
912 if (ret)
913 goto error;
914
915 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
916 if (ret)
917 goto error;
918 }
919
920 return 0;
921error:
922 irq_domain_free_irqs_parent(d, virq, nr_irqs);
923 return ret;
924}
925
926void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
927 unsigned int nr_irqs)
928{
929 irq_domain_free_irqs_parent(d, virq, nr_irqs);
930}
931
932int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
933 enum irq_domain_bus_token bus_token)
934{
935 bool is_ipi;
936
937 switch (bus_token) {
938 case DOMAIN_BUS_IPI:
939 is_ipi = d->bus_token == bus_token;
940 return to_of_node(d->fwnode) == node && is_ipi;
941 break;
942 default:
943 return 0;
944 }
945}
946
947static struct irq_domain_ops gic_ipi_domain_ops = {
948 .xlate = gic_ipi_domain_xlate,
949 .alloc = gic_ipi_domain_alloc,
950 .free = gic_ipi_domain_free,
951 .match = gic_ipi_domain_match,
952};
953
954static void __init __gic_init(unsigned long gic_base_addr,
955 unsigned long gic_addrspace_size,
956 unsigned int cpu_vec, unsigned int irqbase,
957 struct device_node *node)
958{
959 unsigned int gicconfig;
960 unsigned int v[2];
961
962 __gic_base_addr = gic_base_addr;
963
964 gic_base = ioremap_nocache(gic_base_addr, gic_addrspace_size);
965
966 gicconfig = gic_read(GIC_REG(SHARED, GIC_SH_CONFIG));
967 gic_shared_intrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
968 GIC_SH_CONFIG_NUMINTRS_SHF;
969 gic_shared_intrs = ((gic_shared_intrs + 1) * 8);
970
971 gic_vpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
972 GIC_SH_CONFIG_NUMVPES_SHF;
973 gic_vpes = gic_vpes + 1;
974
975 if (cpu_has_veic) {
976 /* Always use vector 1 in EIC mode */
977 gic_cpu_pin = 0;
978 timer_cpu_pin = gic_cpu_pin;
979 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
980 __gic_irq_dispatch);
981 } else {
982 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
983 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
984 gic_irq_dispatch);
985 /*
986 * With the CMP implementation of SMP (deprecated), other CPUs
987 * are started by the bootloader and put into a timer based
988 * waiting poll loop. We must not re-route those CPU's local
989 * timer interrupts as the wait instruction will never finish,
990 * so just handle whatever CPU interrupt it is routed to by
991 * default.
992 *
993 * This workaround should be removed when CMP support is
994 * dropped.
995 */
996 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
997 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
998 timer_cpu_pin = gic_read32(GIC_REG(VPE_LOCAL,
999 GIC_VPE_TIMER_MAP)) &
1000 GIC_MAP_MSK;
1001 irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
1002 GIC_CPU_PIN_OFFSET +
1003 timer_cpu_pin,
1004 gic_irq_dispatch);
1005 } else {
1006 timer_cpu_pin = gic_cpu_pin;
1007 }
1008 }
1009
1010 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
1011 gic_shared_intrs, irqbase,
1012 &gic_irq_domain_ops, NULL);
1013 if (!gic_irq_domain)
1014 panic("Failed to add GIC IRQ domain");
1015
1016 gic_dev_domain = irq_domain_add_hierarchy(gic_irq_domain, 0,
1017 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
1018 node, &gic_dev_domain_ops, NULL);
1019 if (!gic_dev_domain)
1020 panic("Failed to add GIC DEV domain");
1021
1022 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
1023 IRQ_DOMAIN_FLAG_IPI_PER_CPU,
1024 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
1025 node, &gic_ipi_domain_ops, NULL);
1026 if (!gic_ipi_domain)
1027 panic("Failed to add GIC IPI domain");
1028
1029 gic_ipi_domain->bus_token = DOMAIN_BUS_IPI;
1030
1031 if (node &&
1032 !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
1033 bitmap_set(ipi_resrv, v[0], v[1]);
1034 } else {
1035 /* Make the last 2 * gic_vpes available for IPIs */
1036 bitmap_set(ipi_resrv,
1037 gic_shared_intrs - 2 * gic_vpes,
1038 2 * gic_vpes);
1039 }
1040
1041 gic_basic_init();
1042}
1043
1044void __init gic_init(unsigned long gic_base_addr,
1045 unsigned long gic_addrspace_size,
1046 unsigned int cpu_vec, unsigned int irqbase)
1047{
1048 __gic_init(gic_base_addr, gic_addrspace_size, cpu_vec, irqbase, NULL);
1049}
1050
1051static int __init gic_of_init(struct device_node *node,
1052 struct device_node *parent)
1053{
1054 struct resource res;
1055 unsigned int cpu_vec, i = 0, reserved = 0;
1056 phys_addr_t gic_base;
1057 size_t gic_len;
1058
1059 /* Find the first available CPU vector. */
1060 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
1061 i++, &cpu_vec))
1062 reserved |= BIT(cpu_vec);
1063 for (cpu_vec = 2; cpu_vec < 8; cpu_vec++) {
1064 if (!(reserved & BIT(cpu_vec)))
1065 break;
1066 }
1067 if (cpu_vec == 8) {
1068 pr_err("No CPU vectors available for GIC\n");
1069 return -ENODEV;
1070 }
1071
1072 if (of_address_to_resource(node, 0, &res)) {
1073 /*
1074 * Probe the CM for the GIC base address if not specified
1075 * in the device-tree.
1076 */
1077 if (mips_cm_present()) {
1078 gic_base = read_gcr_gic_base() &
1079 ~CM_GCR_GIC_BASE_GICEN_MSK;
1080 gic_len = 0x20000;
1081 } else {
1082 pr_err("Failed to get GIC memory range\n");
1083 return -ENODEV;
1084 }
1085 } else {
1086 gic_base = res.start;
1087 gic_len = resource_size(&res);
1088 }
1089
1090 if (mips_cm_present())
1091 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN_MSK);
1092 gic_present = true;
1093
1094 __gic_init(gic_base, gic_len, cpu_vec, 0, node);
1095
1096 return 0;
1097}
1098IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
7 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
8 */
9
10#define pr_fmt(fmt) "irq-mips-gic: " fmt
11
12#include <linux/bitfield.h>
13#include <linux/bitmap.h>
14#include <linux/clocksource.h>
15#include <linux/cpuhotplug.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqchip.h>
20#include <linux/irqdomain.h>
21#include <linux/of_address.h>
22#include <linux/percpu.h>
23#include <linux/sched.h>
24#include <linux/smp.h>
25
26#include <asm/mips-cps.h>
27#include <asm/setup.h>
28#include <asm/traps.h>
29
30#include <dt-bindings/interrupt-controller/mips-gic.h>
31
32#define GIC_MAX_INTRS 256
33#define GIC_MAX_LONGS BITS_TO_LONGS(GIC_MAX_INTRS)
34
35/* Add 2 to convert GIC CPU pin to core interrupt */
36#define GIC_CPU_PIN_OFFSET 2
37
38/* Mapped interrupt to pin X, then GIC will generate the vector (X+1). */
39#define GIC_PIN_TO_VEC_OFFSET 1
40
41/* Convert between local/shared IRQ number and GIC HW IRQ number. */
42#define GIC_LOCAL_HWIRQ_BASE 0
43#define GIC_LOCAL_TO_HWIRQ(x) (GIC_LOCAL_HWIRQ_BASE + (x))
44#define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
45#define GIC_SHARED_HWIRQ_BASE GIC_NUM_LOCAL_INTRS
46#define GIC_SHARED_TO_HWIRQ(x) (GIC_SHARED_HWIRQ_BASE + (x))
47#define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
48
49void __iomem *mips_gic_base;
50
51static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[GIC_MAX_LONGS], pcpu_masks);
52
53static DEFINE_SPINLOCK(gic_lock);
54static struct irq_domain *gic_irq_domain;
55static int gic_shared_intrs;
56static unsigned int gic_cpu_pin;
57static unsigned int timer_cpu_pin;
58static struct irq_chip gic_level_irq_controller, gic_edge_irq_controller;
59
60#ifdef CONFIG_GENERIC_IRQ_IPI
61static DECLARE_BITMAP(ipi_resrv, GIC_MAX_INTRS);
62static DECLARE_BITMAP(ipi_available, GIC_MAX_INTRS);
63#endif /* CONFIG_GENERIC_IRQ_IPI */
64
65static struct gic_all_vpes_chip_data {
66 u32 map;
67 bool mask;
68} gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS];
69
70static void gic_clear_pcpu_masks(unsigned int intr)
71{
72 unsigned int i;
73
74 /* Clear the interrupt's bit in all pcpu_masks */
75 for_each_possible_cpu(i)
76 clear_bit(intr, per_cpu_ptr(pcpu_masks, i));
77}
78
79static bool gic_local_irq_is_routable(int intr)
80{
81 u32 vpe_ctl;
82
83 /* All local interrupts are routable in EIC mode. */
84 if (cpu_has_veic)
85 return true;
86
87 vpe_ctl = read_gic_vl_ctl();
88 switch (intr) {
89 case GIC_LOCAL_INT_TIMER:
90 return vpe_ctl & GIC_VX_CTL_TIMER_ROUTABLE;
91 case GIC_LOCAL_INT_PERFCTR:
92 return vpe_ctl & GIC_VX_CTL_PERFCNT_ROUTABLE;
93 case GIC_LOCAL_INT_FDC:
94 return vpe_ctl & GIC_VX_CTL_FDC_ROUTABLE;
95 case GIC_LOCAL_INT_SWINT0:
96 case GIC_LOCAL_INT_SWINT1:
97 return vpe_ctl & GIC_VX_CTL_SWINT_ROUTABLE;
98 default:
99 return true;
100 }
101}
102
103static void gic_bind_eic_interrupt(int irq, int set)
104{
105 /* Convert irq vector # to hw int # */
106 irq -= GIC_PIN_TO_VEC_OFFSET;
107
108 /* Set irq to use shadow set */
109 write_gic_vl_eic_shadow_set(irq, set);
110}
111
112static void gic_send_ipi(struct irq_data *d, unsigned int cpu)
113{
114 irq_hw_number_t hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(d));
115
116 write_gic_wedge(GIC_WEDGE_RW | hwirq);
117}
118
119int gic_get_c0_compare_int(void)
120{
121 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER))
122 return MIPS_CPU_IRQ_BASE + cp0_compare_irq;
123 return irq_create_mapping(gic_irq_domain,
124 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_TIMER));
125}
126
127int gic_get_c0_perfcount_int(void)
128{
129 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_PERFCTR)) {
130 /* Is the performance counter shared with the timer? */
131 if (cp0_perfcount_irq < 0)
132 return -1;
133 return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
134 }
135 return irq_create_mapping(gic_irq_domain,
136 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_PERFCTR));
137}
138
139int gic_get_c0_fdc_int(void)
140{
141 if (!gic_local_irq_is_routable(GIC_LOCAL_INT_FDC)) {
142 /* Is the FDC IRQ even present? */
143 if (cp0_fdc_irq < 0)
144 return -1;
145 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
146 }
147
148 return irq_create_mapping(gic_irq_domain,
149 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_FDC));
150}
151
152static void gic_handle_shared_int(bool chained)
153{
154 unsigned int intr;
155 unsigned long *pcpu_mask;
156 DECLARE_BITMAP(pending, GIC_MAX_INTRS);
157
158 /* Get per-cpu bitmaps */
159 pcpu_mask = this_cpu_ptr(pcpu_masks);
160
161 if (mips_cm_is64)
162 __ioread64_copy(pending, addr_gic_pend(),
163 DIV_ROUND_UP(gic_shared_intrs, 64));
164 else
165 __ioread32_copy(pending, addr_gic_pend(),
166 DIV_ROUND_UP(gic_shared_intrs, 32));
167
168 bitmap_and(pending, pending, pcpu_mask, gic_shared_intrs);
169
170 for_each_set_bit(intr, pending, gic_shared_intrs) {
171 if (chained)
172 generic_handle_domain_irq(gic_irq_domain,
173 GIC_SHARED_TO_HWIRQ(intr));
174 else
175 do_domain_IRQ(gic_irq_domain,
176 GIC_SHARED_TO_HWIRQ(intr));
177 }
178}
179
180static void gic_mask_irq(struct irq_data *d)
181{
182 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
183
184 write_gic_rmask(intr);
185 gic_clear_pcpu_masks(intr);
186}
187
188static void gic_unmask_irq(struct irq_data *d)
189{
190 unsigned int intr = GIC_HWIRQ_TO_SHARED(d->hwirq);
191 unsigned int cpu;
192
193 write_gic_smask(intr);
194
195 gic_clear_pcpu_masks(intr);
196 cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
197 set_bit(intr, per_cpu_ptr(pcpu_masks, cpu));
198}
199
200static void gic_ack_irq(struct irq_data *d)
201{
202 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
203
204 write_gic_wedge(irq);
205}
206
207static int gic_set_type(struct irq_data *d, unsigned int type)
208{
209 unsigned int irq, pol, trig, dual;
210 unsigned long flags;
211
212 irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
213
214 spin_lock_irqsave(&gic_lock, flags);
215 switch (type & IRQ_TYPE_SENSE_MASK) {
216 case IRQ_TYPE_EDGE_FALLING:
217 pol = GIC_POL_FALLING_EDGE;
218 trig = GIC_TRIG_EDGE;
219 dual = GIC_DUAL_SINGLE;
220 break;
221 case IRQ_TYPE_EDGE_RISING:
222 pol = GIC_POL_RISING_EDGE;
223 trig = GIC_TRIG_EDGE;
224 dual = GIC_DUAL_SINGLE;
225 break;
226 case IRQ_TYPE_EDGE_BOTH:
227 pol = 0; /* Doesn't matter */
228 trig = GIC_TRIG_EDGE;
229 dual = GIC_DUAL_DUAL;
230 break;
231 case IRQ_TYPE_LEVEL_LOW:
232 pol = GIC_POL_ACTIVE_LOW;
233 trig = GIC_TRIG_LEVEL;
234 dual = GIC_DUAL_SINGLE;
235 break;
236 case IRQ_TYPE_LEVEL_HIGH:
237 default:
238 pol = GIC_POL_ACTIVE_HIGH;
239 trig = GIC_TRIG_LEVEL;
240 dual = GIC_DUAL_SINGLE;
241 break;
242 }
243
244 change_gic_pol(irq, pol);
245 change_gic_trig(irq, trig);
246 change_gic_dual(irq, dual);
247
248 if (trig == GIC_TRIG_EDGE)
249 irq_set_chip_handler_name_locked(d, &gic_edge_irq_controller,
250 handle_edge_irq, NULL);
251 else
252 irq_set_chip_handler_name_locked(d, &gic_level_irq_controller,
253 handle_level_irq, NULL);
254 spin_unlock_irqrestore(&gic_lock, flags);
255
256 return 0;
257}
258
259#ifdef CONFIG_SMP
260static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
261 bool force)
262{
263 unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq);
264 unsigned long flags;
265 unsigned int cpu;
266
267 cpu = cpumask_first_and(cpumask, cpu_online_mask);
268 if (cpu >= NR_CPUS)
269 return -EINVAL;
270
271 /* Assumption : cpumask refers to a single CPU */
272 spin_lock_irqsave(&gic_lock, flags);
273
274 /* Re-route this IRQ */
275 write_gic_map_vp(irq, BIT(mips_cm_vp_id(cpu)));
276
277 /* Update the pcpu_masks */
278 gic_clear_pcpu_masks(irq);
279 if (read_gic_mask(irq))
280 set_bit(irq, per_cpu_ptr(pcpu_masks, cpu));
281
282 irq_data_update_effective_affinity(d, cpumask_of(cpu));
283 spin_unlock_irqrestore(&gic_lock, flags);
284
285 return IRQ_SET_MASK_OK;
286}
287#endif
288
289static struct irq_chip gic_level_irq_controller = {
290 .name = "MIPS GIC",
291 .irq_mask = gic_mask_irq,
292 .irq_unmask = gic_unmask_irq,
293 .irq_set_type = gic_set_type,
294#ifdef CONFIG_SMP
295 .irq_set_affinity = gic_set_affinity,
296#endif
297};
298
299static struct irq_chip gic_edge_irq_controller = {
300 .name = "MIPS GIC",
301 .irq_ack = gic_ack_irq,
302 .irq_mask = gic_mask_irq,
303 .irq_unmask = gic_unmask_irq,
304 .irq_set_type = gic_set_type,
305#ifdef CONFIG_SMP
306 .irq_set_affinity = gic_set_affinity,
307#endif
308 .ipi_send_single = gic_send_ipi,
309};
310
311static void gic_handle_local_int(bool chained)
312{
313 unsigned long pending, masked;
314 unsigned int intr;
315
316 pending = read_gic_vl_pend();
317 masked = read_gic_vl_mask();
318
319 bitmap_and(&pending, &pending, &masked, GIC_NUM_LOCAL_INTRS);
320
321 for_each_set_bit(intr, &pending, GIC_NUM_LOCAL_INTRS) {
322 if (chained)
323 generic_handle_domain_irq(gic_irq_domain,
324 GIC_LOCAL_TO_HWIRQ(intr));
325 else
326 do_domain_IRQ(gic_irq_domain,
327 GIC_LOCAL_TO_HWIRQ(intr));
328 }
329}
330
331static void gic_mask_local_irq(struct irq_data *d)
332{
333 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
334
335 write_gic_vl_rmask(BIT(intr));
336}
337
338static void gic_unmask_local_irq(struct irq_data *d)
339{
340 int intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
341
342 write_gic_vl_smask(BIT(intr));
343}
344
345static struct irq_chip gic_local_irq_controller = {
346 .name = "MIPS GIC Local",
347 .irq_mask = gic_mask_local_irq,
348 .irq_unmask = gic_unmask_local_irq,
349};
350
351static void gic_mask_local_irq_all_vpes(struct irq_data *d)
352{
353 struct gic_all_vpes_chip_data *cd;
354 unsigned long flags;
355 int intr, cpu;
356
357 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
358 cd = irq_data_get_irq_chip_data(d);
359 cd->mask = false;
360
361 spin_lock_irqsave(&gic_lock, flags);
362 for_each_online_cpu(cpu) {
363 write_gic_vl_other(mips_cm_vp_id(cpu));
364 write_gic_vo_rmask(BIT(intr));
365 }
366 spin_unlock_irqrestore(&gic_lock, flags);
367}
368
369static void gic_unmask_local_irq_all_vpes(struct irq_data *d)
370{
371 struct gic_all_vpes_chip_data *cd;
372 unsigned long flags;
373 int intr, cpu;
374
375 intr = GIC_HWIRQ_TO_LOCAL(d->hwirq);
376 cd = irq_data_get_irq_chip_data(d);
377 cd->mask = true;
378
379 spin_lock_irqsave(&gic_lock, flags);
380 for_each_online_cpu(cpu) {
381 write_gic_vl_other(mips_cm_vp_id(cpu));
382 write_gic_vo_smask(BIT(intr));
383 }
384 spin_unlock_irqrestore(&gic_lock, flags);
385}
386
387static void gic_all_vpes_irq_cpu_online(void)
388{
389 static const unsigned int local_intrs[] = {
390 GIC_LOCAL_INT_TIMER,
391 GIC_LOCAL_INT_PERFCTR,
392 GIC_LOCAL_INT_FDC,
393 };
394 unsigned long flags;
395 int i;
396
397 spin_lock_irqsave(&gic_lock, flags);
398
399 for (i = 0; i < ARRAY_SIZE(local_intrs); i++) {
400 unsigned int intr = local_intrs[i];
401 struct gic_all_vpes_chip_data *cd;
402
403 cd = &gic_all_vpes_chip_data[intr];
404 write_gic_vl_map(mips_gic_vx_map_reg(intr), cd->map);
405 if (cd->mask)
406 write_gic_vl_smask(BIT(intr));
407 }
408
409 spin_unlock_irqrestore(&gic_lock, flags);
410}
411
412static struct irq_chip gic_all_vpes_local_irq_controller = {
413 .name = "MIPS GIC Local",
414 .irq_mask = gic_mask_local_irq_all_vpes,
415 .irq_unmask = gic_unmask_local_irq_all_vpes,
416};
417
418static void __gic_irq_dispatch(void)
419{
420 gic_handle_local_int(false);
421 gic_handle_shared_int(false);
422}
423
424static void gic_irq_dispatch(struct irq_desc *desc)
425{
426 gic_handle_local_int(true);
427 gic_handle_shared_int(true);
428}
429
430static int gic_shared_irq_domain_map(struct irq_domain *d, unsigned int virq,
431 irq_hw_number_t hw, unsigned int cpu)
432{
433 int intr = GIC_HWIRQ_TO_SHARED(hw);
434 struct irq_data *data;
435 unsigned long flags;
436
437 data = irq_get_irq_data(virq);
438
439 spin_lock_irqsave(&gic_lock, flags);
440 write_gic_map_pin(intr, GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin);
441 write_gic_map_vp(intr, BIT(mips_cm_vp_id(cpu)));
442 irq_data_update_effective_affinity(data, cpumask_of(cpu));
443 spin_unlock_irqrestore(&gic_lock, flags);
444
445 return 0;
446}
447
448static int gic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
449 const u32 *intspec, unsigned int intsize,
450 irq_hw_number_t *out_hwirq,
451 unsigned int *out_type)
452{
453 if (intsize != 3)
454 return -EINVAL;
455
456 if (intspec[0] == GIC_SHARED)
457 *out_hwirq = GIC_SHARED_TO_HWIRQ(intspec[1]);
458 else if (intspec[0] == GIC_LOCAL)
459 *out_hwirq = GIC_LOCAL_TO_HWIRQ(intspec[1]);
460 else
461 return -EINVAL;
462 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
463
464 return 0;
465}
466
467static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq,
468 irq_hw_number_t hwirq)
469{
470 struct gic_all_vpes_chip_data *cd;
471 unsigned long flags;
472 unsigned int intr;
473 int err, cpu;
474 u32 map;
475
476 if (hwirq >= GIC_SHARED_HWIRQ_BASE) {
477#ifdef CONFIG_GENERIC_IRQ_IPI
478 /* verify that shared irqs don't conflict with an IPI irq */
479 if (test_bit(GIC_HWIRQ_TO_SHARED(hwirq), ipi_resrv))
480 return -EBUSY;
481#endif /* CONFIG_GENERIC_IRQ_IPI */
482
483 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
484 &gic_level_irq_controller,
485 NULL);
486 if (err)
487 return err;
488
489 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
490 return gic_shared_irq_domain_map(d, virq, hwirq, 0);
491 }
492
493 intr = GIC_HWIRQ_TO_LOCAL(hwirq);
494 map = GIC_MAP_PIN_MAP_TO_PIN | gic_cpu_pin;
495
496 /*
497 * If adding support for more per-cpu interrupts, keep the
498 * array in gic_all_vpes_irq_cpu_online() in sync.
499 */
500 switch (intr) {
501 case GIC_LOCAL_INT_TIMER:
502 /* CONFIG_MIPS_CMP workaround (see __gic_init) */
503 map = GIC_MAP_PIN_MAP_TO_PIN | timer_cpu_pin;
504 fallthrough;
505 case GIC_LOCAL_INT_PERFCTR:
506 case GIC_LOCAL_INT_FDC:
507 /*
508 * HACK: These are all really percpu interrupts, but
509 * the rest of the MIPS kernel code does not use the
510 * percpu IRQ API for them.
511 */
512 cd = &gic_all_vpes_chip_data[intr];
513 cd->map = map;
514 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
515 &gic_all_vpes_local_irq_controller,
516 cd);
517 if (err)
518 return err;
519
520 irq_set_handler(virq, handle_percpu_irq);
521 break;
522
523 default:
524 err = irq_domain_set_hwirq_and_chip(d, virq, hwirq,
525 &gic_local_irq_controller,
526 NULL);
527 if (err)
528 return err;
529
530 irq_set_handler(virq, handle_percpu_devid_irq);
531 irq_set_percpu_devid(virq);
532 break;
533 }
534
535 if (!gic_local_irq_is_routable(intr))
536 return -EPERM;
537
538 spin_lock_irqsave(&gic_lock, flags);
539 for_each_online_cpu(cpu) {
540 write_gic_vl_other(mips_cm_vp_id(cpu));
541 write_gic_vo_map(mips_gic_vx_map_reg(intr), map);
542 }
543 spin_unlock_irqrestore(&gic_lock, flags);
544
545 return 0;
546}
547
548static int gic_irq_domain_alloc(struct irq_domain *d, unsigned int virq,
549 unsigned int nr_irqs, void *arg)
550{
551 struct irq_fwspec *fwspec = arg;
552 irq_hw_number_t hwirq;
553
554 if (fwspec->param[0] == GIC_SHARED)
555 hwirq = GIC_SHARED_TO_HWIRQ(fwspec->param[1]);
556 else
557 hwirq = GIC_LOCAL_TO_HWIRQ(fwspec->param[1]);
558
559 return gic_irq_domain_map(d, virq, hwirq);
560}
561
562void gic_irq_domain_free(struct irq_domain *d, unsigned int virq,
563 unsigned int nr_irqs)
564{
565}
566
567static const struct irq_domain_ops gic_irq_domain_ops = {
568 .xlate = gic_irq_domain_xlate,
569 .alloc = gic_irq_domain_alloc,
570 .free = gic_irq_domain_free,
571 .map = gic_irq_domain_map,
572};
573
574#ifdef CONFIG_GENERIC_IRQ_IPI
575
576static int gic_ipi_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
577 const u32 *intspec, unsigned int intsize,
578 irq_hw_number_t *out_hwirq,
579 unsigned int *out_type)
580{
581 /*
582 * There's nothing to translate here. hwirq is dynamically allocated and
583 * the irq type is always edge triggered.
584 * */
585 *out_hwirq = 0;
586 *out_type = IRQ_TYPE_EDGE_RISING;
587
588 return 0;
589}
590
591static int gic_ipi_domain_alloc(struct irq_domain *d, unsigned int virq,
592 unsigned int nr_irqs, void *arg)
593{
594 struct cpumask *ipimask = arg;
595 irq_hw_number_t hwirq, base_hwirq;
596 int cpu, ret, i;
597
598 base_hwirq = find_first_bit(ipi_available, gic_shared_intrs);
599 if (base_hwirq == gic_shared_intrs)
600 return -ENOMEM;
601
602 /* check that we have enough space */
603 for (i = base_hwirq; i < nr_irqs; i++) {
604 if (!test_bit(i, ipi_available))
605 return -EBUSY;
606 }
607 bitmap_clear(ipi_available, base_hwirq, nr_irqs);
608
609 /* map the hwirq for each cpu consecutively */
610 i = 0;
611 for_each_cpu(cpu, ipimask) {
612 hwirq = GIC_SHARED_TO_HWIRQ(base_hwirq + i);
613
614 ret = irq_domain_set_hwirq_and_chip(d, virq + i, hwirq,
615 &gic_edge_irq_controller,
616 NULL);
617 if (ret)
618 goto error;
619
620 ret = irq_domain_set_hwirq_and_chip(d->parent, virq + i, hwirq,
621 &gic_edge_irq_controller,
622 NULL);
623 if (ret)
624 goto error;
625
626 ret = irq_set_irq_type(virq + i, IRQ_TYPE_EDGE_RISING);
627 if (ret)
628 goto error;
629
630 ret = gic_shared_irq_domain_map(d, virq + i, hwirq, cpu);
631 if (ret)
632 goto error;
633
634 i++;
635 }
636
637 return 0;
638error:
639 bitmap_set(ipi_available, base_hwirq, nr_irqs);
640 return ret;
641}
642
643static void gic_ipi_domain_free(struct irq_domain *d, unsigned int virq,
644 unsigned int nr_irqs)
645{
646 irq_hw_number_t base_hwirq;
647 struct irq_data *data;
648
649 data = irq_get_irq_data(virq);
650 if (!data)
651 return;
652
653 base_hwirq = GIC_HWIRQ_TO_SHARED(irqd_to_hwirq(data));
654 bitmap_set(ipi_available, base_hwirq, nr_irqs);
655}
656
657static int gic_ipi_domain_match(struct irq_domain *d, struct device_node *node,
658 enum irq_domain_bus_token bus_token)
659{
660 bool is_ipi;
661
662 switch (bus_token) {
663 case DOMAIN_BUS_IPI:
664 is_ipi = d->bus_token == bus_token;
665 return (!node || to_of_node(d->fwnode) == node) && is_ipi;
666 break;
667 default:
668 return 0;
669 }
670}
671
672static const struct irq_domain_ops gic_ipi_domain_ops = {
673 .xlate = gic_ipi_domain_xlate,
674 .alloc = gic_ipi_domain_alloc,
675 .free = gic_ipi_domain_free,
676 .match = gic_ipi_domain_match,
677};
678
679static int gic_register_ipi_domain(struct device_node *node)
680{
681 struct irq_domain *gic_ipi_domain;
682 unsigned int v[2], num_ipis;
683
684 gic_ipi_domain = irq_domain_add_hierarchy(gic_irq_domain,
685 IRQ_DOMAIN_FLAG_IPI_PER_CPU,
686 GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
687 node, &gic_ipi_domain_ops, NULL);
688 if (!gic_ipi_domain) {
689 pr_err("Failed to add IPI domain");
690 return -ENXIO;
691 }
692
693 irq_domain_update_bus_token(gic_ipi_domain, DOMAIN_BUS_IPI);
694
695 if (node &&
696 !of_property_read_u32_array(node, "mti,reserved-ipi-vectors", v, 2)) {
697 bitmap_set(ipi_resrv, v[0], v[1]);
698 } else {
699 /*
700 * Reserve 2 interrupts per possible CPU/VP for use as IPIs,
701 * meeting the requirements of arch/mips SMP.
702 */
703 num_ipis = 2 * num_possible_cpus();
704 bitmap_set(ipi_resrv, gic_shared_intrs - num_ipis, num_ipis);
705 }
706
707 bitmap_copy(ipi_available, ipi_resrv, GIC_MAX_INTRS);
708
709 return 0;
710}
711
712#else /* !CONFIG_GENERIC_IRQ_IPI */
713
714static inline int gic_register_ipi_domain(struct device_node *node)
715{
716 return 0;
717}
718
719#endif /* !CONFIG_GENERIC_IRQ_IPI */
720
721static int gic_cpu_startup(unsigned int cpu)
722{
723 /* Enable or disable EIC */
724 change_gic_vl_ctl(GIC_VX_CTL_EIC,
725 cpu_has_veic ? GIC_VX_CTL_EIC : 0);
726
727 /* Clear all local IRQ masks (ie. disable all local interrupts) */
728 write_gic_vl_rmask(~0);
729
730 /* Enable desired interrupts */
731 gic_all_vpes_irq_cpu_online();
732
733 return 0;
734}
735
736static int __init gic_of_init(struct device_node *node,
737 struct device_node *parent)
738{
739 unsigned int cpu_vec, i, gicconfig;
740 unsigned long reserved;
741 phys_addr_t gic_base;
742 struct resource res;
743 size_t gic_len;
744 int ret;
745
746 /* Find the first available CPU vector. */
747 i = 0;
748 reserved = (C_SW0 | C_SW1) >> __ffs(C_SW0);
749 while (!of_property_read_u32_index(node, "mti,reserved-cpu-vectors",
750 i++, &cpu_vec))
751 reserved |= BIT(cpu_vec);
752
753 cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
754 if (cpu_vec == hweight_long(ST0_IM)) {
755 pr_err("No CPU vectors available\n");
756 return -ENODEV;
757 }
758
759 if (of_address_to_resource(node, 0, &res)) {
760 /*
761 * Probe the CM for the GIC base address if not specified
762 * in the device-tree.
763 */
764 if (mips_cm_present()) {
765 gic_base = read_gcr_gic_base() &
766 ~CM_GCR_GIC_BASE_GICEN;
767 gic_len = 0x20000;
768 pr_warn("Using inherited base address %pa\n",
769 &gic_base);
770 } else {
771 pr_err("Failed to get memory range\n");
772 return -ENODEV;
773 }
774 } else {
775 gic_base = res.start;
776 gic_len = resource_size(&res);
777 }
778
779 if (mips_cm_present()) {
780 write_gcr_gic_base(gic_base | CM_GCR_GIC_BASE_GICEN);
781 /* Ensure GIC region is enabled before trying to access it */
782 __sync();
783 }
784
785 mips_gic_base = ioremap(gic_base, gic_len);
786 if (!mips_gic_base) {
787 pr_err("Failed to ioremap gic_base\n");
788 return -ENOMEM;
789 }
790
791 gicconfig = read_gic_config();
792 gic_shared_intrs = FIELD_GET(GIC_CONFIG_NUMINTERRUPTS, gicconfig);
793 gic_shared_intrs = (gic_shared_intrs + 1) * 8;
794
795 if (cpu_has_veic) {
796 /* Always use vector 1 in EIC mode */
797 gic_cpu_pin = 0;
798 timer_cpu_pin = gic_cpu_pin;
799 set_vi_handler(gic_cpu_pin + GIC_PIN_TO_VEC_OFFSET,
800 __gic_irq_dispatch);
801 } else {
802 gic_cpu_pin = cpu_vec - GIC_CPU_PIN_OFFSET;
803 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + cpu_vec,
804 gic_irq_dispatch);
805 /*
806 * With the CMP implementation of SMP (deprecated), other CPUs
807 * are started by the bootloader and put into a timer based
808 * waiting poll loop. We must not re-route those CPU's local
809 * timer interrupts as the wait instruction will never finish,
810 * so just handle whatever CPU interrupt it is routed to by
811 * default.
812 *
813 * This workaround should be removed when CMP support is
814 * dropped.
815 */
816 if (IS_ENABLED(CONFIG_MIPS_CMP) &&
817 gic_local_irq_is_routable(GIC_LOCAL_INT_TIMER)) {
818 timer_cpu_pin = read_gic_vl_timer_map() & GIC_MAP_PIN_MAP;
819 irq_set_chained_handler(MIPS_CPU_IRQ_BASE +
820 GIC_CPU_PIN_OFFSET +
821 timer_cpu_pin,
822 gic_irq_dispatch);
823 } else {
824 timer_cpu_pin = gic_cpu_pin;
825 }
826 }
827
828 gic_irq_domain = irq_domain_add_simple(node, GIC_NUM_LOCAL_INTRS +
829 gic_shared_intrs, 0,
830 &gic_irq_domain_ops, NULL);
831 if (!gic_irq_domain) {
832 pr_err("Failed to add IRQ domain");
833 return -ENXIO;
834 }
835
836 ret = gic_register_ipi_domain(node);
837 if (ret)
838 return ret;
839
840 board_bind_eic_interrupt = &gic_bind_eic_interrupt;
841
842 /* Setup defaults */
843 for (i = 0; i < gic_shared_intrs; i++) {
844 change_gic_pol(i, GIC_POL_ACTIVE_HIGH);
845 change_gic_trig(i, GIC_TRIG_LEVEL);
846 write_gic_rmask(i);
847 }
848
849 return cpuhp_setup_state(CPUHP_AP_IRQ_MIPS_GIC_STARTING,
850 "irqchip/mips/gic:starting",
851 gic_cpu_startup, NULL);
852}
853IRQCHIP_DECLARE(mips_gic, "mti,gic", gic_of_init);