1/*
  2 * Meta External interrupt code.
  3 *
  4 * Copyright (C) 2005-2012 Imagination Technologies Ltd.
  5 *
  6 * External interrupts on Meta are configured at two-levels, in the CPU core and
  7 * in the external trigger block. Interrupts from SoC peripherals are
  8 * multiplexed onto a single Meta CPU "trigger" - traditionally it has always
  9 * been trigger 2 (TR2). For info on how de-multiplexing happens check out
 10 * meta_intc_irq_demux().
 11 */
 12
 13#include <linux/interrupt.h>
 14#include <linux/irqchip/metag-ext.h>
 15#include <linux/irqdomain.h>
 16#include <linux/io.h>
 17#include <linux/of.h>
 18#include <linux/slab.h>
 19#include <linux/syscore_ops.h>
 20
 21#include <asm/irq.h>
 22#include <asm/hwthread.h>
 23
 24#define HWSTAT_STRIDE 8
 25#define HWVEC_BLK_STRIDE 0x1000
 26
 27/**
 28 * struct meta_intc_priv - private meta external interrupt data
 29 * @nr_banks:		Number of interrupt banks
 30 * @domain:		IRQ domain for all banks of external IRQs
 31 * @unmasked:		Record of unmasked IRQs
 32 * @levels_altered:	Record of altered level bits
 33 */
 34struct meta_intc_priv {
 35	unsigned int		nr_banks;
 36	struct irq_domain	*domain;
 37
 38	unsigned long		unmasked[4];
 39
 40#ifdef CONFIG_METAG_SUSPEND_MEM
 41	unsigned long		levels_altered[4];
 42#endif
 43};
 44
 45/* Private data for the one and only external interrupt controller */
 46static struct meta_intc_priv meta_intc_priv;
 47
 48/**
 49 * meta_intc_offset() - Get the offset into the bank of a hardware IRQ number
 50 * @hw:		Hardware IRQ number (within external trigger block)
 51 *
 52 * Returns:	Bit offset into the IRQ's bank registers
 53 */
 54static unsigned int meta_intc_offset(irq_hw_number_t hw)
 55{
 56	return hw & 0x1f;
 57}
 58
 59/**
 60 * meta_intc_bank() - Get the bank number of a hardware IRQ number
 61 * @hw:		Hardware IRQ number (within external trigger block)
 62 *
 63 * Returns:	Bank number indicating which register the IRQ's bits are
 64 */
 65static unsigned int meta_intc_bank(irq_hw_number_t hw)
 66{
 67	return hw >> 5;
 68}
 69
 70/**
 71 * meta_intc_stat_addr() - Get the address of a HWSTATEXT register
 72 * @hw:		Hardware IRQ number (within external trigger block)
 73 *
 74 * Returns:	Address of a HWSTATEXT register containing the status bit for
 75 *		the specified hardware IRQ number
 76 */
 77static void __iomem *meta_intc_stat_addr(irq_hw_number_t hw)
 78{
 79	return (void __iomem *)(HWSTATEXT +
 80				HWSTAT_STRIDE * meta_intc_bank(hw));
 81}
 82
 83/**
 84 * meta_intc_level_addr() - Get the address of a HWLEVELEXT register
 85 * @hw:		Hardware IRQ number (within external trigger block)
 86 *
 87 * Returns:	Address of a HWLEVELEXT register containing the sense bit for
 88 *		the specified hardware IRQ number
 89 */
 90static void __iomem *meta_intc_level_addr(irq_hw_number_t hw)
 91{
 92	return (void __iomem *)(HWLEVELEXT +
 93				HWSTAT_STRIDE * meta_intc_bank(hw));
 94}
 95
 96/**
 97 * meta_intc_mask_addr() - Get the address of a HWMASKEXT register
 98 * @hw:		Hardware IRQ number (within external trigger block)
 99 *
100 * Returns:	Address of a HWMASKEXT register containing the mask bit for the
101 *		specified hardware IRQ number
102 */
103static void __iomem *meta_intc_mask_addr(irq_hw_number_t hw)
104{
105	return (void __iomem *)(HWMASKEXT +
106				HWSTAT_STRIDE * meta_intc_bank(hw));
107}
108
109/**
110 * meta_intc_vec_addr() - Get the vector address of a hardware interrupt
111 * @hw:		Hardware IRQ number (within external trigger block)
112 *
113 * Returns:	Address of a HWVECEXT register controlling the core trigger to
114 *		vector the IRQ onto
115 */
116static inline void __iomem *meta_intc_vec_addr(irq_hw_number_t hw)
117{
118	return (void __iomem *)(HWVEC0EXT +
119				HWVEC_BLK_STRIDE * meta_intc_bank(hw) +
120				HWVECnEXT_STRIDE * meta_intc_offset(hw));
121}
122
123/**
124 * meta_intc_startup_irq() - set up an external irq
125 * @data:	data for the external irq to start up
126 *
127 * Multiplex interrupts for irq onto TR2. Clear any pending interrupts and
128 * unmask irq, both using the appropriate callbacks.
129 */
130static unsigned int meta_intc_startup_irq(struct irq_data *data)
131{
132	irq_hw_number_t hw = data->hwirq;
133	void __iomem *vec_addr = meta_intc_vec_addr(hw);
134	int thread = hard_processor_id();
135
136	/* Perform any necessary acking. */
137	if (data->chip->irq_ack)
138		data->chip->irq_ack(data);
139
140	/* Wire up this interrupt to the core with HWVECxEXT. */
141	metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr);
142
143	/* Perform any necessary unmasking. */
144	data->chip->irq_unmask(data);
145
146	return 0;
147}
148
149/**
150 * meta_intc_shutdown_irq() - turn off an external irq
151 * @data:	data for the external irq to turn off
152 *
153 * Mask irq using the appropriate callback and stop muxing it onto TR2.
154 */
155static void meta_intc_shutdown_irq(struct irq_data *data)
156{
157	irq_hw_number_t hw = data->hwirq;
158	void __iomem *vec_addr = meta_intc_vec_addr(hw);
159
160	/* Mask the IRQ */
161	data->chip->irq_mask(data);
162
163	/*
164	 * Disable the IRQ at the core by removing the interrupt from
165	 * the HW vector mapping.
166	 */
167	metag_out32(0, vec_addr);
168}
169
170/**
171 * meta_intc_ack_irq() - acknowledge an external irq
172 * @data:	data for the external irq to ack
173 *
174 * Clear down an edge interrupt in the status register.
175 */
176static void meta_intc_ack_irq(struct irq_data *data)
177{
178	irq_hw_number_t hw = data->hwirq;
179	unsigned int bit = 1 << meta_intc_offset(hw);
180	void __iomem *stat_addr = meta_intc_stat_addr(hw);
181
182	/* Ack the int, if it is still 'on'.
183	 * NOTE - this only works for edge triggered interrupts.
184	 */
185	if (metag_in32(stat_addr) & bit)
186		metag_out32(bit, stat_addr);
187}
188
189/**
190 * record_irq_is_masked() - record the IRQ masked so it doesn't get handled
191 * @data:	data for the external irq to record
192 *
193 * This should get called whenever an external IRQ is masked (by whichever
194 * callback is used). It records the IRQ masked so that it doesn't get handled
195 * if it still shows up in the status register.
196 */
197static void record_irq_is_masked(struct irq_data *data)
198{
199	struct meta_intc_priv *priv = &meta_intc_priv;
200	irq_hw_number_t hw = data->hwirq;
201
202	clear_bit(meta_intc_offset(hw), &priv->unmasked[meta_intc_bank(hw)]);
203}
204
205/**
206 * record_irq_is_unmasked() - record the IRQ unmasked so it can be handled
207 * @data:	data for the external irq to record
208 *
209 * This should get called whenever an external IRQ is unmasked (by whichever
210 * callback is used). It records the IRQ unmasked so that it gets handled if it
211 * shows up in the status register.
212 */
213static void record_irq_is_unmasked(struct irq_data *data)
214{
215	struct meta_intc_priv *priv = &meta_intc_priv;
216	irq_hw_number_t hw = data->hwirq;
217
218	set_bit(meta_intc_offset(hw), &priv->unmasked[meta_intc_bank(hw)]);
219}
220
221/*
222 * For use by wrapper IRQ drivers
223 */
224
225/**
226 * meta_intc_mask_irq_simple() - minimal mask used by wrapper IRQ drivers
227 * @data:	data for the external irq being masked
228 *
229 * This should be called by any wrapper IRQ driver mask functions. it doesn't do
230 * any masking but records the IRQ as masked so that the core code knows the
231 * mask has taken place. It is the callers responsibility to ensure that the IRQ
232 * won't trigger an interrupt to the core.
233 */
234void meta_intc_mask_irq_simple(struct irq_data *data)
235{
236	record_irq_is_masked(data);
237}
238
239/**
240 * meta_intc_unmask_irq_simple() - minimal unmask used by wrapper IRQ drivers
241 * @data:	data for the external irq being unmasked
242 *
243 * This should be called by any wrapper IRQ driver unmask functions. it doesn't
244 * do any unmasking but records the IRQ as unmasked so that the core code knows
245 * the unmask has taken place. It is the callers responsibility to ensure that
246 * the IRQ can now trigger an interrupt to the core.
247 */
248void meta_intc_unmask_irq_simple(struct irq_data *data)
249{
250	record_irq_is_unmasked(data);
251}
252
253
254/**
255 * meta_intc_mask_irq() - mask an external irq using HWMASKEXT
256 * @data:	data for the external irq to mask
257 *
258 * This is a default implementation of a mask function which makes use of the
259 * HWMASKEXT registers available in newer versions.
260 *
261 * Earlier versions without these registers should use SoC level IRQ masking
262 * which call the meta_intc_*_simple() functions above, or if that isn't
263 * available should use the fallback meta_intc_*_nomask() functions below.
264 */
265static void meta_intc_mask_irq(struct irq_data *data)
266{
267	irq_hw_number_t hw = data->hwirq;
268	unsigned int bit = 1 << meta_intc_offset(hw);
269	void __iomem *mask_addr = meta_intc_mask_addr(hw);
270	unsigned long flags;
271
272	record_irq_is_masked(data);
273
274	/* update the interrupt mask */
275	__global_lock2(flags);
276	metag_out32(metag_in32(mask_addr) & ~bit, mask_addr);
277	__global_unlock2(flags);
278}
279
280/**
281 * meta_intc_unmask_irq() - unmask an external irq using HWMASKEXT
282 * @data:	data for the external irq to unmask
283 *
284 * This is a default implementation of an unmask function which makes use of the
285 * HWMASKEXT registers available on new versions. It should be paired with
286 * meta_intc_mask_irq() above.
287 */
288static void meta_intc_unmask_irq(struct irq_data *data)
289{
290	irq_hw_number_t hw = data->hwirq;
291	unsigned int bit = 1 << meta_intc_offset(hw);
292	void __iomem *mask_addr = meta_intc_mask_addr(hw);
293	unsigned long flags;
294
295	record_irq_is_unmasked(data);
296
297	/* update the interrupt mask */
298	__global_lock2(flags);
299	metag_out32(metag_in32(mask_addr) | bit, mask_addr);
300	__global_unlock2(flags);
301}
302
303/**
304 * meta_intc_mask_irq_nomask() - mask an external irq by unvectoring
305 * @data:	data for the external irq to mask
306 *
307 * This is the version of the mask function for older versions which don't have
308 * HWMASKEXT registers, or a SoC level means of masking IRQs. Instead the IRQ is
309 * unvectored from the core and retriggered if necessary later.
310 */
311static void meta_intc_mask_irq_nomask(struct irq_data *data)
312{
313	irq_hw_number_t hw = data->hwirq;
314	void __iomem *vec_addr = meta_intc_vec_addr(hw);
315
316	record_irq_is_masked(data);
317
318	/* there is no interrupt mask, so unvector the interrupt */
319	metag_out32(0, vec_addr);
320}
321
322/**
323 * meta_intc_unmask_edge_irq_nomask() - unmask an edge irq by revectoring
324 * @data:	data for the external irq to unmask
325 *
326 * This is the version of the unmask function for older versions which don't
327 * have HWMASKEXT registers, or a SoC level means of masking IRQs. Instead the
328 * IRQ is revectored back to the core and retriggered if necessary.
329 *
330 * The retriggering done by this function is specific to edge interrupts.
331 */
332static void meta_intc_unmask_edge_irq_nomask(struct irq_data *data)
333{
334	irq_hw_number_t hw = data->hwirq;
335	unsigned int bit = 1 << meta_intc_offset(hw);
336	void __iomem *stat_addr = meta_intc_stat_addr(hw);
337	void __iomem *vec_addr = meta_intc_vec_addr(hw);
338	unsigned int thread = hard_processor_id();
339
340	record_irq_is_unmasked(data);
341
342	/* there is no interrupt mask, so revector the interrupt */
343	metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr);
344
345	/*
346	 * Re-trigger interrupt
347	 *
348	 * Writing a 1 toggles, and a 0->1 transition triggers. We only
349	 * retrigger if the status bit is already set, which means we
350	 * need to clear it first. Retriggering is fundamentally racy
351	 * because if the interrupt fires again after we clear it we
352	 * could end up clearing it again and the interrupt handler
353	 * thinking it hasn't fired. Therefore we need to keep trying to
354	 * retrigger until the bit is set.
355	 */
356	if (metag_in32(stat_addr) & bit) {
357		metag_out32(bit, stat_addr);
358		while (!(metag_in32(stat_addr) & bit))
359			metag_out32(bit, stat_addr);
360	}
361}
362
363/**
364 * meta_intc_unmask_level_irq_nomask() - unmask a level irq by revectoring
365 * @data:	data for the external irq to unmask
366 *
367 * This is the version of the unmask function for older versions which don't
368 * have HWMASKEXT registers, or a SoC level means of masking IRQs. Instead the
369 * IRQ is revectored back to the core and retriggered if necessary.
370 *
371 * The retriggering done by this function is specific to level interrupts.
372 */
373static void meta_intc_unmask_level_irq_nomask(struct irq_data *data)
374{
375	irq_hw_number_t hw = data->hwirq;
376	unsigned int bit = 1 << meta_intc_offset(hw);
377	void __iomem *stat_addr = meta_intc_stat_addr(hw);
378	void __iomem *vec_addr = meta_intc_vec_addr(hw);
379	unsigned int thread = hard_processor_id();
380
381	record_irq_is_unmasked(data);
382
383	/* there is no interrupt mask, so revector the interrupt */
384	metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr);
385
386	/* Re-trigger interrupt */
387	/* Writing a 1 triggers interrupt */
388	if (metag_in32(stat_addr) & bit)
389		metag_out32(bit, stat_addr);
390}
391
392/**
393 * meta_intc_irq_set_type() - set the type of an external irq
394 * @data:	data for the external irq to set the type of
395 * @flow_type:	new irq flow type
396 *
397 * Set the flow type of an external interrupt. This updates the irq chip and irq
398 * handler depending on whether the irq is edge or level sensitive (the polarity
399 * is ignored), and also sets up the bit in HWLEVELEXT so the hardware knows
400 * when to trigger.
401 */
402static int meta_intc_irq_set_type(struct irq_data *data, unsigned int flow_type)
403{
404#ifdef CONFIG_METAG_SUSPEND_MEM
405	struct meta_intc_priv *priv = &meta_intc_priv;
406#endif
407	irq_hw_number_t hw = data->hwirq;
408	unsigned int bit = 1 << meta_intc_offset(hw);
409	void __iomem *level_addr = meta_intc_level_addr(hw);
410	unsigned long flags;
411	unsigned int level;
412
413	/* update the chip/handler */
414	if (flow_type & IRQ_TYPE_LEVEL_MASK)
415		irq_set_chip_handler_name_locked(data, &meta_intc_level_chip,
416						 handle_level_irq, NULL);
417	else
418		irq_set_chip_handler_name_locked(data, &meta_intc_edge_chip,
419						 handle_edge_irq, NULL);
420
421	/* and clear/set the bit in HWLEVELEXT */
422	__global_lock2(flags);
423	level = metag_in32(level_addr);
424	if (flow_type & IRQ_TYPE_LEVEL_MASK)
425		level |= bit;
426	else
427		level &= ~bit;
428	metag_out32(level, level_addr);
429#ifdef CONFIG_METAG_SUSPEND_MEM
430	priv->levels_altered[meta_intc_bank(hw)] |= bit;
431#endif
432	__global_unlock2(flags);
433
434	return 0;
435}
436
437/**
438 * meta_intc_irq_demux() - external irq de-multiplexer
439 * @irq:	the virtual interrupt number
440 * @desc:	the interrupt description structure for this irq
441 *
442 * The cpu receives an interrupt on TR2 when a SoC interrupt has occurred. It is
443 * this function's job to demux this irq and figure out exactly which external
444 * irq needs servicing.
445 *
446 * Whilst using TR2 to detect external interrupts is a software convention it is
447 * (hopefully) unlikely to change.
448 */
449static void meta_intc_irq_demux(struct irq_desc *desc)
450{
451	struct meta_intc_priv *priv = &meta_intc_priv;
452	irq_hw_number_t hw;
453	unsigned int bank, irq_no, status;
454	void __iomem *stat_addr = meta_intc_stat_addr(0);
455
456	/*
457	 * Locate which interrupt has caused our handler to run.
458	 */
459	for (bank = 0; bank < priv->nr_banks; ++bank) {
460		/* Which interrupts are currently pending in this bank? */
461recalculate:
462		status = metag_in32(stat_addr) & priv->unmasked[bank];
463
464		for (hw = bank*32; status; status >>= 1, ++hw) {
465			if (status & 0x1) {
466				/*
467				 * Map the hardware IRQ number to a virtual
468				 * Linux IRQ number.
469				 */
470				irq_no = irq_linear_revmap(priv->domain, hw);
471
472				/*
473				 * Only fire off external interrupts that are
474				 * registered to be handled by the kernel.
475				 * Other external interrupts are probably being
476				 * handled by other Meta hardware threads.
477				 */
478				generic_handle_irq(irq_no);
479
480				/*
481				 * The handler may have re-enabled interrupts
482				 * which could have caused a nested invocation
483				 * of this code and make the copy of the
484				 * status register we are using invalid.
485				 */
486				goto recalculate;
487			}
488		}
489		stat_addr += HWSTAT_STRIDE;
490	}
491}
492
493#ifdef CONFIG_SMP
494/**
495 * meta_intc_set_affinity() - set the affinity for an interrupt
496 * @data:	data for the external irq to set the affinity of
497 * @cpumask:	cpu mask representing cpus which can handle the interrupt
498 * @force:	whether to force (ignored)
499 *
500 * Revector the specified external irq onto a specific cpu's TR2 trigger, so
501 * that that cpu tends to be the one who handles it.
502 */
503static int meta_intc_set_affinity(struct irq_data *data,
504				  const struct cpumask *cpumask, bool force)
505{
506	irq_hw_number_t hw = data->hwirq;
507	void __iomem *vec_addr = meta_intc_vec_addr(hw);
508	unsigned int cpu, thread;
509
510	/*
511	 * Wire up this interrupt from HWVECxEXT to the Meta core.
512	 *
513	 * Note that we can't wire up HWVECxEXT to interrupt more than
514	 * one cpu (the interrupt code doesn't support it), so we just
515	 * pick the first cpu we find in 'cpumask'.
516	 */
517	cpu = cpumask_any_and(cpumask, cpu_online_mask);
518	thread = cpu_2_hwthread_id[cpu];
519
520	metag_out32(TBI_TRIG_VEC(TBID_SIGNUM_TR2(thread)), vec_addr);
521
522	return 0;
523}
524#else
525#define meta_intc_set_affinity	NULL
526#endif
527
528#ifdef CONFIG_PM_SLEEP
529#define META_INTC_CHIP_FLAGS	(IRQCHIP_MASK_ON_SUSPEND \
530				| IRQCHIP_SKIP_SET_WAKE)
531#else
532#define META_INTC_CHIP_FLAGS	0
533#endif
534
535/* public edge/level irq chips which SoCs can override */
536
537struct irq_chip meta_intc_edge_chip = {
538	.irq_startup		= meta_intc_startup_irq,
539	.irq_shutdown		= meta_intc_shutdown_irq,
540	.irq_ack		= meta_intc_ack_irq,
541	.irq_mask		= meta_intc_mask_irq,
542	.irq_unmask		= meta_intc_unmask_irq,
543	.irq_set_type		= meta_intc_irq_set_type,
544	.irq_set_affinity	= meta_intc_set_affinity,
545	.flags			= META_INTC_CHIP_FLAGS,
546};
547
548struct irq_chip meta_intc_level_chip = {
549	.irq_startup		= meta_intc_startup_irq,
550	.irq_shutdown		= meta_intc_shutdown_irq,
551	.irq_set_type		= meta_intc_irq_set_type,
552	.irq_mask		= meta_intc_mask_irq,
553	.irq_unmask		= meta_intc_unmask_irq,
554	.irq_set_affinity	= meta_intc_set_affinity,
555	.flags			= META_INTC_CHIP_FLAGS,
556};
557
558/**
559 * meta_intc_map() - map an external irq
560 * @d:		irq domain of external trigger block
561 * @irq:	virtual irq number
562 * @hw:		hardware irq number within external trigger block
563 *
564 * This sets up a virtual irq for a specified hardware interrupt. The irq chip
565 * and handler is configured, using the HWLEVELEXT registers to determine
566 * edge/level flow type. These registers will have been set when the irq type is
567 * set (or set to a default at init time).
568 */
569static int meta_intc_map(struct irq_domain *d, unsigned int irq,
570			 irq_hw_number_t hw)
571{
572	unsigned int bit = 1 << meta_intc_offset(hw);
573	void __iomem *level_addr = meta_intc_level_addr(hw);
574
575	/* Go by the current sense in the HWLEVELEXT register */
576	if (metag_in32(level_addr) & bit)
577		irq_set_chip_and_handler(irq, &meta_intc_level_chip,
578					 handle_level_irq);
579	else
580		irq_set_chip_and_handler(irq, &meta_intc_edge_chip,
581					 handle_edge_irq);
582	return 0;
583}
584
585static const struct irq_domain_ops meta_intc_domain_ops = {
586	.map = meta_intc_map,
587	.xlate = irq_domain_xlate_twocell,
588};
589
590#ifdef CONFIG_METAG_SUSPEND_MEM
591
592/**
593 * struct meta_intc_context - suspend context
594 * @levels:	State of HWLEVELEXT registers
595 * @masks:	State of HWMASKEXT registers
596 * @vectors:	State of HWVECEXT registers
597 * @txvecint:	State of TxVECINT registers
598 *
599 * This structure stores the IRQ state across suspend.
600 */
601struct meta_intc_context {
602	u32 levels[4];
603	u32 masks[4];
604	u8 vectors[4*32];
605
606	u8 txvecint[4][4];
607};
608
609/* suspend context */
610static struct meta_intc_context *meta_intc_context;
611
612/**
613 * meta_intc_suspend() - store irq state
614 *
615 * To avoid interfering with other threads we only save the IRQ state of IRQs in
616 * use by Linux.
617 */
618static int meta_intc_suspend(void)
619{
620	struct meta_intc_priv *priv = &meta_intc_priv;
621	int i, j;
622	irq_hw_number_t hw;
623	unsigned int bank;
624	unsigned long flags;
625	struct meta_intc_context *context;
626	void __iomem *level_addr, *mask_addr, *vec_addr;
627	u32 mask, bit;
628
629	context = kzalloc(sizeof(*context), GFP_ATOMIC);
630	if (!context)
631		return -ENOMEM;
632
633	hw = 0;
634	level_addr = meta_intc_level_addr(0);
635	mask_addr = meta_intc_mask_addr(0);
636	for (bank = 0; bank < priv->nr_banks; ++bank) {
637		vec_addr = meta_intc_vec_addr(hw);
638
639		/* create mask of interrupts in use */
640		mask = 0;
641		for (bit = 1; bit; bit <<= 1) {
642			i = irq_linear_revmap(priv->domain, hw);
643			/* save mapped irqs which are enabled or have actions */
644			if (i && (!irqd_irq_disabled(irq_get_irq_data(i)) ||
645				  irq_has_action(i))) {
646				mask |= bit;
647
648				/* save trigger vector */
649				context->vectors[hw] = metag_in32(vec_addr);
650			}
651
652			++hw;
653			vec_addr += HWVECnEXT_STRIDE;
654		}
655
656		/* save level state if any IRQ levels altered */
657		if (priv->levels_altered[bank])
658			context->levels[bank] = metag_in32(level_addr);
659		/* save mask state if any IRQs in use */
660		if (mask)
661			context->masks[bank] = metag_in32(mask_addr);
662
663		level_addr += HWSTAT_STRIDE;
664		mask_addr += HWSTAT_STRIDE;
665	}
666
667	/* save trigger matrixing */
668	__global_lock2(flags);
669	for (i = 0; i < 4; ++i)
670		for (j = 0; j < 4; ++j)
671			context->txvecint[i][j] = metag_in32(T0VECINT_BHALT +
672							     TnVECINT_STRIDE*i +
673							     8*j);
674	__global_unlock2(flags);
675
676	meta_intc_context = context;
677	return 0;
678}
679
680/**
681 * meta_intc_resume() - restore saved irq state
682 *
683 * Restore the saved IRQ state and drop it.
684 */
685static void meta_intc_resume(void)
686{
687	struct meta_intc_priv *priv = &meta_intc_priv;
688	int i, j;
689	irq_hw_number_t hw;
690	unsigned int bank;
691	unsigned long flags;
692	struct meta_intc_context *context = meta_intc_context;
693	void __iomem *level_addr, *mask_addr, *vec_addr;
694	u32 mask, bit, tmp;
695
696	meta_intc_context = NULL;
697
698	hw = 0;
699	level_addr = meta_intc_level_addr(0);
700	mask_addr = meta_intc_mask_addr(0);
701	for (bank = 0; bank < priv->nr_banks; ++bank) {
702		vec_addr = meta_intc_vec_addr(hw);
703
704		/* create mask of interrupts in use */
705		mask = 0;
706		for (bit = 1; bit; bit <<= 1) {
707			i = irq_linear_revmap(priv->domain, hw);
708			/* restore mapped irqs, enabled or with actions */
709			if (i && (!irqd_irq_disabled(irq_get_irq_data(i)) ||
710				  irq_has_action(i))) {
711				mask |= bit;
712
713				/* restore trigger vector */
714				metag_out32(context->vectors[hw], vec_addr);
715			}
716
717			++hw;
718			vec_addr += HWVECnEXT_STRIDE;
719		}
720
721		if (mask) {
722			/* restore mask state */
723			__global_lock2(flags);
724			tmp = metag_in32(mask_addr);
725			tmp = (tmp & ~mask) | (context->masks[bank] & mask);
726			metag_out32(tmp, mask_addr);
727			__global_unlock2(flags);
728		}
729
730		mask = priv->levels_altered[bank];
731		if (mask) {
732			/* restore level state */
733			__global_lock2(flags);
734			tmp = metag_in32(level_addr);
735			tmp = (tmp & ~mask) | (context->levels[bank] & mask);
736			metag_out32(tmp, level_addr);
737			__global_unlock2(flags);
738		}
739
740		level_addr += HWSTAT_STRIDE;
741		mask_addr += HWSTAT_STRIDE;
742	}
743
744	/* restore trigger matrixing */
745	__global_lock2(flags);
746	for (i = 0; i < 4; ++i) {
747		for (j = 0; j < 4; ++j) {
748			metag_out32(context->txvecint[i][j],
749				    T0VECINT_BHALT +
750				    TnVECINT_STRIDE*i +
751				    8*j);
752		}
753	}
754	__global_unlock2(flags);
755
756	kfree(context);
757}
758
759static struct syscore_ops meta_intc_syscore_ops = {
760	.suspend = meta_intc_suspend,
761	.resume = meta_intc_resume,
762};
763
764static void __init meta_intc_init_syscore_ops(struct meta_intc_priv *priv)
765{
766	register_syscore_ops(&meta_intc_syscore_ops);
767}
768#else
769#define meta_intc_init_syscore_ops(priv) do {} while (0)
770#endif
771
772/**
773 * meta_intc_init_cpu() - register with a Meta cpu
774 * @priv:	private interrupt controller data
775 * @cpu:	the CPU to register on
776 *
777 * Configure @cpu's TR2 irq so that we can demux external irqs.
778 */
779static void __init meta_intc_init_cpu(struct meta_intc_priv *priv, int cpu)
780{
781	unsigned int thread = cpu_2_hwthread_id[cpu];
782	unsigned int signum = TBID_SIGNUM_TR2(thread);
783	int irq = tbisig_map(signum);
784
785	/* Register the multiplexed IRQ handler */
786	irq_set_chained_handler(irq, meta_intc_irq_demux);
787	irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
788}
789
790/**
791 * meta_intc_no_mask() - indicate lack of HWMASKEXT registers
792 *
793 * Called from SoC code (or init code below) to dynamically indicate the lack of
794 * HWMASKEXT registers (for example depending on some SoC revision register).
795 * This alters the irq mask and unmask callbacks to use the fallback
796 * unvectoring/retriggering technique instead of using HWMASKEXT registers.
797 */
798void __init meta_intc_no_mask(void)
799{
800	meta_intc_edge_chip.irq_mask	= meta_intc_mask_irq_nomask;
801	meta_intc_edge_chip.irq_unmask	= meta_intc_unmask_edge_irq_nomask;
802	meta_intc_level_chip.irq_mask	= meta_intc_mask_irq_nomask;
803	meta_intc_level_chip.irq_unmask	= meta_intc_unmask_level_irq_nomask;
804}
805
806/**
807 * init_external_IRQ() - initialise the external irq controller
808 *
809 * Set up the external irq controller using device tree properties. This is
810 * called from init_IRQ().
811 */
812int __init init_external_IRQ(void)
813{
814	struct meta_intc_priv *priv = &meta_intc_priv;
815	struct device_node *node;
816	int ret, cpu;
817	u32 val;
818	bool no_masks = false;
819
820	node = of_find_compatible_node(NULL, NULL, "img,meta-intc");
821	if (!node)
822		return -ENOENT;
823
824	/* Get number of banks */
825	ret = of_property_read_u32(node, "num-banks", &val);
826	if (ret) {
827		pr_err("meta-intc: No num-banks property found\n");
828		return ret;
829	}
830	if (val < 1 || val > 4) {
831		pr_err("meta-intc: num-banks (%u) out of range\n", val);
832		return -EINVAL;
833	}
834	priv->nr_banks = val;
835
836	/* Are any mask registers present? */
837	if (of_get_property(node, "no-mask", NULL))
838		no_masks = true;
839
840	/* No HWMASKEXT registers present? */
841	if (no_masks)
842		meta_intc_no_mask();
843
844	/* Set up an IRQ domain */
845	/*
846	 * This is a legacy IRQ domain for now until all the platform setup code
847	 * has been converted to devicetree.
848	 */
849	priv->domain = irq_domain_add_linear(node, priv->nr_banks*32,
850					     &meta_intc_domain_ops, priv);
851	if (unlikely(!priv->domain)) {
852		pr_err("meta-intc: cannot add IRQ domain\n");
853		return -ENOMEM;
854	}
855
856	/* Setup TR2 for all cpus. */
857	for_each_possible_cpu(cpu)
858		meta_intc_init_cpu(priv, cpu);
859
860	/* Set up system suspend/resume callbacks */
861	meta_intc_init_syscore_ops(priv);
862
863	pr_info("meta-intc: External IRQ controller initialised (%u IRQs)\n",
864		priv->nr_banks*32);
865
866	return 0;
867}