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1/*
2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Interrupt architecture for the GIC:
9 *
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
12 *
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
18 *
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
22 */
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/err.h>
26#include <linux/module.h>
27#include <linux/list.h>
28#include <linux/smp.h>
29#include <linux/cpu.h>
30#include <linux/cpu_pm.h>
31#include <linux/cpumask.h>
32#include <linux/io.h>
33#include <linux/of.h>
34#include <linux/of_address.h>
35#include <linux/of_irq.h>
36#include <linux/acpi.h>
37#include <linux/irqdomain.h>
38#include <linux/interrupt.h>
39#include <linux/percpu.h>
40#include <linux/slab.h>
41#include <linux/irqchip.h>
42#include <linux/irqchip/chained_irq.h>
43#include <linux/irqchip/arm-gic.h>
44
45#include <asm/cputype.h>
46#include <asm/irq.h>
47#include <asm/exception.h>
48#include <asm/smp_plat.h>
49#include <asm/virt.h>
50
51#include "irq-gic-common.h"
52
53#ifdef CONFIG_ARM64
54#include <asm/cpufeature.h>
55
56static void gic_check_cpu_features(void)
57{
58 WARN_TAINT_ONCE(cpus_have_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
59 TAINT_CPU_OUT_OF_SPEC,
60 "GICv3 system registers enabled, broken firmware!\n");
61}
62#else
63#define gic_check_cpu_features() do { } while(0)
64#endif
65
66union gic_base {
67 void __iomem *common_base;
68 void __percpu * __iomem *percpu_base;
69};
70
71struct gic_chip_data {
72 struct irq_chip chip;
73 union gic_base dist_base;
74 union gic_base cpu_base;
75#ifdef CONFIG_CPU_PM
76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
77 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
78 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
79 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
80 u32 __percpu *saved_ppi_enable;
81 u32 __percpu *saved_ppi_active;
82 u32 __percpu *saved_ppi_conf;
83#endif
84 struct irq_domain *domain;
85 unsigned int gic_irqs;
86#ifdef CONFIG_GIC_NON_BANKED
87 void __iomem *(*get_base)(union gic_base *);
88#endif
89};
90
91static DEFINE_RAW_SPINLOCK(irq_controller_lock);
92
93/*
94 * The GIC mapping of CPU interfaces does not necessarily match
95 * the logical CPU numbering. Let's use a mapping as returned
96 * by the GIC itself.
97 */
98#define NR_GIC_CPU_IF 8
99static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
100
101static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE;
102
103static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
104
105#ifdef CONFIG_GIC_NON_BANKED
106static void __iomem *gic_get_percpu_base(union gic_base *base)
107{
108 return raw_cpu_read(*base->percpu_base);
109}
110
111static void __iomem *gic_get_common_base(union gic_base *base)
112{
113 return base->common_base;
114}
115
116static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
117{
118 return data->get_base(&data->dist_base);
119}
120
121static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
122{
123 return data->get_base(&data->cpu_base);
124}
125
126static inline void gic_set_base_accessor(struct gic_chip_data *data,
127 void __iomem *(*f)(union gic_base *))
128{
129 data->get_base = f;
130}
131#else
132#define gic_data_dist_base(d) ((d)->dist_base.common_base)
133#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
134#define gic_set_base_accessor(d, f)
135#endif
136
137static inline void __iomem *gic_dist_base(struct irq_data *d)
138{
139 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
140 return gic_data_dist_base(gic_data);
141}
142
143static inline void __iomem *gic_cpu_base(struct irq_data *d)
144{
145 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
146 return gic_data_cpu_base(gic_data);
147}
148
149static inline unsigned int gic_irq(struct irq_data *d)
150{
151 return d->hwirq;
152}
153
154static inline bool cascading_gic_irq(struct irq_data *d)
155{
156 void *data = irq_data_get_irq_handler_data(d);
157
158 /*
159 * If handler_data is set, this is a cascading interrupt, and
160 * it cannot possibly be forwarded.
161 */
162 return data != NULL;
163}
164
165/*
166 * Routines to acknowledge, disable and enable interrupts
167 */
168static void gic_poke_irq(struct irq_data *d, u32 offset)
169{
170 u32 mask = 1 << (gic_irq(d) % 32);
171 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
172}
173
174static int gic_peek_irq(struct irq_data *d, u32 offset)
175{
176 u32 mask = 1 << (gic_irq(d) % 32);
177 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
178}
179
180static void gic_mask_irq(struct irq_data *d)
181{
182 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
183}
184
185static void gic_eoimode1_mask_irq(struct irq_data *d)
186{
187 gic_mask_irq(d);
188 /*
189 * When masking a forwarded interrupt, make sure it is
190 * deactivated as well.
191 *
192 * This ensures that an interrupt that is getting
193 * disabled/masked will not get "stuck", because there is
194 * noone to deactivate it (guest is being terminated).
195 */
196 if (irqd_is_forwarded_to_vcpu(d))
197 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
198}
199
200static void gic_unmask_irq(struct irq_data *d)
201{
202 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
203}
204
205static void gic_eoi_irq(struct irq_data *d)
206{
207 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
208}
209
210static void gic_eoimode1_eoi_irq(struct irq_data *d)
211{
212 /* Do not deactivate an IRQ forwarded to a vcpu. */
213 if (irqd_is_forwarded_to_vcpu(d))
214 return;
215
216 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
217}
218
219static int gic_irq_set_irqchip_state(struct irq_data *d,
220 enum irqchip_irq_state which, bool val)
221{
222 u32 reg;
223
224 switch (which) {
225 case IRQCHIP_STATE_PENDING:
226 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
227 break;
228
229 case IRQCHIP_STATE_ACTIVE:
230 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
231 break;
232
233 case IRQCHIP_STATE_MASKED:
234 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
235 break;
236
237 default:
238 return -EINVAL;
239 }
240
241 gic_poke_irq(d, reg);
242 return 0;
243}
244
245static int gic_irq_get_irqchip_state(struct irq_data *d,
246 enum irqchip_irq_state which, bool *val)
247{
248 switch (which) {
249 case IRQCHIP_STATE_PENDING:
250 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
251 break;
252
253 case IRQCHIP_STATE_ACTIVE:
254 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
255 break;
256
257 case IRQCHIP_STATE_MASKED:
258 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
259 break;
260
261 default:
262 return -EINVAL;
263 }
264
265 return 0;
266}
267
268static int gic_set_type(struct irq_data *d, unsigned int type)
269{
270 void __iomem *base = gic_dist_base(d);
271 unsigned int gicirq = gic_irq(d);
272
273 /* Interrupt configuration for SGIs can't be changed */
274 if (gicirq < 16)
275 return -EINVAL;
276
277 /* SPIs have restrictions on the supported types */
278 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
279 type != IRQ_TYPE_EDGE_RISING)
280 return -EINVAL;
281
282 return gic_configure_irq(gicirq, type, base, NULL);
283}
284
285static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
286{
287 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
288 if (cascading_gic_irq(d))
289 return -EINVAL;
290
291 if (vcpu)
292 irqd_set_forwarded_to_vcpu(d);
293 else
294 irqd_clr_forwarded_to_vcpu(d);
295 return 0;
296}
297
298#ifdef CONFIG_SMP
299static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
300 bool force)
301{
302 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
303 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
304 u32 val, mask, bit;
305 unsigned long flags;
306
307 if (!force)
308 cpu = cpumask_any_and(mask_val, cpu_online_mask);
309 else
310 cpu = cpumask_first(mask_val);
311
312 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
313 return -EINVAL;
314
315 raw_spin_lock_irqsave(&irq_controller_lock, flags);
316 mask = 0xff << shift;
317 bit = gic_cpu_map[cpu] << shift;
318 val = readl_relaxed(reg) & ~mask;
319 writel_relaxed(val | bit, reg);
320 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
321
322 return IRQ_SET_MASK_OK_DONE;
323}
324#endif
325
326static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
327{
328 u32 irqstat, irqnr;
329 struct gic_chip_data *gic = &gic_data[0];
330 void __iomem *cpu_base = gic_data_cpu_base(gic);
331
332 do {
333 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
334 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
335
336 if (likely(irqnr > 15 && irqnr < 1020)) {
337 if (static_key_true(&supports_deactivate))
338 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
339 handle_domain_irq(gic->domain, irqnr, regs);
340 continue;
341 }
342 if (irqnr < 16) {
343 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
344 if (static_key_true(&supports_deactivate))
345 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE);
346#ifdef CONFIG_SMP
347 handle_IPI(irqnr, regs);
348#endif
349 continue;
350 }
351 break;
352 } while (1);
353}
354
355static void gic_handle_cascade_irq(struct irq_desc *desc)
356{
357 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
358 struct irq_chip *chip = irq_desc_get_chip(desc);
359 unsigned int cascade_irq, gic_irq;
360 unsigned long status;
361
362 chained_irq_enter(chip, desc);
363
364 raw_spin_lock(&irq_controller_lock);
365 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
366 raw_spin_unlock(&irq_controller_lock);
367
368 gic_irq = (status & GICC_IAR_INT_ID_MASK);
369 if (gic_irq == GICC_INT_SPURIOUS)
370 goto out;
371
372 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
373 if (unlikely(gic_irq < 32 || gic_irq > 1020))
374 handle_bad_irq(desc);
375 else
376 generic_handle_irq(cascade_irq);
377
378 out:
379 chained_irq_exit(chip, desc);
380}
381
382static struct irq_chip gic_chip = {
383 .irq_mask = gic_mask_irq,
384 .irq_unmask = gic_unmask_irq,
385 .irq_eoi = gic_eoi_irq,
386 .irq_set_type = gic_set_type,
387 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
388 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
389 .flags = IRQCHIP_SET_TYPE_MASKED |
390 IRQCHIP_SKIP_SET_WAKE |
391 IRQCHIP_MASK_ON_SUSPEND,
392};
393
394static struct irq_chip gic_eoimode1_chip = {
395 .name = "GICv2",
396 .irq_mask = gic_eoimode1_mask_irq,
397 .irq_unmask = gic_unmask_irq,
398 .irq_eoi = gic_eoimode1_eoi_irq,
399 .irq_set_type = gic_set_type,
400 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
401 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
402 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
403 .flags = IRQCHIP_SET_TYPE_MASKED |
404 IRQCHIP_SKIP_SET_WAKE |
405 IRQCHIP_MASK_ON_SUSPEND,
406};
407
408void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
409{
410 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
411 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
412 &gic_data[gic_nr]);
413}
414
415static u8 gic_get_cpumask(struct gic_chip_data *gic)
416{
417 void __iomem *base = gic_data_dist_base(gic);
418 u32 mask, i;
419
420 for (i = mask = 0; i < 32; i += 4) {
421 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
422 mask |= mask >> 16;
423 mask |= mask >> 8;
424 if (mask)
425 break;
426 }
427
428 if (!mask && num_possible_cpus() > 1)
429 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
430
431 return mask;
432}
433
434static void gic_cpu_if_up(struct gic_chip_data *gic)
435{
436 void __iomem *cpu_base = gic_data_cpu_base(gic);
437 u32 bypass = 0;
438 u32 mode = 0;
439
440 if (gic == &gic_data[0] && static_key_true(&supports_deactivate))
441 mode = GIC_CPU_CTRL_EOImodeNS;
442
443 /*
444 * Preserve bypass disable bits to be written back later
445 */
446 bypass = readl(cpu_base + GIC_CPU_CTRL);
447 bypass &= GICC_DIS_BYPASS_MASK;
448
449 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
450}
451
452
453static void __init gic_dist_init(struct gic_chip_data *gic)
454{
455 unsigned int i;
456 u32 cpumask;
457 unsigned int gic_irqs = gic->gic_irqs;
458 void __iomem *base = gic_data_dist_base(gic);
459
460 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
461
462 /*
463 * Set all global interrupts to this CPU only.
464 */
465 cpumask = gic_get_cpumask(gic);
466 cpumask |= cpumask << 8;
467 cpumask |= cpumask << 16;
468 for (i = 32; i < gic_irqs; i += 4)
469 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
470
471 gic_dist_config(base, gic_irqs, NULL);
472
473 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
474}
475
476static void gic_cpu_init(struct gic_chip_data *gic)
477{
478 void __iomem *dist_base = gic_data_dist_base(gic);
479 void __iomem *base = gic_data_cpu_base(gic);
480 unsigned int cpu_mask, cpu = smp_processor_id();
481 int i;
482
483 /*
484 * Setting up the CPU map is only relevant for the primary GIC
485 * because any nested/secondary GICs do not directly interface
486 * with the CPU(s).
487 */
488 if (gic == &gic_data[0]) {
489 /*
490 * Get what the GIC says our CPU mask is.
491 */
492 BUG_ON(cpu >= NR_GIC_CPU_IF);
493 cpu_mask = gic_get_cpumask(gic);
494 gic_cpu_map[cpu] = cpu_mask;
495
496 /*
497 * Clear our mask from the other map entries in case they're
498 * still undefined.
499 */
500 for (i = 0; i < NR_GIC_CPU_IF; i++)
501 if (i != cpu)
502 gic_cpu_map[i] &= ~cpu_mask;
503 }
504
505 gic_cpu_config(dist_base, NULL);
506
507 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
508 gic_cpu_if_up(gic);
509}
510
511int gic_cpu_if_down(unsigned int gic_nr)
512{
513 void __iomem *cpu_base;
514 u32 val = 0;
515
516 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
517 return -EINVAL;
518
519 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
520 val = readl(cpu_base + GIC_CPU_CTRL);
521 val &= ~GICC_ENABLE;
522 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
523
524 return 0;
525}
526
527#ifdef CONFIG_CPU_PM
528/*
529 * Saves the GIC distributor registers during suspend or idle. Must be called
530 * with interrupts disabled but before powering down the GIC. After calling
531 * this function, no interrupts will be delivered by the GIC, and another
532 * platform-specific wakeup source must be enabled.
533 */
534static void gic_dist_save(unsigned int gic_nr)
535{
536 unsigned int gic_irqs;
537 void __iomem *dist_base;
538 int i;
539
540 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
541
542 gic_irqs = gic_data[gic_nr].gic_irqs;
543 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
544
545 if (!dist_base)
546 return;
547
548 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
549 gic_data[gic_nr].saved_spi_conf[i] =
550 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
551
552 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
553 gic_data[gic_nr].saved_spi_target[i] =
554 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
555
556 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
557 gic_data[gic_nr].saved_spi_enable[i] =
558 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
559
560 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
561 gic_data[gic_nr].saved_spi_active[i] =
562 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
563}
564
565/*
566 * Restores the GIC distributor registers during resume or when coming out of
567 * idle. Must be called before enabling interrupts. If a level interrupt
568 * that occured while the GIC was suspended is still present, it will be
569 * handled normally, but any edge interrupts that occured will not be seen by
570 * the GIC and need to be handled by the platform-specific wakeup source.
571 */
572static void gic_dist_restore(unsigned int gic_nr)
573{
574 unsigned int gic_irqs;
575 unsigned int i;
576 void __iomem *dist_base;
577
578 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
579
580 gic_irqs = gic_data[gic_nr].gic_irqs;
581 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
582
583 if (!dist_base)
584 return;
585
586 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
587
588 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
589 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
590 dist_base + GIC_DIST_CONFIG + i * 4);
591
592 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
593 writel_relaxed(GICD_INT_DEF_PRI_X4,
594 dist_base + GIC_DIST_PRI + i * 4);
595
596 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
597 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
598 dist_base + GIC_DIST_TARGET + i * 4);
599
600 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
601 writel_relaxed(GICD_INT_EN_CLR_X32,
602 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
603 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
604 dist_base + GIC_DIST_ENABLE_SET + i * 4);
605 }
606
607 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
608 writel_relaxed(GICD_INT_EN_CLR_X32,
609 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
610 writel_relaxed(gic_data[gic_nr].saved_spi_active[i],
611 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
612 }
613
614 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
615}
616
617static void gic_cpu_save(unsigned int gic_nr)
618{
619 int i;
620 u32 *ptr;
621 void __iomem *dist_base;
622 void __iomem *cpu_base;
623
624 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
625
626 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
627 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
628
629 if (!dist_base || !cpu_base)
630 return;
631
632 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
633 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
634 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
635
636 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active);
637 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
638 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
639
640 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
641 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
642 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
643
644}
645
646static void gic_cpu_restore(unsigned int gic_nr)
647{
648 int i;
649 u32 *ptr;
650 void __iomem *dist_base;
651 void __iomem *cpu_base;
652
653 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
654
655 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
656 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
657
658 if (!dist_base || !cpu_base)
659 return;
660
661 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
662 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
663 writel_relaxed(GICD_INT_EN_CLR_X32,
664 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
665 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
666 }
667
668 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active);
669 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
670 writel_relaxed(GICD_INT_EN_CLR_X32,
671 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
672 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
673 }
674
675 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
676 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
677 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
678
679 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
680 writel_relaxed(GICD_INT_DEF_PRI_X4,
681 dist_base + GIC_DIST_PRI + i * 4);
682
683 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
684 gic_cpu_if_up(&gic_data[gic_nr]);
685}
686
687static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
688{
689 int i;
690
691 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
692#ifdef CONFIG_GIC_NON_BANKED
693 /* Skip over unused GICs */
694 if (!gic_data[i].get_base)
695 continue;
696#endif
697 switch (cmd) {
698 case CPU_PM_ENTER:
699 gic_cpu_save(i);
700 break;
701 case CPU_PM_ENTER_FAILED:
702 case CPU_PM_EXIT:
703 gic_cpu_restore(i);
704 break;
705 case CPU_CLUSTER_PM_ENTER:
706 gic_dist_save(i);
707 break;
708 case CPU_CLUSTER_PM_ENTER_FAILED:
709 case CPU_CLUSTER_PM_EXIT:
710 gic_dist_restore(i);
711 break;
712 }
713 }
714
715 return NOTIFY_OK;
716}
717
718static struct notifier_block gic_notifier_block = {
719 .notifier_call = gic_notifier,
720};
721
722static void __init gic_pm_init(struct gic_chip_data *gic)
723{
724 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
725 sizeof(u32));
726 BUG_ON(!gic->saved_ppi_enable);
727
728 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
729 sizeof(u32));
730 BUG_ON(!gic->saved_ppi_active);
731
732 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
733 sizeof(u32));
734 BUG_ON(!gic->saved_ppi_conf);
735
736 if (gic == &gic_data[0])
737 cpu_pm_register_notifier(&gic_notifier_block);
738}
739#else
740static void __init gic_pm_init(struct gic_chip_data *gic)
741{
742}
743#endif
744
745#ifdef CONFIG_SMP
746static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
747{
748 int cpu;
749 unsigned long flags, map = 0;
750
751 raw_spin_lock_irqsave(&irq_controller_lock, flags);
752
753 /* Convert our logical CPU mask into a physical one. */
754 for_each_cpu(cpu, mask)
755 map |= gic_cpu_map[cpu];
756
757 /*
758 * Ensure that stores to Normal memory are visible to the
759 * other CPUs before they observe us issuing the IPI.
760 */
761 dmb(ishst);
762
763 /* this always happens on GIC0 */
764 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
765
766 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
767}
768#endif
769
770#ifdef CONFIG_BL_SWITCHER
771/*
772 * gic_send_sgi - send a SGI directly to given CPU interface number
773 *
774 * cpu_id: the ID for the destination CPU interface
775 * irq: the IPI number to send a SGI for
776 */
777void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
778{
779 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
780 cpu_id = 1 << cpu_id;
781 /* this always happens on GIC0 */
782 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
783}
784
785/*
786 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
787 *
788 * @cpu: the logical CPU number to get the GIC ID for.
789 *
790 * Return the CPU interface ID for the given logical CPU number,
791 * or -1 if the CPU number is too large or the interface ID is
792 * unknown (more than one bit set).
793 */
794int gic_get_cpu_id(unsigned int cpu)
795{
796 unsigned int cpu_bit;
797
798 if (cpu >= NR_GIC_CPU_IF)
799 return -1;
800 cpu_bit = gic_cpu_map[cpu];
801 if (cpu_bit & (cpu_bit - 1))
802 return -1;
803 return __ffs(cpu_bit);
804}
805
806/*
807 * gic_migrate_target - migrate IRQs to another CPU interface
808 *
809 * @new_cpu_id: the CPU target ID to migrate IRQs to
810 *
811 * Migrate all peripheral interrupts with a target matching the current CPU
812 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
813 * is also updated. Targets to other CPU interfaces are unchanged.
814 * This must be called with IRQs locally disabled.
815 */
816void gic_migrate_target(unsigned int new_cpu_id)
817{
818 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
819 void __iomem *dist_base;
820 int i, ror_val, cpu = smp_processor_id();
821 u32 val, cur_target_mask, active_mask;
822
823 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
824
825 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
826 if (!dist_base)
827 return;
828 gic_irqs = gic_data[gic_nr].gic_irqs;
829
830 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
831 cur_target_mask = 0x01010101 << cur_cpu_id;
832 ror_val = (cur_cpu_id - new_cpu_id) & 31;
833
834 raw_spin_lock(&irq_controller_lock);
835
836 /* Update the target interface for this logical CPU */
837 gic_cpu_map[cpu] = 1 << new_cpu_id;
838
839 /*
840 * Find all the peripheral interrupts targetting the current
841 * CPU interface and migrate them to the new CPU interface.
842 * We skip DIST_TARGET 0 to 7 as they are read-only.
843 */
844 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
845 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
846 active_mask = val & cur_target_mask;
847 if (active_mask) {
848 val &= ~active_mask;
849 val |= ror32(active_mask, ror_val);
850 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
851 }
852 }
853
854 raw_spin_unlock(&irq_controller_lock);
855
856 /*
857 * Now let's migrate and clear any potential SGIs that might be
858 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
859 * is a banked register, we can only forward the SGI using
860 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
861 * doesn't use that information anyway.
862 *
863 * For the same reason we do not adjust SGI source information
864 * for previously sent SGIs by us to other CPUs either.
865 */
866 for (i = 0; i < 16; i += 4) {
867 int j;
868 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
869 if (!val)
870 continue;
871 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
872 for (j = i; j < i + 4; j++) {
873 if (val & 0xff)
874 writel_relaxed((1 << (new_cpu_id + 16)) | j,
875 dist_base + GIC_DIST_SOFTINT);
876 val >>= 8;
877 }
878 }
879}
880
881/*
882 * gic_get_sgir_physaddr - get the physical address for the SGI register
883 *
884 * REturn the physical address of the SGI register to be used
885 * by some early assembly code when the kernel is not yet available.
886 */
887static unsigned long gic_dist_physaddr;
888
889unsigned long gic_get_sgir_physaddr(void)
890{
891 if (!gic_dist_physaddr)
892 return 0;
893 return gic_dist_physaddr + GIC_DIST_SOFTINT;
894}
895
896void __init gic_init_physaddr(struct device_node *node)
897{
898 struct resource res;
899 if (of_address_to_resource(node, 0, &res) == 0) {
900 gic_dist_physaddr = res.start;
901 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
902 }
903}
904
905#else
906#define gic_init_physaddr(node) do { } while (0)
907#endif
908
909static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
910 irq_hw_number_t hw)
911{
912 struct gic_chip_data *gic = d->host_data;
913
914 if (hw < 32) {
915 irq_set_percpu_devid(irq);
916 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
917 handle_percpu_devid_irq, NULL, NULL);
918 irq_set_status_flags(irq, IRQ_NOAUTOEN);
919 } else {
920 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
921 handle_fasteoi_irq, NULL, NULL);
922 irq_set_probe(irq);
923 }
924 return 0;
925}
926
927static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
928{
929}
930
931static int gic_irq_domain_translate(struct irq_domain *d,
932 struct irq_fwspec *fwspec,
933 unsigned long *hwirq,
934 unsigned int *type)
935{
936 if (is_of_node(fwspec->fwnode)) {
937 if (fwspec->param_count < 3)
938 return -EINVAL;
939
940 /* Get the interrupt number and add 16 to skip over SGIs */
941 *hwirq = fwspec->param[1] + 16;
942
943 /*
944 * For SPIs, we need to add 16 more to get the GIC irq
945 * ID number
946 */
947 if (!fwspec->param[0])
948 *hwirq += 16;
949
950 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
951 return 0;
952 }
953
954 if (is_fwnode_irqchip(fwspec->fwnode)) {
955 if(fwspec->param_count != 2)
956 return -EINVAL;
957
958 *hwirq = fwspec->param[0];
959 *type = fwspec->param[1];
960 return 0;
961 }
962
963 return -EINVAL;
964}
965
966#ifdef CONFIG_SMP
967static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
968 void *hcpu)
969{
970 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
971 gic_cpu_init(&gic_data[0]);
972 return NOTIFY_OK;
973}
974
975/*
976 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
977 * priority because the GIC needs to be up before the ARM generic timers.
978 */
979static struct notifier_block gic_cpu_notifier = {
980 .notifier_call = gic_secondary_init,
981 .priority = 100,
982};
983#endif
984
985static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
986 unsigned int nr_irqs, void *arg)
987{
988 int i, ret;
989 irq_hw_number_t hwirq;
990 unsigned int type = IRQ_TYPE_NONE;
991 struct irq_fwspec *fwspec = arg;
992
993 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
994 if (ret)
995 return ret;
996
997 for (i = 0; i < nr_irqs; i++)
998 gic_irq_domain_map(domain, virq + i, hwirq + i);
999
1000 return 0;
1001}
1002
1003static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1004 .translate = gic_irq_domain_translate,
1005 .alloc = gic_irq_domain_alloc,
1006 .free = irq_domain_free_irqs_top,
1007};
1008
1009static const struct irq_domain_ops gic_irq_domain_ops = {
1010 .map = gic_irq_domain_map,
1011 .unmap = gic_irq_domain_unmap,
1012};
1013
1014static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
1015 void __iomem *dist_base, void __iomem *cpu_base,
1016 u32 percpu_offset, struct fwnode_handle *handle)
1017{
1018 irq_hw_number_t hwirq_base;
1019 struct gic_chip_data *gic;
1020 int gic_irqs, irq_base, i;
1021
1022 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
1023
1024 gic_check_cpu_features();
1025
1026 gic = &gic_data[gic_nr];
1027
1028 /* Initialize irq_chip */
1029 if (static_key_true(&supports_deactivate) && gic_nr == 0) {
1030 gic->chip = gic_eoimode1_chip;
1031 } else {
1032 gic->chip = gic_chip;
1033 gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
1034 }
1035
1036#ifdef CONFIG_SMP
1037 if (gic_nr == 0)
1038 gic->chip.irq_set_affinity = gic_set_affinity;
1039#endif
1040
1041#ifdef CONFIG_GIC_NON_BANKED
1042 if (percpu_offset) { /* Frankein-GIC without banked registers... */
1043 unsigned int cpu;
1044
1045 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1046 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1047 if (WARN_ON(!gic->dist_base.percpu_base ||
1048 !gic->cpu_base.percpu_base)) {
1049 free_percpu(gic->dist_base.percpu_base);
1050 free_percpu(gic->cpu_base.percpu_base);
1051 return;
1052 }
1053
1054 for_each_possible_cpu(cpu) {
1055 u32 mpidr = cpu_logical_map(cpu);
1056 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1057 unsigned long offset = percpu_offset * core_id;
1058 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
1059 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
1060 }
1061
1062 gic_set_base_accessor(gic, gic_get_percpu_base);
1063 } else
1064#endif
1065 { /* Normal, sane GIC... */
1066 WARN(percpu_offset,
1067 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1068 percpu_offset);
1069 gic->dist_base.common_base = dist_base;
1070 gic->cpu_base.common_base = cpu_base;
1071 gic_set_base_accessor(gic, gic_get_common_base);
1072 }
1073
1074 /*
1075 * Find out how many interrupts are supported.
1076 * The GIC only supports up to 1020 interrupt sources.
1077 */
1078 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1079 gic_irqs = (gic_irqs + 1) * 32;
1080 if (gic_irqs > 1020)
1081 gic_irqs = 1020;
1082 gic->gic_irqs = gic_irqs;
1083
1084 if (handle) { /* DT/ACPI */
1085 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1086 &gic_irq_domain_hierarchy_ops,
1087 gic);
1088 } else { /* Legacy support */
1089 /*
1090 * For primary GICs, skip over SGIs.
1091 * For secondary GICs, skip over PPIs, too.
1092 */
1093 if (gic_nr == 0 && (irq_start & 31) > 0) {
1094 hwirq_base = 16;
1095 if (irq_start != -1)
1096 irq_start = (irq_start & ~31) + 16;
1097 } else {
1098 hwirq_base = 32;
1099 }
1100
1101 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1102
1103 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1104 numa_node_id());
1105 if (IS_ERR_VALUE(irq_base)) {
1106 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1107 irq_start);
1108 irq_base = irq_start;
1109 }
1110
1111 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1112 hwirq_base, &gic_irq_domain_ops, gic);
1113 }
1114
1115 if (WARN_ON(!gic->domain))
1116 return;
1117
1118 if (gic_nr == 0) {
1119 /*
1120 * Initialize the CPU interface map to all CPUs.
1121 * It will be refined as each CPU probes its ID.
1122 * This is only necessary for the primary GIC.
1123 */
1124 for (i = 0; i < NR_GIC_CPU_IF; i++)
1125 gic_cpu_map[i] = 0xff;
1126#ifdef CONFIG_SMP
1127 set_smp_cross_call(gic_raise_softirq);
1128 register_cpu_notifier(&gic_cpu_notifier);
1129#endif
1130 set_handle_irq(gic_handle_irq);
1131 if (static_key_true(&supports_deactivate))
1132 pr_info("GIC: Using split EOI/Deactivate mode\n");
1133 }
1134
1135 gic_dist_init(gic);
1136 gic_cpu_init(gic);
1137 gic_pm_init(gic);
1138}
1139
1140void __init gic_init(unsigned int gic_nr, int irq_start,
1141 void __iomem *dist_base, void __iomem *cpu_base)
1142{
1143 /*
1144 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1145 * bother with these...
1146 */
1147 static_key_slow_dec(&supports_deactivate);
1148 __gic_init_bases(gic_nr, irq_start, dist_base, cpu_base, 0, NULL);
1149}
1150
1151#ifdef CONFIG_OF
1152static int gic_cnt __initdata;
1153
1154static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1155{
1156 struct resource cpuif_res;
1157
1158 of_address_to_resource(node, 1, &cpuif_res);
1159
1160 if (!is_hyp_mode_available())
1161 return false;
1162 if (resource_size(&cpuif_res) < SZ_8K)
1163 return false;
1164 if (resource_size(&cpuif_res) == SZ_128K) {
1165 u32 val_low, val_high;
1166
1167 /*
1168 * Verify that we have the first 4kB of a GIC400
1169 * aliased over the first 64kB by checking the
1170 * GICC_IIDR register on both ends.
1171 */
1172 val_low = readl_relaxed(*base + GIC_CPU_IDENT);
1173 val_high = readl_relaxed(*base + GIC_CPU_IDENT + 0xf000);
1174 if ((val_low & 0xffff0fff) != 0x0202043B ||
1175 val_low != val_high)
1176 return false;
1177
1178 /*
1179 * Move the base up by 60kB, so that we have a 8kB
1180 * contiguous region, which allows us to use GICC_DIR
1181 * at its normal offset. Please pass me that bucket.
1182 */
1183 *base += 0xf000;
1184 cpuif_res.start += 0xf000;
1185 pr_warn("GIC: Adjusting CPU interface base to %pa",
1186 &cpuif_res.start);
1187 }
1188
1189 return true;
1190}
1191
1192int __init
1193gic_of_init(struct device_node *node, struct device_node *parent)
1194{
1195 void __iomem *cpu_base;
1196 void __iomem *dist_base;
1197 u32 percpu_offset;
1198 int irq;
1199
1200 if (WARN_ON(!node))
1201 return -ENODEV;
1202
1203 dist_base = of_iomap(node, 0);
1204 WARN(!dist_base, "unable to map gic dist registers\n");
1205
1206 cpu_base = of_iomap(node, 1);
1207 WARN(!cpu_base, "unable to map gic cpu registers\n");
1208
1209 /*
1210 * Disable split EOI/Deactivate if either HYP is not available
1211 * or the CPU interface is too small.
1212 */
1213 if (gic_cnt == 0 && !gic_check_eoimode(node, &cpu_base))
1214 static_key_slow_dec(&supports_deactivate);
1215
1216 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1217 percpu_offset = 0;
1218
1219 __gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset,
1220 &node->fwnode);
1221 if (!gic_cnt)
1222 gic_init_physaddr(node);
1223
1224 if (parent) {
1225 irq = irq_of_parse_and_map(node, 0);
1226 gic_cascade_irq(gic_cnt, irq);
1227 }
1228
1229 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1230 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1231
1232 gic_cnt++;
1233 return 0;
1234}
1235IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1236IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1237IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1238IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1239IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1240IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1241IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1242IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1243IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1244
1245#endif
1246
1247#ifdef CONFIG_ACPI
1248static phys_addr_t cpu_phy_base __initdata;
1249
1250static int __init
1251gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
1252 const unsigned long end)
1253{
1254 struct acpi_madt_generic_interrupt *processor;
1255 phys_addr_t gic_cpu_base;
1256 static int cpu_base_assigned;
1257
1258 processor = (struct acpi_madt_generic_interrupt *)header;
1259
1260 if (BAD_MADT_GICC_ENTRY(processor, end))
1261 return -EINVAL;
1262
1263 /*
1264 * There is no support for non-banked GICv1/2 register in ACPI spec.
1265 * All CPU interface addresses have to be the same.
1266 */
1267 gic_cpu_base = processor->base_address;
1268 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
1269 return -EINVAL;
1270
1271 cpu_phy_base = gic_cpu_base;
1272 cpu_base_assigned = 1;
1273 return 0;
1274}
1275
1276/* The things you have to do to just *count* something... */
1277static int __init acpi_dummy_func(struct acpi_subtable_header *header,
1278 const unsigned long end)
1279{
1280 return 0;
1281}
1282
1283static bool __init acpi_gic_redist_is_present(void)
1284{
1285 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1286 acpi_dummy_func, 0) > 0;
1287}
1288
1289static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1290 struct acpi_probe_entry *ape)
1291{
1292 struct acpi_madt_generic_distributor *dist;
1293 dist = (struct acpi_madt_generic_distributor *)header;
1294
1295 return (dist->version == ape->driver_data &&
1296 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1297 !acpi_gic_redist_is_present()));
1298}
1299
1300#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1301#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1302
1303static int __init gic_v2_acpi_init(struct acpi_subtable_header *header,
1304 const unsigned long end)
1305{
1306 struct acpi_madt_generic_distributor *dist;
1307 void __iomem *cpu_base, *dist_base;
1308 struct fwnode_handle *domain_handle;
1309 int count;
1310
1311 /* Collect CPU base addresses */
1312 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1313 gic_acpi_parse_madt_cpu, 0);
1314 if (count <= 0) {
1315 pr_err("No valid GICC entries exist\n");
1316 return -EINVAL;
1317 }
1318
1319 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1320 if (!cpu_base) {
1321 pr_err("Unable to map GICC registers\n");
1322 return -ENOMEM;
1323 }
1324
1325 dist = (struct acpi_madt_generic_distributor *)header;
1326 dist_base = ioremap(dist->base_address, ACPI_GICV2_DIST_MEM_SIZE);
1327 if (!dist_base) {
1328 pr_err("Unable to map GICD registers\n");
1329 iounmap(cpu_base);
1330 return -ENOMEM;
1331 }
1332
1333 /*
1334 * Disable split EOI/Deactivate if HYP is not available. ACPI
1335 * guarantees that we'll always have a GICv2, so the CPU
1336 * interface will always be the right size.
1337 */
1338 if (!is_hyp_mode_available())
1339 static_key_slow_dec(&supports_deactivate);
1340
1341 /*
1342 * Initialize GIC instance zero (no multi-GIC support).
1343 */
1344 domain_handle = irq_domain_alloc_fwnode(dist_base);
1345 if (!domain_handle) {
1346 pr_err("Unable to allocate domain handle\n");
1347 iounmap(cpu_base);
1348 iounmap(dist_base);
1349 return -ENOMEM;
1350 }
1351
1352 __gic_init_bases(0, -1, dist_base, cpu_base, 0, domain_handle);
1353
1354 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle);
1355
1356 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1357 gicv2m_init(NULL, gic_data[0].domain);
1358
1359 return 0;
1360}
1361IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1362 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1363 gic_v2_acpi_init);
1364IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1365 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1366 gic_v2_acpi_init);
1367#endif
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
4 *
5 * Interrupt architecture for the GIC:
6 *
7 * o There is one Interrupt Distributor, which receives interrupts
8 * from system devices and sends them to the Interrupt Controllers.
9 *
10 * o There is one CPU Interface per CPU, which sends interrupts sent
11 * by the Distributor, and interrupts generated locally, to the
12 * associated CPU. The base address of the CPU interface is usually
13 * aliased so that the same address points to different chips depending
14 * on the CPU it is accessed from.
15 *
16 * Note that IRQs 0-31 are special - they are local to each CPU.
17 * As such, the enable set/clear, pending set/clear and active bit
18 * registers are banked per-cpu for these sources.
19 */
20#include <linux/init.h>
21#include <linux/kernel.h>
22#include <linux/kstrtox.h>
23#include <linux/err.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/smp.h>
27#include <linux/cpu.h>
28#include <linux/cpu_pm.h>
29#include <linux/cpumask.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
34#include <linux/acpi.h>
35#include <linux/irqdomain.h>
36#include <linux/interrupt.h>
37#include <linux/percpu.h>
38#include <linux/seq_file.h>
39#include <linux/slab.h>
40#include <linux/irqchip.h>
41#include <linux/irqchip/chained_irq.h>
42#include <linux/irqchip/arm-gic.h>
43
44#include <asm/cputype.h>
45#include <asm/irq.h>
46#include <asm/exception.h>
47#include <asm/smp_plat.h>
48#include <asm/virt.h>
49
50#include "irq-gic-common.h"
51
52#ifdef CONFIG_ARM64
53#include <asm/cpufeature.h>
54
55static void gic_check_cpu_features(void)
56{
57 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF),
58 TAINT_CPU_OUT_OF_SPEC,
59 "GICv3 system registers enabled, broken firmware!\n");
60}
61#else
62#define gic_check_cpu_features() do { } while(0)
63#endif
64
65union gic_base {
66 void __iomem *common_base;
67 void __percpu * __iomem *percpu_base;
68};
69
70struct gic_chip_data {
71 union gic_base dist_base;
72 union gic_base cpu_base;
73 void __iomem *raw_dist_base;
74 void __iomem *raw_cpu_base;
75 u32 percpu_offset;
76#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
77 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
78 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
79 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
80 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
81 u32 __percpu *saved_ppi_enable;
82 u32 __percpu *saved_ppi_active;
83 u32 __percpu *saved_ppi_conf;
84#endif
85 struct irq_domain *domain;
86 unsigned int gic_irqs;
87};
88
89#ifdef CONFIG_BL_SWITCHER
90
91static DEFINE_RAW_SPINLOCK(cpu_map_lock);
92
93#define gic_lock_irqsave(f) \
94 raw_spin_lock_irqsave(&cpu_map_lock, (f))
95#define gic_unlock_irqrestore(f) \
96 raw_spin_unlock_irqrestore(&cpu_map_lock, (f))
97
98#define gic_lock() raw_spin_lock(&cpu_map_lock)
99#define gic_unlock() raw_spin_unlock(&cpu_map_lock)
100
101#else
102
103#define gic_lock_irqsave(f) do { (void)(f); } while(0)
104#define gic_unlock_irqrestore(f) do { (void)(f); } while(0)
105
106#define gic_lock() do { } while(0)
107#define gic_unlock() do { } while(0)
108
109#endif
110
111static DEFINE_STATIC_KEY_FALSE(needs_rmw_access);
112
113/*
114 * The GIC mapping of CPU interfaces does not necessarily match
115 * the logical CPU numbering. Let's use a mapping as returned
116 * by the GIC itself.
117 */
118#define NR_GIC_CPU_IF 8
119static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
120
121static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
122
123static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly;
124
125static struct gic_kvm_info gic_v2_kvm_info __initdata;
126
127static DEFINE_PER_CPU(u32, sgi_intid);
128
129#ifdef CONFIG_GIC_NON_BANKED
130static DEFINE_STATIC_KEY_FALSE(frankengic_key);
131
132static void enable_frankengic(void)
133{
134 static_branch_enable(&frankengic_key);
135}
136
137static inline void __iomem *__get_base(union gic_base *base)
138{
139 if (static_branch_unlikely(&frankengic_key))
140 return raw_cpu_read(*base->percpu_base);
141
142 return base->common_base;
143}
144
145#define gic_data_dist_base(d) __get_base(&(d)->dist_base)
146#define gic_data_cpu_base(d) __get_base(&(d)->cpu_base)
147#else
148#define gic_data_dist_base(d) ((d)->dist_base.common_base)
149#define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
150#define enable_frankengic() do { } while(0)
151#endif
152
153static inline void __iomem *gic_dist_base(struct irq_data *d)
154{
155 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
156 return gic_data_dist_base(gic_data);
157}
158
159static inline void __iomem *gic_cpu_base(struct irq_data *d)
160{
161 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
162 return gic_data_cpu_base(gic_data);
163}
164
165static inline unsigned int gic_irq(struct irq_data *d)
166{
167 return d->hwirq;
168}
169
170static inline bool cascading_gic_irq(struct irq_data *d)
171{
172 void *data = irq_data_get_irq_handler_data(d);
173
174 /*
175 * If handler_data is set, this is a cascading interrupt, and
176 * it cannot possibly be forwarded.
177 */
178 return data != NULL;
179}
180
181/*
182 * Routines to acknowledge, disable and enable interrupts
183 */
184static void gic_poke_irq(struct irq_data *d, u32 offset)
185{
186 u32 mask = 1 << (gic_irq(d) % 32);
187 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4);
188}
189
190static int gic_peek_irq(struct irq_data *d, u32 offset)
191{
192 u32 mask = 1 << (gic_irq(d) % 32);
193 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask);
194}
195
196static void gic_mask_irq(struct irq_data *d)
197{
198 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR);
199}
200
201static void gic_eoimode1_mask_irq(struct irq_data *d)
202{
203 gic_mask_irq(d);
204 /*
205 * When masking a forwarded interrupt, make sure it is
206 * deactivated as well.
207 *
208 * This ensures that an interrupt that is getting
209 * disabled/masked will not get "stuck", because there is
210 * noone to deactivate it (guest is being terminated).
211 */
212 if (irqd_is_forwarded_to_vcpu(d))
213 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR);
214}
215
216static void gic_unmask_irq(struct irq_data *d)
217{
218 gic_poke_irq(d, GIC_DIST_ENABLE_SET);
219}
220
221static void gic_eoi_irq(struct irq_data *d)
222{
223 u32 hwirq = gic_irq(d);
224
225 if (hwirq < 16)
226 hwirq = this_cpu_read(sgi_intid);
227
228 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI);
229}
230
231static void gic_eoimode1_eoi_irq(struct irq_data *d)
232{
233 u32 hwirq = gic_irq(d);
234
235 /* Do not deactivate an IRQ forwarded to a vcpu. */
236 if (irqd_is_forwarded_to_vcpu(d))
237 return;
238
239 if (hwirq < 16)
240 hwirq = this_cpu_read(sgi_intid);
241
242 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE);
243}
244
245static int gic_irq_set_irqchip_state(struct irq_data *d,
246 enum irqchip_irq_state which, bool val)
247{
248 u32 reg;
249
250 switch (which) {
251 case IRQCHIP_STATE_PENDING:
252 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR;
253 break;
254
255 case IRQCHIP_STATE_ACTIVE:
256 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR;
257 break;
258
259 case IRQCHIP_STATE_MASKED:
260 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET;
261 break;
262
263 default:
264 return -EINVAL;
265 }
266
267 gic_poke_irq(d, reg);
268 return 0;
269}
270
271static int gic_irq_get_irqchip_state(struct irq_data *d,
272 enum irqchip_irq_state which, bool *val)
273{
274 switch (which) {
275 case IRQCHIP_STATE_PENDING:
276 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET);
277 break;
278
279 case IRQCHIP_STATE_ACTIVE:
280 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET);
281 break;
282
283 case IRQCHIP_STATE_MASKED:
284 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET);
285 break;
286
287 default:
288 return -EINVAL;
289 }
290
291 return 0;
292}
293
294static int gic_set_type(struct irq_data *d, unsigned int type)
295{
296 void __iomem *base = gic_dist_base(d);
297 unsigned int gicirq = gic_irq(d);
298 int ret;
299
300 /* Interrupt configuration for SGIs can't be changed */
301 if (gicirq < 16)
302 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0;
303
304 /* SPIs have restrictions on the supported types */
305 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
306 type != IRQ_TYPE_EDGE_RISING)
307 return -EINVAL;
308
309 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL);
310 if (ret && gicirq < 32) {
311 /* Misconfigured PPIs are usually not fatal */
312 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);
313 ret = 0;
314 }
315
316 return ret;
317}
318
319static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
320{
321 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */
322 if (cascading_gic_irq(d) || gic_irq(d) < 16)
323 return -EINVAL;
324
325 if (vcpu)
326 irqd_set_forwarded_to_vcpu(d);
327 else
328 irqd_clr_forwarded_to_vcpu(d);
329 return 0;
330}
331
332static int gic_retrigger(struct irq_data *data)
333{
334 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true);
335}
336
337static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
338{
339 u32 irqstat, irqnr;
340 struct gic_chip_data *gic = &gic_data[0];
341 void __iomem *cpu_base = gic_data_cpu_base(gic);
342
343 do {
344 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
345 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
346
347 if (unlikely(irqnr >= 1020))
348 break;
349
350 if (static_branch_likely(&supports_deactivate_key))
351 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
352 isb();
353
354 /*
355 * Ensure any shared data written by the CPU sending the IPI
356 * is read after we've read the ACK register on the GIC.
357 *
358 * Pairs with the write barrier in gic_ipi_send_mask
359 */
360 if (irqnr <= 15) {
361 smp_rmb();
362
363 /*
364 * The GIC encodes the source CPU in GICC_IAR,
365 * leading to the deactivation to fail if not
366 * written back as is to GICC_EOI. Stash the INTID
367 * away for gic_eoi_irq() to write back. This only
368 * works because we don't nest SGIs...
369 */
370 this_cpu_write(sgi_intid, irqstat);
371 }
372
373 generic_handle_domain_irq(gic->domain, irqnr);
374 } while (1);
375}
376
377static void gic_handle_cascade_irq(struct irq_desc *desc)
378{
379 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc);
380 struct irq_chip *chip = irq_desc_get_chip(desc);
381 unsigned int gic_irq;
382 unsigned long status;
383 int ret;
384
385 chained_irq_enter(chip, desc);
386
387 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
388
389 gic_irq = (status & GICC_IAR_INT_ID_MASK);
390 if (gic_irq == GICC_INT_SPURIOUS)
391 goto out;
392
393 isb();
394 ret = generic_handle_domain_irq(chip_data->domain, gic_irq);
395 if (unlikely(ret))
396 handle_bad_irq(desc);
397 out:
398 chained_irq_exit(chip, desc);
399}
400
401static void gic_irq_print_chip(struct irq_data *d, struct seq_file *p)
402{
403 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
404
405 if (gic->domain->pm_dev)
406 seq_printf(p, gic->domain->pm_dev->of_node->name);
407 else
408 seq_printf(p, "GIC-%d", (int)(gic - &gic_data[0]));
409}
410
411void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
412{
413 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
414 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq,
415 &gic_data[gic_nr]);
416}
417
418static u8 gic_get_cpumask(struct gic_chip_data *gic)
419{
420 void __iomem *base = gic_data_dist_base(gic);
421 u32 mask, i;
422
423 for (i = mask = 0; i < 32; i += 4) {
424 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
425 mask |= mask >> 16;
426 mask |= mask >> 8;
427 if (mask)
428 break;
429 }
430
431 if (!mask && num_possible_cpus() > 1)
432 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
433
434 return mask;
435}
436
437static bool gic_check_gicv2(void __iomem *base)
438{
439 u32 val = readl_relaxed(base + GIC_CPU_IDENT);
440 return (val & 0xff0fff) == 0x02043B;
441}
442
443static void gic_cpu_if_up(struct gic_chip_data *gic)
444{
445 void __iomem *cpu_base = gic_data_cpu_base(gic);
446 u32 bypass = 0;
447 u32 mode = 0;
448 int i;
449
450 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))
451 mode = GIC_CPU_CTRL_EOImodeNS;
452
453 if (gic_check_gicv2(cpu_base))
454 for (i = 0; i < 4; i++)
455 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4);
456
457 /*
458 * Preserve bypass disable bits to be written back later
459 */
460 bypass = readl(cpu_base + GIC_CPU_CTRL);
461 bypass &= GICC_DIS_BYPASS_MASK;
462
463 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
464}
465
466
467static void gic_dist_init(struct gic_chip_data *gic)
468{
469 unsigned int i;
470 u32 cpumask;
471 unsigned int gic_irqs = gic->gic_irqs;
472 void __iomem *base = gic_data_dist_base(gic);
473
474 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
475
476 /*
477 * Set all global interrupts to this CPU only.
478 */
479 cpumask = gic_get_cpumask(gic);
480 cpumask |= cpumask << 8;
481 cpumask |= cpumask << 16;
482 for (i = 32; i < gic_irqs; i += 4)
483 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
484
485 gic_dist_config(base, gic_irqs, NULL);
486
487 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
488}
489
490static int gic_cpu_init(struct gic_chip_data *gic)
491{
492 void __iomem *dist_base = gic_data_dist_base(gic);
493 void __iomem *base = gic_data_cpu_base(gic);
494 unsigned int cpu_mask, cpu = smp_processor_id();
495 int i;
496
497 /*
498 * Setting up the CPU map is only relevant for the primary GIC
499 * because any nested/secondary GICs do not directly interface
500 * with the CPU(s).
501 */
502 if (gic == &gic_data[0]) {
503 /*
504 * Get what the GIC says our CPU mask is.
505 */
506 if (WARN_ON(cpu >= NR_GIC_CPU_IF))
507 return -EINVAL;
508
509 gic_check_cpu_features();
510 cpu_mask = gic_get_cpumask(gic);
511 gic_cpu_map[cpu] = cpu_mask;
512
513 /*
514 * Clear our mask from the other map entries in case they're
515 * still undefined.
516 */
517 for (i = 0; i < NR_GIC_CPU_IF; i++)
518 if (i != cpu)
519 gic_cpu_map[i] &= ~cpu_mask;
520 }
521
522 gic_cpu_config(dist_base, 32, NULL);
523
524 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
525 gic_cpu_if_up(gic);
526
527 return 0;
528}
529
530int gic_cpu_if_down(unsigned int gic_nr)
531{
532 void __iomem *cpu_base;
533 u32 val = 0;
534
535 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR)
536 return -EINVAL;
537
538 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
539 val = readl(cpu_base + GIC_CPU_CTRL);
540 val &= ~GICC_ENABLE;
541 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
542
543 return 0;
544}
545
546#if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM)
547/*
548 * Saves the GIC distributor registers during suspend or idle. Must be called
549 * with interrupts disabled but before powering down the GIC. After calling
550 * this function, no interrupts will be delivered by the GIC, and another
551 * platform-specific wakeup source must be enabled.
552 */
553void gic_dist_save(struct gic_chip_data *gic)
554{
555 unsigned int gic_irqs;
556 void __iomem *dist_base;
557 int i;
558
559 if (WARN_ON(!gic))
560 return;
561
562 gic_irqs = gic->gic_irqs;
563 dist_base = gic_data_dist_base(gic);
564
565 if (!dist_base)
566 return;
567
568 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
569 gic->saved_spi_conf[i] =
570 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
571
572 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
573 gic->saved_spi_target[i] =
574 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
575
576 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
577 gic->saved_spi_enable[i] =
578 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
579
580 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
581 gic->saved_spi_active[i] =
582 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
583}
584
585/*
586 * Restores the GIC distributor registers during resume or when coming out of
587 * idle. Must be called before enabling interrupts. If a level interrupt
588 * that occurred while the GIC was suspended is still present, it will be
589 * handled normally, but any edge interrupts that occurred will not be seen by
590 * the GIC and need to be handled by the platform-specific wakeup source.
591 */
592void gic_dist_restore(struct gic_chip_data *gic)
593{
594 unsigned int gic_irqs;
595 unsigned int i;
596 void __iomem *dist_base;
597
598 if (WARN_ON(!gic))
599 return;
600
601 gic_irqs = gic->gic_irqs;
602 dist_base = gic_data_dist_base(gic);
603
604 if (!dist_base)
605 return;
606
607 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
608
609 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
610 writel_relaxed(gic->saved_spi_conf[i],
611 dist_base + GIC_DIST_CONFIG + i * 4);
612
613 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
614 writel_relaxed(GICD_INT_DEF_PRI_X4,
615 dist_base + GIC_DIST_PRI + i * 4);
616
617 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
618 writel_relaxed(gic->saved_spi_target[i],
619 dist_base + GIC_DIST_TARGET + i * 4);
620
621 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
622 writel_relaxed(GICD_INT_EN_CLR_X32,
623 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
624 writel_relaxed(gic->saved_spi_enable[i],
625 dist_base + GIC_DIST_ENABLE_SET + i * 4);
626 }
627
628 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
629 writel_relaxed(GICD_INT_EN_CLR_X32,
630 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
631 writel_relaxed(gic->saved_spi_active[i],
632 dist_base + GIC_DIST_ACTIVE_SET + i * 4);
633 }
634
635 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
636}
637
638void gic_cpu_save(struct gic_chip_data *gic)
639{
640 int i;
641 u32 *ptr;
642 void __iomem *dist_base;
643 void __iomem *cpu_base;
644
645 if (WARN_ON(!gic))
646 return;
647
648 dist_base = gic_data_dist_base(gic);
649 cpu_base = gic_data_cpu_base(gic);
650
651 if (!dist_base || !cpu_base)
652 return;
653
654 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
655 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
656 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
657
658 ptr = raw_cpu_ptr(gic->saved_ppi_active);
659 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
660 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
661
662 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
663 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
664 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
665
666}
667
668void gic_cpu_restore(struct gic_chip_data *gic)
669{
670 int i;
671 u32 *ptr;
672 void __iomem *dist_base;
673 void __iomem *cpu_base;
674
675 if (WARN_ON(!gic))
676 return;
677
678 dist_base = gic_data_dist_base(gic);
679 cpu_base = gic_data_cpu_base(gic);
680
681 if (!dist_base || !cpu_base)
682 return;
683
684 ptr = raw_cpu_ptr(gic->saved_ppi_enable);
685 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
686 writel_relaxed(GICD_INT_EN_CLR_X32,
687 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
688 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
689 }
690
691 ptr = raw_cpu_ptr(gic->saved_ppi_active);
692 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
693 writel_relaxed(GICD_INT_EN_CLR_X32,
694 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
695 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
696 }
697
698 ptr = raw_cpu_ptr(gic->saved_ppi_conf);
699 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
700 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
701
702 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
703 writel_relaxed(GICD_INT_DEF_PRI_X4,
704 dist_base + GIC_DIST_PRI + i * 4);
705
706 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
707 gic_cpu_if_up(gic);
708}
709
710static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
711{
712 int i;
713
714 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) {
715 switch (cmd) {
716 case CPU_PM_ENTER:
717 gic_cpu_save(&gic_data[i]);
718 break;
719 case CPU_PM_ENTER_FAILED:
720 case CPU_PM_EXIT:
721 gic_cpu_restore(&gic_data[i]);
722 break;
723 case CPU_CLUSTER_PM_ENTER:
724 gic_dist_save(&gic_data[i]);
725 break;
726 case CPU_CLUSTER_PM_ENTER_FAILED:
727 case CPU_CLUSTER_PM_EXIT:
728 gic_dist_restore(&gic_data[i]);
729 break;
730 }
731 }
732
733 return NOTIFY_OK;
734}
735
736static struct notifier_block gic_notifier_block = {
737 .notifier_call = gic_notifier,
738};
739
740static int gic_pm_init(struct gic_chip_data *gic)
741{
742 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
743 sizeof(u32));
744 if (WARN_ON(!gic->saved_ppi_enable))
745 return -ENOMEM;
746
747 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
748 sizeof(u32));
749 if (WARN_ON(!gic->saved_ppi_active))
750 goto free_ppi_enable;
751
752 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
753 sizeof(u32));
754 if (WARN_ON(!gic->saved_ppi_conf))
755 goto free_ppi_active;
756
757 if (gic == &gic_data[0])
758 cpu_pm_register_notifier(&gic_notifier_block);
759
760 return 0;
761
762free_ppi_active:
763 free_percpu(gic->saved_ppi_active);
764free_ppi_enable:
765 free_percpu(gic->saved_ppi_enable);
766
767 return -ENOMEM;
768}
769#else
770static int gic_pm_init(struct gic_chip_data *gic)
771{
772 return 0;
773}
774#endif
775
776#ifdef CONFIG_SMP
777static void rmw_writeb(u8 bval, void __iomem *addr)
778{
779 static DEFINE_RAW_SPINLOCK(rmw_lock);
780 unsigned long offset = (unsigned long)addr & 3UL;
781 unsigned long shift = offset * 8;
782 unsigned long flags;
783 u32 val;
784
785 raw_spin_lock_irqsave(&rmw_lock, flags);
786
787 addr -= offset;
788 val = readl_relaxed(addr);
789 val &= ~GENMASK(shift + 7, shift);
790 val |= bval << shift;
791 writel_relaxed(val, addr);
792
793 raw_spin_unlock_irqrestore(&rmw_lock, flags);
794}
795
796static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
797 bool force)
798{
799 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
800 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d);
801 unsigned int cpu;
802
803 if (unlikely(gic != &gic_data[0]))
804 return -EINVAL;
805
806 if (!force)
807 cpu = cpumask_any_and(mask_val, cpu_online_mask);
808 else
809 cpu = cpumask_first(mask_val);
810
811 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
812 return -EINVAL;
813
814 if (static_branch_unlikely(&needs_rmw_access))
815 rmw_writeb(gic_cpu_map[cpu], reg);
816 else
817 writeb_relaxed(gic_cpu_map[cpu], reg);
818 irq_data_update_effective_affinity(d, cpumask_of(cpu));
819
820 return IRQ_SET_MASK_OK_DONE;
821}
822
823static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
824{
825 int cpu;
826 unsigned long flags, map = 0;
827
828 if (unlikely(nr_cpu_ids == 1)) {
829 /* Only one CPU? let's do a self-IPI... */
830 writel_relaxed(2 << 24 | d->hwirq,
831 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
832 return;
833 }
834
835 gic_lock_irqsave(flags);
836
837 /* Convert our logical CPU mask into a physical one. */
838 for_each_cpu(cpu, mask)
839 map |= gic_cpu_map[cpu];
840
841 /*
842 * Ensure that stores to Normal memory are visible to the
843 * other CPUs before they observe us issuing the IPI.
844 */
845 dmb(ishst);
846
847 /* this always happens on GIC0 */
848 writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
849
850 gic_unlock_irqrestore(flags);
851}
852
853static int gic_starting_cpu(unsigned int cpu)
854{
855 gic_cpu_init(&gic_data[0]);
856 return 0;
857}
858
859static __init void gic_smp_init(void)
860{
861 struct irq_fwspec sgi_fwspec = {
862 .fwnode = gic_data[0].domain->fwnode,
863 .param_count = 1,
864 };
865 int base_sgi;
866
867 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING,
868 "irqchip/arm/gic:starting",
869 gic_starting_cpu, NULL);
870
871 base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8,
872 NUMA_NO_NODE, &sgi_fwspec,
873 false, NULL);
874 if (WARN_ON(base_sgi <= 0))
875 return;
876
877 set_smp_ipi_range(base_sgi, 8);
878}
879#else
880#define gic_smp_init() do { } while(0)
881#define gic_set_affinity NULL
882#define gic_ipi_send_mask NULL
883#endif
884
885static const struct irq_chip gic_chip = {
886 .irq_mask = gic_mask_irq,
887 .irq_unmask = gic_unmask_irq,
888 .irq_eoi = gic_eoi_irq,
889 .irq_set_type = gic_set_type,
890 .irq_retrigger = gic_retrigger,
891 .irq_set_affinity = gic_set_affinity,
892 .ipi_send_mask = gic_ipi_send_mask,
893 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
894 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
895 .irq_print_chip = gic_irq_print_chip,
896 .flags = IRQCHIP_SET_TYPE_MASKED |
897 IRQCHIP_SKIP_SET_WAKE |
898 IRQCHIP_MASK_ON_SUSPEND,
899};
900
901static const struct irq_chip gic_chip_mode1 = {
902 .name = "GICv2",
903 .irq_mask = gic_eoimode1_mask_irq,
904 .irq_unmask = gic_unmask_irq,
905 .irq_eoi = gic_eoimode1_eoi_irq,
906 .irq_set_type = gic_set_type,
907 .irq_retrigger = gic_retrigger,
908 .irq_set_affinity = gic_set_affinity,
909 .ipi_send_mask = gic_ipi_send_mask,
910 .irq_get_irqchip_state = gic_irq_get_irqchip_state,
911 .irq_set_irqchip_state = gic_irq_set_irqchip_state,
912 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity,
913 .flags = IRQCHIP_SET_TYPE_MASKED |
914 IRQCHIP_SKIP_SET_WAKE |
915 IRQCHIP_MASK_ON_SUSPEND,
916};
917
918#ifdef CONFIG_BL_SWITCHER
919/*
920 * gic_send_sgi - send a SGI directly to given CPU interface number
921 *
922 * cpu_id: the ID for the destination CPU interface
923 * irq: the IPI number to send a SGI for
924 */
925void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
926{
927 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
928 cpu_id = 1 << cpu_id;
929 /* this always happens on GIC0 */
930 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
931}
932
933/*
934 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
935 *
936 * @cpu: the logical CPU number to get the GIC ID for.
937 *
938 * Return the CPU interface ID for the given logical CPU number,
939 * or -1 if the CPU number is too large or the interface ID is
940 * unknown (more than one bit set).
941 */
942int gic_get_cpu_id(unsigned int cpu)
943{
944 unsigned int cpu_bit;
945
946 if (cpu >= NR_GIC_CPU_IF)
947 return -1;
948 cpu_bit = gic_cpu_map[cpu];
949 if (cpu_bit & (cpu_bit - 1))
950 return -1;
951 return __ffs(cpu_bit);
952}
953
954/*
955 * gic_migrate_target - migrate IRQs to another CPU interface
956 *
957 * @new_cpu_id: the CPU target ID to migrate IRQs to
958 *
959 * Migrate all peripheral interrupts with a target matching the current CPU
960 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
961 * is also updated. Targets to other CPU interfaces are unchanged.
962 * This must be called with IRQs locally disabled.
963 */
964void gic_migrate_target(unsigned int new_cpu_id)
965{
966 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
967 void __iomem *dist_base;
968 int i, ror_val, cpu = smp_processor_id();
969 u32 val, cur_target_mask, active_mask;
970
971 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
972
973 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
974 if (!dist_base)
975 return;
976 gic_irqs = gic_data[gic_nr].gic_irqs;
977
978 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
979 cur_target_mask = 0x01010101 << cur_cpu_id;
980 ror_val = (cur_cpu_id - new_cpu_id) & 31;
981
982 gic_lock();
983
984 /* Update the target interface for this logical CPU */
985 gic_cpu_map[cpu] = 1 << new_cpu_id;
986
987 /*
988 * Find all the peripheral interrupts targeting the current
989 * CPU interface and migrate them to the new CPU interface.
990 * We skip DIST_TARGET 0 to 7 as they are read-only.
991 */
992 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
993 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
994 active_mask = val & cur_target_mask;
995 if (active_mask) {
996 val &= ~active_mask;
997 val |= ror32(active_mask, ror_val);
998 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
999 }
1000 }
1001
1002 gic_unlock();
1003
1004 /*
1005 * Now let's migrate and clear any potential SGIs that might be
1006 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
1007 * is a banked register, we can only forward the SGI using
1008 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
1009 * doesn't use that information anyway.
1010 *
1011 * For the same reason we do not adjust SGI source information
1012 * for previously sent SGIs by us to other CPUs either.
1013 */
1014 for (i = 0; i < 16; i += 4) {
1015 int j;
1016 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
1017 if (!val)
1018 continue;
1019 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
1020 for (j = i; j < i + 4; j++) {
1021 if (val & 0xff)
1022 writel_relaxed((1 << (new_cpu_id + 16)) | j,
1023 dist_base + GIC_DIST_SOFTINT);
1024 val >>= 8;
1025 }
1026 }
1027}
1028
1029/*
1030 * gic_get_sgir_physaddr - get the physical address for the SGI register
1031 *
1032 * Return the physical address of the SGI register to be used
1033 * by some early assembly code when the kernel is not yet available.
1034 */
1035static unsigned long gic_dist_physaddr;
1036
1037unsigned long gic_get_sgir_physaddr(void)
1038{
1039 if (!gic_dist_physaddr)
1040 return 0;
1041 return gic_dist_physaddr + GIC_DIST_SOFTINT;
1042}
1043
1044static void __init gic_init_physaddr(struct device_node *node)
1045{
1046 struct resource res;
1047 if (of_address_to_resource(node, 0, &res) == 0) {
1048 gic_dist_physaddr = res.start;
1049 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
1050 }
1051}
1052
1053#else
1054#define gic_init_physaddr(node) do { } while (0)
1055#endif
1056
1057static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
1058 irq_hw_number_t hw)
1059{
1060 struct gic_chip_data *gic = d->host_data;
1061 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq));
1062 const struct irq_chip *chip;
1063
1064 chip = (static_branch_likely(&supports_deactivate_key) &&
1065 gic == &gic_data[0]) ? &gic_chip_mode1 : &gic_chip;
1066
1067 switch (hw) {
1068 case 0 ... 31:
1069 irq_set_percpu_devid(irq);
1070 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1071 handle_percpu_devid_irq, NULL, NULL);
1072 break;
1073 default:
1074 irq_domain_set_info(d, irq, hw, chip, d->host_data,
1075 handle_fasteoi_irq, NULL, NULL);
1076 irq_set_probe(irq);
1077 irqd_set_single_target(irqd);
1078 break;
1079 }
1080
1081 /* Prevents SW retriggers which mess up the ACK/EOI ordering */
1082 irqd_set_handle_enforce_irqctx(irqd);
1083 return 0;
1084}
1085
1086static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
1087{
1088}
1089
1090static int gic_irq_domain_translate(struct irq_domain *d,
1091 struct irq_fwspec *fwspec,
1092 unsigned long *hwirq,
1093 unsigned int *type)
1094{
1095 if (fwspec->param_count == 1 && fwspec->param[0] < 16) {
1096 *hwirq = fwspec->param[0];
1097 *type = IRQ_TYPE_EDGE_RISING;
1098 return 0;
1099 }
1100
1101 if (is_of_node(fwspec->fwnode)) {
1102 if (fwspec->param_count < 3)
1103 return -EINVAL;
1104
1105 switch (fwspec->param[0]) {
1106 case 0: /* SPI */
1107 *hwirq = fwspec->param[1] + 32;
1108 break;
1109 case 1: /* PPI */
1110 *hwirq = fwspec->param[1] + 16;
1111 break;
1112 default:
1113 return -EINVAL;
1114 }
1115
1116 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
1117
1118 /* Make it clear that broken DTs are... broken */
1119 WARN(*type == IRQ_TYPE_NONE,
1120 "HW irq %ld has invalid type\n", *hwirq);
1121 return 0;
1122 }
1123
1124 if (is_fwnode_irqchip(fwspec->fwnode)) {
1125 if(fwspec->param_count != 2)
1126 return -EINVAL;
1127
1128 if (fwspec->param[0] < 16) {
1129 pr_err(FW_BUG "Illegal GSI%d translation request\n",
1130 fwspec->param[0]);
1131 return -EINVAL;
1132 }
1133
1134 *hwirq = fwspec->param[0];
1135 *type = fwspec->param[1];
1136
1137 WARN(*type == IRQ_TYPE_NONE,
1138 "HW irq %ld has invalid type\n", *hwirq);
1139 return 0;
1140 }
1141
1142 return -EINVAL;
1143}
1144
1145static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
1146 unsigned int nr_irqs, void *arg)
1147{
1148 int i, ret;
1149 irq_hw_number_t hwirq;
1150 unsigned int type = IRQ_TYPE_NONE;
1151 struct irq_fwspec *fwspec = arg;
1152
1153 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type);
1154 if (ret)
1155 return ret;
1156
1157 for (i = 0; i < nr_irqs; i++) {
1158 ret = gic_irq_domain_map(domain, virq + i, hwirq + i);
1159 if (ret)
1160 return ret;
1161 }
1162
1163 return 0;
1164}
1165
1166static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
1167 .translate = gic_irq_domain_translate,
1168 .alloc = gic_irq_domain_alloc,
1169 .free = irq_domain_free_irqs_top,
1170};
1171
1172static const struct irq_domain_ops gic_irq_domain_ops = {
1173 .map = gic_irq_domain_map,
1174 .unmap = gic_irq_domain_unmap,
1175};
1176
1177static int gic_init_bases(struct gic_chip_data *gic,
1178 struct fwnode_handle *handle)
1179{
1180 int gic_irqs, ret;
1181
1182 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1183 /* Frankein-GIC without banked registers... */
1184 unsigned int cpu;
1185
1186 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
1187 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
1188 if (WARN_ON(!gic->dist_base.percpu_base ||
1189 !gic->cpu_base.percpu_base)) {
1190 ret = -ENOMEM;
1191 goto error;
1192 }
1193
1194 for_each_possible_cpu(cpu) {
1195 u32 mpidr = cpu_logical_map(cpu);
1196 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
1197 unsigned long offset = gic->percpu_offset * core_id;
1198 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) =
1199 gic->raw_dist_base + offset;
1200 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =
1201 gic->raw_cpu_base + offset;
1202 }
1203
1204 enable_frankengic();
1205 } else {
1206 /* Normal, sane GIC... */
1207 WARN(gic->percpu_offset,
1208 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
1209 gic->percpu_offset);
1210 gic->dist_base.common_base = gic->raw_dist_base;
1211 gic->cpu_base.common_base = gic->raw_cpu_base;
1212 }
1213
1214 /*
1215 * Find out how many interrupts are supported.
1216 * The GIC only supports up to 1020 interrupt sources.
1217 */
1218 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
1219 gic_irqs = (gic_irqs + 1) * 32;
1220 if (gic_irqs > 1020)
1221 gic_irqs = 1020;
1222 gic->gic_irqs = gic_irqs;
1223
1224 if (handle) { /* DT/ACPI */
1225 gic->domain = irq_domain_create_linear(handle, gic_irqs,
1226 &gic_irq_domain_hierarchy_ops,
1227 gic);
1228 } else { /* Legacy support */
1229 /*
1230 * For primary GICs, skip over SGIs.
1231 * No secondary GIC support whatsoever.
1232 */
1233 int irq_base;
1234
1235 gic_irqs -= 16; /* calculate # of irqs to allocate */
1236
1237 irq_base = irq_alloc_descs(16, 16, gic_irqs,
1238 numa_node_id());
1239 if (irq_base < 0) {
1240 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n");
1241 irq_base = 16;
1242 }
1243
1244 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,
1245 16, &gic_irq_domain_ops, gic);
1246 }
1247
1248 if (WARN_ON(!gic->domain)) {
1249 ret = -ENODEV;
1250 goto error;
1251 }
1252
1253 gic_dist_init(gic);
1254 ret = gic_cpu_init(gic);
1255 if (ret)
1256 goto error;
1257
1258 ret = gic_pm_init(gic);
1259 if (ret)
1260 goto error;
1261
1262 return 0;
1263
1264error:
1265 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {
1266 free_percpu(gic->dist_base.percpu_base);
1267 free_percpu(gic->cpu_base.percpu_base);
1268 }
1269
1270 return ret;
1271}
1272
1273static int __init __gic_init_bases(struct gic_chip_data *gic,
1274 struct fwnode_handle *handle)
1275{
1276 int i, ret;
1277
1278 if (WARN_ON(!gic || gic->domain))
1279 return -EINVAL;
1280
1281 if (gic == &gic_data[0]) {
1282 /*
1283 * Initialize the CPU interface map to all CPUs.
1284 * It will be refined as each CPU probes its ID.
1285 * This is only necessary for the primary GIC.
1286 */
1287 for (i = 0; i < NR_GIC_CPU_IF; i++)
1288 gic_cpu_map[i] = 0xff;
1289
1290 set_handle_irq(gic_handle_irq);
1291 if (static_branch_likely(&supports_deactivate_key))
1292 pr_info("GIC: Using split EOI/Deactivate mode\n");
1293 }
1294
1295 ret = gic_init_bases(gic, handle);
1296 if (gic == &gic_data[0])
1297 gic_smp_init();
1298
1299 return ret;
1300}
1301
1302void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base)
1303{
1304 struct gic_chip_data *gic;
1305
1306 /*
1307 * Non-DT/ACPI systems won't run a hypervisor, so let's not
1308 * bother with these...
1309 */
1310 static_branch_disable(&supports_deactivate_key);
1311
1312 gic = &gic_data[0];
1313 gic->raw_dist_base = dist_base;
1314 gic->raw_cpu_base = cpu_base;
1315
1316 __gic_init_bases(gic, NULL);
1317}
1318
1319static void gic_teardown(struct gic_chip_data *gic)
1320{
1321 if (WARN_ON(!gic))
1322 return;
1323
1324 if (gic->raw_dist_base)
1325 iounmap(gic->raw_dist_base);
1326 if (gic->raw_cpu_base)
1327 iounmap(gic->raw_cpu_base);
1328}
1329
1330#ifdef CONFIG_OF
1331static int gic_cnt __initdata;
1332static bool gicv2_force_probe;
1333
1334static int __init gicv2_force_probe_cfg(char *buf)
1335{
1336 return kstrtobool(buf, &gicv2_force_probe);
1337}
1338early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg);
1339
1340static bool gic_check_eoimode(struct device_node *node, void __iomem **base)
1341{
1342 struct resource cpuif_res;
1343
1344 of_address_to_resource(node, 1, &cpuif_res);
1345
1346 if (!is_hyp_mode_available())
1347 return false;
1348 if (resource_size(&cpuif_res) < SZ_8K) {
1349 void __iomem *alt;
1350 /*
1351 * Check for a stupid firmware that only exposes the
1352 * first page of a GICv2.
1353 */
1354 if (!gic_check_gicv2(*base))
1355 return false;
1356
1357 if (!gicv2_force_probe) {
1358 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");
1359 return false;
1360 }
1361
1362 alt = ioremap(cpuif_res.start, SZ_8K);
1363 if (!alt)
1364 return false;
1365 if (!gic_check_gicv2(alt + SZ_4K)) {
1366 /*
1367 * The first page was that of a GICv2, and
1368 * the second was *something*. Let's trust it
1369 * to be a GICv2, and update the mapping.
1370 */
1371 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",
1372 &cpuif_res.start);
1373 iounmap(*base);
1374 *base = alt;
1375 return true;
1376 }
1377
1378 /*
1379 * We detected *two* initial GICv2 pages in a
1380 * row. Could be a GICv2 aliased over two 64kB
1381 * pages. Update the resource, map the iospace, and
1382 * pray.
1383 */
1384 iounmap(alt);
1385 alt = ioremap(cpuif_res.start, SZ_128K);
1386 if (!alt)
1387 return false;
1388 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",
1389 &cpuif_res.start);
1390 cpuif_res.end = cpuif_res.start + SZ_128K -1;
1391 iounmap(*base);
1392 *base = alt;
1393 }
1394 if (resource_size(&cpuif_res) == SZ_128K) {
1395 /*
1396 * Verify that we have the first 4kB of a GICv2
1397 * aliased over the first 64kB by checking the
1398 * GICC_IIDR register on both ends.
1399 */
1400 if (!gic_check_gicv2(*base) ||
1401 !gic_check_gicv2(*base + 0xf000))
1402 return false;
1403
1404 /*
1405 * Move the base up by 60kB, so that we have a 8kB
1406 * contiguous region, which allows us to use GICC_DIR
1407 * at its normal offset. Please pass me that bucket.
1408 */
1409 *base += 0xf000;
1410 cpuif_res.start += 0xf000;
1411 pr_warn("GIC: Adjusting CPU interface base to %pa\n",
1412 &cpuif_res.start);
1413 }
1414
1415 return true;
1416}
1417
1418static bool gic_enable_rmw_access(void *data)
1419{
1420 /*
1421 * The EMEV2 class of machines has a broken interconnect, and
1422 * locks up on accesses that are less than 32bit. So far, only
1423 * the affinity setting requires it.
1424 */
1425 if (of_machine_is_compatible("renesas,emev2")) {
1426 static_branch_enable(&needs_rmw_access);
1427 return true;
1428 }
1429
1430 return false;
1431}
1432
1433static const struct gic_quirk gic_quirks[] = {
1434 {
1435 .desc = "broken byte access",
1436 .compatible = "arm,pl390",
1437 .init = gic_enable_rmw_access,
1438 },
1439 { },
1440};
1441
1442static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)
1443{
1444 if (!gic || !node)
1445 return -EINVAL;
1446
1447 gic->raw_dist_base = of_iomap(node, 0);
1448 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))
1449 goto error;
1450
1451 gic->raw_cpu_base = of_iomap(node, 1);
1452 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))
1453 goto error;
1454
1455 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))
1456 gic->percpu_offset = 0;
1457
1458 gic_enable_of_quirks(node, gic_quirks, gic);
1459
1460 return 0;
1461
1462error:
1463 gic_teardown(gic);
1464
1465 return -ENOMEM;
1466}
1467
1468int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1469{
1470 int ret;
1471
1472 if (!dev || !dev->of_node || !gic || !irq)
1473 return -EINVAL;
1474
1475 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);
1476 if (!*gic)
1477 return -ENOMEM;
1478
1479 ret = gic_of_setup(*gic, dev->of_node);
1480 if (ret)
1481 return ret;
1482
1483 ret = gic_init_bases(*gic, &dev->of_node->fwnode);
1484 if (ret) {
1485 gic_teardown(*gic);
1486 return ret;
1487 }
1488
1489 irq_domain_set_pm_device((*gic)->domain, dev);
1490 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);
1491
1492 return 0;
1493}
1494
1495static void __init gic_of_setup_kvm_info(struct device_node *node)
1496{
1497 int ret;
1498 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1499 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1500
1501 gic_v2_kvm_info.type = GIC_V2;
1502
1503 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0);
1504 if (!gic_v2_kvm_info.maint_irq)
1505 return;
1506
1507 ret = of_address_to_resource(node, 2, vctrl_res);
1508 if (ret)
1509 return;
1510
1511 ret = of_address_to_resource(node, 3, vcpu_res);
1512 if (ret)
1513 return;
1514
1515 if (static_branch_likely(&supports_deactivate_key))
1516 vgic_set_kvm_info(&gic_v2_kvm_info);
1517}
1518
1519int __init
1520gic_of_init(struct device_node *node, struct device_node *parent)
1521{
1522 struct gic_chip_data *gic;
1523 int irq, ret;
1524
1525 if (WARN_ON(!node))
1526 return -ENODEV;
1527
1528 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR))
1529 return -EINVAL;
1530
1531 gic = &gic_data[gic_cnt];
1532
1533 ret = gic_of_setup(gic, node);
1534 if (ret)
1535 return ret;
1536
1537 /*
1538 * Disable split EOI/Deactivate if either HYP is not available
1539 * or the CPU interface is too small.
1540 */
1541 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))
1542 static_branch_disable(&supports_deactivate_key);
1543
1544 ret = __gic_init_bases(gic, &node->fwnode);
1545 if (ret) {
1546 gic_teardown(gic);
1547 return ret;
1548 }
1549
1550 if (!gic_cnt) {
1551 gic_init_physaddr(node);
1552 gic_of_setup_kvm_info(node);
1553 }
1554
1555 if (parent) {
1556 irq = irq_of_parse_and_map(node, 0);
1557 gic_cascade_irq(gic_cnt, irq);
1558 }
1559
1560 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1561 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain);
1562
1563 gic_cnt++;
1564 return 0;
1565}
1566IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1567IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1568IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1569IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1570IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1571IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1572IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1573IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1574IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init);
1575#else
1576int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)
1577{
1578 return -ENOTSUPP;
1579}
1580#endif
1581
1582#ifdef CONFIG_ACPI
1583static struct
1584{
1585 phys_addr_t cpu_phys_base;
1586 u32 maint_irq;
1587 int maint_irq_mode;
1588 phys_addr_t vctrl_base;
1589 phys_addr_t vcpu_base;
1590} acpi_data __initdata;
1591
1592static int __init
1593gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header,
1594 const unsigned long end)
1595{
1596 struct acpi_madt_generic_interrupt *processor;
1597 phys_addr_t gic_cpu_base;
1598 static int cpu_base_assigned;
1599
1600 processor = (struct acpi_madt_generic_interrupt *)header;
1601
1602 if (BAD_MADT_GICC_ENTRY(processor, end))
1603 return -EINVAL;
1604
1605 /*
1606 * There is no support for non-banked GICv1/2 register in ACPI spec.
1607 * All CPU interface addresses have to be the same.
1608 */
1609 gic_cpu_base = processor->base_address;
1610 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base)
1611 return -EINVAL;
1612
1613 acpi_data.cpu_phys_base = gic_cpu_base;
1614 acpi_data.maint_irq = processor->vgic_interrupt;
1615 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
1616 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
1617 acpi_data.vctrl_base = processor->gich_base_address;
1618 acpi_data.vcpu_base = processor->gicv_base_address;
1619
1620 cpu_base_assigned = 1;
1621 return 0;
1622}
1623
1624/* The things you have to do to just *count* something... */
1625static int __init acpi_dummy_func(union acpi_subtable_headers *header,
1626 const unsigned long end)
1627{
1628 return 0;
1629}
1630
1631static bool __init acpi_gic_redist_is_present(void)
1632{
1633 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR,
1634 acpi_dummy_func, 0) > 0;
1635}
1636
1637static bool __init gic_validate_dist(struct acpi_subtable_header *header,
1638 struct acpi_probe_entry *ape)
1639{
1640 struct acpi_madt_generic_distributor *dist;
1641 dist = (struct acpi_madt_generic_distributor *)header;
1642
1643 return (dist->version == ape->driver_data &&
1644 (dist->version != ACPI_MADT_GIC_VERSION_NONE ||
1645 !acpi_gic_redist_is_present()));
1646}
1647
1648#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
1649#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
1650#define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K)
1651#define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K)
1652
1653static void __init gic_acpi_setup_kvm_info(void)
1654{
1655 int irq;
1656 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl;
1657 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu;
1658
1659 gic_v2_kvm_info.type = GIC_V2;
1660
1661 if (!acpi_data.vctrl_base)
1662 return;
1663
1664 vctrl_res->flags = IORESOURCE_MEM;
1665 vctrl_res->start = acpi_data.vctrl_base;
1666 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1;
1667
1668 if (!acpi_data.vcpu_base)
1669 return;
1670
1671 vcpu_res->flags = IORESOURCE_MEM;
1672 vcpu_res->start = acpi_data.vcpu_base;
1673 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1;
1674
1675 irq = acpi_register_gsi(NULL, acpi_data.maint_irq,
1676 acpi_data.maint_irq_mode,
1677 ACPI_ACTIVE_HIGH);
1678 if (irq <= 0)
1679 return;
1680
1681 gic_v2_kvm_info.maint_irq = irq;
1682
1683 vgic_set_kvm_info(&gic_v2_kvm_info);
1684}
1685
1686static struct fwnode_handle *gsi_domain_handle;
1687
1688static struct fwnode_handle *gic_v2_get_gsi_domain_id(u32 gsi)
1689{
1690 return gsi_domain_handle;
1691}
1692
1693static int __init gic_v2_acpi_init(union acpi_subtable_headers *header,
1694 const unsigned long end)
1695{
1696 struct acpi_madt_generic_distributor *dist;
1697 struct gic_chip_data *gic = &gic_data[0];
1698 int count, ret;
1699
1700 /* Collect CPU base addresses */
1701 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
1702 gic_acpi_parse_madt_cpu, 0);
1703 if (count <= 0) {
1704 pr_err("No valid GICC entries exist\n");
1705 return -EINVAL;
1706 }
1707
1708 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);
1709 if (!gic->raw_cpu_base) {
1710 pr_err("Unable to map GICC registers\n");
1711 return -ENOMEM;
1712 }
1713
1714 dist = (struct acpi_madt_generic_distributor *)header;
1715 gic->raw_dist_base = ioremap(dist->base_address,
1716 ACPI_GICV2_DIST_MEM_SIZE);
1717 if (!gic->raw_dist_base) {
1718 pr_err("Unable to map GICD registers\n");
1719 gic_teardown(gic);
1720 return -ENOMEM;
1721 }
1722
1723 /*
1724 * Disable split EOI/Deactivate if HYP is not available. ACPI
1725 * guarantees that we'll always have a GICv2, so the CPU
1726 * interface will always be the right size.
1727 */
1728 if (!is_hyp_mode_available())
1729 static_branch_disable(&supports_deactivate_key);
1730
1731 /*
1732 * Initialize GIC instance zero (no multi-GIC support).
1733 */
1734 gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address);
1735 if (!gsi_domain_handle) {
1736 pr_err("Unable to allocate domain handle\n");
1737 gic_teardown(gic);
1738 return -ENOMEM;
1739 }
1740
1741 ret = __gic_init_bases(gic, gsi_domain_handle);
1742 if (ret) {
1743 pr_err("Failed to initialise GIC\n");
1744 irq_domain_free_fwnode(gsi_domain_handle);
1745 gic_teardown(gic);
1746 return ret;
1747 }
1748
1749 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, gic_v2_get_gsi_domain_id);
1750
1751 if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1752 gicv2m_init(NULL, gic_data[0].domain);
1753
1754 if (static_branch_likely(&supports_deactivate_key))
1755 gic_acpi_setup_kvm_info();
1756
1757 return 0;
1758}
1759IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1760 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2,
1761 gic_v2_acpi_init);
1762IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR,
1763 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE,
1764 gic_v2_acpi_init);
1765#endif