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1/*
2 * Copyright (c) 2013 NVIDIA Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 *
16 */
17
18 /*
19 * Function naming determines intended use:
20 *
21 * <x>_r(void) : Returns the offset for register <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50
51#ifndef HOST1X_HW_HOST1X02_UCLASS_H
52#define HOST1X_HW_HOST1X02_UCLASS_H
53
54static inline u32 host1x_uclass_incr_syncpt_r(void)
55{
56 return 0x0;
57}
58#define HOST1X_UCLASS_INCR_SYNCPT \
59 host1x_uclass_incr_syncpt_r()
60static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
61{
62 return (v & 0xff) << 8;
63}
64#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
65 host1x_uclass_incr_syncpt_cond_f(v)
66static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
67{
68 return (v & 0xff) << 0;
69}
70#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
71 host1x_uclass_incr_syncpt_indx_f(v)
72static inline u32 host1x_uclass_wait_syncpt_r(void)
73{
74 return 0x8;
75}
76#define HOST1X_UCLASS_WAIT_SYNCPT \
77 host1x_uclass_wait_syncpt_r()
78static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
79{
80 return (v & 0xff) << 24;
81}
82#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
83 host1x_uclass_wait_syncpt_indx_f(v)
84static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
85{
86 return (v & 0xffffff) << 0;
87}
88#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
89 host1x_uclass_wait_syncpt_thresh_f(v)
90static inline u32 host1x_uclass_wait_syncpt_base_r(void)
91{
92 return 0x9;
93}
94#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
95 host1x_uclass_wait_syncpt_base_r()
96static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
97{
98 return (v & 0xff) << 24;
99}
100#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
101 host1x_uclass_wait_syncpt_base_indx_f(v)
102static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
103{
104 return (v & 0xff) << 16;
105}
106#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
107 host1x_uclass_wait_syncpt_base_base_indx_f(v)
108static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
109{
110 return (v & 0xffff) << 0;
111}
112#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
113 host1x_uclass_wait_syncpt_base_offset_f(v)
114static inline u32 host1x_uclass_load_syncpt_base_r(void)
115{
116 return 0xb;
117}
118#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
119 host1x_uclass_load_syncpt_base_r()
120static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
121{
122 return (v & 0xff) << 24;
123}
124#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
125 host1x_uclass_load_syncpt_base_base_indx_f(v)
126static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
127{
128 return (v & 0xffffff) << 0;
129}
130#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
131 host1x_uclass_load_syncpt_base_value_f(v)
132static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
133{
134 return (v & 0xff) << 24;
135}
136#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
137 host1x_uclass_incr_syncpt_base_base_indx_f(v)
138static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
139{
140 return (v & 0xffffff) << 0;
141}
142#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
143 host1x_uclass_incr_syncpt_base_offset_f(v)
144static inline u32 host1x_uclass_indoff_r(void)
145{
146 return 0x2d;
147}
148#define HOST1X_UCLASS_INDOFF \
149 host1x_uclass_indoff_r()
150static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
151{
152 return (v & 0xf) << 28;
153}
154#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
155 host1x_uclass_indoff_indbe_f(v)
156static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
157{
158 return (v & 0x1) << 27;
159}
160#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
161 host1x_uclass_indoff_autoinc_f(v)
162static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
163{
164 return (v & 0xff) << 18;
165}
166#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
167 host1x_uclass_indoff_indmodid_f(v)
168static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
169{
170 return (v & 0xffff) << 2;
171}
172#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
173 host1x_uclass_indoff_indroffset_f(v)
174static inline u32 host1x_uclass_indoff_rwn_read_v(void)
175{
176 return 1;
177}
178#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
179 host1x_uclass_indoff_indroffset_f(v)
180
181#endif
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2013 NVIDIA Corporation.
4 */
5
6 /*
7 * Function naming determines intended use:
8 *
9 * <x>_r(void) : Returns the offset for register <x>.
10 *
11 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
12 *
13 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
14 *
15 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
16 * and masked to place it at field <y> of register <x>. This value
17 * can be |'d with others to produce a full register value for
18 * register <x>.
19 *
20 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
21 * value can be ~'d and then &'d to clear the value of field <y> for
22 * register <x>.
23 *
24 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
25 * to place it at field <y> of register <x>. This value can be |'d
26 * with others to produce a full register value for <x>.
27 *
28 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
29 * <x> value 'r' after being shifted to place its LSB at bit 0.
30 * This value is suitable for direct comparison with other unshifted
31 * values appropriate for use in field <y> of register <x>.
32 *
33 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
34 * field <y> of register <x>. This value is suitable for direct
35 * comparison with unshifted values appropriate for use in field <y>
36 * of register <x>.
37 */
38
39#ifndef HOST1X_HW_HOST1X02_UCLASS_H
40#define HOST1X_HW_HOST1X02_UCLASS_H
41
42static inline u32 host1x_uclass_incr_syncpt_r(void)
43{
44 return 0x0;
45}
46#define HOST1X_UCLASS_INCR_SYNCPT \
47 host1x_uclass_incr_syncpt_r()
48static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
49{
50 return (v & 0xff) << 8;
51}
52#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
53 host1x_uclass_incr_syncpt_cond_f(v)
54static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
55{
56 return (v & 0xff) << 0;
57}
58#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
59 host1x_uclass_incr_syncpt_indx_f(v)
60static inline u32 host1x_uclass_wait_syncpt_r(void)
61{
62 return 0x8;
63}
64#define HOST1X_UCLASS_WAIT_SYNCPT \
65 host1x_uclass_wait_syncpt_r()
66static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
67{
68 return (v & 0xff) << 24;
69}
70#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
71 host1x_uclass_wait_syncpt_indx_f(v)
72static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
73{
74 return (v & 0xffffff) << 0;
75}
76#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
77 host1x_uclass_wait_syncpt_thresh_f(v)
78static inline u32 host1x_uclass_wait_syncpt_base_r(void)
79{
80 return 0x9;
81}
82#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
83 host1x_uclass_wait_syncpt_base_r()
84static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
85{
86 return (v & 0xff) << 24;
87}
88#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
89 host1x_uclass_wait_syncpt_base_indx_f(v)
90static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
91{
92 return (v & 0xff) << 16;
93}
94#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
95 host1x_uclass_wait_syncpt_base_base_indx_f(v)
96static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
97{
98 return (v & 0xffff) << 0;
99}
100#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
101 host1x_uclass_wait_syncpt_base_offset_f(v)
102static inline u32 host1x_uclass_load_syncpt_base_r(void)
103{
104 return 0xb;
105}
106#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
107 host1x_uclass_load_syncpt_base_r()
108static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
109{
110 return (v & 0xff) << 24;
111}
112#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
113 host1x_uclass_load_syncpt_base_base_indx_f(v)
114static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
115{
116 return (v & 0xffffff) << 0;
117}
118#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
119 host1x_uclass_load_syncpt_base_value_f(v)
120static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
121{
122 return (v & 0xff) << 24;
123}
124#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
125 host1x_uclass_incr_syncpt_base_base_indx_f(v)
126static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
127{
128 return (v & 0xffffff) << 0;
129}
130#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
131 host1x_uclass_incr_syncpt_base_offset_f(v)
132static inline u32 host1x_uclass_indoff_r(void)
133{
134 return 0x2d;
135}
136#define HOST1X_UCLASS_INDOFF \
137 host1x_uclass_indoff_r()
138static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
139{
140 return (v & 0xf) << 28;
141}
142#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
143 host1x_uclass_indoff_indbe_f(v)
144static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
145{
146 return (v & 0x1) << 27;
147}
148#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
149 host1x_uclass_indoff_autoinc_f(v)
150static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
151{
152 return (v & 0xff) << 18;
153}
154#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
155 host1x_uclass_indoff_indmodid_f(v)
156static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
157{
158 return (v & 0xffff) << 2;
159}
160#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
161 host1x_uclass_indoff_indroffset_f(v)
162static inline u32 host1x_uclass_indoff_rwn_read_v(void)
163{
164 return 1;
165}
166#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
167 host1x_uclass_indoff_indroffset_f(v)
168static inline u32 host1x_uclass_load_syncpt_payload_32_r(void)
169{
170 return 0x4e;
171}
172#define HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32 \
173 host1x_uclass_load_syncpt_payload_32_r()
174static inline u32 host1x_uclass_wait_syncpt_32_r(void)
175{
176 return 0x50;
177}
178#define HOST1X_UCLASS_WAIT_SYNCPT_32 \
179 host1x_uclass_wait_syncpt_32_r()
180
181#endif