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1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#ifndef VIRTIO_DRV_H
27#define VIRTIO_DRV_H
28
29#include <linux/virtio.h>
30#include <linux/virtio_ids.h>
31#include <linux/virtio_config.h>
32#include <linux/virtio_gpu.h>
33
34#include <drm/drmP.h>
35#include <drm/drm_gem.h>
36#include <drm/drm_crtc_helper.h>
37#include <ttm/ttm_bo_api.h>
38#include <ttm/ttm_bo_driver.h>
39#include <ttm/ttm_placement.h>
40#include <ttm/ttm_module.h>
41
42#define DRIVER_NAME "virtio_gpu"
43#define DRIVER_DESC "virtio GPU"
44#define DRIVER_DATE "0"
45
46#define DRIVER_MAJOR 0
47#define DRIVER_MINOR 0
48#define DRIVER_PATCHLEVEL 1
49
50/* virtgpu_drm_bus.c */
51int drm_virtio_set_busid(struct drm_device *dev, struct drm_master *master);
52int drm_virtio_init(struct drm_driver *driver, struct virtio_device *vdev);
53
54struct virtio_gpu_object {
55 struct drm_gem_object gem_base;
56 uint32_t hw_res_handle;
57
58 struct sg_table *pages;
59 void *vmap;
60 bool dumb;
61 struct ttm_place placement_code;
62 struct ttm_placement placement;
63 struct ttm_buffer_object tbo;
64 struct ttm_bo_kmap_obj kmap;
65};
66#define gem_to_virtio_gpu_obj(gobj) \
67 container_of((gobj), struct virtio_gpu_object, gem_base)
68
69struct virtio_gpu_vbuffer;
70struct virtio_gpu_device;
71
72typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
73 struct virtio_gpu_vbuffer *vbuf);
74
75struct virtio_gpu_fence_driver {
76 atomic64_t last_seq;
77 uint64_t sync_seq;
78 struct list_head fences;
79 spinlock_t lock;
80};
81
82struct virtio_gpu_fence {
83 struct fence f;
84 struct virtio_gpu_fence_driver *drv;
85 struct list_head node;
86 uint64_t seq;
87};
88#define to_virtio_fence(x) \
89 container_of(x, struct virtio_gpu_fence, f)
90
91struct virtio_gpu_vbuffer {
92 char *buf;
93 int size;
94
95 void *data_buf;
96 uint32_t data_size;
97
98 char *resp_buf;
99 int resp_size;
100
101 virtio_gpu_resp_cb resp_cb;
102
103 struct list_head list;
104};
105
106struct virtio_gpu_output {
107 int index;
108 struct drm_crtc crtc;
109 struct drm_connector conn;
110 struct drm_encoder enc;
111 struct virtio_gpu_display_one info;
112 struct virtio_gpu_update_cursor cursor;
113 int cur_x;
114 int cur_y;
115};
116#define drm_crtc_to_virtio_gpu_output(x) \
117 container_of(x, struct virtio_gpu_output, crtc)
118#define drm_connector_to_virtio_gpu_output(x) \
119 container_of(x, struct virtio_gpu_output, conn)
120#define drm_encoder_to_virtio_gpu_output(x) \
121 container_of(x, struct virtio_gpu_output, enc)
122
123struct virtio_gpu_framebuffer {
124 struct drm_framebuffer base;
125 struct drm_gem_object *obj;
126 int x1, y1, x2, y2; /* dirty rect */
127 spinlock_t dirty_lock;
128 uint32_t hw_res_handle;
129};
130#define to_virtio_gpu_framebuffer(x) \
131 container_of(x, struct virtio_gpu_framebuffer, base)
132
133struct virtio_gpu_mman {
134 struct ttm_bo_global_ref bo_global_ref;
135 struct drm_global_reference mem_global_ref;
136 bool mem_global_referenced;
137 struct ttm_bo_device bdev;
138};
139
140struct virtio_gpu_fbdev;
141
142struct virtio_gpu_queue {
143 struct virtqueue *vq;
144 spinlock_t qlock;
145 wait_queue_head_t ack_queue;
146 struct work_struct dequeue_work;
147};
148
149struct virtio_gpu_drv_capset {
150 uint32_t id;
151 uint32_t max_version;
152 uint32_t max_size;
153};
154
155struct virtio_gpu_drv_cap_cache {
156 struct list_head head;
157 void *caps_cache;
158 uint32_t id;
159 uint32_t version;
160 uint32_t size;
161 atomic_t is_valid;
162};
163
164struct virtio_gpu_device {
165 struct device *dev;
166 struct drm_device *ddev;
167
168 struct virtio_device *vdev;
169
170 struct virtio_gpu_mman mman;
171
172 /* pointer to fbdev info structure */
173 struct virtio_gpu_fbdev *vgfbdev;
174 struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
175 uint32_t num_scanouts;
176
177 struct virtio_gpu_queue ctrlq;
178 struct virtio_gpu_queue cursorq;
179 struct list_head free_vbufs;
180 spinlock_t free_vbufs_lock;
181 void *vbufs;
182 bool vqs_ready;
183
184 struct idr resource_idr;
185 spinlock_t resource_idr_lock;
186
187 wait_queue_head_t resp_wq;
188 /* current display info */
189 spinlock_t display_info_lock;
190 bool display_info_pending;
191
192 struct virtio_gpu_fence_driver fence_drv;
193
194 struct idr ctx_id_idr;
195 spinlock_t ctx_id_idr_lock;
196
197 bool has_virgl_3d;
198
199 struct work_struct config_changed_work;
200
201 struct virtio_gpu_drv_capset *capsets;
202 uint32_t num_capsets;
203 struct list_head cap_cache;
204};
205
206struct virtio_gpu_fpriv {
207 uint32_t ctx_id;
208};
209
210/* virtio_ioctl.c */
211#define DRM_VIRTIO_NUM_IOCTLS 10
212extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
213
214/* virtio_kms.c */
215int virtio_gpu_driver_load(struct drm_device *dev, unsigned long flags);
216int virtio_gpu_driver_unload(struct drm_device *dev);
217int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
218void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);
219
220/* virtio_gem.c */
221void virtio_gpu_gem_free_object(struct drm_gem_object *gem_obj);
222int virtio_gpu_gem_init(struct virtio_gpu_device *vgdev);
223void virtio_gpu_gem_fini(struct virtio_gpu_device *vgdev);
224int virtio_gpu_gem_create(struct drm_file *file,
225 struct drm_device *dev,
226 uint64_t size,
227 struct drm_gem_object **obj_p,
228 uint32_t *handle_p);
229int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
230 struct drm_file *file);
231void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
232 struct drm_file *file);
233struct virtio_gpu_object *virtio_gpu_alloc_object(struct drm_device *dev,
234 size_t size, bool kernel,
235 bool pinned);
236int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
237 struct drm_device *dev,
238 struct drm_mode_create_dumb *args);
239int virtio_gpu_mode_dumb_destroy(struct drm_file *file_priv,
240 struct drm_device *dev,
241 uint32_t handle);
242int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
243 struct drm_device *dev,
244 uint32_t handle, uint64_t *offset_p);
245
246/* virtio_fb */
247#define VIRTIO_GPUFB_CONN_LIMIT 1
248int virtio_gpu_fbdev_init(struct virtio_gpu_device *vgdev);
249void virtio_gpu_fbdev_fini(struct virtio_gpu_device *vgdev);
250int virtio_gpu_surface_dirty(struct virtio_gpu_framebuffer *qfb,
251 struct drm_clip_rect *clips,
252 unsigned num_clips);
253/* virtio vg */
254int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
255void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
256void virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,
257 uint32_t *resid);
258void virtio_gpu_resource_id_put(struct virtio_gpu_device *vgdev, uint32_t id);
259void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
260 uint32_t resource_id,
261 uint32_t format,
262 uint32_t width,
263 uint32_t height);
264void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
265 uint32_t resource_id);
266void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
267 uint32_t resource_id, uint64_t offset,
268 __le32 width, __le32 height,
269 __le32 x, __le32 y,
270 struct virtio_gpu_fence **fence);
271void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
272 uint32_t resource_id,
273 uint32_t x, uint32_t y,
274 uint32_t width, uint32_t height);
275void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
276 uint32_t scanout_id, uint32_t resource_id,
277 uint32_t width, uint32_t height,
278 uint32_t x, uint32_t y);
279int virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
280 struct virtio_gpu_object *obj,
281 uint32_t resource_id,
282 struct virtio_gpu_fence **fence);
283int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev);
284int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev);
285void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
286 struct virtio_gpu_output *output);
287int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
288void virtio_gpu_cmd_resource_inval_backing(struct virtio_gpu_device *vgdev,
289 uint32_t resource_id);
290int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
291int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
292 int idx, int version,
293 struct virtio_gpu_drv_cap_cache **cache_p);
294void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
295 uint32_t nlen, const char *name);
296void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
297 uint32_t id);
298void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
299 uint32_t ctx_id,
300 uint32_t resource_id);
301void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
302 uint32_t ctx_id,
303 uint32_t resource_id);
304void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
305 void *data, uint32_t data_size,
306 uint32_t ctx_id, struct virtio_gpu_fence **fence);
307void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
308 uint32_t resource_id, uint32_t ctx_id,
309 uint64_t offset, uint32_t level,
310 struct virtio_gpu_box *box,
311 struct virtio_gpu_fence **fence);
312void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
313 uint32_t resource_id, uint32_t ctx_id,
314 uint64_t offset, uint32_t level,
315 struct virtio_gpu_box *box,
316 struct virtio_gpu_fence **fence);
317void
318virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
319 struct virtio_gpu_resource_create_3d *rc_3d,
320 struct virtio_gpu_fence **fence);
321void virtio_gpu_ctrl_ack(struct virtqueue *vq);
322void virtio_gpu_cursor_ack(struct virtqueue *vq);
323void virtio_gpu_fence_ack(struct virtqueue *vq);
324void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
325void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
326void virtio_gpu_dequeue_fence_func(struct work_struct *work);
327
328/* virtio_gpu_display.c */
329int virtio_gpu_framebuffer_init(struct drm_device *dev,
330 struct virtio_gpu_framebuffer *vgfb,
331 const struct drm_mode_fb_cmd2 *mode_cmd,
332 struct drm_gem_object *obj);
333int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
334void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
335
336/* virtio_gpu_plane.c */
337struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
338 int index);
339
340/* virtio_gpu_ttm.c */
341int virtio_gpu_ttm_init(struct virtio_gpu_device *vgdev);
342void virtio_gpu_ttm_fini(struct virtio_gpu_device *vgdev);
343int virtio_gpu_mmap(struct file *filp, struct vm_area_struct *vma);
344
345/* virtio_gpu_fence.c */
346int virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
347 struct virtio_gpu_ctrl_hdr *cmd_hdr,
348 struct virtio_gpu_fence **fence);
349void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
350 u64 last_seq);
351
352/* virtio_gpu_object */
353int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
354 unsigned long size, bool kernel, bool pinned,
355 struct virtio_gpu_object **bo_ptr);
356int virtio_gpu_object_kmap(struct virtio_gpu_object *bo, void **ptr);
357int virtio_gpu_object_get_sg_table(struct virtio_gpu_device *qdev,
358 struct virtio_gpu_object *bo);
359void virtio_gpu_object_free_sg_table(struct virtio_gpu_object *bo);
360int virtio_gpu_object_wait(struct virtio_gpu_object *bo, bool no_wait);
361
362/* virtgpu_prime.c */
363int virtgpu_gem_prime_pin(struct drm_gem_object *obj);
364void virtgpu_gem_prime_unpin(struct drm_gem_object *obj);
365struct sg_table *virtgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
366struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
367 struct drm_device *dev, struct dma_buf_attachment *attach,
368 struct sg_table *sgt);
369void *virtgpu_gem_prime_vmap(struct drm_gem_object *obj);
370void virtgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
371int virtgpu_gem_prime_mmap(struct drm_gem_object *obj,
372 struct vm_area_struct *vma);
373
374static inline struct virtio_gpu_object*
375virtio_gpu_object_ref(struct virtio_gpu_object *bo)
376{
377 ttm_bo_reference(&bo->tbo);
378 return bo;
379}
380
381static inline void virtio_gpu_object_unref(struct virtio_gpu_object **bo)
382{
383 struct ttm_buffer_object *tbo;
384
385 if ((*bo) == NULL)
386 return;
387 tbo = &((*bo)->tbo);
388 ttm_bo_unref(&tbo);
389 if (tbo == NULL)
390 *bo = NULL;
391}
392
393static inline u64 virtio_gpu_object_mmap_offset(struct virtio_gpu_object *bo)
394{
395 return drm_vma_node_offset_addr(&bo->tbo.vma_node);
396}
397
398static inline int virtio_gpu_object_reserve(struct virtio_gpu_object *bo,
399 bool no_wait)
400{
401 int r;
402
403 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
404 if (unlikely(r != 0)) {
405 if (r != -ERESTARTSYS) {
406 struct virtio_gpu_device *qdev =
407 bo->gem_base.dev->dev_private;
408 dev_err(qdev->dev, "%p reserve failed\n", bo);
409 }
410 return r;
411 }
412 return 0;
413}
414
415static inline void virtio_gpu_object_unreserve(struct virtio_gpu_object *bo)
416{
417 ttm_bo_unreserve(&bo->tbo);
418}
419
420/* virgl debufs */
421int virtio_gpu_debugfs_init(struct drm_minor *minor);
422void virtio_gpu_debugfs_takedown(struct drm_minor *minor);
423
424#endif
1/*
2 * Copyright (C) 2015 Red Hat, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#ifndef VIRTIO_DRV_H
27#define VIRTIO_DRV_H
28
29#include <linux/dma-direction.h>
30#include <linux/virtio.h>
31#include <linux/virtio_ids.h>
32#include <linux/virtio_config.h>
33#include <linux/virtio_gpu.h>
34
35#include <drm/drm_atomic.h>
36#include <drm/drm_drv.h>
37#include <drm/drm_encoder.h>
38#include <drm/drm_fourcc.h>
39#include <drm/drm_framebuffer.h>
40#include <drm/drm_gem.h>
41#include <drm/drm_gem_shmem_helper.h>
42#include <drm/drm_ioctl.h>
43#include <drm/drm_probe_helper.h>
44#include <drm/virtgpu_drm.h>
45
46#define DRIVER_NAME "virtio_gpu"
47#define DRIVER_DESC "virtio GPU"
48#define DRIVER_DATE "0"
49
50#define DRIVER_MAJOR 0
51#define DRIVER_MINOR 1
52#define DRIVER_PATCHLEVEL 0
53
54#define STATE_INITIALIZING 0
55#define STATE_OK 1
56#define STATE_ERR 2
57
58#define MAX_CAPSET_ID 63
59#define MAX_RINGS 64
60
61struct virtio_gpu_object_params {
62 unsigned long size;
63 bool dumb;
64 /* 3d */
65 bool virgl;
66 bool blob;
67
68 /* classic resources only */
69 uint32_t format;
70 uint32_t width;
71 uint32_t height;
72 uint32_t target;
73 uint32_t bind;
74 uint32_t depth;
75 uint32_t array_size;
76 uint32_t last_level;
77 uint32_t nr_samples;
78 uint32_t flags;
79
80 /* blob resources only */
81 uint32_t ctx_id;
82 uint32_t blob_mem;
83 uint32_t blob_flags;
84 uint64_t blob_id;
85};
86
87struct virtio_gpu_object {
88 struct drm_gem_shmem_object base;
89 uint32_t hw_res_handle;
90 bool dumb;
91 bool created;
92 bool host3d_blob, guest_blob;
93 uint32_t blob_mem, blob_flags;
94
95 int uuid_state;
96 uuid_t uuid;
97};
98#define gem_to_virtio_gpu_obj(gobj) \
99 container_of((gobj), struct virtio_gpu_object, base.base)
100
101struct virtio_gpu_object_shmem {
102 struct virtio_gpu_object base;
103};
104
105struct virtio_gpu_object_vram {
106 struct virtio_gpu_object base;
107 uint32_t map_state;
108 uint32_t map_info;
109 struct drm_mm_node vram_node;
110};
111
112#define to_virtio_gpu_shmem(virtio_gpu_object) \
113 container_of((virtio_gpu_object), struct virtio_gpu_object_shmem, base)
114
115#define to_virtio_gpu_vram(virtio_gpu_object) \
116 container_of((virtio_gpu_object), struct virtio_gpu_object_vram, base)
117
118struct virtio_gpu_object_array {
119 struct ww_acquire_ctx ticket;
120 struct list_head next;
121 u32 nents, total;
122 struct drm_gem_object *objs[];
123};
124
125struct virtio_gpu_vbuffer;
126struct virtio_gpu_device;
127
128typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,
129 struct virtio_gpu_vbuffer *vbuf);
130
131struct virtio_gpu_fence_driver {
132 atomic64_t last_fence_id;
133 uint64_t current_fence_id;
134 uint64_t context;
135 struct list_head fences;
136 spinlock_t lock;
137};
138
139struct virtio_gpu_fence_event {
140 struct drm_pending_event base;
141 struct drm_event event;
142};
143
144struct virtio_gpu_fence {
145 struct dma_fence f;
146 uint32_t ring_idx;
147 uint64_t fence_id;
148 bool emit_fence_info;
149 struct virtio_gpu_fence_event *e;
150 struct virtio_gpu_fence_driver *drv;
151 struct list_head node;
152};
153
154struct virtio_gpu_vbuffer {
155 char *buf;
156 int size;
157
158 void *data_buf;
159 uint32_t data_size;
160
161 char *resp_buf;
162 int resp_size;
163 virtio_gpu_resp_cb resp_cb;
164 void *resp_cb_data;
165
166 struct virtio_gpu_object_array *objs;
167 struct list_head list;
168};
169
170struct virtio_gpu_output {
171 int index;
172 struct drm_crtc crtc;
173 struct drm_connector conn;
174 struct drm_encoder enc;
175 struct virtio_gpu_display_one info;
176 struct virtio_gpu_update_cursor cursor;
177 struct edid *edid;
178 int cur_x;
179 int cur_y;
180 bool needs_modeset;
181};
182#define drm_crtc_to_virtio_gpu_output(x) \
183 container_of(x, struct virtio_gpu_output, crtc)
184
185struct virtio_gpu_framebuffer {
186 struct drm_framebuffer base;
187 struct virtio_gpu_fence *fence;
188};
189#define to_virtio_gpu_framebuffer(x) \
190 container_of(x, struct virtio_gpu_framebuffer, base)
191
192struct virtio_gpu_queue {
193 struct virtqueue *vq;
194 spinlock_t qlock;
195 wait_queue_head_t ack_queue;
196 struct work_struct dequeue_work;
197};
198
199struct virtio_gpu_drv_capset {
200 uint32_t id;
201 uint32_t max_version;
202 uint32_t max_size;
203};
204
205struct virtio_gpu_drv_cap_cache {
206 struct list_head head;
207 void *caps_cache;
208 uint32_t id;
209 uint32_t version;
210 uint32_t size;
211 atomic_t is_valid;
212};
213
214struct virtio_gpu_device {
215 struct drm_device *ddev;
216
217 struct virtio_device *vdev;
218
219 struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];
220 uint32_t num_scanouts;
221
222 struct virtio_gpu_queue ctrlq;
223 struct virtio_gpu_queue cursorq;
224 struct kmem_cache *vbufs;
225
226 atomic_t pending_commands;
227
228 struct ida resource_ida;
229
230 wait_queue_head_t resp_wq;
231 /* current display info */
232 spinlock_t display_info_lock;
233 bool display_info_pending;
234
235 struct virtio_gpu_fence_driver fence_drv;
236
237 struct ida ctx_id_ida;
238
239 bool has_virgl_3d;
240 bool has_edid;
241 bool has_indirect;
242 bool has_resource_assign_uuid;
243 bool has_resource_blob;
244 bool has_host_visible;
245 bool has_context_init;
246 struct virtio_shm_region host_visible_region;
247 struct drm_mm host_visible_mm;
248
249 struct work_struct config_changed_work;
250
251 struct work_struct obj_free_work;
252 spinlock_t obj_free_lock;
253 struct list_head obj_free_list;
254
255 struct virtio_gpu_drv_capset *capsets;
256 uint32_t num_capsets;
257 uint64_t capset_id_mask;
258 struct list_head cap_cache;
259
260 /* protects uuid state when exporting */
261 spinlock_t resource_export_lock;
262 /* protects map state and host_visible_mm */
263 spinlock_t host_visible_lock;
264};
265
266struct virtio_gpu_fpriv {
267 uint32_t ctx_id;
268 uint32_t context_init;
269 bool context_created;
270 uint32_t num_rings;
271 uint64_t base_fence_ctx;
272 uint64_t ring_idx_mask;
273 struct mutex context_lock;
274};
275
276/* virtgpu_ioctl.c */
277#define DRM_VIRTIO_NUM_IOCTLS 12
278extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];
279void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file);
280
281/* virtgpu_kms.c */
282int virtio_gpu_init(struct virtio_device *vdev, struct drm_device *dev);
283void virtio_gpu_deinit(struct drm_device *dev);
284void virtio_gpu_release(struct drm_device *dev);
285int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);
286void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);
287
288/* virtgpu_gem.c */
289int virtio_gpu_gem_object_open(struct drm_gem_object *obj,
290 struct drm_file *file);
291void virtio_gpu_gem_object_close(struct drm_gem_object *obj,
292 struct drm_file *file);
293int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,
294 struct drm_device *dev,
295 struct drm_mode_create_dumb *args);
296int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,
297 struct drm_device *dev,
298 uint32_t handle, uint64_t *offset_p);
299
300struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents);
301struct virtio_gpu_object_array*
302virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents);
303void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs,
304 struct drm_gem_object *obj);
305int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs);
306void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs);
307void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs,
308 struct dma_fence *fence);
309void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs);
310void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev,
311 struct virtio_gpu_object_array *objs);
312void virtio_gpu_array_put_free_work(struct work_struct *work);
313
314/* virtgpu_vq.c */
315int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);
316void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);
317void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,
318 struct virtio_gpu_object *bo,
319 struct virtio_gpu_object_params *params,
320 struct virtio_gpu_object_array *objs,
321 struct virtio_gpu_fence *fence);
322void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,
323 struct virtio_gpu_object *bo);
324void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,
325 uint64_t offset,
326 uint32_t width, uint32_t height,
327 uint32_t x, uint32_t y,
328 struct virtio_gpu_object_array *objs,
329 struct virtio_gpu_fence *fence);
330void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,
331 uint32_t resource_id,
332 uint32_t x, uint32_t y,
333 uint32_t width, uint32_t height,
334 struct virtio_gpu_object_array *objs,
335 struct virtio_gpu_fence *fence);
336void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,
337 uint32_t scanout_id, uint32_t resource_id,
338 uint32_t width, uint32_t height,
339 uint32_t x, uint32_t y);
340void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,
341 struct virtio_gpu_object *obj,
342 struct virtio_gpu_mem_entry *ents,
343 unsigned int nents);
344int virtio_gpu_attach_status_page(struct virtio_gpu_device *vgdev);
345int virtio_gpu_detach_status_page(struct virtio_gpu_device *vgdev);
346void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,
347 struct virtio_gpu_output *output);
348int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);
349int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);
350int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,
351 int idx, int version,
352 struct virtio_gpu_drv_cap_cache **cache_p);
353int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);
354void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,
355 uint32_t context_init, uint32_t nlen,
356 const char *name);
357void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,
358 uint32_t id);
359void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,
360 uint32_t ctx_id,
361 struct virtio_gpu_object_array *objs);
362void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,
363 uint32_t ctx_id,
364 struct virtio_gpu_object_array *objs);
365void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,
366 void *data, uint32_t data_size,
367 uint32_t ctx_id,
368 struct virtio_gpu_object_array *objs,
369 struct virtio_gpu_fence *fence);
370void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,
371 uint32_t ctx_id,
372 uint64_t offset, uint32_t level,
373 uint32_t stride,
374 uint32_t layer_stride,
375 struct drm_virtgpu_3d_box *box,
376 struct virtio_gpu_object_array *objs,
377 struct virtio_gpu_fence *fence);
378void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,
379 uint32_t ctx_id,
380 uint64_t offset, uint32_t level,
381 uint32_t stride,
382 uint32_t layer_stride,
383 struct drm_virtgpu_3d_box *box,
384 struct virtio_gpu_object_array *objs,
385 struct virtio_gpu_fence *fence);
386void
387virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,
388 struct virtio_gpu_object *bo,
389 struct virtio_gpu_object_params *params,
390 struct virtio_gpu_object_array *objs,
391 struct virtio_gpu_fence *fence);
392void virtio_gpu_ctrl_ack(struct virtqueue *vq);
393void virtio_gpu_cursor_ack(struct virtqueue *vq);
394void virtio_gpu_fence_ack(struct virtqueue *vq);
395void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);
396void virtio_gpu_dequeue_cursor_func(struct work_struct *work);
397void virtio_gpu_dequeue_fence_func(struct work_struct *work);
398
399void virtio_gpu_notify(struct virtio_gpu_device *vgdev);
400
401int
402virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev,
403 struct virtio_gpu_object_array *objs);
404
405int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev,
406 struct virtio_gpu_object_array *objs, uint64_t offset);
407
408void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev,
409 struct virtio_gpu_object *bo);
410
411void
412virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev,
413 struct virtio_gpu_object *bo,
414 struct virtio_gpu_object_params *params,
415 struct virtio_gpu_mem_entry *ents,
416 uint32_t nents);
417void
418virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev,
419 uint32_t scanout_id,
420 struct virtio_gpu_object *bo,
421 struct drm_framebuffer *fb,
422 uint32_t width, uint32_t height,
423 uint32_t x, uint32_t y);
424
425/* virtgpu_display.c */
426int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);
427void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);
428
429/* virtgpu_plane.c */
430uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);
431struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,
432 enum drm_plane_type type,
433 int index);
434
435/* virtgpu_fence.c */
436struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev,
437 uint64_t base_fence_ctx,
438 uint32_t ring_idx);
439void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
440 struct virtio_gpu_ctrl_hdr *cmd_hdr,
441 struct virtio_gpu_fence *fence);
442void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,
443 u64 fence_id);
444
445/* virtgpu_object.c */
446void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo);
447struct drm_gem_object *virtio_gpu_create_object(struct drm_device *dev,
448 size_t size);
449int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,
450 struct virtio_gpu_object_params *params,
451 struct virtio_gpu_object **bo_ptr,
452 struct virtio_gpu_fence *fence);
453
454bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo);
455
456int virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,
457 uint32_t *resid);
458/* virtgpu_prime.c */
459int virtio_gpu_resource_assign_uuid(struct virtio_gpu_device *vgdev,
460 struct virtio_gpu_object *bo);
461struct dma_buf *virtgpu_gem_prime_export(struct drm_gem_object *obj,
462 int flags);
463struct drm_gem_object *virtgpu_gem_prime_import(struct drm_device *dev,
464 struct dma_buf *buf);
465int virtgpu_gem_prime_get_uuid(struct drm_gem_object *obj,
466 uuid_t *uuid);
467struct drm_gem_object *virtgpu_gem_prime_import_sg_table(
468 struct drm_device *dev, struct dma_buf_attachment *attach,
469 struct sg_table *sgt);
470
471/* virtgpu_debugfs.c */
472void virtio_gpu_debugfs_init(struct drm_minor *minor);
473
474/* virtgpu_vram.c */
475bool virtio_gpu_is_vram(struct virtio_gpu_object *bo);
476int virtio_gpu_vram_create(struct virtio_gpu_device *vgdev,
477 struct virtio_gpu_object_params *params,
478 struct virtio_gpu_object **bo_ptr);
479struct sg_table *virtio_gpu_vram_map_dma_buf(struct virtio_gpu_object *bo,
480 struct device *dev,
481 enum dma_data_direction dir);
482void virtio_gpu_vram_unmap_dma_buf(struct device *dev,
483 struct sg_table *sgt,
484 enum dma_data_direction dir);
485
486#endif