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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright © 2018 Broadcom
4 *
5 * Authors:
6 * Eric Anholt <eric@anholt.net>
7 * Boris Brezillon <boris.brezillon@bootlin.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/of_graph.h>
13#include <linux/of_platform.h>
14#include <linux/pm_runtime.h>
15
16#include <drm/drm_atomic.h>
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_drv.h>
19#include <drm/drm_edid.h>
20#include <drm/drm_fb_dma_helper.h>
21#include <drm/drm_fourcc.h>
22#include <drm/drm_framebuffer.h>
23#include <drm/drm_panel.h>
24#include <drm/drm_probe_helper.h>
25#include <drm/drm_vblank.h>
26#include <drm/drm_writeback.h>
27
28#include "vc4_drv.h"
29#include "vc4_regs.h"
30
31/* Base address of the output. Raster formats must be 4-byte aligned,
32 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are
33 * inconsistent, but probably utile).
34 */
35#define TXP_DST_PTR 0x00
36
37/* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's
38 * the width in tiles.
39 */
40#define TXP_DST_PITCH 0x04
41/* For T-tiled imgaes, DST_PITCH should be the number of tiles wide,
42 * shifted up.
43 */
44# define TXP_T_TILE_WIDTH_SHIFT 7
45/* For LT-tiled images, DST_PITCH should be the number of utiles wide,
46 * shifted up.
47 */
48# define TXP_LT_TILE_WIDTH_SHIFT 4
49
50/* Pre-rotation width/height of the image. Must match HVS config.
51 *
52 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit
53 * and width/height must be tile or utile-aligned as appropriate. If
54 * transposing (rotating), width is limited to 1920.
55 *
56 * Height is limited to various numbers between 4088 and 4095. I'd
57 * just use 4088 to be safe.
58 */
59#define TXP_DIM 0x08
60# define TXP_HEIGHT_SHIFT 16
61# define TXP_HEIGHT_MASK GENMASK(31, 16)
62# define TXP_WIDTH_SHIFT 0
63# define TXP_WIDTH_MASK GENMASK(15, 0)
64
65#define TXP_DST_CTRL 0x0c
66/* These bits are set to 0x54 */
67#define TXP_PILOT_SHIFT 24
68#define TXP_PILOT_MASK GENMASK(31, 24)
69/* Bits 22-23 are set to 0x01 */
70#define TXP_VERSION_SHIFT 22
71#define TXP_VERSION_MASK GENMASK(23, 22)
72
73/* Powers down the internal memory. */
74# define TXP_POWERDOWN BIT(21)
75
76/* Enables storing the alpha component in 8888/4444, instead of
77 * filling with ~ALPHA_INVERT.
78 */
79# define TXP_ALPHA_ENABLE BIT(20)
80
81/* 4 bits, each enables stores for a channel in each set of 4 bytes.
82 * Set to 0xf for normal operation.
83 */
84# define TXP_BYTE_ENABLE_SHIFT 16
85# define TXP_BYTE_ENABLE_MASK GENMASK(19, 16)
86
87/* Debug: Generate VSTART again at EOF. */
88# define TXP_VSTART_AT_EOF BIT(15)
89
90/* Debug: Terminate the current frame immediately. Stops AXI
91 * writes.
92 */
93# define TXP_ABORT BIT(14)
94
95# define TXP_DITHER BIT(13)
96
97/* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for
98 * !TXP_ALPHA_ENABLE.
99 */
100# define TXP_ALPHA_INVERT BIT(12)
101
102/* Note: I've listed the channels here in high bit (in byte 3/2/1) to
103 * low bit (in byte 0) order.
104 */
105# define TXP_FORMAT_SHIFT 8
106# define TXP_FORMAT_MASK GENMASK(11, 8)
107# define TXP_FORMAT_ABGR4444 0
108# define TXP_FORMAT_ARGB4444 1
109# define TXP_FORMAT_BGRA4444 2
110# define TXP_FORMAT_RGBA4444 3
111# define TXP_FORMAT_BGR565 6
112# define TXP_FORMAT_RGB565 7
113/* 888s are non-rotated, raster-only */
114# define TXP_FORMAT_BGR888 8
115# define TXP_FORMAT_RGB888 9
116# define TXP_FORMAT_ABGR8888 12
117# define TXP_FORMAT_ARGB8888 13
118# define TXP_FORMAT_BGRA8888 14
119# define TXP_FORMAT_RGBA8888 15
120
121/* If TFORMAT is set, generates LT instead of T format. */
122# define TXP_LINEAR_UTILE BIT(7)
123
124/* Rotate output by 90 degrees. */
125# define TXP_TRANSPOSE BIT(6)
126
127/* Generate a tiled format for V3D. */
128# define TXP_TFORMAT BIT(5)
129
130/* Generates some undefined test mode output. */
131# define TXP_TEST_MODE BIT(4)
132
133/* Request odd field from HVS. */
134# define TXP_FIELD BIT(3)
135
136/* Raise interrupt when idle. */
137# define TXP_EI BIT(2)
138
139/* Set when generating a frame, clears when idle. */
140# define TXP_BUSY BIT(1)
141
142/* Starts a frame. Self-clearing. */
143# define TXP_GO BIT(0)
144
145/* Number of lines received and committed to memory. */
146#define TXP_PROGRESS 0x10
147
148#define TXP_READ(offset) readl(txp->regs + (offset))
149#define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))
150
151struct vc4_txp {
152 struct vc4_crtc base;
153
154 struct platform_device *pdev;
155
156 struct drm_writeback_connector connector;
157
158 void __iomem *regs;
159};
160
161static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder)
162{
163 return container_of(encoder, struct vc4_txp, connector.encoder);
164}
165
166static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn)
167{
168 return container_of(conn, struct vc4_txp, connector.base);
169}
170
171static const struct debugfs_reg32 txp_regs[] = {
172 VC4_REG32(TXP_DST_PTR),
173 VC4_REG32(TXP_DST_PITCH),
174 VC4_REG32(TXP_DIM),
175 VC4_REG32(TXP_DST_CTRL),
176 VC4_REG32(TXP_PROGRESS),
177};
178
179static int vc4_txp_connector_get_modes(struct drm_connector *connector)
180{
181 struct drm_device *dev = connector->dev;
182
183 return drm_add_modes_noedid(connector, dev->mode_config.max_width,
184 dev->mode_config.max_height);
185}
186
187static enum drm_mode_status
188vc4_txp_connector_mode_valid(struct drm_connector *connector,
189 struct drm_display_mode *mode)
190{
191 struct drm_device *dev = connector->dev;
192 struct drm_mode_config *mode_config = &dev->mode_config;
193 int w = mode->hdisplay, h = mode->vdisplay;
194
195 if (w < mode_config->min_width || w > mode_config->max_width)
196 return MODE_BAD_HVALUE;
197
198 if (h < mode_config->min_height || h > mode_config->max_height)
199 return MODE_BAD_VVALUE;
200
201 return MODE_OK;
202}
203
204static const u32 drm_fmts[] = {
205 DRM_FORMAT_RGB888,
206 DRM_FORMAT_BGR888,
207 DRM_FORMAT_XRGB8888,
208 DRM_FORMAT_XBGR8888,
209 DRM_FORMAT_ARGB8888,
210 DRM_FORMAT_ABGR8888,
211 DRM_FORMAT_RGBX8888,
212 DRM_FORMAT_BGRX8888,
213 DRM_FORMAT_RGBA8888,
214 DRM_FORMAT_BGRA8888,
215};
216
217static const u32 txp_fmts[] = {
218 TXP_FORMAT_RGB888,
219 TXP_FORMAT_BGR888,
220 TXP_FORMAT_ARGB8888,
221 TXP_FORMAT_ABGR8888,
222 TXP_FORMAT_ARGB8888,
223 TXP_FORMAT_ABGR8888,
224 TXP_FORMAT_RGBA8888,
225 TXP_FORMAT_BGRA8888,
226 TXP_FORMAT_RGBA8888,
227 TXP_FORMAT_BGRA8888,
228};
229
230static void vc4_txp_armed(struct drm_crtc_state *state)
231{
232 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
233
234 vc4_state->txp_armed = true;
235}
236
237static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
238 struct drm_atomic_state *state)
239{
240 struct drm_connector_state *conn_state;
241 struct drm_crtc_state *crtc_state;
242 struct drm_framebuffer *fb;
243 int i;
244
245 conn_state = drm_atomic_get_new_connector_state(state, conn);
246 if (!conn_state->writeback_job)
247 return 0;
248
249 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
250
251 fb = conn_state->writeback_job->fb;
252 if (fb->width != crtc_state->mode.hdisplay ||
253 fb->height != crtc_state->mode.vdisplay) {
254 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
255 fb->width, fb->height);
256 return -EINVAL;
257 }
258
259 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
260 if (fb->format->format == drm_fmts[i])
261 break;
262 }
263
264 if (i == ARRAY_SIZE(drm_fmts))
265 return -EINVAL;
266
267 /* Pitch must be aligned on 16 bytes. */
268 if (fb->pitches[0] & GENMASK(3, 0))
269 return -EINVAL;
270
271 vc4_txp_armed(crtc_state);
272
273 return 0;
274}
275
276static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
277 struct drm_atomic_state *state)
278{
279 struct drm_device *drm = conn->dev;
280 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state,
281 conn);
282 struct vc4_txp *txp = connector_to_vc4_txp(conn);
283 struct drm_gem_dma_object *gem;
284 struct drm_display_mode *mode;
285 struct drm_framebuffer *fb;
286 u32 ctrl;
287 int idx;
288 int i;
289
290 if (WARN_ON(!conn_state->writeback_job))
291 return;
292
293 mode = &conn_state->crtc->state->adjusted_mode;
294 fb = conn_state->writeback_job->fb;
295
296 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
297 if (fb->format->format == drm_fmts[i])
298 break;
299 }
300
301 if (WARN_ON(i == ARRAY_SIZE(drm_fmts)))
302 return;
303
304 ctrl = TXP_GO | TXP_EI |
305 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) |
306 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);
307
308 if (fb->format->has_alpha)
309 ctrl |= TXP_ALPHA_ENABLE;
310 else
311 /*
312 * If TXP_ALPHA_ENABLE isn't set and TXP_ALPHA_INVERT is, the
313 * hardware will force the output padding to be 0xff.
314 */
315 ctrl |= TXP_ALPHA_INVERT;
316
317 if (!drm_dev_enter(drm, &idx))
318 return;
319
320 gem = drm_fb_dma_get_gem_obj(fb, 0);
321 TXP_WRITE(TXP_DST_PTR, gem->dma_addr + fb->offsets[0]);
322 TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
323 TXP_WRITE(TXP_DIM,
324 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) |
325 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT));
326
327 TXP_WRITE(TXP_DST_CTRL, ctrl);
328
329 drm_writeback_queue_job(&txp->connector, conn_state);
330
331 drm_dev_exit(idx);
332}
333
334static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
335 .get_modes = vc4_txp_connector_get_modes,
336 .mode_valid = vc4_txp_connector_mode_valid,
337 .atomic_check = vc4_txp_connector_atomic_check,
338 .atomic_commit = vc4_txp_connector_atomic_commit,
339};
340
341static enum drm_connector_status
342vc4_txp_connector_detect(struct drm_connector *connector, bool force)
343{
344 return connector_status_connected;
345}
346
347static const struct drm_connector_funcs vc4_txp_connector_funcs = {
348 .detect = vc4_txp_connector_detect,
349 .fill_modes = drm_helper_probe_single_connector_modes,
350 .destroy = drm_connector_cleanup,
351 .reset = drm_atomic_helper_connector_reset,
352 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
353 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
354};
355
356static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
357{
358 struct drm_device *drm = encoder->dev;
359 struct vc4_txp *txp = encoder_to_vc4_txp(encoder);
360 int idx;
361
362 if (!drm_dev_enter(drm, &idx))
363 return;
364
365 if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
366 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
367
368 TXP_WRITE(TXP_DST_CTRL, TXP_ABORT);
369
370 while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY &&
371 time_before(jiffies, timeout))
372 ;
373
374 WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY);
375 }
376
377 TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
378
379 drm_dev_exit(idx);
380}
381
382static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
383 .disable = vc4_txp_encoder_disable,
384};
385
386static int vc4_txp_enable_vblank(struct drm_crtc *crtc)
387{
388 return 0;
389}
390
391static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {}
392
393static const struct drm_crtc_funcs vc4_txp_crtc_funcs = {
394 .set_config = drm_atomic_helper_set_config,
395 .page_flip = vc4_page_flip,
396 .reset = vc4_crtc_reset,
397 .atomic_duplicate_state = vc4_crtc_duplicate_state,
398 .atomic_destroy_state = vc4_crtc_destroy_state,
399 .enable_vblank = vc4_txp_enable_vblank,
400 .disable_vblank = vc4_txp_disable_vblank,
401 .late_register = vc4_crtc_late_register,
402};
403
404static int vc4_txp_atomic_check(struct drm_crtc *crtc,
405 struct drm_atomic_state *state)
406{
407 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
408 crtc);
409 int ret;
410
411 ret = vc4_hvs_atomic_check(crtc, state);
412 if (ret)
413 return ret;
414
415 crtc_state->no_vblank = true;
416
417 return 0;
418}
419
420static void vc4_txp_atomic_enable(struct drm_crtc *crtc,
421 struct drm_atomic_state *state)
422{
423 drm_crtc_vblank_on(crtc);
424 vc4_hvs_atomic_enable(crtc, state);
425}
426
427static void vc4_txp_atomic_disable(struct drm_crtc *crtc,
428 struct drm_atomic_state *state)
429{
430 struct drm_device *dev = crtc->dev;
431
432 /* Disable vblank irq handling before crtc is disabled. */
433 drm_crtc_vblank_off(crtc);
434
435 vc4_hvs_atomic_disable(crtc, state);
436
437 /*
438 * Make sure we issue a vblank event after disabling the CRTC if
439 * someone was waiting it.
440 */
441 if (crtc->state->event) {
442 unsigned long flags;
443
444 spin_lock_irqsave(&dev->event_lock, flags);
445 drm_crtc_send_vblank_event(crtc, crtc->state->event);
446 crtc->state->event = NULL;
447 spin_unlock_irqrestore(&dev->event_lock, flags);
448 }
449}
450
451static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = {
452 .atomic_check = vc4_txp_atomic_check,
453 .atomic_begin = vc4_hvs_atomic_begin,
454 .atomic_flush = vc4_hvs_atomic_flush,
455 .atomic_enable = vc4_txp_atomic_enable,
456 .atomic_disable = vc4_txp_atomic_disable,
457};
458
459static irqreturn_t vc4_txp_interrupt(int irq, void *data)
460{
461 struct vc4_txp *txp = data;
462 struct vc4_crtc *vc4_crtc = &txp->base;
463
464 /*
465 * We don't need to protect the register access using
466 * drm_dev_enter() there because the interrupt handler lifetime
467 * is tied to the device itself, and not to the DRM device.
468 *
469 * So when the device will be gone, one of the first thing we
470 * will be doing will be to unregister the interrupt handler,
471 * and then unregister the DRM device. drm_dev_enter() would
472 * thus always succeed if we are here.
473 */
474 TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
475 vc4_crtc_handle_vblank(vc4_crtc);
476 drm_writeback_signal_completion(&txp->connector, 0);
477
478 return IRQ_HANDLED;
479}
480
481static const struct vc4_crtc_data vc4_txp_crtc_data = {
482 .debugfs_name = "txp_regs",
483 .hvs_available_channels = BIT(2),
484 .hvs_output = 2,
485};
486
487static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
488{
489 struct platform_device *pdev = to_platform_device(dev);
490 struct drm_device *drm = dev_get_drvdata(master);
491 struct vc4_crtc *vc4_crtc;
492 struct vc4_txp *txp;
493 struct drm_crtc *crtc;
494 struct drm_encoder *encoder;
495 int ret, irq;
496
497 irq = platform_get_irq(pdev, 0);
498 if (irq < 0)
499 return irq;
500
501 txp = drmm_kzalloc(drm, sizeof(*txp), GFP_KERNEL);
502 if (!txp)
503 return -ENOMEM;
504 vc4_crtc = &txp->base;
505 crtc = &vc4_crtc->base;
506
507 vc4_crtc->pdev = pdev;
508 vc4_crtc->data = &vc4_txp_crtc_data;
509 vc4_crtc->feeds_txp = true;
510
511 txp->pdev = pdev;
512
513 txp->regs = vc4_ioremap_regs(pdev, 0);
514 if (IS_ERR(txp->regs))
515 return PTR_ERR(txp->regs);
516 vc4_crtc->regset.base = txp->regs;
517 vc4_crtc->regset.regs = txp_regs;
518 vc4_crtc->regset.nregs = ARRAY_SIZE(txp_regs);
519
520 drm_connector_helper_add(&txp->connector.base,
521 &vc4_txp_connector_helper_funcs);
522 ret = drm_writeback_connector_init(drm, &txp->connector,
523 &vc4_txp_connector_funcs,
524 &vc4_txp_encoder_helper_funcs,
525 drm_fmts, ARRAY_SIZE(drm_fmts),
526 0);
527 if (ret)
528 return ret;
529
530 ret = vc4_crtc_init(drm, vc4_crtc,
531 &vc4_txp_crtc_funcs, &vc4_txp_crtc_helper_funcs);
532 if (ret)
533 return ret;
534
535 encoder = &txp->connector.encoder;
536 encoder->possible_crtcs = drm_crtc_mask(crtc);
537
538 ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
539 dev_name(dev), txp);
540 if (ret)
541 return ret;
542
543 dev_set_drvdata(dev, txp);
544
545 return 0;
546}
547
548static void vc4_txp_unbind(struct device *dev, struct device *master,
549 void *data)
550{
551 struct vc4_txp *txp = dev_get_drvdata(dev);
552
553 drm_connector_cleanup(&txp->connector.base);
554}
555
556static const struct component_ops vc4_txp_ops = {
557 .bind = vc4_txp_bind,
558 .unbind = vc4_txp_unbind,
559};
560
561static int vc4_txp_probe(struct platform_device *pdev)
562{
563 return component_add(&pdev->dev, &vc4_txp_ops);
564}
565
566static int vc4_txp_remove(struct platform_device *pdev)
567{
568 component_del(&pdev->dev, &vc4_txp_ops);
569 return 0;
570}
571
572static const struct of_device_id vc4_txp_dt_match[] = {
573 { .compatible = "brcm,bcm2835-txp" },
574 { /* sentinel */ },
575};
576
577struct platform_driver vc4_txp_driver = {
578 .probe = vc4_txp_probe,
579 .remove = vc4_txp_remove,
580 .driver = {
581 .name = "vc4_txp",
582 .of_match_table = vc4_txp_dt_match,
583 },
584};