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1/*
2 * Copyright © 2014-2015 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef VC4_REGS_H
10#define VC4_REGS_H
11
12#include <linux/bitops.h>
13
14#define VC4_MASK(high, low) ((u32)GENMASK(high, low))
15/* Using the GNU statement expression extension */
16#define VC4_SET_FIELD(value, field) \
17 ({ \
18 uint32_t fieldval = (value) << field##_SHIFT; \
19 WARN_ON((fieldval & ~field##_MASK) != 0); \
20 fieldval & field##_MASK; \
21 })
22
23#define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \
24 field##_SHIFT)
25
26#define V3D_IDENT0 0x00000
27# define V3D_EXPECTED_IDENT0 \
28 ((2 << 24) | \
29 ('V' << 0) | \
30 ('3' << 8) | \
31 ('D' << 16))
32
33#define V3D_IDENT1 0x00004
34/* Multiples of 1kb */
35# define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
36# define V3D_IDENT1_VPM_SIZE_SHIFT 28
37# define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
38# define V3D_IDENT1_NSEM_SHIFT 16
39# define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
40# define V3D_IDENT1_TUPS_SHIFT 12
41# define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
42# define V3D_IDENT1_QUPS_SHIFT 8
43# define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
44# define V3D_IDENT1_NSLC_SHIFT 4
45# define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
46# define V3D_IDENT1_REV_SHIFT 0
47
48#define V3D_IDENT2 0x00008
49#define V3D_SCRATCH 0x00010
50#define V3D_L2CACTL 0x00020
51# define V3D_L2CACTL_L2CCLR BIT(2)
52# define V3D_L2CACTL_L2CDIS BIT(1)
53# define V3D_L2CACTL_L2CENA BIT(0)
54
55#define V3D_SLCACTL 0x00024
56# define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
57# define V3D_SLCACTL_T1CC_SHIFT 24
58# define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
59# define V3D_SLCACTL_T0CC_SHIFT 16
60# define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
61# define V3D_SLCACTL_UCC_SHIFT 8
62# define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
63# define V3D_SLCACTL_ICC_SHIFT 0
64
65#define V3D_INTCTL 0x00030
66#define V3D_INTENA 0x00034
67#define V3D_INTDIS 0x00038
68# define V3D_INT_SPILLUSE BIT(3)
69# define V3D_INT_OUTOMEM BIT(2)
70# define V3D_INT_FLDONE BIT(1)
71# define V3D_INT_FRDONE BIT(0)
72
73#define V3D_CT0CS 0x00100
74#define V3D_CT1CS 0x00104
75#define V3D_CTNCS(n) (V3D_CT0CS + 4 * n)
76# define V3D_CTRSTA BIT(15)
77# define V3D_CTSEMA BIT(12)
78# define V3D_CTRTSD BIT(8)
79# define V3D_CTRUN BIT(5)
80# define V3D_CTSUBS BIT(4)
81# define V3D_CTERR BIT(3)
82# define V3D_CTMODE BIT(0)
83
84#define V3D_CT0EA 0x00108
85#define V3D_CT1EA 0x0010c
86#define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n))
87#define V3D_CT0CA 0x00110
88#define V3D_CT1CA 0x00114
89#define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n))
90#define V3D_CT00RA0 0x00118
91#define V3D_CT01RA0 0x0011c
92#define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n))
93#define V3D_CT0LC 0x00120
94#define V3D_CT1LC 0x00124
95#define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n))
96#define V3D_CT0PC 0x00128
97#define V3D_CT1PC 0x0012c
98#define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n))
99
100#define V3D_PCS 0x00130
101# define V3D_BMOOM BIT(8)
102# define V3D_RMBUSY BIT(3)
103# define V3D_RMACTIVE BIT(2)
104# define V3D_BMBUSY BIT(1)
105# define V3D_BMACTIVE BIT(0)
106
107#define V3D_BFC 0x00134
108#define V3D_RFC 0x00138
109#define V3D_BPCA 0x00300
110#define V3D_BPCS 0x00304
111#define V3D_BPOA 0x00308
112#define V3D_BPOS 0x0030c
113#define V3D_BXCF 0x00310
114#define V3D_SQRSV0 0x00410
115#define V3D_SQRSV1 0x00414
116#define V3D_SQCNTL 0x00418
117#define V3D_SRQPC 0x00430
118#define V3D_SRQUA 0x00434
119#define V3D_SRQUL 0x00438
120#define V3D_SRQCS 0x0043c
121#define V3D_VPACNTL 0x00500
122#define V3D_VPMBASE 0x00504
123#define V3D_PCTRC 0x00670
124#define V3D_PCTRE 0x00674
125#define V3D_PCTR0 0x00680
126#define V3D_PCTRS0 0x00684
127#define V3D_PCTR1 0x00688
128#define V3D_PCTRS1 0x0068c
129#define V3D_PCTR2 0x00690
130#define V3D_PCTRS2 0x00694
131#define V3D_PCTR3 0x00698
132#define V3D_PCTRS3 0x0069c
133#define V3D_PCTR4 0x006a0
134#define V3D_PCTRS4 0x006a4
135#define V3D_PCTR5 0x006a8
136#define V3D_PCTRS5 0x006ac
137#define V3D_PCTR6 0x006b0
138#define V3D_PCTRS6 0x006b4
139#define V3D_PCTR7 0x006b8
140#define V3D_PCTRS7 0x006bc
141#define V3D_PCTR8 0x006c0
142#define V3D_PCTRS8 0x006c4
143#define V3D_PCTR9 0x006c8
144#define V3D_PCTRS9 0x006cc
145#define V3D_PCTR10 0x006d0
146#define V3D_PCTRS10 0x006d4
147#define V3D_PCTR11 0x006d8
148#define V3D_PCTRS11 0x006dc
149#define V3D_PCTR12 0x006e0
150#define V3D_PCTRS12 0x006e4
151#define V3D_PCTR13 0x006e8
152#define V3D_PCTRS13 0x006ec
153#define V3D_PCTR14 0x006f0
154#define V3D_PCTRS14 0x006f4
155#define V3D_PCTR15 0x006f8
156#define V3D_PCTRS15 0x006fc
157#define V3D_DBGE 0x00f00
158#define V3D_FDBGO 0x00f04
159#define V3D_FDBGB 0x00f08
160#define V3D_FDBGR 0x00f0c
161#define V3D_FDBGS 0x00f10
162#define V3D_ERRSTAT 0x00f20
163
164#define PV_CONTROL 0x00
165# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
166# define PV_CONTROL_FORMAT_SHIFT 21
167# define PV_CONTROL_FORMAT_24 0
168# define PV_CONTROL_FORMAT_DSIV_16 1
169# define PV_CONTROL_FORMAT_DSIC_16 2
170# define PV_CONTROL_FORMAT_DSIV_18 3
171# define PV_CONTROL_FORMAT_DSIV_24 4
172
173# define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)
174# define PV_CONTROL_FIFO_LEVEL_SHIFT 15
175# define PV_CONTROL_CLR_AT_START BIT(14)
176# define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
177# define PV_CONTROL_WAIT_HSTART BIT(12)
178# define PV_CONTROL_CLK_SELECT_DSI_VEC 0
179# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
180# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
181# define PV_CONTROL_CLK_SELECT_SHIFT 2
182# define PV_CONTROL_FIFO_CLR BIT(1)
183# define PV_CONTROL_EN BIT(0)
184
185#define PV_V_CONTROL 0x04
186# define PV_VCONTROL_INTERLACE BIT(4)
187# define PV_VCONTROL_CONTINUOUS BIT(1)
188# define PV_VCONTROL_VIDEN BIT(0)
189
190#define PV_VSYNCD_EVEN 0x08
191
192#define PV_HORZA 0x0c
193# define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
194# define PV_HORZA_HBP_SHIFT 16
195# define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
196# define PV_HORZA_HSYNC_SHIFT 0
197
198#define PV_HORZB 0x10
199# define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
200# define PV_HORZB_HFP_SHIFT 16
201# define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
202# define PV_HORZB_HACTIVE_SHIFT 0
203
204#define PV_VERTA 0x14
205# define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
206# define PV_VERTA_VBP_SHIFT 16
207# define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
208# define PV_VERTA_VSYNC_SHIFT 0
209
210#define PV_VERTB 0x18
211# define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
212# define PV_VERTB_VFP_SHIFT 16
213# define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)
214# define PV_VERTB_VACTIVE_SHIFT 0
215
216#define PV_VERTA_EVEN 0x1c
217#define PV_VERTB_EVEN 0x20
218
219#define PV_INTEN 0x24
220#define PV_INTSTAT 0x28
221# define PV_INT_VID_IDLE BIT(9)
222# define PV_INT_VFP_END BIT(8)
223# define PV_INT_VFP_START BIT(7)
224# define PV_INT_VACT_START BIT(6)
225# define PV_INT_VBP_START BIT(5)
226# define PV_INT_VSYNC_START BIT(4)
227# define PV_INT_HFP_START BIT(3)
228# define PV_INT_HACT_START BIT(2)
229# define PV_INT_HBP_START BIT(1)
230# define PV_INT_HSYNC_START BIT(0)
231
232#define PV_STAT 0x2c
233
234#define PV_HACT_ACT 0x30
235
236#define SCALER_DISPCTRL 0x00000000
237/* Global register for clock gating the HVS */
238# define SCALER_DISPCTRL_ENABLE BIT(31)
239# define SCALER_DISPCTRL_DSP2EISLUR BIT(15)
240# define SCALER_DISPCTRL_DSP1EISLUR BIT(14)
241/* Enables Display 0 short line and underrun contribution to
242 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are
243 * always enabled.
244 */
245# define SCALER_DISPCTRL_DSP0EISLUR BIT(13)
246# define SCALER_DISPCTRL_DSP2EIEOLN BIT(12)
247# define SCALER_DISPCTRL_DSP2EIEOF BIT(11)
248# define SCALER_DISPCTRL_DSP1EIEOLN BIT(10)
249# define SCALER_DISPCTRL_DSP1EIEOF BIT(9)
250/* Enables Display 0 end-of-line-N contribution to
251 * SCALER_DISPSTAT_IRQDISP0
252 */
253# define SCALER_DISPCTRL_DSP0EIEOLN BIT(8)
254/* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
255# define SCALER_DISPCTRL_DSP0EIEOF BIT(7)
256
257# define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
258# define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
259# define SCALER_DISPCTRL_DMAEIRQ BIT(4)
260# define SCALER_DISPCTRL_DISP2EIRQ BIT(3)
261# define SCALER_DISPCTRL_DISP1EIRQ BIT(2)
262/* Enables interrupt generation on the enabled EOF/EOLN/EISLUR
263 * bits and short frames..
264 */
265# define SCALER_DISPCTRL_DISP0EIRQ BIT(1)
266/* Enables interrupt generation on scaler profiler interrupt. */
267# define SCALER_DISPCTRL_SCLEIRQ BIT(0)
268
269#define SCALER_DISPSTAT 0x00000004
270# define SCALER_DISPSTAT_COBLOW2 BIT(29)
271# define SCALER_DISPSTAT_EOLN2 BIT(28)
272# define SCALER_DISPSTAT_ESFRAME2 BIT(27)
273# define SCALER_DISPSTAT_ESLINE2 BIT(26)
274# define SCALER_DISPSTAT_EUFLOW2 BIT(25)
275# define SCALER_DISPSTAT_EOF2 BIT(24)
276
277# define SCALER_DISPSTAT_COBLOW1 BIT(21)
278# define SCALER_DISPSTAT_EOLN1 BIT(20)
279# define SCALER_DISPSTAT_ESFRAME1 BIT(19)
280# define SCALER_DISPSTAT_ESLINE1 BIT(18)
281# define SCALER_DISPSTAT_EUFLOW1 BIT(17)
282# define SCALER_DISPSTAT_EOF1 BIT(16)
283
284# define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)
285# define SCALER_DISPSTAT_RESP_SHIFT 14
286# define SCALER_DISPSTAT_RESP_OKAY 0
287# define SCALER_DISPSTAT_RESP_EXOKAY 1
288# define SCALER_DISPSTAT_RESP_SLVERR 2
289# define SCALER_DISPSTAT_RESP_DECERR 3
290
291# define SCALER_DISPSTAT_COBLOW0 BIT(13)
292/* Set when the DISPEOLN line is done compositing. */
293# define SCALER_DISPSTAT_EOLN0 BIT(12)
294/* Set when VSTART is seen but there are still pixels in the current
295 * output line.
296 */
297# define SCALER_DISPSTAT_ESFRAME0 BIT(11)
298/* Set when HSTART is seen but there are still pixels in the current
299 * output line.
300 */
301# define SCALER_DISPSTAT_ESLINE0 BIT(10)
302/* Set when the the downstream tries to read from the display FIFO
303 * while it's empty.
304 */
305# define SCALER_DISPSTAT_EUFLOW0 BIT(9)
306/* Set when the display mode changes from RUN to EOF */
307# define SCALER_DISPSTAT_EOF0 BIT(8)
308
309/* Set on AXI invalid DMA ID error. */
310# define SCALER_DISPSTAT_DMA_ERROR BIT(7)
311/* Set on AXI slave read decode error */
312# define SCALER_DISPSTAT_IRQSLVRD BIT(6)
313/* Set on AXI slave write decode error */
314# define SCALER_DISPSTAT_IRQSLVWR BIT(5)
315/* Set when SCALER_DISPSTAT_DMA_ERROR is set, or
316 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY.
317 */
318# define SCALER_DISPSTAT_IRQDMA BIT(4)
319# define SCALER_DISPSTAT_IRQDISP2 BIT(3)
320# define SCALER_DISPSTAT_IRQDISP1 BIT(2)
321/* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their
322 * corresponding interrupt bit is enabled in DISPCTRL.
323 */
324# define SCALER_DISPSTAT_IRQDISP0 BIT(1)
325/* On read, the profiler interrupt. On write, clear *all* interrupt bits. */
326# define SCALER_DISPSTAT_IRQSCL BIT(0)
327
328#define SCALER_DISPID 0x00000008
329#define SCALER_DISPECTRL 0x0000000c
330#define SCALER_DISPPROF 0x00000010
331#define SCALER_DISPDITHER 0x00000014
332#define SCALER_DISPEOLN 0x00000018
333#define SCALER_DISPLIST0 0x00000020
334#define SCALER_DISPLIST1 0x00000024
335#define SCALER_DISPLIST2 0x00000028
336#define SCALER_DISPLSTAT 0x0000002c
337#define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \
338 (x) * (SCALER_DISPLIST1 - \
339 SCALER_DISPLIST0))
340
341#define SCALER_DISPLACT0 0x00000030
342#define SCALER_DISPLACT1 0x00000034
343#define SCALER_DISPLACT2 0x00000038
344#define SCALER_DISPCTRL0 0x00000040
345# define SCALER_DISPCTRLX_ENABLE BIT(31)
346# define SCALER_DISPCTRLX_RESET BIT(30)
347# define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)
348# define SCALER_DISPCTRLX_WIDTH_SHIFT 12
349# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
350# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
351
352#define SCALER_DISPBKGND0 0x00000044
353# define SCALER_DISPBKGND_AUTOHS BIT(31)
354# define SCALER_DISPBKGND_INTERLACE BIT(30)
355# define SCALER_DISPBKGND_GAMMA BIT(29)
356# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
357# define SCALER_DISPBKGND_TESTMODE_SHIFT 25
358/* Enables filling the scaler line with the RGB value in the low 24
359 * bits before compositing. Costs cycles, so should be skipped if
360 * opaque display planes will cover everything.
361 */
362# define SCALER_DISPBKGND_FILL BIT(24)
363
364#define SCALER_DISPSTAT0 0x00000048
365#define SCALER_DISPBASE0 0x0000004c
366# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
367# define SCALER_DISPSTATX_MODE_SHIFT 30
368# define SCALER_DISPSTATX_MODE_DISABLED 0
369# define SCALER_DISPSTATX_MODE_INIT 1
370# define SCALER_DISPSTATX_MODE_RUN 2
371# define SCALER_DISPSTATX_MODE_EOF 3
372# define SCALER_DISPSTATX_FULL BIT(29)
373# define SCALER_DISPSTATX_EMPTY BIT(28)
374#define SCALER_DISPCTRL1 0x00000050
375#define SCALER_DISPBKGND1 0x00000054
376#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
377 (x) * (SCALER_DISPBKGND1 - \
378 SCALER_DISPBKGND0))
379#define SCALER_DISPSTAT1 0x00000058
380#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
381 (x) * (SCALER_DISPSTAT1 - \
382 SCALER_DISPSTAT0))
383#define SCALER_DISPBASE1 0x0000005c
384#define SCALER_DISPCTRL2 0x00000060
385#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
386 (x) * (SCALER_DISPCTRL1 - \
387 SCALER_DISPCTRL0))
388#define SCALER_DISPBKGND2 0x00000064
389#define SCALER_DISPSTAT2 0x00000068
390#define SCALER_DISPBASE2 0x0000006c
391#define SCALER_DISPALPHA2 0x00000070
392#define SCALER_GAMADDR 0x00000078
393#define SCALER_GAMDATA 0x000000e0
394#define SCALER_DLIST_START 0x00002000
395#define SCALER_DLIST_SIZE 0x00004000
396
397#define VC4_HDMI_CORE_REV 0x000
398
399#define VC4_HDMI_SW_RESET_CONTROL 0x004
400# define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
401# define VC4_HDMI_SW_RESET_HDMI BIT(0)
402
403#define VC4_HDMI_HOTPLUG_INT 0x008
404
405#define VC4_HDMI_HOTPLUG 0x00c
406# define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
407
408#define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0
409# define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
410
411#define VC4_HDMI_HORZA 0x0c4
412# define VC4_HDMI_HORZA_VPOS BIT(14)
413# define VC4_HDMI_HORZA_HPOS BIT(13)
414/* Horizontal active pixels (hdisplay). */
415# define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)
416# define VC4_HDMI_HORZA_HAP_SHIFT 0
417
418#define VC4_HDMI_HORZB 0x0c8
419/* Horizontal pack porch (htotal - hsync_end). */
420# define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)
421# define VC4_HDMI_HORZB_HBP_SHIFT 20
422/* Horizontal sync pulse (hsync_end - hsync_start). */
423# define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)
424# define VC4_HDMI_HORZB_HSP_SHIFT 10
425/* Horizontal front porch (hsync_start - hdisplay). */
426# define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)
427# define VC4_HDMI_HORZB_HFP_SHIFT 0
428
429#define VC4_HDMI_FIFO_CTL 0x05c
430# define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
431# define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
432# define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
433# define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
434# define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
435# define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
436# define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
437# define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
438# define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
439# define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
440# define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff
441
442#define VC4_HDMI_SCHEDULER_CONTROL 0x0c0
443# define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
444# define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
445# define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
446# define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
447# define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
448
449#define VC4_HDMI_VERTA0 0x0cc
450#define VC4_HDMI_VERTA1 0x0d4
451/* Vertical sync pulse (vsync_end - vsync_start). */
452# define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)
453# define VC4_HDMI_VERTA_VSP_SHIFT 20
454/* Vertical front porch (vsync_start - vdisplay). */
455# define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)
456# define VC4_HDMI_VERTA_VFP_SHIFT 13
457/* Vertical active lines (vdisplay). */
458# define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
459# define VC4_HDMI_VERTA_VAL_SHIFT 0
460
461#define VC4_HDMI_VERTB0 0x0d0
462#define VC4_HDMI_VERTB1 0x0d8
463/* Vertical sync pulse offset (for interlaced) */
464# define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)
465# define VC4_HDMI_VERTB_VSPO_SHIFT 9
466/* Vertical pack porch (vtotal - vsync_end). */
467# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
468# define VC4_HDMI_VERTB_VBP_SHIFT 0
469
470#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
471
472#define VC4_HD_M_CTL 0x00c
473# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
474# define VC4_HD_M_RAM_STANDBY (3 << 4)
475# define VC4_HD_M_SW_RST BIT(2)
476# define VC4_HD_M_ENABLE BIT(0)
477
478#define VC4_HD_MAI_CTL 0x014
479
480#define VC4_HD_VID_CTL 0x038
481# define VC4_HD_VID_CTL_ENABLE BIT(31)
482# define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
483# define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
484# define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
485# define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
486
487#define VC4_HD_CSC_CTL 0x040
488# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)
489# define VC4_HD_CSC_CTL_ORDER_SHIFT 5
490# define VC4_HD_CSC_CTL_ORDER_RGB 0
491# define VC4_HD_CSC_CTL_ORDER_BGR 1
492# define VC4_HD_CSC_CTL_ORDER_BRG 2
493# define VC4_HD_CSC_CTL_ORDER_GRB 3
494# define VC4_HD_CSC_CTL_ORDER_GBR 4
495# define VC4_HD_CSC_CTL_ORDER_RBG 5
496# define VC4_HD_CSC_CTL_PADMSB BIT(4)
497# define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)
498# define VC4_HD_CSC_CTL_MODE_SHIFT 2
499# define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
500# define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1
501# define VC4_HD_CSC_CTL_MODE_CUSTOM 2
502# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
503# define VC4_HD_CSC_CTL_ENABLE BIT(0)
504
505#define VC4_HD_FRAME_COUNT 0x068
506
507/* HVS display list information. */
508#define HVS_BOOTLOADER_DLIST_END 32
509
510enum hvs_pixel_format {
511 /* 8bpp */
512 HVS_PIXEL_FORMAT_RGB332 = 0,
513 /* 16bpp */
514 HVS_PIXEL_FORMAT_RGBA4444 = 1,
515 HVS_PIXEL_FORMAT_RGB555 = 2,
516 HVS_PIXEL_FORMAT_RGBA5551 = 3,
517 HVS_PIXEL_FORMAT_RGB565 = 4,
518 /* 24bpp */
519 HVS_PIXEL_FORMAT_RGB888 = 5,
520 HVS_PIXEL_FORMAT_RGBA6666 = 6,
521 /* 32bpp */
522 HVS_PIXEL_FORMAT_RGBA8888 = 7,
523
524 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
525 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
526 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
527 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
528};
529
530/* Note: the LSB is the rightmost character shown. Only valid for
531 * HVS_PIXEL_FORMAT_RGB8888, not RGB888.
532 */
533#define HVS_PIXEL_ORDER_RGBA 0
534#define HVS_PIXEL_ORDER_BGRA 1
535#define HVS_PIXEL_ORDER_ARGB 2
536#define HVS_PIXEL_ORDER_ABGR 3
537
538#define HVS_PIXEL_ORDER_XBRG 0
539#define HVS_PIXEL_ORDER_XRBG 1
540#define HVS_PIXEL_ORDER_XRGB 2
541#define HVS_PIXEL_ORDER_XBGR 3
542
543#define HVS_PIXEL_ORDER_XYCBCR 0
544#define HVS_PIXEL_ORDER_XYCRCB 1
545#define HVS_PIXEL_ORDER_YXCBCR 2
546#define HVS_PIXEL_ORDER_YXCRCB 3
547
548#define SCALER_CTL0_END BIT(31)
549#define SCALER_CTL0_VALID BIT(30)
550
551#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
552#define SCALER_CTL0_SIZE_SHIFT 24
553
554#define SCALER_CTL0_HFLIP BIT(16)
555#define SCALER_CTL0_VFLIP BIT(15)
556
557#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
558#define SCALER_CTL0_ORDER_SHIFT 13
559
560#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
561#define SCALER_CTL0_SCL1_SHIFT 8
562
563#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
564#define SCALER_CTL0_SCL0_SHIFT 5
565
566#define SCALER_CTL0_SCL_H_PPF_V_PPF 0
567#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
568#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
569#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
570#define SCALER_CTL0_SCL_H_PPF_V_NONE 4
571#define SCALER_CTL0_SCL_H_NONE_V_PPF 5
572#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
573#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
574
575/* Set to indicate no scaling. */
576#define SCALER_CTL0_UNITY BIT(4)
577
578#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
579#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
580
581#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
582#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
583
584#define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)
585#define SCALER_POS0_START_Y_SHIFT 12
586
587#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
588#define SCALER_POS0_START_X_SHIFT 0
589
590#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
591#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
592
593#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
594#define SCALER_POS1_SCL_WIDTH_SHIFT 0
595
596#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
597#define SCALER_POS2_ALPHA_MODE_SHIFT 30
598#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
599#define SCALER_POS2_ALPHA_MODE_FIXED 1
600#define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2
601#define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3
602
603#define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)
604#define SCALER_POS2_HEIGHT_SHIFT 16
605
606#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
607#define SCALER_POS2_WIDTH_SHIFT 0
608
609/* Color Space Conversion words. Some values are S2.8 signed
610 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
611 * 0x2: 2, 0x3: -1}
612 */
613/* bottom 8 bits of S2.8 contribution of Cr to Blue */
614#define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
615#define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
616/* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */
617#define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
618#define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
619/* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
620#define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
621#define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
622/* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
623#define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
624#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
625#define SCALER_CSC0_ITR_R_601_5 0x00f00000
626#define SCALER_CSC0_ITR_R_709_3 0x00f00000
627#define SCALER_CSC0_JPEG_JFIF 0x00000000
628
629/* S2.8 contribution of Cb to Green */
630#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
631#define SCALER_CSC1_COEF_CB_GRN_SHIFT 22
632/* S2.8 contribution of Cr to Green */
633#define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)
634#define SCALER_CSC1_COEF_CR_GRN_SHIFT 12
635/* S2.8 contribution of Y to all of RGB */
636#define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)
637#define SCALER_CSC1_COEF_YY_ALL_SHIFT 2
638/* top 2 bits of S2.8 contribution of Cr to Blue */
639#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
640#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
641#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
642#define SCALER_CSC1_ITR_R_709_3 0xf2b784a8
643#define SCALER_CSC1_JPEG_JFIF 0xea34a400
644
645/* S2.8 contribution of Cb to Red */
646#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
647#define SCALER_CSC2_COEF_CB_RED_SHIFT 20
648/* S2.8 contribution of Cr to Red */
649#define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)
650#define SCALER_CSC2_COEF_CR_RED_SHIFT 10
651/* S2.8 contribution of Cb to Blue */
652#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
653#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
654#define SCALER_CSC2_ITR_R_601_5 0x00066204
655#define SCALER_CSC2_ITR_R_709_3 0x00072a1c
656#define SCALER_CSC2_JPEG_JFIF 0x000599c5
657
658#define SCALER_TPZ0_VERT_RECALC BIT(31)
659#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
660#define SCALER_TPZ0_SCALE_SHIFT 8
661#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
662#define SCALER_TPZ0_IPHASE_SHIFT 0
663#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
664#define SCALER_TPZ1_RECIP_SHIFT 0
665
666/* Skips interpolating coefficients to 64 phases, so just 8 are used.
667 * Required for nearest neighbor.
668 */
669#define SCALER_PPF_NOINTERP BIT(31)
670/* Replaes the highest valued coefficient with one that makes all 4
671 * sum to unity.
672 */
673#define SCALER_PPF_AGC BIT(30)
674#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
675#define SCALER_PPF_SCALE_SHIFT 8
676#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
677#define SCALER_PPF_IPHASE_SHIFT 0
678
679#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
680#define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
681#define SCALER_PPF_KERNEL_UNCACHED BIT(31)
682
683#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
684#define SCALER_SRC_PITCH_SHIFT 0
685
686#endif /* VC4_REGS_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright © 2014-2015 Broadcom
4 */
5
6#ifndef VC4_REGS_H
7#define VC4_REGS_H
8
9#include <linux/bitfield.h>
10#include <linux/bitops.h>
11
12#define VC4_MASK(high, low) ((u32)GENMASK(high, low))
13/* Using the GNU statement expression extension */
14#define VC4_SET_FIELD(value, field) \
15 ({ \
16 WARN_ON(!FIELD_FIT(field##_MASK, value)); \
17 FIELD_PREP(field##_MASK, value); \
18 })
19
20#define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word)
21
22#define V3D_IDENT0 0x00000
23# define V3D_EXPECTED_IDENT0 \
24 ((2 << 24) | \
25 ('V' << 0) | \
26 ('3' << 8) | \
27 ('D' << 16))
28
29#define V3D_IDENT1 0x00004
30/* Multiples of 1kb */
31# define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)
32# define V3D_IDENT1_VPM_SIZE_SHIFT 28
33# define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
34# define V3D_IDENT1_NSEM_SHIFT 16
35# define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
36# define V3D_IDENT1_TUPS_SHIFT 12
37# define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
38# define V3D_IDENT1_QUPS_SHIFT 8
39# define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)
40# define V3D_IDENT1_NSLC_SHIFT 4
41# define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)
42# define V3D_IDENT1_REV_SHIFT 0
43
44#define V3D_IDENT2 0x00008
45#define V3D_SCRATCH 0x00010
46#define V3D_L2CACTL 0x00020
47# define V3D_L2CACTL_L2CCLR BIT(2)
48# define V3D_L2CACTL_L2CDIS BIT(1)
49# define V3D_L2CACTL_L2CENA BIT(0)
50
51#define V3D_SLCACTL 0x00024
52# define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)
53# define V3D_SLCACTL_T1CC_SHIFT 24
54# define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
55# define V3D_SLCACTL_T0CC_SHIFT 16
56# define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
57# define V3D_SLCACTL_UCC_SHIFT 8
58# define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)
59# define V3D_SLCACTL_ICC_SHIFT 0
60
61#define V3D_INTCTL 0x00030
62#define V3D_INTENA 0x00034
63#define V3D_INTDIS 0x00038
64# define V3D_INT_SPILLUSE BIT(3)
65# define V3D_INT_OUTOMEM BIT(2)
66# define V3D_INT_FLDONE BIT(1)
67# define V3D_INT_FRDONE BIT(0)
68
69#define V3D_CT0CS 0x00100
70#define V3D_CT1CS 0x00104
71#define V3D_CTNCS(n) (V3D_CT0CS + 4 * n)
72# define V3D_CTRSTA BIT(15)
73# define V3D_CTSEMA BIT(12)
74# define V3D_CTRTSD BIT(8)
75# define V3D_CTRUN BIT(5)
76# define V3D_CTSUBS BIT(4)
77# define V3D_CTERR BIT(3)
78# define V3D_CTMODE BIT(0)
79
80#define V3D_CT0EA 0x00108
81#define V3D_CT1EA 0x0010c
82#define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n))
83#define V3D_CT0CA 0x00110
84#define V3D_CT1CA 0x00114
85#define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n))
86#define V3D_CT00RA0 0x00118
87#define V3D_CT01RA0 0x0011c
88#define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n))
89#define V3D_CT0LC 0x00120
90#define V3D_CT1LC 0x00124
91#define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n))
92#define V3D_CT0PC 0x00128
93#define V3D_CT1PC 0x0012c
94#define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n))
95
96#define V3D_PCS 0x00130
97# define V3D_BMOOM BIT(8)
98# define V3D_RMBUSY BIT(3)
99# define V3D_RMACTIVE BIT(2)
100# define V3D_BMBUSY BIT(1)
101# define V3D_BMACTIVE BIT(0)
102
103#define V3D_BFC 0x00134
104#define V3D_RFC 0x00138
105#define V3D_BPCA 0x00300
106#define V3D_BPCS 0x00304
107#define V3D_BPOA 0x00308
108#define V3D_BPOS 0x0030c
109#define V3D_BXCF 0x00310
110#define V3D_SQRSV0 0x00410
111#define V3D_SQRSV1 0x00414
112#define V3D_SQCNTL 0x00418
113#define V3D_SRQPC 0x00430
114#define V3D_SRQUA 0x00434
115#define V3D_SRQUL 0x00438
116#define V3D_SRQCS 0x0043c
117#define V3D_VPACNTL 0x00500
118#define V3D_VPMBASE 0x00504
119#define V3D_PCTRC 0x00670
120#define V3D_PCTRE 0x00674
121# define V3D_PCTRE_EN BIT(31)
122#define V3D_PCTR(x) (0x00680 + ((x) * 8))
123#define V3D_PCTRS(x) (0x00684 + ((x) * 8))
124#define V3D_DBGE 0x00f00
125#define V3D_FDBGO 0x00f04
126#define V3D_FDBGB 0x00f08
127#define V3D_FDBGR 0x00f0c
128#define V3D_FDBGS 0x00f10
129#define V3D_ERRSTAT 0x00f20
130
131#define PV_CONTROL 0x00
132# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25)
133# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT 25
134# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
135# define PV_CONTROL_FORMAT_SHIFT 21
136# define PV_CONTROL_FORMAT_24 0
137# define PV_CONTROL_FORMAT_DSIV_16 1
138# define PV_CONTROL_FORMAT_DSIC_16 2
139# define PV_CONTROL_FORMAT_DSIV_18 3
140# define PV_CONTROL_FORMAT_DSIV_24 4
141
142# define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)
143# define PV_CONTROL_FIFO_LEVEL_SHIFT 15
144# define PV_CONTROL_CLR_AT_START BIT(14)
145# define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
146# define PV_CONTROL_WAIT_HSTART BIT(12)
147# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)
148# define PV_CONTROL_PIXEL_REP_SHIFT 4
149# define PV_CONTROL_CLK_SELECT_DSI 0
150# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1
151# define PV_CONTROL_CLK_SELECT_VEC 2
152# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)
153# define PV_CONTROL_CLK_SELECT_SHIFT 2
154# define PV_CONTROL_FIFO_CLR BIT(1)
155# define PV_CONTROL_EN BIT(0)
156
157#define PV_V_CONTROL 0x04
158# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
159# define PV_VCONTROL_ODD_DELAY_SHIFT 6
160# define PV_VCONTROL_ODD_FIRST BIT(5)
161# define PV_VCONTROL_INTERLACE BIT(4)
162# define PV_VCONTROL_DSI BIT(3)
163# define PV_VCONTROL_COMMAND BIT(2)
164# define PV_VCONTROL_CONTINUOUS BIT(1)
165# define PV_VCONTROL_VIDEN BIT(0)
166
167#define PV_VSYNCD_EVEN 0x08
168
169#define PV_HORZA 0x0c
170# define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
171# define PV_HORZA_HBP_SHIFT 16
172# define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)
173# define PV_HORZA_HSYNC_SHIFT 0
174
175#define PV_HORZB 0x10
176# define PV_HORZB_HFP_MASK VC4_MASK(31, 16)
177# define PV_HORZB_HFP_SHIFT 16
178# define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)
179# define PV_HORZB_HACTIVE_SHIFT 0
180
181#define PV_VERTA 0x14
182# define PV_VERTA_VBP_MASK VC4_MASK(31, 16)
183# define PV_VERTA_VBP_SHIFT 16
184# define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)
185# define PV_VERTA_VSYNC_SHIFT 0
186
187#define PV_VERTB 0x18
188# define PV_VERTB_VFP_MASK VC4_MASK(31, 16)
189# define PV_VERTB_VFP_SHIFT 16
190# define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)
191# define PV_VERTB_VACTIVE_SHIFT 0
192
193#define PV_VERTA_EVEN 0x1c
194#define PV_VERTB_EVEN 0x20
195
196#define PV_INTEN 0x24
197#define PV_INTSTAT 0x28
198# define PV_INT_VID_IDLE BIT(9)
199# define PV_INT_VFP_END BIT(8)
200# define PV_INT_VFP_START BIT(7)
201# define PV_INT_VACT_START BIT(6)
202# define PV_INT_VBP_START BIT(5)
203# define PV_INT_VSYNC_START BIT(4)
204# define PV_INT_HFP_START BIT(3)
205# define PV_INT_HACT_START BIT(2)
206# define PV_INT_HBP_START BIT(1)
207# define PV_INT_HSYNC_START BIT(0)
208
209#define PV_STAT 0x2c
210
211#define PV_HACT_ACT 0x30
212
213#define PV_MUX_CFG 0x34
214# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2)
215# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2
216# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8
217
218#define SCALER_CHANNELS_COUNT 3
219
220#define SCALER_DISPCTRL 0x00000000
221/* Global register for clock gating the HVS */
222# define SCALER_DISPCTRL_ENABLE BIT(31)
223# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)
224# define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18
225
226/* Enables Display 0 short line and underrun contribution to
227 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are
228 * always enabled.
229 */
230# define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
231/* Enables Display 0 end-of-line-N contribution to
232 * SCALER_DISPSTAT_IRQDISP0
233 */
234# define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
235/* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */
236# define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
237
238# define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
239# define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
240# define SCALER_DISPCTRL_DMAEIRQ BIT(4)
241/* Enables interrupt generation on the enabled EOF/EOLN/EISLUR
242 * bits and short frames..
243 */
244# define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
245/* Enables interrupt generation on scaler profiler interrupt. */
246# define SCALER_DISPCTRL_SCLEIRQ BIT(0)
247
248#define SCALER_DISPSTAT 0x00000004
249# define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)
250# define SCALER_DISPSTAT_RESP_SHIFT 14
251# define SCALER_DISPSTAT_RESP_OKAY 0
252# define SCALER_DISPSTAT_RESP_EXOKAY 1
253# define SCALER_DISPSTAT_RESP_SLVERR 2
254# define SCALER_DISPSTAT_RESP_DECERR 3
255
256# define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
257/* Set when the DISPEOLN line is done compositing. */
258# define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
259/* Set when VSTART is seen but there are still pixels in the current
260 * output line.
261 */
262# define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
263/* Set when HSTART is seen but there are still pixels in the current
264 * output line.
265 */
266# define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
267/* Set when the downstream tries to read from the display FIFO
268 * while it's empty.
269 */
270# define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
271/* Set when the display mode changes from RUN to EOF */
272# define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
273
274# define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \
275 8 + ((x) * 8))
276
277/* Set on AXI invalid DMA ID error. */
278# define SCALER_DISPSTAT_DMA_ERROR BIT(7)
279/* Set on AXI slave read decode error */
280# define SCALER_DISPSTAT_IRQSLVRD BIT(6)
281/* Set on AXI slave write decode error */
282# define SCALER_DISPSTAT_IRQSLVWR BIT(5)
283/* Set when SCALER_DISPSTAT_DMA_ERROR is set, or
284 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY.
285 */
286# define SCALER_DISPSTAT_IRQDMA BIT(4)
287/* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their
288 * corresponding interrupt bit is enabled in DISPCTRL.
289 */
290# define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
291/* On read, the profiler interrupt. On write, clear *all* interrupt bits. */
292# define SCALER_DISPSTAT_IRQSCL BIT(0)
293
294#define SCALER_DISPID 0x00000008
295#define SCALER_DISPECTRL 0x0000000c
296# define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31
297# define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)
298
299#define SCALER_DISPPROF 0x00000010
300
301#define SCALER_DISPDITHER 0x00000014
302# define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
303# define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
304
305#define SCALER_DISPEOLN 0x00000018
306# define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
307# define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
308
309#define SCALER_DISPLIST0 0x00000020
310#define SCALER_DISPLIST1 0x00000024
311#define SCALER_DISPLIST2 0x00000028
312#define SCALER_DISPLSTAT 0x0000002c
313#define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \
314 (x) * (SCALER_DISPLIST1 - \
315 SCALER_DISPLIST0))
316
317#define SCALER_DISPLACT0 0x00000030
318#define SCALER_DISPLACT1 0x00000034
319#define SCALER_DISPLACT2 0x00000038
320#define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \
321 (x) * (SCALER_DISPLACT1 - \
322 SCALER_DISPLACT0))
323
324#define SCALER_DISPCTRL0 0x00000040
325# define SCALER_DISPCTRLX_ENABLE BIT(31)
326# define SCALER_DISPCTRLX_RESET BIT(30)
327/* Generates a single frame when VSTART is seen and stops at the last
328 * pixel read from the FIFO.
329 */
330# define SCALER_DISPCTRLX_ONESHOT BIT(29)
331/* Processes a single context in the dlist and then task switch,
332 * instead of an entire line.
333 */
334# define SCALER_DISPCTRLX_ONECTX BIT(28)
335/* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
336# define SCALER_DISPCTRLX_FIFO32 BIT(27)
337/* Turns on output to the DISPSLAVE register instead of the normal
338 * FIFO.
339 */
340# define SCALER_DISPCTRLX_FIFOREG BIT(26)
341
342# define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)
343# define SCALER_DISPCTRLX_WIDTH_SHIFT 12
344# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
345# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
346
347# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
348# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
349/* Generates a single frame when VSTART is seen and stops at the last
350 * pixel read from the FIFO.
351 */
352# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
353/* Processes a single context in the dlist and then task switch,
354 * instead of an entire line.
355 */
356# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
357# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
358# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
359# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
360
361#define SCALER_DISPBKGND0 0x00000044
362# define SCALER_DISPBKGND_AUTOHS BIT(31)
363# define SCALER_DISPBKGND_INTERLACE BIT(30)
364# define SCALER_DISPBKGND_GAMMA BIT(29)
365# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
366# define SCALER_DISPBKGND_TESTMODE_SHIFT 25
367/* Enables filling the scaler line with the RGB value in the low 24
368 * bits before compositing. Costs cycles, so should be skipped if
369 * opaque display planes will cover everything.
370 */
371# define SCALER_DISPBKGND_FILL BIT(24)
372
373#define SCALER_DISPSTAT0 0x00000048
374# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
375# define SCALER_DISPSTATX_MODE_SHIFT 30
376# define SCALER_DISPSTATX_MODE_DISABLED 0
377# define SCALER_DISPSTATX_MODE_INIT 1
378# define SCALER_DISPSTATX_MODE_RUN 2
379# define SCALER_DISPSTATX_MODE_EOF 3
380# define SCALER_DISPSTATX_FULL BIT(29)
381# define SCALER_DISPSTATX_EMPTY BIT(28)
382# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)
383# define SCALER_DISPSTATX_LINE_SHIFT 0
384
385#define SCALER_DISPBASE0 0x0000004c
386/* Last pixel in the COB (display FIFO memory) allocated to this HVS
387 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the
388 * next COB base).
389 */
390# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)
391# define SCALER_DISPBASEX_TOP_SHIFT 16
392/* First pixel in the COB (display FIFO memory) allocated to this HVS
393 * channel. Must be 4-pixel aligned.
394 */
395# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)
396# define SCALER_DISPBASEX_BASE_SHIFT 0
397
398#define SCALER_DISPCTRL1 0x00000050
399#define SCALER_DISPBKGND1 0x00000054
400#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
401 (x) * (SCALER_DISPBKGND1 - \
402 SCALER_DISPBKGND0))
403#define SCALER_DISPSTAT1 0x00000058
404# define SCALER_DISPSTAT1_FRCNT0_MASK VC4_MASK(23, 18)
405# define SCALER_DISPSTAT1_FRCNT0_SHIFT 18
406# define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12)
407# define SCALER_DISPSTAT1_FRCNT1_SHIFT 12
408
409#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
410 (x) * (SCALER_DISPSTAT1 - \
411 SCALER_DISPSTAT0))
412
413#define SCALER_DISPBASE1 0x0000005c
414#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \
415 (x) * (SCALER_DISPBASE1 - \
416 SCALER_DISPBASE0))
417#define SCALER_DISPCTRL2 0x00000060
418#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \
419 (x) * (SCALER_DISPCTRL1 - \
420 SCALER_DISPCTRL0))
421#define SCALER_DISPBKGND2 0x00000064
422
423#define SCALER_DISPSTAT2 0x00000068
424# define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12)
425# define SCALER_DISPSTAT2_FRCNT2_SHIFT 12
426
427#define SCALER_DISPBASE2 0x0000006c
428#define SCALER_DISPALPHA2 0x00000070
429#define SCALER_GAMADDR 0x00000078
430# define SCALER_GAMADDR_AUTOINC BIT(31)
431/* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma
432 * enabled.
433 */
434# define SCALER_GAMADDR_SRAMENB BIT(30)
435
436#define SCALER_OLEDOFFS 0x00000080
437/* Clamps R to [16,235] and G/B to [16,240]. */
438# define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
439
440/* Chooses which display FIFO the matrix applies to. */
441# define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24)
442# define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24
443# define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0
444# define SCALER_OLEDOFFS_DISPFIFO_0 1
445# define SCALER_OLEDOFFS_DISPFIFO_1 2
446# define SCALER_OLEDOFFS_DISPFIFO_2 3
447
448/* Offsets are 8-bit 2s-complement. */
449# define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16)
450# define SCALER_OLEDOFFS_RED_SHIFT 16
451# define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)
452# define SCALER_OLEDOFFS_GREEN_SHIFT 8
453# define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0)
454# define SCALER_OLEDOFFS_BLUE_SHIFT 0
455
456/* The coefficients are S0.9 fractions. */
457#define SCALER_OLEDCOEF0 0x00000084
458# define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20)
459# define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20
460# define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10)
461# define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10
462# define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0)
463# define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0
464
465#define SCALER_OLEDCOEF1 0x00000088
466# define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20)
467# define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20
468# define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10)
469# define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10
470# define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0)
471# define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0
472
473#define SCALER_OLEDCOEF2 0x0000008c
474# define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20)
475# define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20
476# define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10)
477# define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10
478# define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0)
479# define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0
480
481/* Slave addresses for DMAing from HVS composition output to other
482 * devices. The top bits are valid only in !FIFO32 mode.
483 */
484#define SCALER_DISPSLAVE0 0x000000c0
485#define SCALER_DISPSLAVE1 0x000000c9
486#define SCALER_DISPSLAVE2 0x000000d0
487# define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
488# define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
489/* Set when the current line has been read and an HSTART is required. */
490# define SCALER_DISPSLAVE_EOL BIT(26)
491/* Set when the display FIFO is empty. */
492# define SCALER_DISPSLAVE_EMPTY BIT(25)
493/* Set when there is RGB data ready to read. */
494# define SCALER_DISPSLAVE_VALID BIT(24)
495# define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0)
496# define SCALER_DISPSLAVE_RGB_SHIFT 0
497
498#define SCALER_GAMDATA 0x000000e0
499#define SCALER_DLIST_START 0x00002000
500#define SCALER_DLIST_SIZE 0x00004000
501
502#define SCALER5_DLIST_START 0x00004000
503
504# define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
505# define VC4_HDMI_SW_RESET_HDMI BIT(0)
506
507# define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
508
509# define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
510# define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
511# define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)
512# define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0
513
514# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
515# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
516# define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
517# define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
518# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)
519# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10
520/* If set, then multichannel, otherwise 2 channel. */
521# define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
522/* If set, then AUDIO_LAYOUT overrides audio_cea_mask */
523# define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
524# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)
525# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0
526
527# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK VC4_MASK(23, 16)
528# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_SHIFT 16
529
530enum {
531 VC4_HDMI_MAI_FORMAT_PCM = 2,
532 VC4_HDMI_MAI_FORMAT_HBR = 200,
533};
534
535# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK VC4_MASK(15, 8)
536# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_SHIFT 8
537
538enum {
539 VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED = 0,
540 VC4_HDMI_MAI_SAMPLE_RATE_8000 = 1,
541 VC4_HDMI_MAI_SAMPLE_RATE_11025 = 2,
542 VC4_HDMI_MAI_SAMPLE_RATE_12000 = 3,
543 VC4_HDMI_MAI_SAMPLE_RATE_16000 = 4,
544 VC4_HDMI_MAI_SAMPLE_RATE_22050 = 5,
545 VC4_HDMI_MAI_SAMPLE_RATE_24000 = 6,
546 VC4_HDMI_MAI_SAMPLE_RATE_32000 = 7,
547 VC4_HDMI_MAI_SAMPLE_RATE_44100 = 8,
548 VC4_HDMI_MAI_SAMPLE_RATE_48000 = 9,
549 VC4_HDMI_MAI_SAMPLE_RATE_64000 = 10,
550 VC4_HDMI_MAI_SAMPLE_RATE_88200 = 11,
551 VC4_HDMI_MAI_SAMPLE_RATE_96000 = 12,
552 VC4_HDMI_MAI_SAMPLE_RATE_128000 = 13,
553 VC4_HDMI_MAI_SAMPLE_RATE_176400 = 14,
554 VC4_HDMI_MAI_SAMPLE_RATE_192000 = 15,
555};
556
557# define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
558
559/* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead
560 * of pixel clock.
561 */
562# define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
563/* When set, no CRP packets will be sent. */
564# define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
565/* If set, generates CTS values based on N, audio clock, and video
566 * clock. N must be divisible by 128.
567 */
568# define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
569# define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)
570# define VC4_HDMI_CRP_CFG_N_SHIFT 0
571
572# define VC4_HDMI_HORZA_VPOS BIT(14)
573# define VC4_HDMI_HORZA_HPOS BIT(13)
574/* Horizontal active pixels (hdisplay). */
575# define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)
576# define VC4_HDMI_HORZA_HAP_SHIFT 0
577
578/* Horizontal pack porch (htotal - hsync_end). */
579# define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)
580# define VC4_HDMI_HORZB_HBP_SHIFT 20
581/* Horizontal sync pulse (hsync_end - hsync_start). */
582# define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)
583# define VC4_HDMI_HORZB_HSP_SHIFT 10
584/* Horizontal front porch (hsync_start - hdisplay). */
585# define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)
586# define VC4_HDMI_HORZB_HFP_SHIFT 0
587
588# define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
589# define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
590# define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
591# define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
592# define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
593# define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
594# define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
595# define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
596# define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
597# define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
598# define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff
599
600# define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
601# define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
602# define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
603# define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
604# define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
605
606/* Vertical sync pulse (vsync_end - vsync_start). */
607# define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)
608# define VC4_HDMI_VERTA_VSP_SHIFT 20
609/* Vertical front porch (vsync_start - vdisplay). */
610# define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)
611# define VC4_HDMI_VERTA_VFP_SHIFT 13
612/* Vertical active lines (vdisplay). */
613# define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
614# define VC4_HDMI_VERTA_VAL_SHIFT 0
615
616/* Vertical sync pulse offset (for interlaced) */
617# define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)
618# define VC4_HDMI_VERTB_VSPO_SHIFT 9
619/* Vertical pack porch (vtotal - vsync_end). */
620# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
621# define VC4_HDMI_VERTB_VBP_SHIFT 0
622
623/* Set when the transmission has ended. */
624# define VC4_HDMI_CEC_TX_EOM BIT(31)
625/* If set, transmission was acked on the 1st or 2nd attempt (only one
626 * retry is attempted). If in continuous mode, this means TX needs to
627 * be filled if !TX_EOM.
628 */
629# define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
630# define VC4_HDMI_CEC_RX_EOM BIT(29)
631# define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
632/* Number of bytes received for the message. */
633# define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
634# define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24
635/* Sets continuous receive mode. Generates interrupt after each 8
636 * bytes to signal that RX_DATA should be consumed, and at RX_EOM.
637 *
638 * If disabled, maximum 16 bytes will be received (including header),
639 * and interrupt at RX_EOM. Later bytes will be acked but not put
640 * into the RX_DATA.
641 */
642# define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
643# define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
644/* Set this after a CEC interrupt. */
645# define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
646/* Starts a TX. Will wait for appropriate idel time before CEC
647 * activity. Must be cleared in between transmits.
648 */
649# define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
650# define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)
651# define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
652/* Device's CEC address */
653# define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)
654# define VC4_HDMI_CEC_ADDR_SHIFT 12
655/* Divides off of HSM clock to generate CEC bit clock. */
656/* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
657# define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
658# define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0
659
660/* Set these fields to how many bit clock cycles get to that many
661 * microseconds.
662 */
663# define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
664# define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
665# define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)
666# define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17
667# define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)
668# define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11
669# define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)
670# define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5
671# define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)
672# define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0
673
674# define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
675# define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
676# define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)
677# define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
678# define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
679# define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
680# define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)
681# define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0
682
683# define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
684# define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24
685# define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)
686# define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16
687# define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
688# define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
689# define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)
690# define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0
691
692# define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
693# define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
694# define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
695# define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
696# define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
697# define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)
698# define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16
699# define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
700# define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
701# define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)
702# define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0
703
704# define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
705
706# define VC4_HDMI_CPU_CEC BIT(6)
707# define VC4_HDMI_CPU_HOTPLUG BIT(0)
708
709/* Debug: Current receive value on the CEC pad. */
710# define VC4_HD_CECRXD BIT(9)
711/* Debug: Override CEC output to 0. */
712# define VC4_HD_CECOVR BIT(8)
713# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
714# define VC4_HD_M_RAM_STANDBY (3 << 4)
715# define VC4_HD_M_SW_RST BIT(2)
716# define VC4_HD_M_ENABLE BIT(0)
717
718/* Set when audio stream is received at a slower rate than the
719 * sampling period, so MAI fifo goes empty. Write 1 to clear.
720 */
721# define VC4_HD_MAI_CTL_DLATE BIT(15)
722# define VC4_HD_MAI_CTL_BUSY BIT(14)
723# define VC4_HD_MAI_CTL_CHALIGN BIT(13)
724# define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
725# define VC4_HD_MAI_CTL_FULL BIT(11)
726# define VC4_HD_MAI_CTL_EMPTY BIT(10)
727# define VC4_HD_MAI_CTL_FLUSH BIT(9)
728/* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
729 * through.
730 */
731# define VC4_HD_MAI_CTL_PAREN BIT(8)
732# define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4)
733# define VC4_HD_MAI_CTL_CHNUM_SHIFT 4
734# define VC4_HD_MAI_CTL_ENABLE BIT(3)
735/* Underflow error status bit, write 1 to clear. */
736# define VC4_HD_MAI_CTL_ERRORE BIT(2)
737/* Overflow error status bit, write 1 to clear. */
738# define VC4_HD_MAI_CTL_ERRORF BIT(1)
739/* Single-shot reset bit. Read value is undefined. */
740# define VC4_HD_MAI_CTL_RESET BIT(0)
741
742# define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)
743# define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24
744# define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)
745# define VC4_HD_MAI_THR_PANICLOW_SHIFT 16
746# define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
747# define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
748# define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)
749# define VC4_HD_MAI_THR_DREQLOW_SHIFT 0
750
751/* Divider from HDMI HSM clock to MAI serial clock. Sampling period
752 * converges to N / (M + 1) cycles.
753 */
754# define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
755# define VC4_HD_MAI_SMP_N_SHIFT 8
756# define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)
757# define VC4_HD_MAI_SMP_M_SHIFT 0
758
759# define VC4_HD_VID_CTL_ENABLE BIT(31)
760# define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
761# define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
762# define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
763# define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
764# define VC4_HD_VID_CTL_CLRSYNC BIT(24)
765# define VC4_HD_VID_CTL_CLRRGB BIT(23)
766# define VC4_HD_VID_CTL_BLANKPIX BIT(18)
767
768# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)
769# define VC4_HD_CSC_CTL_ORDER_SHIFT 5
770# define VC4_HD_CSC_CTL_ORDER_RGB 0
771# define VC4_HD_CSC_CTL_ORDER_BGR 1
772# define VC4_HD_CSC_CTL_ORDER_BRG 2
773# define VC4_HD_CSC_CTL_ORDER_GRB 3
774# define VC4_HD_CSC_CTL_ORDER_GBR 4
775# define VC4_HD_CSC_CTL_ORDER_RBG 5
776# define VC4_HD_CSC_CTL_PADMSB BIT(4)
777# define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)
778# define VC4_HD_CSC_CTL_MODE_SHIFT 2
779# define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0
780# define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1
781# define VC4_HD_CSC_CTL_MODE_CUSTOM 3
782# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
783# define VC4_HD_CSC_CTL_ENABLE BIT(0)
784
785# define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6)
786# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_MASK \
787 VC4_MASK(5, 4)
788# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD \
789 3
790# define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)
791# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)
792# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)
793
794# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_MASK \
795 VC4_MASK(7, 6)
796# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE \
797 2
798
799# define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
800
801# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_MASK \
802 VC4_MASK(3, 2)
803# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY \
804 2
805
806/* HVS display list information. */
807#define HVS_BOOTLOADER_DLIST_END 32
808
809enum hvs_pixel_format {
810 /* 8bpp */
811 HVS_PIXEL_FORMAT_RGB332 = 0,
812 /* 16bpp */
813 HVS_PIXEL_FORMAT_RGBA4444 = 1,
814 HVS_PIXEL_FORMAT_RGB555 = 2,
815 HVS_PIXEL_FORMAT_RGBA5551 = 3,
816 HVS_PIXEL_FORMAT_RGB565 = 4,
817 /* 24bpp */
818 HVS_PIXEL_FORMAT_RGB888 = 5,
819 HVS_PIXEL_FORMAT_RGBA6666 = 6,
820 /* 32bpp */
821 HVS_PIXEL_FORMAT_RGBA8888 = 7,
822
823 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
824 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,
825 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,
826 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,
827 HVS_PIXEL_FORMAT_H264 = 12,
828 HVS_PIXEL_FORMAT_PALETTE = 13,
829 HVS_PIXEL_FORMAT_YUV444_RGB = 14,
830 HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
831 HVS_PIXEL_FORMAT_RGBA1010102 = 16,
832 HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
833};
834
835/* Note: the LSB is the rightmost character shown. Only valid for
836 * HVS_PIXEL_FORMAT_RGB8888, not RGB888.
837 */
838#define HVS_PIXEL_ORDER_RGBA 0
839#define HVS_PIXEL_ORDER_BGRA 1
840#define HVS_PIXEL_ORDER_ARGB 2
841#define HVS_PIXEL_ORDER_ABGR 3
842
843#define HVS_PIXEL_ORDER_XBRG 0
844#define HVS_PIXEL_ORDER_XRBG 1
845#define HVS_PIXEL_ORDER_XRGB 2
846#define HVS_PIXEL_ORDER_XBGR 3
847
848#define HVS_PIXEL_ORDER_XYCBCR 0
849#define HVS_PIXEL_ORDER_XYCRCB 1
850#define HVS_PIXEL_ORDER_YXCBCR 2
851#define HVS_PIXEL_ORDER_YXCRCB 3
852
853#define SCALER_CTL0_END BIT(31)
854#define SCALER_CTL0_VALID BIT(30)
855
856#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)
857#define SCALER_CTL0_SIZE_SHIFT 24
858
859#define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)
860#define SCALER_CTL0_TILING_SHIFT 20
861#define SCALER_CTL0_TILING_LINEAR 0
862#define SCALER_CTL0_TILING_64B 1
863#define SCALER_CTL0_TILING_128B 2
864#define SCALER_CTL0_TILING_256B_OR_T 3
865
866#define SCALER_CTL0_ALPHA_MASK BIT(19)
867#define SCALER_CTL0_HFLIP BIT(16)
868#define SCALER_CTL0_VFLIP BIT(15)
869
870#define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17)
871#define SCALER_CTL0_KEY_MODE_SHIFT 17
872#define SCALER_CTL0_KEY_DISABLED 0
873#define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1
874#define SCALER_CTL0_KEY_MATCH 2 /* turn transparent */
875#define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */
876
877#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)
878#define SCALER_CTL0_ORDER_SHIFT 13
879
880#define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11)
881#define SCALER_CTL0_RGBA_EXPAND_SHIFT 11
882#define SCALER_CTL0_RGBA_EXPAND_ZERO 0
883#define SCALER_CTL0_RGBA_EXPAND_LSB 1
884#define SCALER_CTL0_RGBA_EXPAND_MSB 2
885#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
886
887#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
888
889#define SCALER5_CTL0_RGB_EXPAND BIT(11)
890
891#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
892#define SCALER_CTL0_SCL1_SHIFT 8
893
894#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)
895#define SCALER_CTL0_SCL0_SHIFT 5
896
897#define SCALER_CTL0_SCL_H_PPF_V_PPF 0
898#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1
899#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2
900#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3
901#define SCALER_CTL0_SCL_H_PPF_V_NONE 4
902#define SCALER_CTL0_SCL_H_NONE_V_PPF 5
903#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6
904#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7
905
906/* Set to indicate no scaling. */
907#define SCALER_CTL0_UNITY BIT(4)
908#define SCALER5_CTL0_UNITY BIT(15)
909
910#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
911#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
912
913#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
914
915#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
916#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
917
918#define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)
919#define SCALER_POS0_START_Y_SHIFT 12
920
921#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
922#define SCALER_POS0_START_X_SHIFT 0
923
924#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
925#define SCALER5_POS0_START_Y_SHIFT 16
926
927#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
928#define SCALER5_POS0_START_X_SHIFT 0
929
930#define SCALER5_POS0_VFLIP BIT(31)
931#define SCALER5_POS0_HFLIP BIT(15)
932
933#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
934#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
935#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
936#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
937#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
938#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
939
940#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
941
942#define SCALER5_CTL2_ALPHA_MIX BIT(28)
943
944#define SCALER5_CTL2_ALPHA_LOC BIT(25)
945
946#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
947#define SCALER5_CTL2_MAP_SEL_SHIFT 17
948
949#define SCALER5_CTL2_GAMMA BIT(16)
950
951#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
952#define SCALER5_CTL2_ALPHA_SHIFT 4
953
954#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
955#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
956
957#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
958#define SCALER_POS1_SCL_WIDTH_SHIFT 0
959
960#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
961#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
962
963#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
964#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
965
966#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
967#define SCALER_POS2_ALPHA_MODE_SHIFT 30
968#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
969#define SCALER_POS2_ALPHA_MODE_FIXED 1
970#define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2
971#define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3
972#define SCALER_POS2_ALPHA_PREMULT BIT(29)
973#define SCALER_POS2_ALPHA_MIX BIT(28)
974
975#define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)
976#define SCALER_POS2_HEIGHT_SHIFT 16
977
978#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
979#define SCALER_POS2_WIDTH_SHIFT 0
980
981#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
982#define SCALER5_POS2_HEIGHT_SHIFT 16
983
984#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
985#define SCALER5_POS2_WIDTH_SHIFT 0
986
987/* Color Space Conversion words. Some values are S2.8 signed
988 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
989 * 0x2: 2, 0x3: -1}
990 */
991/* bottom 8 bits of S2.8 contribution of Cr to Blue */
992#define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)
993#define SCALER_CSC0_COEF_CR_BLU_SHIFT 24
994/* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */
995#define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)
996#define SCALER_CSC0_COEF_YY_OFS_SHIFT 16
997/* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */
998#define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
999#define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
1000/* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */
1001#define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)
1002#define SCALER_CSC0_COEF_CR_OFS_SHIFT 0
1003#define SCALER_CSC0_ITR_R_601_5 0x00f00000
1004#define SCALER_CSC0_ITR_R_709_3 0x00f00000
1005#define SCALER_CSC0_ITR_R_2020 0x00f00000
1006#define SCALER_CSC0_JPEG_JFIF 0x00000000
1007#define SCALER_CSC0_ITR_R_709_3_FR 0x00000000
1008#define SCALER_CSC0_ITR_R_2020_FR 0x00000000
1009
1010/* S2.8 contribution of Cb to Green */
1011#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)
1012#define SCALER_CSC1_COEF_CB_GRN_SHIFT 22
1013/* S2.8 contribution of Cr to Green */
1014#define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)
1015#define SCALER_CSC1_COEF_CR_GRN_SHIFT 12
1016/* S2.8 contribution of Y to all of RGB */
1017#define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)
1018#define SCALER_CSC1_COEF_YY_ALL_SHIFT 2
1019/* top 2 bits of S2.8 contribution of Cr to Blue */
1020#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)
1021#define SCALER_CSC1_COEF_CR_BLU_SHIFT 0
1022#define SCALER_CSC1_ITR_R_601_5 0xe73304a8
1023#define SCALER_CSC1_ITR_R_709_3 0xf27784a8
1024#define SCALER_CSC1_ITR_R_2020 0xf43594a8
1025#define SCALER_CSC1_JPEG_JFIF 0xea349400
1026#define SCALER_CSC1_ITR_R_709_3_FR 0xf4388400
1027#define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d400
1028
1029/* S2.8 contribution of Cb to Red */
1030#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)
1031#define SCALER_CSC2_COEF_CB_RED_SHIFT 20
1032/* S2.8 contribution of Cr to Red */
1033#define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)
1034#define SCALER_CSC2_COEF_CR_RED_SHIFT 10
1035/* S2.8 contribution of Cb to Blue */
1036#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)
1037#define SCALER_CSC2_COEF_CB_BLU_SHIFT 10
1038#define SCALER_CSC2_ITR_R_601_5 0x00066604
1039#define SCALER_CSC2_ITR_R_709_3 0x00072e1d
1040#define SCALER_CSC2_ITR_R_2020 0x0006b624
1041#define SCALER_CSC2_JPEG_JFIF 0x00059dc6
1042#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb
1043#define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e2
1044
1045#define SCALER_TPZ0_VERT_RECALC BIT(31)
1046#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
1047#define SCALER_TPZ0_SCALE_SHIFT 8
1048#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)
1049#define SCALER_TPZ0_IPHASE_SHIFT 0
1050#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)
1051#define SCALER_TPZ1_RECIP_SHIFT 0
1052
1053/* Skips interpolating coefficients to 64 phases, so just 8 are used.
1054 * Required for nearest neighbor.
1055 */
1056#define SCALER_PPF_NOINTERP BIT(31)
1057/* Replaes the highest valued coefficient with one that makes all 4
1058 * sum to unity.
1059 */
1060#define SCALER_PPF_AGC BIT(30)
1061#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1062#define SCALER_PPF_SCALE_SHIFT 8
1063#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)
1064#define SCALER_PPF_IPHASE_SHIFT 0
1065
1066#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)
1067#define SCALER_PPF_KERNEL_OFFSET_SHIFT 0
1068#define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1069
1070/* PITCH0/1/2 fields for raster. */
1071#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)
1072#define SCALER_SRC_PITCH_SHIFT 0
1073
1074/* PITCH0/1/2 fields for tiled (SAND). */
1075#define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)
1076#define SCALER_TILE_SKIP_0_SHIFT 16
1077#define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)
1078#define SCALER_TILE_HEIGHT_SHIFT 0
1079
1080/* Common PITCH0 fields */
1081#define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)
1082#define SCALER_PITCH0_SINK_PIX_SHIFT 26
1083
1084/* PITCH0 fields for T-tiled. */
1085#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
1086#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
1087#define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1088#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
1089/* Y offset within a tile. */
1090#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
1091#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
1092#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
1093#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
1094
1095#endif /* VC4_REGS_H */