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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4 * Zheng Yang <zhengyang@rock-chips.com>
5 */
6
7#include <drm/drm_edid.h>
8#include <drm/drm_of.h>
9#include <drm/drm_probe_helper.h>
10#include <drm/drm_simple_kms_helper.h>
11
12#include <linux/clk.h>
13#include <linux/mfd/syscon.h>
14#include <linux/platform_device.h>
15#include <linux/regmap.h>
16
17#include "rk3066_hdmi.h"
18
19#include "rockchip_drm_drv.h"
20#include "rockchip_drm_vop.h"
21
22#define DEFAULT_PLLA_RATE 30000000
23
24struct hdmi_data_info {
25 int vic; /* The CEA Video ID (VIC) of the current drm display mode. */
26 unsigned int enc_out_format;
27 unsigned int colorimetry;
28};
29
30struct rk3066_hdmi_i2c {
31 struct i2c_adapter adap;
32
33 u8 ddc_addr;
34 u8 segment_addr;
35 u8 stat;
36
37 struct mutex i2c_lock; /* For i2c operation. */
38 struct completion cmpltn;
39};
40
41struct rk3066_hdmi {
42 struct device *dev;
43 struct drm_device *drm_dev;
44 struct regmap *grf_regmap;
45 int irq;
46 struct clk *hclk;
47 void __iomem *regs;
48
49 struct drm_connector connector;
50 struct rockchip_encoder encoder;
51
52 struct rk3066_hdmi_i2c *i2c;
53 struct i2c_adapter *ddc;
54
55 unsigned int tmdsclk;
56
57 struct hdmi_data_info hdmi_data;
58 struct drm_display_mode previous_mode;
59};
60
61static struct rk3066_hdmi *encoder_to_rk3066_hdmi(struct drm_encoder *encoder)
62{
63 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
64
65 return container_of(rkencoder, struct rk3066_hdmi, encoder);
66}
67
68static struct rk3066_hdmi *connector_to_rk3066_hdmi(struct drm_connector *connector)
69{
70 return container_of(connector, struct rk3066_hdmi, connector);
71}
72
73static inline u8 hdmi_readb(struct rk3066_hdmi *hdmi, u16 offset)
74{
75 return readl_relaxed(hdmi->regs + offset);
76}
77
78static inline void hdmi_writeb(struct rk3066_hdmi *hdmi, u16 offset, u32 val)
79{
80 writel_relaxed(val, hdmi->regs + offset);
81}
82
83static inline void hdmi_modb(struct rk3066_hdmi *hdmi, u16 offset,
84 u32 msk, u32 val)
85{
86 u8 temp = hdmi_readb(hdmi, offset) & ~msk;
87
88 temp |= val & msk;
89 hdmi_writeb(hdmi, offset, temp);
90}
91
92static void rk3066_hdmi_i2c_init(struct rk3066_hdmi *hdmi)
93{
94 int ddc_bus_freq;
95
96 ddc_bus_freq = (hdmi->tmdsclk >> 2) / HDMI_SCL_RATE;
97
98 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF);
99 hdmi_writeb(hdmi, HDMI_DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF);
100
101 /* Clear the EDID interrupt flag and mute the interrupt. */
102 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
103 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, HDMI_INTR_EDID_MASK);
104}
105
106static inline u8 rk3066_hdmi_get_power_mode(struct rk3066_hdmi *hdmi)
107{
108 return hdmi_readb(hdmi, HDMI_SYS_CTRL) & HDMI_SYS_POWER_MODE_MASK;
109}
110
111static void rk3066_hdmi_set_power_mode(struct rk3066_hdmi *hdmi, int mode)
112{
113 u8 current_mode, next_mode;
114 u8 i = 0;
115
116 current_mode = rk3066_hdmi_get_power_mode(hdmi);
117
118 DRM_DEV_DEBUG(hdmi->dev, "mode :%d\n", mode);
119 DRM_DEV_DEBUG(hdmi->dev, "current_mode :%d\n", current_mode);
120
121 if (current_mode == mode)
122 return;
123
124 do {
125 if (current_mode > mode) {
126 next_mode = current_mode / 2;
127 } else {
128 if (current_mode < HDMI_SYS_POWER_MODE_A)
129 next_mode = HDMI_SYS_POWER_MODE_A;
130 else
131 next_mode = current_mode * 2;
132 }
133
134 DRM_DEV_DEBUG(hdmi->dev, "%d: next_mode :%d\n", i, next_mode);
135
136 if (next_mode != HDMI_SYS_POWER_MODE_D) {
137 hdmi_modb(hdmi, HDMI_SYS_CTRL,
138 HDMI_SYS_POWER_MODE_MASK, next_mode);
139 } else {
140 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
141 HDMI_SYS_POWER_MODE_D |
142 HDMI_SYS_PLL_RESET_MASK);
143 usleep_range(90, 100);
144 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
145 HDMI_SYS_POWER_MODE_D |
146 HDMI_SYS_PLLB_RESET);
147 usleep_range(90, 100);
148 hdmi_writeb(hdmi, HDMI_SYS_CTRL,
149 HDMI_SYS_POWER_MODE_D);
150 }
151 current_mode = next_mode;
152 i = i + 1;
153 } while ((next_mode != mode) && (i < 5));
154
155 /*
156 * When the IP controller isn't configured with accurate video timing,
157 * DDC_CLK should be equal to the PLLA frequency, which is 30MHz,
158 * so we need to init the TMDS rate to the PCLK rate and reconfigure
159 * the DDC clock.
160 */
161 if (mode < HDMI_SYS_POWER_MODE_D)
162 hdmi->tmdsclk = DEFAULT_PLLA_RATE;
163}
164
165static int
166rk3066_hdmi_upload_frame(struct rk3066_hdmi *hdmi, int setup_rc,
167 union hdmi_infoframe *frame, u32 frame_index,
168 u32 mask, u32 disable, u32 enable)
169{
170 if (mask)
171 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, disable);
172
173 hdmi_writeb(hdmi, HDMI_CP_BUF_INDEX, frame_index);
174
175 if (setup_rc >= 0) {
176 u8 packed_frame[HDMI_MAXIMUM_INFO_FRAME_SIZE];
177 ssize_t rc, i;
178
179 rc = hdmi_infoframe_pack(frame, packed_frame,
180 sizeof(packed_frame));
181 if (rc < 0)
182 return rc;
183
184 for (i = 0; i < rc; i++)
185 hdmi_writeb(hdmi, HDMI_CP_BUF_ACC_HB0 + i * 4,
186 packed_frame[i]);
187
188 if (mask)
189 hdmi_modb(hdmi, HDMI_CP_AUTO_SEND_CTRL, mask, enable);
190 }
191
192 return setup_rc;
193}
194
195static int rk3066_hdmi_config_avi(struct rk3066_hdmi *hdmi,
196 struct drm_display_mode *mode)
197{
198 union hdmi_infoframe frame;
199 int rc;
200
201 rc = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
202 &hdmi->connector, mode);
203
204 if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV444)
205 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
206 else if (hdmi->hdmi_data.enc_out_format == HDMI_COLORSPACE_YUV422)
207 frame.avi.colorspace = HDMI_COLORSPACE_YUV422;
208 else
209 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
210
211 frame.avi.colorimetry = hdmi->hdmi_data.colorimetry;
212 frame.avi.scan_mode = HDMI_SCAN_MODE_NONE;
213
214 return rk3066_hdmi_upload_frame(hdmi, rc, &frame,
215 HDMI_INFOFRAME_AVI, 0, 0, 0);
216}
217
218static int rk3066_hdmi_config_video_timing(struct rk3066_hdmi *hdmi,
219 struct drm_display_mode *mode)
220{
221 int value, vsync_offset;
222
223 /* Set the details for the external polarity and interlace mode. */
224 value = HDMI_EXT_VIDEO_SET_EN;
225 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
226 HDMI_VIDEO_HSYNC_ACTIVE_HIGH : HDMI_VIDEO_HSYNC_ACTIVE_LOW;
227 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
228 HDMI_VIDEO_VSYNC_ACTIVE_HIGH : HDMI_VIDEO_VSYNC_ACTIVE_LOW;
229 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
230 HDMI_VIDEO_MODE_INTERLACE : HDMI_VIDEO_MODE_PROGRESSIVE;
231
232 if (hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3)
233 vsync_offset = 6;
234 else
235 vsync_offset = 0;
236
237 value |= vsync_offset << HDMI_VIDEO_VSYNC_OFFSET_SHIFT;
238 hdmi_writeb(hdmi, HDMI_EXT_VIDEO_PARA, value);
239
240 /* Set the details for the external video timing. */
241 value = mode->htotal;
242 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_L, value & 0xFF);
243 hdmi_writeb(hdmi, HDMI_EXT_HTOTAL_H, (value >> 8) & 0xFF);
244
245 value = mode->htotal - mode->hdisplay;
246 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_L, value & 0xFF);
247 hdmi_writeb(hdmi, HDMI_EXT_HBLANK_H, (value >> 8) & 0xFF);
248
249 value = mode->htotal - mode->hsync_start;
250 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_L, value & 0xFF);
251 hdmi_writeb(hdmi, HDMI_EXT_HDELAY_H, (value >> 8) & 0xFF);
252
253 value = mode->hsync_end - mode->hsync_start;
254 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_L, value & 0xFF);
255 hdmi_writeb(hdmi, HDMI_EXT_HDURATION_H, (value >> 8) & 0xFF);
256
257 value = mode->vtotal;
258 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_L, value & 0xFF);
259 hdmi_writeb(hdmi, HDMI_EXT_VTOTAL_H, (value >> 8) & 0xFF);
260
261 value = mode->vtotal - mode->vdisplay;
262 hdmi_writeb(hdmi, HDMI_EXT_VBLANK_L, value & 0xFF);
263
264 value = mode->vtotal - mode->vsync_start + vsync_offset;
265 hdmi_writeb(hdmi, HDMI_EXT_VDELAY, value & 0xFF);
266
267 value = mode->vsync_end - mode->vsync_start;
268 hdmi_writeb(hdmi, HDMI_EXT_VDURATION, value & 0xFF);
269
270 return 0;
271}
272
273static void
274rk3066_hdmi_phy_write(struct rk3066_hdmi *hdmi, u16 offset, u8 value)
275{
276 hdmi_writeb(hdmi, offset, value);
277 hdmi_modb(hdmi, HDMI_SYS_CTRL,
278 HDMI_SYS_PLL_RESET_MASK, HDMI_SYS_PLL_RESET);
279 usleep_range(90, 100);
280 hdmi_modb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_PLL_RESET_MASK, 0);
281 usleep_range(900, 1000);
282}
283
284static void rk3066_hdmi_config_phy(struct rk3066_hdmi *hdmi)
285{
286 /* TMDS uses the same frequency as dclk. */
287 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x22);
288
289 /*
290 * The semi-public documentation does not describe the hdmi registers
291 * used by the function rk3066_hdmi_phy_write(), so we keep using
292 * these magic values for now.
293 */
294 if (hdmi->tmdsclk > 100000000) {
295 rk3066_hdmi_phy_write(hdmi, 0x158, 0x0E);
296 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
297 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
298 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
299 rk3066_hdmi_phy_write(hdmi, 0x168, 0xDA);
300 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA1);
301 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
302 rk3066_hdmi_phy_write(hdmi, 0x174, 0x22);
303 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
304 } else if (hdmi->tmdsclk > 50000000) {
305 rk3066_hdmi_phy_write(hdmi, 0x158, 0x06);
306 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
307 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
308 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
309 rk3066_hdmi_phy_write(hdmi, 0x168, 0xCA);
310 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA3);
311 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
312 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
313 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
314 } else {
315 rk3066_hdmi_phy_write(hdmi, 0x158, 0x02);
316 rk3066_hdmi_phy_write(hdmi, 0x15c, 0x00);
317 rk3066_hdmi_phy_write(hdmi, 0x160, 0x60);
318 rk3066_hdmi_phy_write(hdmi, 0x164, 0x00);
319 rk3066_hdmi_phy_write(hdmi, 0x168, 0xC2);
320 rk3066_hdmi_phy_write(hdmi, 0x16c, 0xA2);
321 rk3066_hdmi_phy_write(hdmi, 0x170, 0x0e);
322 rk3066_hdmi_phy_write(hdmi, 0x174, 0x20);
323 rk3066_hdmi_phy_write(hdmi, 0x178, 0x00);
324 }
325}
326
327static int rk3066_hdmi_setup(struct rk3066_hdmi *hdmi,
328 struct drm_display_mode *mode)
329{
330 struct drm_display_info *display = &hdmi->connector.display_info;
331
332 hdmi->hdmi_data.vic = drm_match_cea_mode(mode);
333 hdmi->hdmi_data.enc_out_format = HDMI_COLORSPACE_RGB;
334
335 if (hdmi->hdmi_data.vic == 6 || hdmi->hdmi_data.vic == 7 ||
336 hdmi->hdmi_data.vic == 21 || hdmi->hdmi_data.vic == 22 ||
337 hdmi->hdmi_data.vic == 2 || hdmi->hdmi_data.vic == 3 ||
338 hdmi->hdmi_data.vic == 17 || hdmi->hdmi_data.vic == 18)
339 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
340 else
341 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
342
343 hdmi->tmdsclk = mode->clock * 1000;
344
345 /* Mute video and audio output. */
346 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2, HDMI_VIDEO_AUDIO_DISABLE_MASK,
347 HDMI_AUDIO_DISABLE | HDMI_VIDEO_DISABLE);
348
349 /* Set power state to mode B. */
350 if (rk3066_hdmi_get_power_mode(hdmi) != HDMI_SYS_POWER_MODE_B)
351 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
352
353 /* Input video mode is RGB 24 bit. Use external data enable signal. */
354 hdmi_modb(hdmi, HDMI_AV_CTRL1,
355 HDMI_VIDEO_DE_MASK, HDMI_VIDEO_EXTERNAL_DE);
356 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL1,
357 HDMI_VIDEO_OUTPUT_RGB444 |
358 HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT |
359 HDMI_VIDEO_INPUT_COLOR_RGB);
360 hdmi_writeb(hdmi, HDMI_DEEP_COLOR_MODE, 0x20);
361
362 rk3066_hdmi_config_video_timing(hdmi, mode);
363
364 if (display->is_hdmi) {
365 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK,
366 HDMI_VIDEO_MODE_HDMI);
367 rk3066_hdmi_config_avi(hdmi, mode);
368 } else {
369 hdmi_modb(hdmi, HDMI_HDCP_CTRL, HDMI_VIDEO_MODE_MASK, 0);
370 }
371
372 rk3066_hdmi_config_phy(hdmi);
373
374 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_E);
375
376 /*
377 * When the IP controller is configured with accurate video
378 * timing, the TMDS clock source should be switched to
379 * DCLK_LCDC, so we need to init the TMDS rate to the pixel mode
380 * clock rate and reconfigure the DDC clock.
381 */
382 rk3066_hdmi_i2c_init(hdmi);
383
384 /* Unmute video output. */
385 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
386 HDMI_VIDEO_AUDIO_DISABLE_MASK, HDMI_AUDIO_DISABLE);
387 return 0;
388}
389
390static void
391rk3066_hdmi_encoder_mode_set(struct drm_encoder *encoder,
392 struct drm_display_mode *mode,
393 struct drm_display_mode *adj_mode)
394{
395 struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
396
397 /* Store the display mode for plugin/DPMS poweron events. */
398 drm_mode_copy(&hdmi->previous_mode, adj_mode);
399}
400
401static void rk3066_hdmi_encoder_enable(struct drm_encoder *encoder)
402{
403 struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
404 int mux, val;
405
406 mux = drm_of_encoder_active_endpoint_id(hdmi->dev->of_node, encoder);
407 if (mux)
408 val = (HDMI_VIDEO_SEL << 16) | HDMI_VIDEO_SEL;
409 else
410 val = HDMI_VIDEO_SEL << 16;
411
412 regmap_write(hdmi->grf_regmap, GRF_SOC_CON0, val);
413
414 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder enable select: vop%s\n",
415 (mux) ? "1" : "0");
416
417 rk3066_hdmi_setup(hdmi, &hdmi->previous_mode);
418}
419
420static void rk3066_hdmi_encoder_disable(struct drm_encoder *encoder)
421{
422 struct rk3066_hdmi *hdmi = encoder_to_rk3066_hdmi(encoder);
423
424 DRM_DEV_DEBUG(hdmi->dev, "hdmi encoder disable\n");
425
426 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_E) {
427 hdmi_writeb(hdmi, HDMI_VIDEO_CTRL2,
428 HDMI_VIDEO_AUDIO_DISABLE_MASK);
429 hdmi_modb(hdmi, HDMI_VIDEO_CTRL2,
430 HDMI_AUDIO_CP_LOGIC_RESET_MASK,
431 HDMI_AUDIO_CP_LOGIC_RESET);
432 usleep_range(500, 510);
433 }
434 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
435}
436
437static bool
438rk3066_hdmi_encoder_mode_fixup(struct drm_encoder *encoder,
439 const struct drm_display_mode *mode,
440 struct drm_display_mode *adj_mode)
441{
442 return true;
443}
444
445static int
446rk3066_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
447 struct drm_crtc_state *crtc_state,
448 struct drm_connector_state *conn_state)
449{
450 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
451
452 s->output_mode = ROCKCHIP_OUT_MODE_P888;
453 s->output_type = DRM_MODE_CONNECTOR_HDMIA;
454
455 return 0;
456}
457
458static const
459struct drm_encoder_helper_funcs rk3066_hdmi_encoder_helper_funcs = {
460 .enable = rk3066_hdmi_encoder_enable,
461 .disable = rk3066_hdmi_encoder_disable,
462 .mode_fixup = rk3066_hdmi_encoder_mode_fixup,
463 .mode_set = rk3066_hdmi_encoder_mode_set,
464 .atomic_check = rk3066_hdmi_encoder_atomic_check,
465};
466
467static enum drm_connector_status
468rk3066_hdmi_connector_detect(struct drm_connector *connector, bool force)
469{
470 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
471
472 return (hdmi_readb(hdmi, HDMI_HPG_MENS_STA) & HDMI_HPG_IN_STATUS_HIGH) ?
473 connector_status_connected : connector_status_disconnected;
474}
475
476static int rk3066_hdmi_connector_get_modes(struct drm_connector *connector)
477{
478 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
479 struct edid *edid;
480 int ret = 0;
481
482 if (!hdmi->ddc)
483 return 0;
484
485 edid = drm_get_edid(connector, hdmi->ddc);
486 if (edid) {
487 drm_connector_update_edid_property(connector, edid);
488 ret = drm_add_edid_modes(connector, edid);
489 kfree(edid);
490 }
491
492 return ret;
493}
494
495static enum drm_mode_status
496rk3066_hdmi_connector_mode_valid(struct drm_connector *connector,
497 struct drm_display_mode *mode)
498{
499 u32 vic = drm_match_cea_mode(mode);
500
501 if (vic > 1)
502 return MODE_OK;
503 else
504 return MODE_BAD;
505}
506
507static struct drm_encoder *
508rk3066_hdmi_connector_best_encoder(struct drm_connector *connector)
509{
510 struct rk3066_hdmi *hdmi = connector_to_rk3066_hdmi(connector);
511
512 return &hdmi->encoder.encoder;
513}
514
515static int
516rk3066_hdmi_probe_single_connector_modes(struct drm_connector *connector,
517 uint32_t maxX, uint32_t maxY)
518{
519 if (maxX > 1920)
520 maxX = 1920;
521 if (maxY > 1080)
522 maxY = 1080;
523
524 return drm_helper_probe_single_connector_modes(connector, maxX, maxY);
525}
526
527static void rk3066_hdmi_connector_destroy(struct drm_connector *connector)
528{
529 drm_connector_unregister(connector);
530 drm_connector_cleanup(connector);
531}
532
533static const struct drm_connector_funcs rk3066_hdmi_connector_funcs = {
534 .fill_modes = rk3066_hdmi_probe_single_connector_modes,
535 .detect = rk3066_hdmi_connector_detect,
536 .destroy = rk3066_hdmi_connector_destroy,
537 .reset = drm_atomic_helper_connector_reset,
538 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
539 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
540};
541
542static const
543struct drm_connector_helper_funcs rk3066_hdmi_connector_helper_funcs = {
544 .get_modes = rk3066_hdmi_connector_get_modes,
545 .mode_valid = rk3066_hdmi_connector_mode_valid,
546 .best_encoder = rk3066_hdmi_connector_best_encoder,
547};
548
549static int
550rk3066_hdmi_register(struct drm_device *drm, struct rk3066_hdmi *hdmi)
551{
552 struct drm_encoder *encoder = &hdmi->encoder.encoder;
553 struct device *dev = hdmi->dev;
554
555 encoder->possible_crtcs =
556 drm_of_find_possible_crtcs(drm, dev->of_node);
557
558 /*
559 * If we failed to find the CRTC(s) which this encoder is
560 * supposed to be connected to, it's because the CRTC has
561 * not been registered yet. Defer probing, and hope that
562 * the required CRTC is added later.
563 */
564 if (encoder->possible_crtcs == 0)
565 return -EPROBE_DEFER;
566
567 drm_encoder_helper_add(encoder, &rk3066_hdmi_encoder_helper_funcs);
568 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
569
570 hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
571
572 drm_connector_helper_add(&hdmi->connector,
573 &rk3066_hdmi_connector_helper_funcs);
574 drm_connector_init_with_ddc(drm, &hdmi->connector,
575 &rk3066_hdmi_connector_funcs,
576 DRM_MODE_CONNECTOR_HDMIA,
577 hdmi->ddc);
578
579 drm_connector_attach_encoder(&hdmi->connector, encoder);
580
581 return 0;
582}
583
584static irqreturn_t rk3066_hdmi_hardirq(int irq, void *dev_id)
585{
586 struct rk3066_hdmi *hdmi = dev_id;
587 irqreturn_t ret = IRQ_NONE;
588 u8 interrupt;
589
590 if (rk3066_hdmi_get_power_mode(hdmi) == HDMI_SYS_POWER_MODE_A)
591 hdmi_writeb(hdmi, HDMI_SYS_CTRL, HDMI_SYS_POWER_MODE_B);
592
593 interrupt = hdmi_readb(hdmi, HDMI_INTR_STATUS1);
594 if (interrupt)
595 hdmi_writeb(hdmi, HDMI_INTR_STATUS1, interrupt);
596
597 if (interrupt & HDMI_INTR_EDID_MASK) {
598 hdmi->i2c->stat = interrupt;
599 complete(&hdmi->i2c->cmpltn);
600 }
601
602 if (interrupt & (HDMI_INTR_HOTPLUG | HDMI_INTR_MSENS))
603 ret = IRQ_WAKE_THREAD;
604
605 return ret;
606}
607
608static irqreturn_t rk3066_hdmi_irq(int irq, void *dev_id)
609{
610 struct rk3066_hdmi *hdmi = dev_id;
611
612 drm_helper_hpd_irq_event(hdmi->connector.dev);
613
614 return IRQ_HANDLED;
615}
616
617static int rk3066_hdmi_i2c_read(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
618{
619 int length = msgs->len;
620 u8 *buf = msgs->buf;
621 int ret;
622
623 ret = wait_for_completion_timeout(&hdmi->i2c->cmpltn, HZ / 10);
624 if (!ret || hdmi->i2c->stat & HDMI_INTR_EDID_ERR)
625 return -EAGAIN;
626
627 while (length--)
628 *buf++ = hdmi_readb(hdmi, HDMI_DDC_READ_FIFO_ADDR);
629
630 return 0;
631}
632
633static int rk3066_hdmi_i2c_write(struct rk3066_hdmi *hdmi, struct i2c_msg *msgs)
634{
635 /*
636 * The DDC module only supports read EDID message, so
637 * we assume that each word write to this i2c adapter
638 * should be the offset of the EDID word address.
639 */
640 if (msgs->len != 1 ||
641 (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR))
642 return -EINVAL;
643
644 reinit_completion(&hdmi->i2c->cmpltn);
645
646 if (msgs->addr == DDC_SEGMENT_ADDR)
647 hdmi->i2c->segment_addr = msgs->buf[0];
648 if (msgs->addr == DDC_ADDR)
649 hdmi->i2c->ddc_addr = msgs->buf[0];
650
651 /* Set edid fifo first address. */
652 hdmi_writeb(hdmi, HDMI_EDID_FIFO_ADDR, 0x00);
653
654 /* Set edid word address 0x00/0x80. */
655 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr);
656
657 /* Set edid segment pointer. */
658 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr);
659
660 return 0;
661}
662
663static int rk3066_hdmi_i2c_xfer(struct i2c_adapter *adap,
664 struct i2c_msg *msgs, int num)
665{
666 struct rk3066_hdmi *hdmi = i2c_get_adapdata(adap);
667 struct rk3066_hdmi_i2c *i2c = hdmi->i2c;
668 int i, ret = 0;
669
670 mutex_lock(&i2c->i2c_lock);
671
672 rk3066_hdmi_i2c_init(hdmi);
673
674 /* Unmute HDMI EDID interrupt. */
675 hdmi_modb(hdmi, HDMI_INTR_MASK1,
676 HDMI_INTR_EDID_MASK, HDMI_INTR_EDID_MASK);
677 i2c->stat = 0;
678
679 for (i = 0; i < num; i++) {
680 DRM_DEV_DEBUG(hdmi->dev,
681 "xfer: num: %d/%d, len: %d, flags: %#x\n",
682 i + 1, num, msgs[i].len, msgs[i].flags);
683
684 if (msgs[i].flags & I2C_M_RD)
685 ret = rk3066_hdmi_i2c_read(hdmi, &msgs[i]);
686 else
687 ret = rk3066_hdmi_i2c_write(hdmi, &msgs[i]);
688
689 if (ret < 0)
690 break;
691 }
692
693 if (!ret)
694 ret = num;
695
696 /* Mute HDMI EDID interrupt. */
697 hdmi_modb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_EDID_MASK, 0);
698
699 mutex_unlock(&i2c->i2c_lock);
700
701 return ret;
702}
703
704static u32 rk3066_hdmi_i2c_func(struct i2c_adapter *adapter)
705{
706 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
707}
708
709static const struct i2c_algorithm rk3066_hdmi_algorithm = {
710 .master_xfer = rk3066_hdmi_i2c_xfer,
711 .functionality = rk3066_hdmi_i2c_func,
712};
713
714static struct i2c_adapter *rk3066_hdmi_i2c_adapter(struct rk3066_hdmi *hdmi)
715{
716 struct i2c_adapter *adap;
717 struct rk3066_hdmi_i2c *i2c;
718 int ret;
719
720 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
721 if (!i2c)
722 return ERR_PTR(-ENOMEM);
723
724 mutex_init(&i2c->i2c_lock);
725 init_completion(&i2c->cmpltn);
726
727 adap = &i2c->adap;
728 adap->class = I2C_CLASS_DDC;
729 adap->owner = THIS_MODULE;
730 adap->dev.parent = hdmi->dev;
731 adap->dev.of_node = hdmi->dev->of_node;
732 adap->algo = &rk3066_hdmi_algorithm;
733 strlcpy(adap->name, "RK3066 HDMI", sizeof(adap->name));
734 i2c_set_adapdata(adap, hdmi);
735
736 ret = i2c_add_adapter(adap);
737 if (ret) {
738 DRM_DEV_ERROR(hdmi->dev, "cannot add %s I2C adapter\n",
739 adap->name);
740 devm_kfree(hdmi->dev, i2c);
741 return ERR_PTR(ret);
742 }
743
744 hdmi->i2c = i2c;
745
746 DRM_DEV_DEBUG(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
747
748 return adap;
749}
750
751static int rk3066_hdmi_bind(struct device *dev, struct device *master,
752 void *data)
753{
754 struct platform_device *pdev = to_platform_device(dev);
755 struct drm_device *drm = data;
756 struct rk3066_hdmi *hdmi;
757 int irq;
758 int ret;
759
760 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
761 if (!hdmi)
762 return -ENOMEM;
763
764 hdmi->dev = dev;
765 hdmi->drm_dev = drm;
766 hdmi->regs = devm_platform_ioremap_resource(pdev, 0);
767 if (IS_ERR(hdmi->regs))
768 return PTR_ERR(hdmi->regs);
769
770 irq = platform_get_irq(pdev, 0);
771 if (irq < 0)
772 return irq;
773
774 hdmi->hclk = devm_clk_get(dev, "hclk");
775 if (IS_ERR(hdmi->hclk)) {
776 DRM_DEV_ERROR(dev, "unable to get HDMI hclk clock\n");
777 return PTR_ERR(hdmi->hclk);
778 }
779
780 ret = clk_prepare_enable(hdmi->hclk);
781 if (ret) {
782 DRM_DEV_ERROR(dev, "cannot enable HDMI hclk clock: %d\n", ret);
783 return ret;
784 }
785
786 hdmi->grf_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
787 "rockchip,grf");
788 if (IS_ERR(hdmi->grf_regmap)) {
789 DRM_DEV_ERROR(dev, "unable to get rockchip,grf\n");
790 ret = PTR_ERR(hdmi->grf_regmap);
791 goto err_disable_hclk;
792 }
793
794 /* internal hclk = hdmi_hclk / 25 */
795 hdmi_writeb(hdmi, HDMI_INTERNAL_CLK_DIVIDER, 25);
796
797 hdmi->ddc = rk3066_hdmi_i2c_adapter(hdmi);
798 if (IS_ERR(hdmi->ddc)) {
799 ret = PTR_ERR(hdmi->ddc);
800 hdmi->ddc = NULL;
801 goto err_disable_hclk;
802 }
803
804 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_B);
805 usleep_range(999, 1000);
806 hdmi_writeb(hdmi, HDMI_INTR_MASK1, HDMI_INTR_HOTPLUG);
807 hdmi_writeb(hdmi, HDMI_INTR_MASK2, 0);
808 hdmi_writeb(hdmi, HDMI_INTR_MASK3, 0);
809 hdmi_writeb(hdmi, HDMI_INTR_MASK4, 0);
810 rk3066_hdmi_set_power_mode(hdmi, HDMI_SYS_POWER_MODE_A);
811
812 ret = rk3066_hdmi_register(drm, hdmi);
813 if (ret)
814 goto err_disable_i2c;
815
816 dev_set_drvdata(dev, hdmi);
817
818 ret = devm_request_threaded_irq(dev, irq, rk3066_hdmi_hardirq,
819 rk3066_hdmi_irq, IRQF_SHARED,
820 dev_name(dev), hdmi);
821 if (ret) {
822 DRM_DEV_ERROR(dev, "failed to request hdmi irq: %d\n", ret);
823 goto err_cleanup_hdmi;
824 }
825
826 return 0;
827
828err_cleanup_hdmi:
829 hdmi->connector.funcs->destroy(&hdmi->connector);
830 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
831err_disable_i2c:
832 i2c_put_adapter(hdmi->ddc);
833err_disable_hclk:
834 clk_disable_unprepare(hdmi->hclk);
835
836 return ret;
837}
838
839static void rk3066_hdmi_unbind(struct device *dev, struct device *master,
840 void *data)
841{
842 struct rk3066_hdmi *hdmi = dev_get_drvdata(dev);
843
844 hdmi->connector.funcs->destroy(&hdmi->connector);
845 hdmi->encoder.encoder.funcs->destroy(&hdmi->encoder.encoder);
846
847 i2c_put_adapter(hdmi->ddc);
848 clk_disable_unprepare(hdmi->hclk);
849}
850
851static const struct component_ops rk3066_hdmi_ops = {
852 .bind = rk3066_hdmi_bind,
853 .unbind = rk3066_hdmi_unbind,
854};
855
856static int rk3066_hdmi_probe(struct platform_device *pdev)
857{
858 return component_add(&pdev->dev, &rk3066_hdmi_ops);
859}
860
861static int rk3066_hdmi_remove(struct platform_device *pdev)
862{
863 component_del(&pdev->dev, &rk3066_hdmi_ops);
864
865 return 0;
866}
867
868static const struct of_device_id rk3066_hdmi_dt_ids[] = {
869 { .compatible = "rockchip,rk3066-hdmi" },
870 { /* sentinel */ },
871};
872MODULE_DEVICE_TABLE(of, rk3066_hdmi_dt_ids);
873
874struct platform_driver rk3066_hdmi_driver = {
875 .probe = rk3066_hdmi_probe,
876 .remove = rk3066_hdmi_remove,
877 .driver = {
878 .name = "rockchip-rk3066-hdmi",
879 .of_match_table = rk3066_hdmi_dt_ids,
880 },
881};