1/* SPDX-License-Identifier: GPL-2.0 */
  2//
  3// Ingenic JZ47xx IPU - Register definitions and private API
  4//
  5// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net>
  6
  7#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H
  8#define DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H
  9
 10#include <linux/bitops.h>
 11
 12#define JZ_REG_IPU_CTRL			0x00
 13#define JZ_REG_IPU_STATUS		0x04
 14#define JZ_REG_IPU_D_FMT		0x08
 15#define JZ_REG_IPU_Y_ADDR		0x0c
 16#define JZ_REG_IPU_U_ADDR		0x10
 17#define JZ_REG_IPU_V_ADDR		0x14
 18#define JZ_REG_IPU_IN_GS		0x18
 19#define JZ_REG_IPU_Y_STRIDE		0x1c
 20#define JZ_REG_IPU_UV_STRIDE		0x20
 21#define JZ_REG_IPU_OUT_ADDR		0x24
 22#define JZ_REG_IPU_OUT_GS		0x28
 23#define JZ_REG_IPU_OUT_STRIDE		0x2c
 24#define JZ_REG_IPU_RSZ_COEF_INDEX	0x30
 25#define JZ_REG_IPU_CSC_C0_COEF		0x34
 26#define JZ_REG_IPU_CSC_C1_COEF		0x38
 27#define JZ_REG_IPU_CSC_C2_COEF		0x3c
 28#define JZ_REG_IPU_CSC_C3_COEF		0x40
 29#define JZ_REG_IPU_CSC_C4_COEF		0x44
 30#define JZ_REG_IPU_HRSZ_COEF_LUT	0x48
 31#define JZ_REG_IPU_VRSZ_COEF_LUT	0x4c
 32#define JZ_REG_IPU_CSC_OFFSET		0x50
 33#define JZ_REG_IPU_Y_PHY_T_ADDR		0x54
 34#define JZ_REG_IPU_U_PHY_T_ADDR		0x58
 35#define JZ_REG_IPU_V_PHY_T_ADDR		0x5c
 36#define JZ_REG_IPU_OUT_PHY_T_ADDR	0x60
 37
 38#define JZ_IPU_CTRL_ADDR_SEL		BIT(20)
 39#define JZ_IPU_CTRL_ZOOM_SEL		BIT(18)
 40#define JZ_IPU_CTRL_DFIX_SEL		BIT(17)
 41#define JZ_IPU_CTRL_LCDC_SEL		BIT(11)
 42#define JZ_IPU_CTRL_SPKG_SEL		BIT(10)
 43#define JZ_IPU_CTRL_VSCALE		BIT(9)
 44#define JZ_IPU_CTRL_HSCALE		BIT(8)
 45#define JZ_IPU_CTRL_STOP		BIT(7)
 46#define JZ_IPU_CTRL_RST			BIT(6)
 47#define JZ_IPU_CTRL_FM_IRQ_EN		BIT(5)
 48#define JZ_IPU_CTRL_CSC_EN		BIT(4)
 49#define JZ_IPU_CTRL_VRSZ_EN		BIT(3)
 50#define JZ_IPU_CTRL_HRSZ_EN		BIT(2)
 51#define JZ_IPU_CTRL_RUN			BIT(1)
 52#define JZ_IPU_CTRL_CHIP_EN		BIT(0)
 53
 54#define JZ_IPU_STATUS_OUT_END		BIT(0)
 55
 56#define JZ_IPU_IN_GS_H_LSB		0x0
 57#define JZ_IPU_IN_GS_W_LSB		0x10
 58#define JZ_IPU_OUT_GS_H_LSB		0x0
 59#define JZ_IPU_OUT_GS_W_LSB		0x10
 60
 61#define JZ_IPU_Y_STRIDE_Y_LSB		0
 62#define JZ_IPU_UV_STRIDE_U_LSB		16
 63#define JZ_IPU_UV_STRIDE_V_LSB		0
 64
 65#define JZ_IPU_D_FMT_IN_FMT_LSB		0
 66#define JZ_IPU_D_FMT_IN_FMT_RGB555	(0x0 << JZ_IPU_D_FMT_IN_FMT_LSB)
 67#define JZ_IPU_D_FMT_IN_FMT_YUV420	(0x0 << JZ_IPU_D_FMT_IN_FMT_LSB)
 68#define JZ_IPU_D_FMT_IN_FMT_YUV422	(0x1 << JZ_IPU_D_FMT_IN_FMT_LSB)
 69#define JZ_IPU_D_FMT_IN_FMT_RGB888	(0x2 << JZ_IPU_D_FMT_IN_FMT_LSB)
 70#define JZ_IPU_D_FMT_IN_FMT_YUV444	(0x2 << JZ_IPU_D_FMT_IN_FMT_LSB)
 71#define JZ_IPU_D_FMT_IN_FMT_RGB565	(0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
 72
 73#define JZ_IPU_D_FMT_YUV_FMT_LSB	2
 74#define JZ_IPU_D_FMT_YUV_Y1UY0V		(0x0 << JZ_IPU_D_FMT_YUV_FMT_LSB)
 75#define JZ_IPU_D_FMT_YUV_Y1VY0U		(0x1 << JZ_IPU_D_FMT_YUV_FMT_LSB)
 76#define JZ_IPU_D_FMT_YUV_UY1VY0		(0x2 << JZ_IPU_D_FMT_YUV_FMT_LSB)
 77#define JZ_IPU_D_FMT_YUV_VY1UY0		(0x3 << JZ_IPU_D_FMT_YUV_FMT_LSB)
 78#define JZ_IPU_D_FMT_IN_FMT_YUV411	(0x3 << JZ_IPU_D_FMT_IN_FMT_LSB)
 79
 80#define JZ_IPU_D_FMT_OUT_FMT_LSB	19
 81#define JZ_IPU_D_FMT_OUT_FMT_RGB555	(0x0 << JZ_IPU_D_FMT_OUT_FMT_LSB)
 82#define JZ_IPU_D_FMT_OUT_FMT_RGB565	(0x1 << JZ_IPU_D_FMT_OUT_FMT_LSB)
 83#define JZ_IPU_D_FMT_OUT_FMT_RGB888	(0x2 << JZ_IPU_D_FMT_OUT_FMT_LSB)
 84#define JZ_IPU_D_FMT_OUT_FMT_YUV422	(0x3 << JZ_IPU_D_FMT_OUT_FMT_LSB)
 85#define JZ_IPU_D_FMT_OUT_FMT_RGBAAA	(0x4 << JZ_IPU_D_FMT_OUT_FMT_LSB)
 86
 87#define JZ_IPU_D_FMT_RGB_OUT_OFT_LSB	22
 88#define JZ_IPU_D_FMT_RGB_OUT_OFT_RGB	(0x0 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
 89#define JZ_IPU_D_FMT_RGB_OUT_OFT_RBG	(0x1 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
 90#define JZ_IPU_D_FMT_RGB_OUT_OFT_GBR	(0x2 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
 91#define JZ_IPU_D_FMT_RGB_OUT_OFT_GRB	(0x3 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
 92#define JZ_IPU_D_FMT_RGB_OUT_OFT_BRG	(0x4 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
 93#define JZ_IPU_D_FMT_RGB_OUT_OFT_BGR	(0x5 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB)
 94
 95#define JZ4725B_IPU_RSZ_LUT_COEF_LSB	2
 96#define JZ4725B_IPU_RSZ_LUT_COEF_MASK	0x7ff
 97#define JZ4725B_IPU_RSZ_LUT_IN_EN	BIT(1)
 98#define JZ4725B_IPU_RSZ_LUT_OUT_EN	BIT(0)
 99
100#define JZ4760_IPU_RSZ_COEF20_LSB	6
101#define JZ4760_IPU_RSZ_COEF31_LSB	17
102#define JZ4760_IPU_RSZ_COEF_MASK	0x7ff
103#define JZ4760_IPU_RSZ_OFFSET_LSB	1
104#define JZ4760_IPU_RSZ_OFFSET_MASK	0x1f
105
106#define JZ_IPU_CSC_OFFSET_CHROMA_LSB	16
107#define JZ_IPU_CSC_OFFSET_LUMA_LSB	16
108
109#endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H */