1#ifndef __IPUV3_PLANE_H__
 2#define __IPUV3_PLANE_H__
 3
 4#include <drm/drm_crtc.h> /* drm_plane */
 5
 6struct drm_plane;
 7struct drm_device;
 8struct ipu_soc;
 9struct drm_crtc;
10struct drm_framebuffer;
11
12struct ipuv3_channel;
13struct dmfc_channel;
14struct ipu_dp;
15
16struct ipu_plane {
17	struct drm_plane	base;
18
19	struct ipu_soc		*ipu;
20	struct ipuv3_channel	*ipu_ch;
 
21	struct dmfc_channel	*dmfc;
22	struct ipu_dp		*dp;
23
24	int			dma;
25	int			dp_flow;
26
27	int			x;
28	int			y;
29	int			w;
30	int			h;
31
32	unsigned int		u_offset;
33	unsigned int		v_offset;
34	unsigned int		stride[2];
35
36	bool			enabled;
37};
38
39struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
40				 int dma, int dp, unsigned int possible_crtcs,
41				 enum drm_plane_type type);
42
43/* Init IDMAC, DMFC, DP */
44int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
45		       struct drm_display_mode *mode,
46		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
47		       unsigned int crtc_w, unsigned int crtc_h,
48		       uint32_t src_x, uint32_t src_y, uint32_t src_w,
49		       uint32_t src_h, bool interlaced);
50
51void ipu_plane_enable(struct ipu_plane *plane);
52void ipu_plane_disable(struct ipu_plane *plane);
53int ipu_plane_set_base(struct ipu_plane *plane, struct drm_framebuffer *fb,
54		       int x, int y);
55
56int ipu_plane_get_resources(struct ipu_plane *plane);
57void ipu_plane_put_resources(struct ipu_plane *plane);
58
59int ipu_plane_irq(struct ipu_plane *plane);
 
 
 
 
60
61#endif

 1/* SPDX-License-Identifier: GPL-2.0 */
 2#ifndef __IPUV3_PLANE_H__
 3#define __IPUV3_PLANE_H__
 4
 5#include <drm/drm_crtc.h> /* drm_plane */
 6
 7struct drm_plane;
 8struct drm_device;
 9struct ipu_soc;
10struct drm_crtc;
11struct drm_framebuffer;
12
13struct ipuv3_channel;
14struct dmfc_channel;
15struct ipu_dp;
16
17struct ipu_plane {
18	struct drm_plane	base;
19
20	struct ipu_soc		*ipu;
21	struct ipuv3_channel	*ipu_ch;
22	struct ipuv3_channel	*alpha_ch;
23	struct dmfc_channel	*dmfc;
24	struct ipu_dp		*dp;
25
26	int			dma;
27	int			dp_flow;
28
29	bool			disabling;
 
 
 
 
 
 
 
 
 
30};
31
32struct ipu_plane *ipu_plane_init(struct drm_device *dev, struct ipu_soc *ipu,
33				 int dma, int dp, unsigned int possible_crtcs,
34				 enum drm_plane_type type);
35
36/* Init IDMAC, DMFC, DP */
37int ipu_plane_mode_set(struct ipu_plane *plane, struct drm_crtc *crtc,
38		       struct drm_display_mode *mode,
39		       struct drm_framebuffer *fb, int crtc_x, int crtc_y,
40		       unsigned int crtc_w, unsigned int crtc_h,
41		       uint32_t src_x, uint32_t src_y, uint32_t src_w,
42		       uint32_t src_h, bool interlaced);
43
 
 
 
 
 
 
 
 
44int ipu_plane_irq(struct ipu_plane *plane);
45
46void ipu_plane_disable(struct ipu_plane *ipu_plane, bool disable_dp_channel);
47void ipu_plane_disable_deferred(struct drm_plane *plane);
48bool ipu_plane_atomic_update_pending(struct drm_plane *plane);
49
50#endif