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1/*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27#include <drm/drmP.h>
28#include <drm/i915_drm.h>
29#include "intel_drv.h"
30#include "i915_reg.h"
31
32static void i915_save_display(struct drm_device *dev)
33{
34 struct drm_i915_private *dev_priv = dev->dev_private;
35
36 /* Display arbitration control */
37 if (INTEL_INFO(dev)->gen <= 4)
38 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
39
40 /* LVDS state */
41 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
42 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
43 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
44 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
45
46 /* Panel power sequencer */
47 if (HAS_PCH_SPLIT(dev)) {
48 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
49 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
50 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
51 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
52 } else if (INTEL_INFO(dev)->gen <= 4) {
53 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
54 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
55 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
56 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
57 }
58
59 /* save FBC interval */
60 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
61 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
62}
63
64static void i915_restore_display(struct drm_device *dev)
65{
66 struct drm_i915_private *dev_priv = dev->dev_private;
67 u32 mask = 0xffffffff;
68
69 /* Display arbitration */
70 if (INTEL_INFO(dev)->gen <= 4)
71 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
72
73 mask = ~LVDS_PORT_EN;
74
75 /* LVDS state */
76 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
77 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
78 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
79 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
80
81 /* Panel power sequencer */
82 if (HAS_PCH_SPLIT(dev)) {
83 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
84 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
85 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
86 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
87 } else if (INTEL_INFO(dev)->gen <= 4) {
88 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
89 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
90 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
91 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
92 }
93
94 /* only restore FBC info on the platform that supports FBC*/
95 intel_fbc_global_disable(dev_priv);
96
97 /* restore FBC interval */
98 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev))
99 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
100
101 i915_redisable_vga(dev);
102}
103
104int i915_save_state(struct drm_device *dev)
105{
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 int i;
108
109 mutex_lock(&dev->struct_mutex);
110
111 i915_save_display(dev);
112
113 if (IS_GEN4(dev))
114 pci_read_config_word(dev->pdev, GCDGMBUS,
115 &dev_priv->regfile.saveGCDGMBUS);
116
117 /* Cache mode state */
118 if (INTEL_INFO(dev)->gen < 7)
119 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
120
121 /* Memory Arbitration state */
122 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
123
124 /* Scratch space */
125 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
126 for (i = 0; i < 7; i++) {
127 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
128 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
129 }
130 for (i = 0; i < 3; i++)
131 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
132 } else if (IS_GEN2(dev_priv)) {
133 for (i = 0; i < 7; i++)
134 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
135 } else if (HAS_GMCH_DISPLAY(dev_priv)) {
136 for (i = 0; i < 16; i++) {
137 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
138 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
139 }
140 for (i = 0; i < 3; i++)
141 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
142 }
143
144 mutex_unlock(&dev->struct_mutex);
145
146 return 0;
147}
148
149int i915_restore_state(struct drm_device *dev)
150{
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 int i;
153
154 mutex_lock(&dev->struct_mutex);
155
156 i915_gem_restore_fences(dev);
157
158 if (IS_GEN4(dev))
159 pci_write_config_word(dev->pdev, GCDGMBUS,
160 dev_priv->regfile.saveGCDGMBUS);
161 i915_restore_display(dev);
162
163 /* Cache mode state */
164 if (INTEL_INFO(dev)->gen < 7)
165 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
166 0xffff0000);
167
168 /* Memory arbitration state */
169 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
170
171 /* Scratch space */
172 if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
173 for (i = 0; i < 7; i++) {
174 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
175 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
176 }
177 for (i = 0; i < 3; i++)
178 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
179 } else if (IS_GEN2(dev_priv)) {
180 for (i = 0; i < 7; i++)
181 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
182 } else if (HAS_GMCH_DISPLAY(dev_priv)) {
183 for (i = 0; i < 16; i++) {
184 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
185 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
186 }
187 for (i = 0; i < 3; i++)
188 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
189 }
190
191 mutex_unlock(&dev->struct_mutex);
192
193 intel_i2c_reset(dev);
194
195 return 0;
196}
1/*
2 *
3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27#include "display/intel_de.h"
28#include "display/intel_gmbus.h"
29#include "display/intel_vga.h"
30
31#include "i915_drv.h"
32#include "i915_reg.h"
33#include "i915_suspend.h"
34#include "intel_pci_config.h"
35
36static void intel_save_swf(struct drm_i915_private *dev_priv)
37{
38 int i;
39
40 /* Scratch space */
41 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) {
42 for (i = 0; i < 7; i++) {
43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
45 }
46 for (i = 0; i < 3; i++)
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
48 } else if (GRAPHICS_VER(dev_priv) == 2) {
49 for (i = 0; i < 7; i++)
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
51 } else if (HAS_GMCH(dev_priv)) {
52 for (i = 0; i < 16; i++) {
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i));
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i));
55 }
56 for (i = 0; i < 3; i++)
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i));
58 }
59}
60
61static void intel_restore_swf(struct drm_i915_private *dev_priv)
62{
63 int i;
64
65 /* Scratch space */
66 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) {
67 for (i = 0; i < 7; i++) {
68 intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
69 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
70 }
71 for (i = 0; i < 3; i++)
72 intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
73 } else if (GRAPHICS_VER(dev_priv) == 2) {
74 for (i = 0; i < 7; i++)
75 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
76 } else if (HAS_GMCH(dev_priv)) {
77 for (i = 0; i < 16; i++) {
78 intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]);
79 intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]);
80 }
81 for (i = 0; i < 3; i++)
82 intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]);
83 }
84}
85
86void i915_save_display(struct drm_i915_private *dev_priv)
87{
88 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
89
90 if (!HAS_DISPLAY(dev_priv))
91 return;
92
93 /* Display arbitration control */
94 if (GRAPHICS_VER(dev_priv) <= 4)
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
96
97 if (GRAPHICS_VER(dev_priv) == 4)
98 pci_read_config_word(pdev, GCDGMBUS,
99 &dev_priv->regfile.saveGCDGMBUS);
100
101 intel_save_swf(dev_priv);
102}
103
104void i915_restore_display(struct drm_i915_private *dev_priv)
105{
106 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
107
108 if (!HAS_DISPLAY(dev_priv))
109 return;
110
111 intel_restore_swf(dev_priv);
112
113 if (GRAPHICS_VER(dev_priv) == 4)
114 pci_write_config_word(pdev, GCDGMBUS,
115 dev_priv->regfile.saveGCDGMBUS);
116
117 /* Display arbitration */
118 if (GRAPHICS_VER(dev_priv) <= 4)
119 intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
120
121 intel_vga_redisable(dev_priv);
122
123 intel_gmbus_reset(dev_priv);
124}