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1/*
2 * SPDX-License-Identifier: MIT
3 *
4 * Copyright © 2017-2018 Intel Corporation
5 */
6
7#include <linux/pm_runtime.h>
8
9#include "gt/intel_engine.h"
10#include "gt/intel_engine_pm.h"
11#include "gt/intel_engine_regs.h"
12#include "gt/intel_engine_user.h"
13#include "gt/intel_gt_pm.h"
14#include "gt/intel_gt_regs.h"
15#include "gt/intel_rc6.h"
16#include "gt/intel_rps.h"
17
18#include "i915_drv.h"
19#include "i915_pmu.h"
20#include "intel_pm.h"
21
22/* Frequency for the sampling timer for events which need it. */
23#define FREQUENCY 200
24#define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)
25
26#define ENGINE_SAMPLE_MASK \
27 (BIT(I915_SAMPLE_BUSY) | \
28 BIT(I915_SAMPLE_WAIT) | \
29 BIT(I915_SAMPLE_SEMA))
30
31static cpumask_t i915_pmu_cpumask;
32static unsigned int i915_pmu_target_cpu = -1;
33
34static u8 engine_config_sample(u64 config)
35{
36 return config & I915_PMU_SAMPLE_MASK;
37}
38
39static u8 engine_event_sample(struct perf_event *event)
40{
41 return engine_config_sample(event->attr.config);
42}
43
44static u8 engine_event_class(struct perf_event *event)
45{
46 return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff;
47}
48
49static u8 engine_event_instance(struct perf_event *event)
50{
51 return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
52}
53
54static bool is_engine_config(u64 config)
55{
56 return config < __I915_PMU_OTHER(0);
57}
58
59static unsigned int other_bit(const u64 config)
60{
61 unsigned int val;
62
63 switch (config) {
64 case I915_PMU_ACTUAL_FREQUENCY:
65 val = __I915_PMU_ACTUAL_FREQUENCY_ENABLED;
66 break;
67 case I915_PMU_REQUESTED_FREQUENCY:
68 val = __I915_PMU_REQUESTED_FREQUENCY_ENABLED;
69 break;
70 case I915_PMU_RC6_RESIDENCY:
71 val = __I915_PMU_RC6_RESIDENCY_ENABLED;
72 break;
73 default:
74 /*
75 * Events that do not require sampling, or tracking state
76 * transitions between enabled and disabled can be ignored.
77 */
78 return -1;
79 }
80
81 return I915_ENGINE_SAMPLE_COUNT + val;
82}
83
84static unsigned int config_bit(const u64 config)
85{
86 if (is_engine_config(config))
87 return engine_config_sample(config);
88 else
89 return other_bit(config);
90}
91
92static u64 config_mask(u64 config)
93{
94 return BIT_ULL(config_bit(config));
95}
96
97static bool is_engine_event(struct perf_event *event)
98{
99 return is_engine_config(event->attr.config);
100}
101
102static unsigned int event_bit(struct perf_event *event)
103{
104 return config_bit(event->attr.config);
105}
106
107static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
108{
109 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
110 u32 enable;
111
112 /*
113 * Only some counters need the sampling timer.
114 *
115 * We start with a bitmask of all currently enabled events.
116 */
117 enable = pmu->enable;
118
119 /*
120 * Mask out all the ones which do not need the timer, or in
121 * other words keep all the ones that could need the timer.
122 */
123 enable &= config_mask(I915_PMU_ACTUAL_FREQUENCY) |
124 config_mask(I915_PMU_REQUESTED_FREQUENCY) |
125 ENGINE_SAMPLE_MASK;
126
127 /*
128 * When the GPU is idle per-engine counters do not need to be
129 * running so clear those bits out.
130 */
131 if (!gpu_active)
132 enable &= ~ENGINE_SAMPLE_MASK;
133 /*
134 * Also there is software busyness tracking available we do not
135 * need the timer for I915_SAMPLE_BUSY counter.
136 */
137 else if (i915->caps.scheduler & I915_SCHEDULER_CAP_ENGINE_BUSY_STATS)
138 enable &= ~BIT(I915_SAMPLE_BUSY);
139
140 /*
141 * If some bits remain it means we need the sampling timer running.
142 */
143 return enable;
144}
145
146static u64 __get_rc6(struct intel_gt *gt)
147{
148 struct drm_i915_private *i915 = gt->i915;
149 u64 val;
150
151 val = intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6);
152
153 if (HAS_RC6p(i915))
154 val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6p);
155
156 if (HAS_RC6pp(i915))
157 val += intel_rc6_residency_ns(>->rc6, INTEL_RC6_RES_RC6pp);
158
159 return val;
160}
161
162static inline s64 ktime_since_raw(const ktime_t kt)
163{
164 return ktime_to_ns(ktime_sub(ktime_get_raw(), kt));
165}
166
167static u64 get_rc6(struct intel_gt *gt)
168{
169 struct drm_i915_private *i915 = gt->i915;
170 struct i915_pmu *pmu = &i915->pmu;
171 unsigned long flags;
172 bool awake = false;
173 u64 val;
174
175 if (intel_gt_pm_get_if_awake(gt)) {
176 val = __get_rc6(gt);
177 intel_gt_pm_put_async(gt);
178 awake = true;
179 }
180
181 spin_lock_irqsave(&pmu->lock, flags);
182
183 if (awake) {
184 pmu->sample[__I915_SAMPLE_RC6].cur = val;
185 } else {
186 /*
187 * We think we are runtime suspended.
188 *
189 * Report the delta from when the device was suspended to now,
190 * on top of the last known real value, as the approximated RC6
191 * counter value.
192 */
193 val = ktime_since_raw(pmu->sleep_last);
194 val += pmu->sample[__I915_SAMPLE_RC6].cur;
195 }
196
197 if (val < pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur)
198 val = pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur;
199 else
200 pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = val;
201
202 spin_unlock_irqrestore(&pmu->lock, flags);
203
204 return val;
205}
206
207static void init_rc6(struct i915_pmu *pmu)
208{
209 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
210 intel_wakeref_t wakeref;
211
212 with_intel_runtime_pm(to_gt(i915)->uncore->rpm, wakeref) {
213 pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
214 pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur =
215 pmu->sample[__I915_SAMPLE_RC6].cur;
216 pmu->sleep_last = ktime_get_raw();
217 }
218}
219
220static void park_rc6(struct drm_i915_private *i915)
221{
222 struct i915_pmu *pmu = &i915->pmu;
223
224 pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(to_gt(i915));
225 pmu->sleep_last = ktime_get_raw();
226}
227
228static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
229{
230 if (!pmu->timer_enabled && pmu_needs_timer(pmu, true)) {
231 pmu->timer_enabled = true;
232 pmu->timer_last = ktime_get();
233 hrtimer_start_range_ns(&pmu->timer,
234 ns_to_ktime(PERIOD), 0,
235 HRTIMER_MODE_REL_PINNED);
236 }
237}
238
239void i915_pmu_gt_parked(struct drm_i915_private *i915)
240{
241 struct i915_pmu *pmu = &i915->pmu;
242
243 if (!pmu->base.event_init)
244 return;
245
246 spin_lock_irq(&pmu->lock);
247
248 park_rc6(i915);
249
250 /*
251 * Signal sampling timer to stop if only engine events are enabled and
252 * GPU went idle.
253 */
254 pmu->timer_enabled = pmu_needs_timer(pmu, false);
255
256 spin_unlock_irq(&pmu->lock);
257}
258
259void i915_pmu_gt_unparked(struct drm_i915_private *i915)
260{
261 struct i915_pmu *pmu = &i915->pmu;
262
263 if (!pmu->base.event_init)
264 return;
265
266 spin_lock_irq(&pmu->lock);
267
268 /*
269 * Re-enable sampling timer when GPU goes active.
270 */
271 __i915_pmu_maybe_start_timer(pmu);
272
273 spin_unlock_irq(&pmu->lock);
274}
275
276static void
277add_sample(struct i915_pmu_sample *sample, u32 val)
278{
279 sample->cur += val;
280}
281
282static bool exclusive_mmio_access(const struct drm_i915_private *i915)
283{
284 /*
285 * We have to avoid concurrent mmio cache line access on gen7 or
286 * risk a machine hang. For a fun history lesson dig out the old
287 * userspace intel_gpu_top and run it on Ivybridge or Haswell!
288 */
289 return GRAPHICS_VER(i915) == 7;
290}
291
292static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
293{
294 struct intel_engine_pmu *pmu = &engine->pmu;
295 bool busy;
296 u32 val;
297
298 val = ENGINE_READ_FW(engine, RING_CTL);
299 if (val == 0) /* powerwell off => engine idle */
300 return;
301
302 if (val & RING_WAIT)
303 add_sample(&pmu->sample[I915_SAMPLE_WAIT], period_ns);
304 if (val & RING_WAIT_SEMAPHORE)
305 add_sample(&pmu->sample[I915_SAMPLE_SEMA], period_ns);
306
307 /* No need to sample when busy stats are supported. */
308 if (intel_engine_supports_stats(engine))
309 return;
310
311 /*
312 * While waiting on a semaphore or event, MI_MODE reports the
313 * ring as idle. However, previously using the seqno, and with
314 * execlists sampling, we account for the ring waiting as the
315 * engine being busy. Therefore, we record the sample as being
316 * busy if either waiting or !idle.
317 */
318 busy = val & (RING_WAIT_SEMAPHORE | RING_WAIT);
319 if (!busy) {
320 val = ENGINE_READ_FW(engine, RING_MI_MODE);
321 busy = !(val & MODE_IDLE);
322 }
323 if (busy)
324 add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
325}
326
327static void
328engines_sample(struct intel_gt *gt, unsigned int period_ns)
329{
330 struct drm_i915_private *i915 = gt->i915;
331 struct intel_engine_cs *engine;
332 enum intel_engine_id id;
333 unsigned long flags;
334
335 if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
336 return;
337
338 if (!intel_gt_pm_is_awake(gt))
339 return;
340
341 for_each_engine(engine, gt, id) {
342 if (!intel_engine_pm_get_if_awake(engine))
343 continue;
344
345 if (exclusive_mmio_access(i915)) {
346 spin_lock_irqsave(&engine->uncore->lock, flags);
347 engine_sample(engine, period_ns);
348 spin_unlock_irqrestore(&engine->uncore->lock, flags);
349 } else {
350 engine_sample(engine, period_ns);
351 }
352
353 intel_engine_pm_put_async(engine);
354 }
355}
356
357static void
358add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul)
359{
360 sample->cur += mul_u32_u32(val, mul);
361}
362
363static bool frequency_sampling_enabled(struct i915_pmu *pmu)
364{
365 return pmu->enable &
366 (config_mask(I915_PMU_ACTUAL_FREQUENCY) |
367 config_mask(I915_PMU_REQUESTED_FREQUENCY));
368}
369
370static void
371frequency_sample(struct intel_gt *gt, unsigned int period_ns)
372{
373 struct drm_i915_private *i915 = gt->i915;
374 struct i915_pmu *pmu = &i915->pmu;
375 struct intel_rps *rps = >->rps;
376
377 if (!frequency_sampling_enabled(pmu))
378 return;
379
380 /* Report 0/0 (actual/requested) frequency while parked. */
381 if (!intel_gt_pm_get_if_awake(gt))
382 return;
383
384 if (pmu->enable & config_mask(I915_PMU_ACTUAL_FREQUENCY)) {
385 u32 val;
386
387 /*
388 * We take a quick peek here without using forcewake
389 * so that we don't perturb the system under observation
390 * (forcewake => !rc6 => increased power use). We expect
391 * that if the read fails because it is outside of the
392 * mmio power well, then it will return 0 -- in which
393 * case we assume the system is running at the intended
394 * frequency. Fortunately, the read should rarely fail!
395 */
396 val = intel_rps_read_rpstat_fw(rps);
397 if (val)
398 val = intel_rps_get_cagf(rps, val);
399 else
400 val = rps->cur_freq;
401
402 add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT],
403 intel_gpu_freq(rps, val), period_ns / 1000);
404 }
405
406 if (pmu->enable & config_mask(I915_PMU_REQUESTED_FREQUENCY)) {
407 add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ],
408 intel_rps_get_requested_frequency(rps),
409 period_ns / 1000);
410 }
411
412 intel_gt_pm_put_async(gt);
413}
414
415static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer)
416{
417 struct drm_i915_private *i915 =
418 container_of(hrtimer, struct drm_i915_private, pmu.timer);
419 struct i915_pmu *pmu = &i915->pmu;
420 struct intel_gt *gt = to_gt(i915);
421 unsigned int period_ns;
422 ktime_t now;
423
424 if (!READ_ONCE(pmu->timer_enabled))
425 return HRTIMER_NORESTART;
426
427 now = ktime_get();
428 period_ns = ktime_to_ns(ktime_sub(now, pmu->timer_last));
429 pmu->timer_last = now;
430
431 /*
432 * Strictly speaking the passed in period may not be 100% accurate for
433 * all internal calculation, since some amount of time can be spent on
434 * grabbing the forcewake. However the potential error from timer call-
435 * back delay greatly dominates this so we keep it simple.
436 */
437 engines_sample(gt, period_ns);
438 frequency_sample(gt, period_ns);
439
440 hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
441
442 return HRTIMER_RESTART;
443}
444
445static void i915_pmu_event_destroy(struct perf_event *event)
446{
447 struct drm_i915_private *i915 =
448 container_of(event->pmu, typeof(*i915), pmu.base);
449
450 drm_WARN_ON(&i915->drm, event->parent);
451
452 drm_dev_put(&i915->drm);
453}
454
455static int
456engine_event_status(struct intel_engine_cs *engine,
457 enum drm_i915_pmu_engine_sample sample)
458{
459 switch (sample) {
460 case I915_SAMPLE_BUSY:
461 case I915_SAMPLE_WAIT:
462 break;
463 case I915_SAMPLE_SEMA:
464 if (GRAPHICS_VER(engine->i915) < 6)
465 return -ENODEV;
466 break;
467 default:
468 return -ENOENT;
469 }
470
471 return 0;
472}
473
474static int
475config_status(struct drm_i915_private *i915, u64 config)
476{
477 struct intel_gt *gt = to_gt(i915);
478
479 switch (config) {
480 case I915_PMU_ACTUAL_FREQUENCY:
481 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
482 /* Requires a mutex for sampling! */
483 return -ENODEV;
484 fallthrough;
485 case I915_PMU_REQUESTED_FREQUENCY:
486 if (GRAPHICS_VER(i915) < 6)
487 return -ENODEV;
488 break;
489 case I915_PMU_INTERRUPTS:
490 break;
491 case I915_PMU_RC6_RESIDENCY:
492 if (!gt->rc6.supported)
493 return -ENODEV;
494 break;
495 case I915_PMU_SOFTWARE_GT_AWAKE_TIME:
496 break;
497 default:
498 return -ENOENT;
499 }
500
501 return 0;
502}
503
504static int engine_event_init(struct perf_event *event)
505{
506 struct drm_i915_private *i915 =
507 container_of(event->pmu, typeof(*i915), pmu.base);
508 struct intel_engine_cs *engine;
509
510 engine = intel_engine_lookup_user(i915, engine_event_class(event),
511 engine_event_instance(event));
512 if (!engine)
513 return -ENODEV;
514
515 return engine_event_status(engine, engine_event_sample(event));
516}
517
518static int i915_pmu_event_init(struct perf_event *event)
519{
520 struct drm_i915_private *i915 =
521 container_of(event->pmu, typeof(*i915), pmu.base);
522 struct i915_pmu *pmu = &i915->pmu;
523 int ret;
524
525 if (pmu->closed)
526 return -ENODEV;
527
528 if (event->attr.type != event->pmu->type)
529 return -ENOENT;
530
531 /* unsupported modes and filters */
532 if (event->attr.sample_period) /* no sampling */
533 return -EINVAL;
534
535 if (has_branch_stack(event))
536 return -EOPNOTSUPP;
537
538 if (event->cpu < 0)
539 return -EINVAL;
540
541 /* only allow running on one cpu at a time */
542 if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask))
543 return -EINVAL;
544
545 if (is_engine_event(event))
546 ret = engine_event_init(event);
547 else
548 ret = config_status(i915, event->attr.config);
549 if (ret)
550 return ret;
551
552 if (!event->parent) {
553 drm_dev_get(&i915->drm);
554 event->destroy = i915_pmu_event_destroy;
555 }
556
557 return 0;
558}
559
560static u64 __i915_pmu_event_read(struct perf_event *event)
561{
562 struct drm_i915_private *i915 =
563 container_of(event->pmu, typeof(*i915), pmu.base);
564 struct i915_pmu *pmu = &i915->pmu;
565 u64 val = 0;
566
567 if (is_engine_event(event)) {
568 u8 sample = engine_event_sample(event);
569 struct intel_engine_cs *engine;
570
571 engine = intel_engine_lookup_user(i915,
572 engine_event_class(event),
573 engine_event_instance(event));
574
575 if (drm_WARN_ON_ONCE(&i915->drm, !engine)) {
576 /* Do nothing */
577 } else if (sample == I915_SAMPLE_BUSY &&
578 intel_engine_supports_stats(engine)) {
579 ktime_t unused;
580
581 val = ktime_to_ns(intel_engine_get_busy_time(engine,
582 &unused));
583 } else {
584 val = engine->pmu.sample[sample].cur;
585 }
586 } else {
587 switch (event->attr.config) {
588 case I915_PMU_ACTUAL_FREQUENCY:
589 val =
590 div_u64(pmu->sample[__I915_SAMPLE_FREQ_ACT].cur,
591 USEC_PER_SEC /* to MHz */);
592 break;
593 case I915_PMU_REQUESTED_FREQUENCY:
594 val =
595 div_u64(pmu->sample[__I915_SAMPLE_FREQ_REQ].cur,
596 USEC_PER_SEC /* to MHz */);
597 break;
598 case I915_PMU_INTERRUPTS:
599 val = READ_ONCE(pmu->irq_count);
600 break;
601 case I915_PMU_RC6_RESIDENCY:
602 val = get_rc6(to_gt(i915));
603 break;
604 case I915_PMU_SOFTWARE_GT_AWAKE_TIME:
605 val = ktime_to_ns(intel_gt_get_awake_time(to_gt(i915)));
606 break;
607 }
608 }
609
610 return val;
611}
612
613static void i915_pmu_event_read(struct perf_event *event)
614{
615 struct drm_i915_private *i915 =
616 container_of(event->pmu, typeof(*i915), pmu.base);
617 struct hw_perf_event *hwc = &event->hw;
618 struct i915_pmu *pmu = &i915->pmu;
619 u64 prev, new;
620
621 if (pmu->closed) {
622 event->hw.state = PERF_HES_STOPPED;
623 return;
624 }
625again:
626 prev = local64_read(&hwc->prev_count);
627 new = __i915_pmu_event_read(event);
628
629 if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
630 goto again;
631
632 local64_add(new - prev, &event->count);
633}
634
635static void i915_pmu_enable(struct perf_event *event)
636{
637 struct drm_i915_private *i915 =
638 container_of(event->pmu, typeof(*i915), pmu.base);
639 struct i915_pmu *pmu = &i915->pmu;
640 unsigned long flags;
641 unsigned int bit;
642
643 bit = event_bit(event);
644 if (bit == -1)
645 goto update;
646
647 spin_lock_irqsave(&pmu->lock, flags);
648
649 /*
650 * Update the bitmask of enabled events and increment
651 * the event reference counter.
652 */
653 BUILD_BUG_ON(ARRAY_SIZE(pmu->enable_count) != I915_PMU_MASK_BITS);
654 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
655 GEM_BUG_ON(pmu->enable_count[bit] == ~0);
656
657 pmu->enable |= BIT_ULL(bit);
658 pmu->enable_count[bit]++;
659
660 /*
661 * Start the sampling timer if needed and not already enabled.
662 */
663 __i915_pmu_maybe_start_timer(pmu);
664
665 /*
666 * For per-engine events the bitmask and reference counting
667 * is stored per engine.
668 */
669 if (is_engine_event(event)) {
670 u8 sample = engine_event_sample(event);
671 struct intel_engine_cs *engine;
672
673 engine = intel_engine_lookup_user(i915,
674 engine_event_class(event),
675 engine_event_instance(event));
676
677 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
678 I915_ENGINE_SAMPLE_COUNT);
679 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
680 I915_ENGINE_SAMPLE_COUNT);
681 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
682 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
683 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
684
685 engine->pmu.enable |= BIT(sample);
686 engine->pmu.enable_count[sample]++;
687 }
688
689 spin_unlock_irqrestore(&pmu->lock, flags);
690
691update:
692 /*
693 * Store the current counter value so we can report the correct delta
694 * for all listeners. Even when the event was already enabled and has
695 * an existing non-zero value.
696 */
697 local64_set(&event->hw.prev_count, __i915_pmu_event_read(event));
698}
699
700static void i915_pmu_disable(struct perf_event *event)
701{
702 struct drm_i915_private *i915 =
703 container_of(event->pmu, typeof(*i915), pmu.base);
704 unsigned int bit = event_bit(event);
705 struct i915_pmu *pmu = &i915->pmu;
706 unsigned long flags;
707
708 if (bit == -1)
709 return;
710
711 spin_lock_irqsave(&pmu->lock, flags);
712
713 if (is_engine_event(event)) {
714 u8 sample = engine_event_sample(event);
715 struct intel_engine_cs *engine;
716
717 engine = intel_engine_lookup_user(i915,
718 engine_event_class(event),
719 engine_event_instance(event));
720
721 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
722 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
723 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
724
725 /*
726 * Decrement the reference count and clear the enabled
727 * bitmask when the last listener on an event goes away.
728 */
729 if (--engine->pmu.enable_count[sample] == 0)
730 engine->pmu.enable &= ~BIT(sample);
731 }
732
733 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
734 GEM_BUG_ON(pmu->enable_count[bit] == 0);
735 /*
736 * Decrement the reference count and clear the enabled
737 * bitmask when the last listener on an event goes away.
738 */
739 if (--pmu->enable_count[bit] == 0) {
740 pmu->enable &= ~BIT_ULL(bit);
741 pmu->timer_enabled &= pmu_needs_timer(pmu, true);
742 }
743
744 spin_unlock_irqrestore(&pmu->lock, flags);
745}
746
747static void i915_pmu_event_start(struct perf_event *event, int flags)
748{
749 struct drm_i915_private *i915 =
750 container_of(event->pmu, typeof(*i915), pmu.base);
751 struct i915_pmu *pmu = &i915->pmu;
752
753 if (pmu->closed)
754 return;
755
756 i915_pmu_enable(event);
757 event->hw.state = 0;
758}
759
760static void i915_pmu_event_stop(struct perf_event *event, int flags)
761{
762 if (flags & PERF_EF_UPDATE)
763 i915_pmu_event_read(event);
764 i915_pmu_disable(event);
765 event->hw.state = PERF_HES_STOPPED;
766}
767
768static int i915_pmu_event_add(struct perf_event *event, int flags)
769{
770 struct drm_i915_private *i915 =
771 container_of(event->pmu, typeof(*i915), pmu.base);
772 struct i915_pmu *pmu = &i915->pmu;
773
774 if (pmu->closed)
775 return -ENODEV;
776
777 if (flags & PERF_EF_START)
778 i915_pmu_event_start(event, flags);
779
780 return 0;
781}
782
783static void i915_pmu_event_del(struct perf_event *event, int flags)
784{
785 i915_pmu_event_stop(event, PERF_EF_UPDATE);
786}
787
788static int i915_pmu_event_event_idx(struct perf_event *event)
789{
790 return 0;
791}
792
793struct i915_str_attribute {
794 struct device_attribute attr;
795 const char *str;
796};
797
798static ssize_t i915_pmu_format_show(struct device *dev,
799 struct device_attribute *attr, char *buf)
800{
801 struct i915_str_attribute *eattr;
802
803 eattr = container_of(attr, struct i915_str_attribute, attr);
804 return sprintf(buf, "%s\n", eattr->str);
805}
806
807#define I915_PMU_FORMAT_ATTR(_name, _config) \
808 (&((struct i915_str_attribute[]) { \
809 { .attr = __ATTR(_name, 0444, i915_pmu_format_show, NULL), \
810 .str = _config, } \
811 })[0].attr.attr)
812
813static struct attribute *i915_pmu_format_attrs[] = {
814 I915_PMU_FORMAT_ATTR(i915_eventid, "config:0-20"),
815 NULL,
816};
817
818static const struct attribute_group i915_pmu_format_attr_group = {
819 .name = "format",
820 .attrs = i915_pmu_format_attrs,
821};
822
823struct i915_ext_attribute {
824 struct device_attribute attr;
825 unsigned long val;
826};
827
828static ssize_t i915_pmu_event_show(struct device *dev,
829 struct device_attribute *attr, char *buf)
830{
831 struct i915_ext_attribute *eattr;
832
833 eattr = container_of(attr, struct i915_ext_attribute, attr);
834 return sprintf(buf, "config=0x%lx\n", eattr->val);
835}
836
837static ssize_t cpumask_show(struct device *dev,
838 struct device_attribute *attr, char *buf)
839{
840 return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask);
841}
842
843static DEVICE_ATTR_RO(cpumask);
844
845static struct attribute *i915_cpumask_attrs[] = {
846 &dev_attr_cpumask.attr,
847 NULL,
848};
849
850static const struct attribute_group i915_pmu_cpumask_attr_group = {
851 .attrs = i915_cpumask_attrs,
852};
853
854#define __event(__config, __name, __unit) \
855{ \
856 .config = (__config), \
857 .name = (__name), \
858 .unit = (__unit), \
859}
860
861#define __engine_event(__sample, __name) \
862{ \
863 .sample = (__sample), \
864 .name = (__name), \
865}
866
867static struct i915_ext_attribute *
868add_i915_attr(struct i915_ext_attribute *attr, const char *name, u64 config)
869{
870 sysfs_attr_init(&attr->attr.attr);
871 attr->attr.attr.name = name;
872 attr->attr.attr.mode = 0444;
873 attr->attr.show = i915_pmu_event_show;
874 attr->val = config;
875
876 return ++attr;
877}
878
879static struct perf_pmu_events_attr *
880add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
881 const char *str)
882{
883 sysfs_attr_init(&attr->attr.attr);
884 attr->attr.attr.name = name;
885 attr->attr.attr.mode = 0444;
886 attr->attr.show = perf_event_sysfs_show;
887 attr->event_str = str;
888
889 return ++attr;
890}
891
892static struct attribute **
893create_event_attributes(struct i915_pmu *pmu)
894{
895 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
896 static const struct {
897 u64 config;
898 const char *name;
899 const char *unit;
900 } events[] = {
901 __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
902 __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"),
903 __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
904 __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
905 __event(I915_PMU_SOFTWARE_GT_AWAKE_TIME, "software-gt-awake-time", "ns"),
906 };
907 static const struct {
908 enum drm_i915_pmu_engine_sample sample;
909 char *name;
910 } engine_events[] = {
911 __engine_event(I915_SAMPLE_BUSY, "busy"),
912 __engine_event(I915_SAMPLE_SEMA, "sema"),
913 __engine_event(I915_SAMPLE_WAIT, "wait"),
914 };
915 unsigned int count = 0;
916 struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
917 struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
918 struct attribute **attr = NULL, **attr_iter;
919 struct intel_engine_cs *engine;
920 unsigned int i;
921
922 /* Count how many counters we will be exposing. */
923 for (i = 0; i < ARRAY_SIZE(events); i++) {
924 if (!config_status(i915, events[i].config))
925 count++;
926 }
927
928 for_each_uabi_engine(engine, i915) {
929 for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
930 if (!engine_event_status(engine,
931 engine_events[i].sample))
932 count++;
933 }
934 }
935
936 /* Allocate attribute objects and table. */
937 i915_attr = kcalloc(count, sizeof(*i915_attr), GFP_KERNEL);
938 if (!i915_attr)
939 goto err_alloc;
940
941 pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
942 if (!pmu_attr)
943 goto err_alloc;
944
945 /* Max one pointer of each attribute type plus a termination entry. */
946 attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
947 if (!attr)
948 goto err_alloc;
949
950 i915_iter = i915_attr;
951 pmu_iter = pmu_attr;
952 attr_iter = attr;
953
954 /* Initialize supported non-engine counters. */
955 for (i = 0; i < ARRAY_SIZE(events); i++) {
956 char *str;
957
958 if (config_status(i915, events[i].config))
959 continue;
960
961 str = kstrdup(events[i].name, GFP_KERNEL);
962 if (!str)
963 goto err;
964
965 *attr_iter++ = &i915_iter->attr.attr;
966 i915_iter = add_i915_attr(i915_iter, str, events[i].config);
967
968 if (events[i].unit) {
969 str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);
970 if (!str)
971 goto err;
972
973 *attr_iter++ = &pmu_iter->attr.attr;
974 pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);
975 }
976 }
977
978 /* Initialize supported engine counters. */
979 for_each_uabi_engine(engine, i915) {
980 for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
981 char *str;
982
983 if (engine_event_status(engine,
984 engine_events[i].sample))
985 continue;
986
987 str = kasprintf(GFP_KERNEL, "%s-%s",
988 engine->name, engine_events[i].name);
989 if (!str)
990 goto err;
991
992 *attr_iter++ = &i915_iter->attr.attr;
993 i915_iter =
994 add_i915_attr(i915_iter, str,
995 __I915_PMU_ENGINE(engine->uabi_class,
996 engine->uabi_instance,
997 engine_events[i].sample));
998
999 str = kasprintf(GFP_KERNEL, "%s-%s.unit",
1000 engine->name, engine_events[i].name);
1001 if (!str)
1002 goto err;
1003
1004 *attr_iter++ = &pmu_iter->attr.attr;
1005 pmu_iter = add_pmu_attr(pmu_iter, str, "ns");
1006 }
1007 }
1008
1009 pmu->i915_attr = i915_attr;
1010 pmu->pmu_attr = pmu_attr;
1011
1012 return attr;
1013
1014err:;
1015 for (attr_iter = attr; *attr_iter; attr_iter++)
1016 kfree((*attr_iter)->name);
1017
1018err_alloc:
1019 kfree(attr);
1020 kfree(i915_attr);
1021 kfree(pmu_attr);
1022
1023 return NULL;
1024}
1025
1026static void free_event_attributes(struct i915_pmu *pmu)
1027{
1028 struct attribute **attr_iter = pmu->events_attr_group.attrs;
1029
1030 for (; *attr_iter; attr_iter++)
1031 kfree((*attr_iter)->name);
1032
1033 kfree(pmu->events_attr_group.attrs);
1034 kfree(pmu->i915_attr);
1035 kfree(pmu->pmu_attr);
1036
1037 pmu->events_attr_group.attrs = NULL;
1038 pmu->i915_attr = NULL;
1039 pmu->pmu_attr = NULL;
1040}
1041
1042static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
1043{
1044 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1045
1046 GEM_BUG_ON(!pmu->base.event_init);
1047
1048 /* Select the first online CPU as a designated reader. */
1049 if (cpumask_empty(&i915_pmu_cpumask))
1050 cpumask_set_cpu(cpu, &i915_pmu_cpumask);
1051
1052 return 0;
1053}
1054
1055static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
1056{
1057 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1058 unsigned int target = i915_pmu_target_cpu;
1059
1060 GEM_BUG_ON(!pmu->base.event_init);
1061
1062 /*
1063 * Unregistering an instance generates a CPU offline event which we must
1064 * ignore to avoid incorrectly modifying the shared i915_pmu_cpumask.
1065 */
1066 if (pmu->closed)
1067 return 0;
1068
1069 if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) {
1070 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
1071
1072 /* Migrate events if there is a valid target */
1073 if (target < nr_cpu_ids) {
1074 cpumask_set_cpu(target, &i915_pmu_cpumask);
1075 i915_pmu_target_cpu = target;
1076 }
1077 }
1078
1079 if (target < nr_cpu_ids && target != pmu->cpuhp.cpu) {
1080 perf_pmu_migrate_context(&pmu->base, cpu, target);
1081 pmu->cpuhp.cpu = target;
1082 }
1083
1084 return 0;
1085}
1086
1087static enum cpuhp_state cpuhp_slot = CPUHP_INVALID;
1088
1089int i915_pmu_init(void)
1090{
1091 int ret;
1092
1093 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
1094 "perf/x86/intel/i915:online",
1095 i915_pmu_cpu_online,
1096 i915_pmu_cpu_offline);
1097 if (ret < 0)
1098 pr_notice("Failed to setup cpuhp state for i915 PMU! (%d)\n",
1099 ret);
1100 else
1101 cpuhp_slot = ret;
1102
1103 return 0;
1104}
1105
1106void i915_pmu_exit(void)
1107{
1108 if (cpuhp_slot != CPUHP_INVALID)
1109 cpuhp_remove_multi_state(cpuhp_slot);
1110}
1111
1112static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
1113{
1114 if (cpuhp_slot == CPUHP_INVALID)
1115 return -EINVAL;
1116
1117 return cpuhp_state_add_instance(cpuhp_slot, &pmu->cpuhp.node);
1118}
1119
1120static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
1121{
1122 cpuhp_state_remove_instance(cpuhp_slot, &pmu->cpuhp.node);
1123}
1124
1125static bool is_igp(struct drm_i915_private *i915)
1126{
1127 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
1128
1129 /* IGP is 0000:00:02.0 */
1130 return pci_domain_nr(pdev->bus) == 0 &&
1131 pdev->bus->number == 0 &&
1132 PCI_SLOT(pdev->devfn) == 2 &&
1133 PCI_FUNC(pdev->devfn) == 0;
1134}
1135
1136void i915_pmu_register(struct drm_i915_private *i915)
1137{
1138 struct i915_pmu *pmu = &i915->pmu;
1139 const struct attribute_group *attr_groups[] = {
1140 &i915_pmu_format_attr_group,
1141 &pmu->events_attr_group,
1142 &i915_pmu_cpumask_attr_group,
1143 NULL
1144 };
1145
1146 int ret = -ENOMEM;
1147
1148 if (GRAPHICS_VER(i915) <= 2) {
1149 drm_info(&i915->drm, "PMU not supported for this GPU.");
1150 return;
1151 }
1152
1153 spin_lock_init(&pmu->lock);
1154 hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1155 pmu->timer.function = i915_sample;
1156 pmu->cpuhp.cpu = -1;
1157 init_rc6(pmu);
1158
1159 if (!is_igp(i915)) {
1160 pmu->name = kasprintf(GFP_KERNEL,
1161 "i915_%s",
1162 dev_name(i915->drm.dev));
1163 if (pmu->name) {
1164 /* tools/perf reserves colons as special. */
1165 strreplace((char *)pmu->name, ':', '_');
1166 }
1167 } else {
1168 pmu->name = "i915";
1169 }
1170 if (!pmu->name)
1171 goto err;
1172
1173 pmu->events_attr_group.name = "events";
1174 pmu->events_attr_group.attrs = create_event_attributes(pmu);
1175 if (!pmu->events_attr_group.attrs)
1176 goto err_name;
1177
1178 pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
1179 GFP_KERNEL);
1180 if (!pmu->base.attr_groups)
1181 goto err_attr;
1182
1183 pmu->base.module = THIS_MODULE;
1184 pmu->base.task_ctx_nr = perf_invalid_context;
1185 pmu->base.event_init = i915_pmu_event_init;
1186 pmu->base.add = i915_pmu_event_add;
1187 pmu->base.del = i915_pmu_event_del;
1188 pmu->base.start = i915_pmu_event_start;
1189 pmu->base.stop = i915_pmu_event_stop;
1190 pmu->base.read = i915_pmu_event_read;
1191 pmu->base.event_idx = i915_pmu_event_event_idx;
1192
1193 ret = perf_pmu_register(&pmu->base, pmu->name, -1);
1194 if (ret)
1195 goto err_groups;
1196
1197 ret = i915_pmu_register_cpuhp_state(pmu);
1198 if (ret)
1199 goto err_unreg;
1200
1201 return;
1202
1203err_unreg:
1204 perf_pmu_unregister(&pmu->base);
1205err_groups:
1206 kfree(pmu->base.attr_groups);
1207err_attr:
1208 pmu->base.event_init = NULL;
1209 free_event_attributes(pmu);
1210err_name:
1211 if (!is_igp(i915))
1212 kfree(pmu->name);
1213err:
1214 drm_notice(&i915->drm, "Failed to register PMU!\n");
1215}
1216
1217void i915_pmu_unregister(struct drm_i915_private *i915)
1218{
1219 struct i915_pmu *pmu = &i915->pmu;
1220
1221 if (!pmu->base.event_init)
1222 return;
1223
1224 /*
1225 * "Disconnect" the PMU callbacks - since all are atomic synchronize_rcu
1226 * ensures all currently executing ones will have exited before we
1227 * proceed with unregistration.
1228 */
1229 pmu->closed = true;
1230 synchronize_rcu();
1231
1232 hrtimer_cancel(&pmu->timer);
1233
1234 i915_pmu_unregister_cpuhp_state(pmu);
1235
1236 perf_pmu_unregister(&pmu->base);
1237 pmu->base.event_init = NULL;
1238 kfree(pmu->base.attr_groups);
1239 if (!is_igp(i915))
1240 kfree(pmu->name);
1241 free_event_attributes(pmu);
1242}