1/*
   2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice (including the next
  12 * paragraph) shall be included in all copies or substantial portions of the
  13 * Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21 * SOFTWARE.
  22 *
  23 * Authors:
  24 *    Ke Yu
  25 *    Kevin Tian <kevin.tian@intel.com>
  26 *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  27 *
  28 * Contributors:
  29 *    Min He <min.he@intel.com>
  30 *    Ping Gao <ping.a.gao@intel.com>
  31 *    Tina Zhang <tina.zhang@intel.com>
  32 *    Yulei Zhang <yulei.zhang@intel.com>
  33 *    Zhi Wang <zhi.a.wang@intel.com>
  34 *
  35 */
  36
  37#include <linux/slab.h>
  38
  39#include "i915_drv.h"
  40#include "i915_reg.h"
  41#include "gt/intel_engine_regs.h"
  42#include "gt/intel_gpu_commands.h"
  43#include "gt/intel_gt_regs.h"
  44#include "gt/intel_lrc.h"
  45#include "gt/intel_ring.h"
  46#include "gt/intel_gt_requests.h"
  47#include "gt/shmem_utils.h"
  48#include "gvt.h"
  49#include "i915_pvinfo.h"
  50#include "trace.h"
  51
  52#include "gem/i915_gem_context.h"
  53#include "gem/i915_gem_pm.h"
  54#include "gt/intel_context.h"
  55
  56#define INVALID_OP    (~0U)
  57
  58#define OP_LEN_MI           9
  59#define OP_LEN_2D           10
  60#define OP_LEN_3D_MEDIA     16
  61#define OP_LEN_MFX_VC       16
  62#define OP_LEN_VEBOX	    16
  63
  64#define CMD_TYPE(cmd)	(((cmd) >> 29) & 7)
  65
  66struct sub_op_bits {
  67	int hi;
  68	int low;
  69};
  70struct decode_info {
  71	const char *name;
  72	int op_len;
  73	int nr_sub_op;
  74	const struct sub_op_bits *sub_op;
  75};
  76
  77#define   MAX_CMD_BUDGET			0x7fffffff
  78#define   MI_WAIT_FOR_PLANE_C_FLIP_PENDING      (1<<15)
  79#define   MI_WAIT_FOR_PLANE_B_FLIP_PENDING      (1<<9)
  80#define   MI_WAIT_FOR_PLANE_A_FLIP_PENDING      (1<<1)
  81
  82#define   MI_WAIT_FOR_SPRITE_C_FLIP_PENDING      (1<<20)
  83#define   MI_WAIT_FOR_SPRITE_B_FLIP_PENDING      (1<<10)
  84#define   MI_WAIT_FOR_SPRITE_A_FLIP_PENDING      (1<<2)
  85
  86/* Render Command Map */
  87
  88/* MI_* command Opcode (28:23) */
  89#define OP_MI_NOOP                          0x0
  90#define OP_MI_SET_PREDICATE                 0x1  /* HSW+ */
  91#define OP_MI_USER_INTERRUPT                0x2
  92#define OP_MI_WAIT_FOR_EVENT                0x3
  93#define OP_MI_FLUSH                         0x4
  94#define OP_MI_ARB_CHECK                     0x5
  95#define OP_MI_RS_CONTROL                    0x6  /* HSW+ */
  96#define OP_MI_REPORT_HEAD                   0x7
  97#define OP_MI_ARB_ON_OFF                    0x8
  98#define OP_MI_URB_ATOMIC_ALLOC              0x9  /* HSW+ */
  99#define OP_MI_BATCH_BUFFER_END              0xA
 100#define OP_MI_SUSPEND_FLUSH                 0xB
 101#define OP_MI_PREDICATE                     0xC  /* IVB+ */
 102#define OP_MI_TOPOLOGY_FILTER               0xD  /* IVB+ */
 103#define OP_MI_SET_APPID                     0xE  /* IVB+ */
 104#define OP_MI_RS_CONTEXT                    0xF  /* HSW+ */
 105#define OP_MI_LOAD_SCAN_LINES_INCL          0x12 /* HSW+ */
 106#define OP_MI_DISPLAY_FLIP                  0x14
 107#define OP_MI_SEMAPHORE_MBOX                0x16
 108#define OP_MI_SET_CONTEXT                   0x18
 109#define OP_MI_MATH                          0x1A
 110#define OP_MI_URB_CLEAR                     0x19
 111#define OP_MI_SEMAPHORE_SIGNAL		    0x1B  /* BDW+ */
 112#define OP_MI_SEMAPHORE_WAIT		    0x1C  /* BDW+ */
 113
 114#define OP_MI_STORE_DATA_IMM                0x20
 115#define OP_MI_STORE_DATA_INDEX              0x21
 116#define OP_MI_LOAD_REGISTER_IMM             0x22
 117#define OP_MI_UPDATE_GTT                    0x23
 118#define OP_MI_STORE_REGISTER_MEM            0x24
 119#define OP_MI_FLUSH_DW                      0x26
 120#define OP_MI_CLFLUSH                       0x27
 121#define OP_MI_REPORT_PERF_COUNT             0x28
 122#define OP_MI_LOAD_REGISTER_MEM             0x29  /* HSW+ */
 123#define OP_MI_LOAD_REGISTER_REG             0x2A  /* HSW+ */
 124#define OP_MI_RS_STORE_DATA_IMM             0x2B  /* HSW+ */
 125#define OP_MI_LOAD_URB_MEM                  0x2C  /* HSW+ */
 126#define OP_MI_STORE_URM_MEM                 0x2D  /* HSW+ */
 127#define OP_MI_2E			    0x2E  /* BDW+ */
 128#define OP_MI_2F			    0x2F  /* BDW+ */
 129#define OP_MI_BATCH_BUFFER_START            0x31
 130
 131/* Bit definition for dword 0 */
 132#define _CMDBIT_BB_START_IN_PPGTT	(1UL << 8)
 133
 134#define OP_MI_CONDITIONAL_BATCH_BUFFER_END  0x36
 135
 136#define BATCH_BUFFER_ADDR_MASK ((1UL << 32) - (1U << 2))
 137#define BATCH_BUFFER_ADDR_HIGH_MASK ((1UL << 16) - (1U))
 138#define BATCH_BUFFER_ADR_SPACE_BIT(x)	(((x) >> 8) & 1U)
 139#define BATCH_BUFFER_2ND_LEVEL_BIT(x)   ((x) >> 22 & 1U)
 140
 141/* 2D command: Opcode (28:22) */
 142#define OP_2D(x)    ((2<<7) | x)
 143
 144#define OP_XY_SETUP_BLT                             OP_2D(0x1)
 145#define OP_XY_SETUP_CLIP_BLT                        OP_2D(0x3)
 146#define OP_XY_SETUP_MONO_PATTERN_SL_BLT             OP_2D(0x11)
 147#define OP_XY_PIXEL_BLT                             OP_2D(0x24)
 148#define OP_XY_SCANLINES_BLT                         OP_2D(0x25)
 149#define OP_XY_TEXT_BLT                              OP_2D(0x26)
 150#define OP_XY_TEXT_IMMEDIATE_BLT                    OP_2D(0x31)
 151#define OP_XY_COLOR_BLT                             OP_2D(0x50)
 152#define OP_XY_PAT_BLT                               OP_2D(0x51)
 153#define OP_XY_MONO_PAT_BLT                          OP_2D(0x52)
 154#define OP_XY_SRC_COPY_BLT                          OP_2D(0x53)
 155#define OP_XY_MONO_SRC_COPY_BLT                     OP_2D(0x54)
 156#define OP_XY_FULL_BLT                              OP_2D(0x55)
 157#define OP_XY_FULL_MONO_SRC_BLT                     OP_2D(0x56)
 158#define OP_XY_FULL_MONO_PATTERN_BLT                 OP_2D(0x57)
 159#define OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT        OP_2D(0x58)
 160#define OP_XY_MONO_PAT_FIXED_BLT                    OP_2D(0x59)
 161#define OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT           OP_2D(0x71)
 162#define OP_XY_PAT_BLT_IMMEDIATE                     OP_2D(0x72)
 163#define OP_XY_SRC_COPY_CHROMA_BLT                   OP_2D(0x73)
 164#define OP_XY_FULL_IMMEDIATE_PATTERN_BLT            OP_2D(0x74)
 165#define OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT   OP_2D(0x75)
 166#define OP_XY_PAT_CHROMA_BLT                        OP_2D(0x76)
 167#define OP_XY_PAT_CHROMA_BLT_IMMEDIATE              OP_2D(0x77)
 168
 169/* 3D/Media Command: Pipeline Type(28:27) Opcode(26:24) Sub Opcode(23:16) */
 170#define OP_3D_MEDIA(sub_type, opcode, sub_opcode) \
 171	((3 << 13) | ((sub_type) << 11) | ((opcode) << 8) | (sub_opcode))
 172
 173#define OP_STATE_PREFETCH                       OP_3D_MEDIA(0x0, 0x0, 0x03)
 174
 175#define OP_STATE_BASE_ADDRESS                   OP_3D_MEDIA(0x0, 0x1, 0x01)
 176#define OP_STATE_SIP                            OP_3D_MEDIA(0x0, 0x1, 0x02)
 177#define OP_3D_MEDIA_0_1_4			OP_3D_MEDIA(0x0, 0x1, 0x04)
 178#define OP_SWTESS_BASE_ADDRESS			OP_3D_MEDIA(0x0, 0x1, 0x03)
 179
 180#define OP_3DSTATE_VF_STATISTICS_GM45           OP_3D_MEDIA(0x1, 0x0, 0x0B)
 181
 182#define OP_PIPELINE_SELECT                      OP_3D_MEDIA(0x1, 0x1, 0x04)
 183
 184#define OP_MEDIA_VFE_STATE                      OP_3D_MEDIA(0x2, 0x0, 0x0)
 185#define OP_MEDIA_CURBE_LOAD                     OP_3D_MEDIA(0x2, 0x0, 0x1)
 186#define OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD      OP_3D_MEDIA(0x2, 0x0, 0x2)
 187#define OP_MEDIA_GATEWAY_STATE                  OP_3D_MEDIA(0x2, 0x0, 0x3)
 188#define OP_MEDIA_STATE_FLUSH                    OP_3D_MEDIA(0x2, 0x0, 0x4)
 189#define OP_MEDIA_POOL_STATE                     OP_3D_MEDIA(0x2, 0x0, 0x5)
 190
 191#define OP_MEDIA_OBJECT                         OP_3D_MEDIA(0x2, 0x1, 0x0)
 192#define OP_MEDIA_OBJECT_PRT                     OP_3D_MEDIA(0x2, 0x1, 0x2)
 193#define OP_MEDIA_OBJECT_WALKER                  OP_3D_MEDIA(0x2, 0x1, 0x3)
 194#define OP_GPGPU_WALKER                         OP_3D_MEDIA(0x2, 0x1, 0x5)
 195
 196#define OP_3DSTATE_CLEAR_PARAMS                 OP_3D_MEDIA(0x3, 0x0, 0x04) /* IVB+ */
 197#define OP_3DSTATE_DEPTH_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x05) /* IVB+ */
 198#define OP_3DSTATE_STENCIL_BUFFER               OP_3D_MEDIA(0x3, 0x0, 0x06) /* IVB+ */
 199#define OP_3DSTATE_HIER_DEPTH_BUFFER            OP_3D_MEDIA(0x3, 0x0, 0x07) /* IVB+ */
 200#define OP_3DSTATE_VERTEX_BUFFERS               OP_3D_MEDIA(0x3, 0x0, 0x08)
 201#define OP_3DSTATE_VERTEX_ELEMENTS              OP_3D_MEDIA(0x3, 0x0, 0x09)
 202#define OP_3DSTATE_INDEX_BUFFER                 OP_3D_MEDIA(0x3, 0x0, 0x0A)
 203#define OP_3DSTATE_VF_STATISTICS                OP_3D_MEDIA(0x3, 0x0, 0x0B)
 204#define OP_3DSTATE_VF                           OP_3D_MEDIA(0x3, 0x0, 0x0C)  /* HSW+ */
 205#define OP_3DSTATE_CC_STATE_POINTERS            OP_3D_MEDIA(0x3, 0x0, 0x0E)
 206#define OP_3DSTATE_SCISSOR_STATE_POINTERS       OP_3D_MEDIA(0x3, 0x0, 0x0F)
 207#define OP_3DSTATE_VS                           OP_3D_MEDIA(0x3, 0x0, 0x10)
 208#define OP_3DSTATE_GS                           OP_3D_MEDIA(0x3, 0x0, 0x11)
 209#define OP_3DSTATE_CLIP                         OP_3D_MEDIA(0x3, 0x0, 0x12)
 210#define OP_3DSTATE_SF                           OP_3D_MEDIA(0x3, 0x0, 0x13)
 211#define OP_3DSTATE_WM                           OP_3D_MEDIA(0x3, 0x0, 0x14)
 212#define OP_3DSTATE_CONSTANT_VS                  OP_3D_MEDIA(0x3, 0x0, 0x15)
 213#define OP_3DSTATE_CONSTANT_GS                  OP_3D_MEDIA(0x3, 0x0, 0x16)
 214#define OP_3DSTATE_CONSTANT_PS                  OP_3D_MEDIA(0x3, 0x0, 0x17)
 215#define OP_3DSTATE_SAMPLE_MASK                  OP_3D_MEDIA(0x3, 0x0, 0x18)
 216#define OP_3DSTATE_CONSTANT_HS                  OP_3D_MEDIA(0x3, 0x0, 0x19) /* IVB+ */
 217#define OP_3DSTATE_CONSTANT_DS                  OP_3D_MEDIA(0x3, 0x0, 0x1A) /* IVB+ */
 218#define OP_3DSTATE_HS                           OP_3D_MEDIA(0x3, 0x0, 0x1B) /* IVB+ */
 219#define OP_3DSTATE_TE                           OP_3D_MEDIA(0x3, 0x0, 0x1C) /* IVB+ */
 220#define OP_3DSTATE_DS                           OP_3D_MEDIA(0x3, 0x0, 0x1D) /* IVB+ */
 221#define OP_3DSTATE_STREAMOUT                    OP_3D_MEDIA(0x3, 0x0, 0x1E) /* IVB+ */
 222#define OP_3DSTATE_SBE                          OP_3D_MEDIA(0x3, 0x0, 0x1F) /* IVB+ */
 223#define OP_3DSTATE_PS                           OP_3D_MEDIA(0x3, 0x0, 0x20) /* IVB+ */
 224#define OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP OP_3D_MEDIA(0x3, 0x0, 0x21) /* IVB+ */
 225#define OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC   OP_3D_MEDIA(0x3, 0x0, 0x23) /* IVB+ */
 226#define OP_3DSTATE_BLEND_STATE_POINTERS         OP_3D_MEDIA(0x3, 0x0, 0x24) /* IVB+ */
 227#define OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS OP_3D_MEDIA(0x3, 0x0, 0x25) /* IVB+ */
 228#define OP_3DSTATE_BINDING_TABLE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x26) /* IVB+ */
 229#define OP_3DSTATE_BINDING_TABLE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x27) /* IVB+ */
 230#define OP_3DSTATE_BINDING_TABLE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x28) /* IVB+ */
 231#define OP_3DSTATE_BINDING_TABLE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x29) /* IVB+ */
 232#define OP_3DSTATE_BINDING_TABLE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2A) /* IVB+ */
 233#define OP_3DSTATE_SAMPLER_STATE_POINTERS_VS    OP_3D_MEDIA(0x3, 0x0, 0x2B) /* IVB+ */
 234#define OP_3DSTATE_SAMPLER_STATE_POINTERS_HS    OP_3D_MEDIA(0x3, 0x0, 0x2C) /* IVB+ */
 235#define OP_3DSTATE_SAMPLER_STATE_POINTERS_DS    OP_3D_MEDIA(0x3, 0x0, 0x2D) /* IVB+ */
 236#define OP_3DSTATE_SAMPLER_STATE_POINTERS_GS    OP_3D_MEDIA(0x3, 0x0, 0x2E) /* IVB+ */
 237#define OP_3DSTATE_SAMPLER_STATE_POINTERS_PS    OP_3D_MEDIA(0x3, 0x0, 0x2F) /* IVB+ */
 238#define OP_3DSTATE_URB_VS                       OP_3D_MEDIA(0x3, 0x0, 0x30) /* IVB+ */
 239#define OP_3DSTATE_URB_HS                       OP_3D_MEDIA(0x3, 0x0, 0x31) /* IVB+ */
 240#define OP_3DSTATE_URB_DS                       OP_3D_MEDIA(0x3, 0x0, 0x32) /* IVB+ */
 241#define OP_3DSTATE_URB_GS                       OP_3D_MEDIA(0x3, 0x0, 0x33) /* IVB+ */
 242#define OP_3DSTATE_GATHER_CONSTANT_VS           OP_3D_MEDIA(0x3, 0x0, 0x34) /* HSW+ */
 243#define OP_3DSTATE_GATHER_CONSTANT_GS           OP_3D_MEDIA(0x3, 0x0, 0x35) /* HSW+ */
 244#define OP_3DSTATE_GATHER_CONSTANT_HS           OP_3D_MEDIA(0x3, 0x0, 0x36) /* HSW+ */
 245#define OP_3DSTATE_GATHER_CONSTANT_DS           OP_3D_MEDIA(0x3, 0x0, 0x37) /* HSW+ */
 246#define OP_3DSTATE_GATHER_CONSTANT_PS           OP_3D_MEDIA(0x3, 0x0, 0x38) /* HSW+ */
 247#define OP_3DSTATE_DX9_CONSTANTF_VS             OP_3D_MEDIA(0x3, 0x0, 0x39) /* HSW+ */
 248#define OP_3DSTATE_DX9_CONSTANTF_PS             OP_3D_MEDIA(0x3, 0x0, 0x3A) /* HSW+ */
 249#define OP_3DSTATE_DX9_CONSTANTI_VS             OP_3D_MEDIA(0x3, 0x0, 0x3B) /* HSW+ */
 250#define OP_3DSTATE_DX9_CONSTANTI_PS             OP_3D_MEDIA(0x3, 0x0, 0x3C) /* HSW+ */
 251#define OP_3DSTATE_DX9_CONSTANTB_VS             OP_3D_MEDIA(0x3, 0x0, 0x3D) /* HSW+ */
 252#define OP_3DSTATE_DX9_CONSTANTB_PS             OP_3D_MEDIA(0x3, 0x0, 0x3E) /* HSW+ */
 253#define OP_3DSTATE_DX9_LOCAL_VALID_VS           OP_3D_MEDIA(0x3, 0x0, 0x3F) /* HSW+ */
 254#define OP_3DSTATE_DX9_LOCAL_VALID_PS           OP_3D_MEDIA(0x3, 0x0, 0x40) /* HSW+ */
 255#define OP_3DSTATE_DX9_GENERATE_ACTIVE_VS       OP_3D_MEDIA(0x3, 0x0, 0x41) /* HSW+ */
 256#define OP_3DSTATE_DX9_GENERATE_ACTIVE_PS       OP_3D_MEDIA(0x3, 0x0, 0x42) /* HSW+ */
 257#define OP_3DSTATE_BINDING_TABLE_EDIT_VS        OP_3D_MEDIA(0x3, 0x0, 0x43) /* HSW+ */
 258#define OP_3DSTATE_BINDING_TABLE_EDIT_GS        OP_3D_MEDIA(0x3, 0x0, 0x44) /* HSW+ */
 259#define OP_3DSTATE_BINDING_TABLE_EDIT_HS        OP_3D_MEDIA(0x3, 0x0, 0x45) /* HSW+ */
 260#define OP_3DSTATE_BINDING_TABLE_EDIT_DS        OP_3D_MEDIA(0x3, 0x0, 0x46) /* HSW+ */
 261#define OP_3DSTATE_BINDING_TABLE_EDIT_PS        OP_3D_MEDIA(0x3, 0x0, 0x47) /* HSW+ */
 262
 263#define OP_3DSTATE_VF_INSTANCING 		OP_3D_MEDIA(0x3, 0x0, 0x49) /* BDW+ */
 264#define OP_3DSTATE_VF_SGVS  			OP_3D_MEDIA(0x3, 0x0, 0x4A) /* BDW+ */
 265#define OP_3DSTATE_VF_TOPOLOGY   		OP_3D_MEDIA(0x3, 0x0, 0x4B) /* BDW+ */
 266#define OP_3DSTATE_WM_CHROMAKEY   		OP_3D_MEDIA(0x3, 0x0, 0x4C) /* BDW+ */
 267#define OP_3DSTATE_PS_BLEND   			OP_3D_MEDIA(0x3, 0x0, 0x4D) /* BDW+ */
 268#define OP_3DSTATE_WM_DEPTH_STENCIL   		OP_3D_MEDIA(0x3, 0x0, 0x4E) /* BDW+ */
 269#define OP_3DSTATE_PS_EXTRA   			OP_3D_MEDIA(0x3, 0x0, 0x4F) /* BDW+ */
 270#define OP_3DSTATE_RASTER   			OP_3D_MEDIA(0x3, 0x0, 0x50) /* BDW+ */
 271#define OP_3DSTATE_SBE_SWIZ   			OP_3D_MEDIA(0x3, 0x0, 0x51) /* BDW+ */
 272#define OP_3DSTATE_WM_HZ_OP   			OP_3D_MEDIA(0x3, 0x0, 0x52) /* BDW+ */
 273#define OP_3DSTATE_COMPONENT_PACKING		OP_3D_MEDIA(0x3, 0x0, 0x55) /* SKL+ */
 274
 275#define OP_3DSTATE_DRAWING_RECTANGLE            OP_3D_MEDIA(0x3, 0x1, 0x00)
 276#define OP_3DSTATE_SAMPLER_PALETTE_LOAD0        OP_3D_MEDIA(0x3, 0x1, 0x02)
 277#define OP_3DSTATE_CHROMA_KEY                   OP_3D_MEDIA(0x3, 0x1, 0x04)
 278#define OP_SNB_3DSTATE_DEPTH_BUFFER             OP_3D_MEDIA(0x3, 0x1, 0x05)
 279#define OP_3DSTATE_POLY_STIPPLE_OFFSET          OP_3D_MEDIA(0x3, 0x1, 0x06)
 280#define OP_3DSTATE_POLY_STIPPLE_PATTERN         OP_3D_MEDIA(0x3, 0x1, 0x07)
 281#define OP_3DSTATE_LINE_STIPPLE                 OP_3D_MEDIA(0x3, 0x1, 0x08)
 282#define OP_3DSTATE_AA_LINE_PARAMS               OP_3D_MEDIA(0x3, 0x1, 0x0A)
 283#define OP_3DSTATE_GS_SVB_INDEX                 OP_3D_MEDIA(0x3, 0x1, 0x0B)
 284#define OP_3DSTATE_SAMPLER_PALETTE_LOAD1        OP_3D_MEDIA(0x3, 0x1, 0x0C)
 285#define OP_3DSTATE_MULTISAMPLE_BDW		OP_3D_MEDIA(0x3, 0x0, 0x0D)
 286#define OP_SNB_3DSTATE_STENCIL_BUFFER           OP_3D_MEDIA(0x3, 0x1, 0x0E)
 287#define OP_SNB_3DSTATE_HIER_DEPTH_BUFFER        OP_3D_MEDIA(0x3, 0x1, 0x0F)
 288#define OP_SNB_3DSTATE_CLEAR_PARAMS             OP_3D_MEDIA(0x3, 0x1, 0x10)
 289#define OP_3DSTATE_MONOFILTER_SIZE              OP_3D_MEDIA(0x3, 0x1, 0x11)
 290#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS       OP_3D_MEDIA(0x3, 0x1, 0x12) /* IVB+ */
 291#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS       OP_3D_MEDIA(0x3, 0x1, 0x13) /* IVB+ */
 292#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS       OP_3D_MEDIA(0x3, 0x1, 0x14) /* IVB+ */
 293#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS       OP_3D_MEDIA(0x3, 0x1, 0x15) /* IVB+ */
 294#define OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS       OP_3D_MEDIA(0x3, 0x1, 0x16) /* IVB+ */
 295#define OP_3DSTATE_SO_DECL_LIST                 OP_3D_MEDIA(0x3, 0x1, 0x17)
 296#define OP_3DSTATE_SO_BUFFER                    OP_3D_MEDIA(0x3, 0x1, 0x18)
 297#define OP_3DSTATE_BINDING_TABLE_POOL_ALLOC     OP_3D_MEDIA(0x3, 0x1, 0x19) /* HSW+ */
 298#define OP_3DSTATE_GATHER_POOL_ALLOC            OP_3D_MEDIA(0x3, 0x1, 0x1A) /* HSW+ */
 299#define OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC OP_3D_MEDIA(0x3, 0x1, 0x1B) /* HSW+ */
 300#define OP_3DSTATE_SAMPLE_PATTERN               OP_3D_MEDIA(0x3, 0x1, 0x1C)
 301#define OP_PIPE_CONTROL                         OP_3D_MEDIA(0x3, 0x2, 0x00)
 302#define OP_3DPRIMITIVE                          OP_3D_MEDIA(0x3, 0x3, 0x00)
 303
 304/* VCCP Command Parser */
 305
 306/*
 307 * Below MFX and VBE cmd definition is from vaapi intel driver project (BSD License)
 308 * git://anongit.freedesktop.org/vaapi/intel-driver
 309 * src/i965_defines.h
 310 *
 311 */
 312
 313#define OP_MFX(pipeline, op, sub_opa, sub_opb)     \
 314	(3 << 13 | \
 315	 (pipeline) << 11 | \
 316	 (op) << 8 | \
 317	 (sub_opa) << 5 | \
 318	 (sub_opb))
 319
 320#define OP_MFX_PIPE_MODE_SELECT                    OP_MFX(2, 0, 0, 0)  /* ALL */
 321#define OP_MFX_SURFACE_STATE                       OP_MFX(2, 0, 0, 1)  /* ALL */
 322#define OP_MFX_PIPE_BUF_ADDR_STATE                 OP_MFX(2, 0, 0, 2)  /* ALL */
 323#define OP_MFX_IND_OBJ_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 3)  /* ALL */
 324#define OP_MFX_BSP_BUF_BASE_ADDR_STATE             OP_MFX(2, 0, 0, 4)  /* ALL */
 325#define OP_2_0_0_5                                 OP_MFX(2, 0, 0, 5)  /* ALL */
 326#define OP_MFX_STATE_POINTER                       OP_MFX(2, 0, 0, 6)  /* ALL */
 327#define OP_MFX_QM_STATE                            OP_MFX(2, 0, 0, 7)  /* IVB+ */
 328#define OP_MFX_FQM_STATE                           OP_MFX(2, 0, 0, 8)  /* IVB+ */
 329#define OP_MFX_PAK_INSERT_OBJECT                   OP_MFX(2, 0, 2, 8)  /* IVB+ */
 330#define OP_MFX_STITCH_OBJECT                       OP_MFX(2, 0, 2, 0xA)  /* IVB+ */
 331
 332#define OP_MFD_IT_OBJECT                           OP_MFX(2, 0, 1, 9) /* ALL */
 333
 334#define OP_MFX_WAIT                                OP_MFX(1, 0, 0, 0) /* IVB+ */
 335#define OP_MFX_AVC_IMG_STATE                       OP_MFX(2, 1, 0, 0) /* ALL */
 336#define OP_MFX_AVC_QM_STATE                        OP_MFX(2, 1, 0, 1) /* ALL */
 337#define OP_MFX_AVC_DIRECTMODE_STATE                OP_MFX(2, 1, 0, 2) /* ALL */
 338#define OP_MFX_AVC_SLICE_STATE                     OP_MFX(2, 1, 0, 3) /* ALL */
 339#define OP_MFX_AVC_REF_IDX_STATE                   OP_MFX(2, 1, 0, 4) /* ALL */
 340#define OP_MFX_AVC_WEIGHTOFFSET_STATE              OP_MFX(2, 1, 0, 5) /* ALL */
 341#define OP_MFD_AVC_PICID_STATE                     OP_MFX(2, 1, 1, 5) /* HSW+ */
 342#define OP_MFD_AVC_DPB_STATE			   OP_MFX(2, 1, 1, 6) /* IVB+ */
 343#define OP_MFD_AVC_SLICEADDR                       OP_MFX(2, 1, 1, 7) /* IVB+ */
 344#define OP_MFD_AVC_BSD_OBJECT                      OP_MFX(2, 1, 1, 8) /* ALL */
 345#define OP_MFC_AVC_PAK_OBJECT                      OP_MFX(2, 1, 2, 9) /* ALL */
 346
 347#define OP_MFX_VC1_PRED_PIPE_STATE                 OP_MFX(2, 2, 0, 1) /* ALL */
 348#define OP_MFX_VC1_DIRECTMODE_STATE                OP_MFX(2, 2, 0, 2) /* ALL */
 349#define OP_MFD_VC1_SHORT_PIC_STATE                 OP_MFX(2, 2, 1, 0) /* IVB+ */
 350#define OP_MFD_VC1_LONG_PIC_STATE                  OP_MFX(2, 2, 1, 1) /* IVB+ */
 351#define OP_MFD_VC1_BSD_OBJECT                      OP_MFX(2, 2, 1, 8) /* ALL */
 352
 353#define OP_MFX_MPEG2_PIC_STATE                     OP_MFX(2, 3, 0, 0) /* ALL */
 354#define OP_MFX_MPEG2_QM_STATE                      OP_MFX(2, 3, 0, 1) /* ALL */
 355#define OP_MFD_MPEG2_BSD_OBJECT                    OP_MFX(2, 3, 1, 8) /* ALL */
 356#define OP_MFC_MPEG2_SLICEGROUP_STATE              OP_MFX(2, 3, 2, 3) /* ALL */
 357#define OP_MFC_MPEG2_PAK_OBJECT                    OP_MFX(2, 3, 2, 9) /* ALL */
 358
 359#define OP_MFX_2_6_0_0                             OP_MFX(2, 6, 0, 0) /* IVB+ */
 360#define OP_MFX_2_6_0_8                             OP_MFX(2, 6, 0, 8) /* IVB+ */
 361#define OP_MFX_2_6_0_9                             OP_MFX(2, 6, 0, 9) /* IVB+ */
 362
 363#define OP_MFX_JPEG_PIC_STATE                      OP_MFX(2, 7, 0, 0)
 364#define OP_MFX_JPEG_HUFF_TABLE_STATE               OP_MFX(2, 7, 0, 2)
 365#define OP_MFD_JPEG_BSD_OBJECT                     OP_MFX(2, 7, 1, 8)
 366
 367#define OP_VEB(pipeline, op, sub_opa, sub_opb) \
 368	(3 << 13 | \
 369	 (pipeline) << 11 | \
 370	 (op) << 8 | \
 371	 (sub_opa) << 5 | \
 372	 (sub_opb))
 373
 374#define OP_VEB_SURFACE_STATE                       OP_VEB(2, 4, 0, 0)
 375#define OP_VEB_STATE                               OP_VEB(2, 4, 0, 2)
 376#define OP_VEB_DNDI_IECP_STATE                     OP_VEB(2, 4, 0, 3)
 377
 378struct parser_exec_state;
 379
 380typedef int (*parser_cmd_handler)(struct parser_exec_state *s);
 381
 382#define GVT_CMD_HASH_BITS   7
 383
 384/* which DWords need address fix */
 385#define ADDR_FIX_1(x1)			(1 << (x1))
 386#define ADDR_FIX_2(x1, x2)		(ADDR_FIX_1(x1) | ADDR_FIX_1(x2))
 387#define ADDR_FIX_3(x1, x2, x3)		(ADDR_FIX_1(x1) | ADDR_FIX_2(x2, x3))
 388#define ADDR_FIX_4(x1, x2, x3, x4)	(ADDR_FIX_1(x1) | ADDR_FIX_3(x2, x3, x4))
 389#define ADDR_FIX_5(x1, x2, x3, x4, x5)  (ADDR_FIX_1(x1) | ADDR_FIX_4(x2, x3, x4, x5))
 390
 391#define DWORD_FIELD(dword, end, start) \
 392	FIELD_GET(GENMASK(end, start), cmd_val(s, dword))
 393
 394#define OP_LENGTH_BIAS 2
 395#define CMD_LEN(value)  (value + OP_LENGTH_BIAS)
 396
 397static int gvt_check_valid_cmd_length(int len, int valid_len)
 398{
 399	if (valid_len != len) {
 400		gvt_err("len is not valid:  len=%u  valid_len=%u\n",
 401			len, valid_len);
 402		return -EFAULT;
 403	}
 404	return 0;
 405}
 406
 407struct cmd_info {
 408	const char *name;
 409	u32 opcode;
 410
 411#define F_LEN_MASK	3U
 412#define F_LEN_CONST  1U
 413#define F_LEN_VAR    0U
 414/* value is const although LEN maybe variable */
 415#define F_LEN_VAR_FIXED    (1<<1)
 416
 417/*
 418 * command has its own ip advance logic
 419 * e.g. MI_BATCH_START, MI_BATCH_END
 420 */
 421#define F_IP_ADVANCE_CUSTOM (1<<2)
 422	u32 flag;
 423
 424#define R_RCS	BIT(RCS0)
 425#define R_VCS1  BIT(VCS0)
 426#define R_VCS2  BIT(VCS1)
 427#define R_VCS	(R_VCS1 | R_VCS2)
 428#define R_BCS	BIT(BCS0)
 429#define R_VECS	BIT(VECS0)
 430#define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS)
 431	/* rings that support this cmd: BLT/RCS/VCS/VECS */
 432	intel_engine_mask_t rings;
 433
 434	/* devices that support this cmd: SNB/IVB/HSW/... */
 435	u16 devices;
 436
 437	/* which DWords are address that need fix up.
 438	 * bit 0 means a 32-bit non address operand in command
 439	 * bit 1 means address operand, which could be 32-bit
 440	 * or 64-bit depending on different architectures.(
 441	 * defined by "gmadr_bytes_in_cmd" in intel_gvt.
 442	 * No matter the address length, each address only takes
 443	 * one bit in the bitmap.
 444	 */
 445	u16 addr_bitmap;
 446
 447	/* flag == F_LEN_CONST : command length
 448	 * flag == F_LEN_VAR : length bias bits
 449	 * Note: length is in DWord
 450	 */
 451	u32 len;
 452
 453	parser_cmd_handler handler;
 454
 455	/* valid length in DWord */
 456	u32 valid_len;
 457};
 458
 459struct cmd_entry {
 460	struct hlist_node hlist;
 461	const struct cmd_info *info;
 462};
 463
 464enum {
 465	RING_BUFFER_INSTRUCTION,
 466	BATCH_BUFFER_INSTRUCTION,
 467	BATCH_BUFFER_2ND_LEVEL,
 468	RING_BUFFER_CTX,
 469};
 470
 471enum {
 472	GTT_BUFFER,
 473	PPGTT_BUFFER
 474};
 475
 476struct parser_exec_state {
 477	struct intel_vgpu *vgpu;
 478	const struct intel_engine_cs *engine;
 479
 480	int buf_type;
 481
 482	/* batch buffer address type */
 483	int buf_addr_type;
 484
 485	/* graphics memory address of ring buffer start */
 486	unsigned long ring_start;
 487	unsigned long ring_size;
 488	unsigned long ring_head;
 489	unsigned long ring_tail;
 490
 491	/* instruction graphics memory address */
 492	unsigned long ip_gma;
 493
 494	/* mapped va of the instr_gma */
 495	void *ip_va;
 496	void *rb_va;
 497
 498	void *ret_bb_va;
 499	/* next instruction when return from  batch buffer to ring buffer */
 500	unsigned long ret_ip_gma_ring;
 501
 502	/* next instruction when return from 2nd batch buffer to batch buffer */
 503	unsigned long ret_ip_gma_bb;
 504
 505	/* batch buffer address type (GTT or PPGTT)
 506	 * used when ret from 2nd level batch buffer
 507	 */
 508	int saved_buf_addr_type;
 509	bool is_ctx_wa;
 510	bool is_init_ctx;
 511
 512	const struct cmd_info *info;
 513
 514	struct intel_vgpu_workload *workload;
 515};
 516
 517#define gmadr_dw_number(s)	\
 518	(s->vgpu->gvt->device_info.gmadr_bytes_in_cmd >> 2)
 519
 520static unsigned long bypass_scan_mask = 0;
 521
 522/* ring ALL, type = 0 */
 523static const struct sub_op_bits sub_op_mi[] = {
 524	{31, 29},
 525	{28, 23},
 526};
 527
 528static const struct decode_info decode_info_mi = {
 529	"MI",
 530	OP_LEN_MI,
 531	ARRAY_SIZE(sub_op_mi),
 532	sub_op_mi,
 533};
 534
 535/* ring RCS, command type 2 */
 536static const struct sub_op_bits sub_op_2d[] = {
 537	{31, 29},
 538	{28, 22},
 539};
 540
 541static const struct decode_info decode_info_2d = {
 542	"2D",
 543	OP_LEN_2D,
 544	ARRAY_SIZE(sub_op_2d),
 545	sub_op_2d,
 546};
 547
 548/* ring RCS, command type 3 */
 549static const struct sub_op_bits sub_op_3d_media[] = {
 550	{31, 29},
 551	{28, 27},
 552	{26, 24},
 553	{23, 16},
 554};
 555
 556static const struct decode_info decode_info_3d_media = {
 557	"3D_Media",
 558	OP_LEN_3D_MEDIA,
 559	ARRAY_SIZE(sub_op_3d_media),
 560	sub_op_3d_media,
 561};
 562
 563/* ring VCS, command type 3 */
 564static const struct sub_op_bits sub_op_mfx_vc[] = {
 565	{31, 29},
 566	{28, 27},
 567	{26, 24},
 568	{23, 21},
 569	{20, 16},
 570};
 571
 572static const struct decode_info decode_info_mfx_vc = {
 573	"MFX_VC",
 574	OP_LEN_MFX_VC,
 575	ARRAY_SIZE(sub_op_mfx_vc),
 576	sub_op_mfx_vc,
 577};
 578
 579/* ring VECS, command type 3 */
 580static const struct sub_op_bits sub_op_vebox[] = {
 581	{31, 29},
 582	{28, 27},
 583	{26, 24},
 584	{23, 21},
 585	{20, 16},
 586};
 587
 588static const struct decode_info decode_info_vebox = {
 589	"VEBOX",
 590	OP_LEN_VEBOX,
 591	ARRAY_SIZE(sub_op_vebox),
 592	sub_op_vebox,
 593};
 594
 595static const struct decode_info *ring_decode_info[I915_NUM_ENGINES][8] = {
 596	[RCS0] = {
 597		&decode_info_mi,
 598		NULL,
 599		NULL,
 600		&decode_info_3d_media,
 601		NULL,
 602		NULL,
 603		NULL,
 604		NULL,
 605	},
 606
 607	[VCS0] = {
 608		&decode_info_mi,
 609		NULL,
 610		NULL,
 611		&decode_info_mfx_vc,
 612		NULL,
 613		NULL,
 614		NULL,
 615		NULL,
 616	},
 617
 618	[BCS0] = {
 619		&decode_info_mi,
 620		NULL,
 621		&decode_info_2d,
 622		NULL,
 623		NULL,
 624		NULL,
 625		NULL,
 626		NULL,
 627	},
 628
 629	[VECS0] = {
 630		&decode_info_mi,
 631		NULL,
 632		NULL,
 633		&decode_info_vebox,
 634		NULL,
 635		NULL,
 636		NULL,
 637		NULL,
 638	},
 639
 640	[VCS1] = {
 641		&decode_info_mi,
 642		NULL,
 643		NULL,
 644		&decode_info_mfx_vc,
 645		NULL,
 646		NULL,
 647		NULL,
 648		NULL,
 649	},
 650};
 651
 652static inline u32 get_opcode(u32 cmd, const struct intel_engine_cs *engine)
 653{
 654	const struct decode_info *d_info;
 655
 656	d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 657	if (d_info == NULL)
 658		return INVALID_OP;
 659
 660	return cmd >> (32 - d_info->op_len);
 661}
 662
 663static inline const struct cmd_info *
 664find_cmd_entry(struct intel_gvt *gvt, unsigned int opcode,
 665	       const struct intel_engine_cs *engine)
 666{
 667	struct cmd_entry *e;
 668
 669	hash_for_each_possible(gvt->cmd_table, e, hlist, opcode) {
 670		if (opcode == e->info->opcode &&
 671		    e->info->rings & engine->mask)
 672			return e->info;
 673	}
 674	return NULL;
 675}
 676
 677static inline const struct cmd_info *
 678get_cmd_info(struct intel_gvt *gvt, u32 cmd,
 679	     const struct intel_engine_cs *engine)
 680{
 681	u32 opcode;
 682
 683	opcode = get_opcode(cmd, engine);
 684	if (opcode == INVALID_OP)
 685		return NULL;
 686
 687	return find_cmd_entry(gvt, opcode, engine);
 688}
 689
 690static inline u32 sub_op_val(u32 cmd, u32 hi, u32 low)
 691{
 692	return (cmd >> low) & ((1U << (hi - low + 1)) - 1);
 693}
 694
 695static inline void print_opcode(u32 cmd, const struct intel_engine_cs *engine)
 696{
 697	const struct decode_info *d_info;
 698	int i;
 699
 700	d_info = ring_decode_info[engine->id][CMD_TYPE(cmd)];
 701	if (d_info == NULL)
 702		return;
 703
 704	gvt_dbg_cmd("opcode=0x%x %s sub_ops:",
 705			cmd >> (32 - d_info->op_len), d_info->name);
 706
 707	for (i = 0; i < d_info->nr_sub_op; i++)
 708		pr_err("0x%x ", sub_op_val(cmd, d_info->sub_op[i].hi,
 709					d_info->sub_op[i].low));
 710
 711	pr_err("\n");
 712}
 713
 714static inline u32 *cmd_ptr(struct parser_exec_state *s, int index)
 715{
 716	return s->ip_va + (index << 2);
 717}
 718
 719static inline u32 cmd_val(struct parser_exec_state *s, int index)
 720{
 721	return *cmd_ptr(s, index);
 722}
 723
 724static inline bool is_init_ctx(struct parser_exec_state *s)
 725{
 726	return (s->buf_type == RING_BUFFER_CTX && s->is_init_ctx);
 727}
 728
 729static void parser_exec_state_dump(struct parser_exec_state *s)
 730{
 731	int cnt = 0;
 732	int i;
 733
 734	gvt_dbg_cmd("  vgpu%d RING%s: ring_start(%08lx) ring_end(%08lx)"
 735		    " ring_head(%08lx) ring_tail(%08lx)\n",
 736		    s->vgpu->id, s->engine->name,
 737		    s->ring_start, s->ring_start + s->ring_size,
 738		    s->ring_head, s->ring_tail);
 739
 740	gvt_dbg_cmd("  %s %s ip_gma(%08lx) ",
 741			s->buf_type == RING_BUFFER_INSTRUCTION ?
 742			"RING_BUFFER" : ((s->buf_type == RING_BUFFER_CTX) ?
 743				"CTX_BUFFER" : "BATCH_BUFFER"),
 744			s->buf_addr_type == GTT_BUFFER ?
 745			"GTT" : "PPGTT", s->ip_gma);
 746
 747	if (s->ip_va == NULL) {
 748		gvt_dbg_cmd(" ip_va(NULL)");
 749		return;
 750	}
 751
 752	gvt_dbg_cmd("  ip_va=%p: %08x %08x %08x %08x\n",
 753			s->ip_va, cmd_val(s, 0), cmd_val(s, 1),
 754			cmd_val(s, 2), cmd_val(s, 3));
 755
 756	print_opcode(cmd_val(s, 0), s->engine);
 757
 758	s->ip_va = (u32 *)((((u64)s->ip_va) >> 12) << 12);
 759
 760	while (cnt < 1024) {
 761		gvt_dbg_cmd("ip_va=%p: ", s->ip_va);
 762		for (i = 0; i < 8; i++)
 763			gvt_dbg_cmd("%08x ", cmd_val(s, i));
 764		gvt_dbg_cmd("\n");
 765
 766		s->ip_va += 8 * sizeof(u32);
 767		cnt += 8;
 768	}
 769}
 770
 771static inline void update_ip_va(struct parser_exec_state *s)
 772{
 773	unsigned long len = 0;
 774
 775	if (WARN_ON(s->ring_head == s->ring_tail))
 776		return;
 777
 778	if (s->buf_type == RING_BUFFER_INSTRUCTION ||
 779			s->buf_type == RING_BUFFER_CTX) {
 780		unsigned long ring_top = s->ring_start + s->ring_size;
 781
 782		if (s->ring_head > s->ring_tail) {
 783			if (s->ip_gma >= s->ring_head && s->ip_gma < ring_top)
 784				len = (s->ip_gma - s->ring_head);
 785			else if (s->ip_gma >= s->ring_start &&
 786					s->ip_gma <= s->ring_tail)
 787				len = (ring_top - s->ring_head) +
 788					(s->ip_gma - s->ring_start);
 789		} else
 790			len = (s->ip_gma - s->ring_head);
 791
 792		s->ip_va = s->rb_va + len;
 793	} else {/* shadow batch buffer */
 794		s->ip_va = s->ret_bb_va;
 795	}
 796}
 797
 798static inline int ip_gma_set(struct parser_exec_state *s,
 799		unsigned long ip_gma)
 800{
 801	WARN_ON(!IS_ALIGNED(ip_gma, 4));
 802
 803	s->ip_gma = ip_gma;
 804	update_ip_va(s);
 805	return 0;
 806}
 807
 808static inline int ip_gma_advance(struct parser_exec_state *s,
 809		unsigned int dw_len)
 810{
 811	s->ip_gma += (dw_len << 2);
 812
 813	if (s->buf_type == RING_BUFFER_INSTRUCTION) {
 814		if (s->ip_gma >= s->ring_start + s->ring_size)
 815			s->ip_gma -= s->ring_size;
 816		update_ip_va(s);
 817	} else {
 818		s->ip_va += (dw_len << 2);
 819	}
 820
 821	return 0;
 822}
 823
 824static inline int get_cmd_length(const struct cmd_info *info, u32 cmd)
 825{
 826	if ((info->flag & F_LEN_MASK) == F_LEN_CONST)
 827		return info->len;
 828	else
 829		return (cmd & ((1U << info->len) - 1)) + 2;
 830	return 0;
 831}
 832
 833static inline int cmd_length(struct parser_exec_state *s)
 834{
 835	return get_cmd_length(s->info, cmd_val(s, 0));
 836}
 837
 838/* do not remove this, some platform may need clflush here */
 839#define patch_value(s, addr, val) do { \
 840	*addr = val; \
 841} while (0)
 842
 843static inline bool is_mocs_mmio(unsigned int offset)
 844{
 845	return ((offset >= 0xc800) && (offset <= 0xcff8)) ||
 846		((offset >= 0xb020) && (offset <= 0xb0a0));
 847}
 848
 849static int is_cmd_update_pdps(unsigned int offset,
 850			      struct parser_exec_state *s)
 851{
 852	u32 base = s->workload->engine->mmio_base;
 853	return i915_mmio_reg_equal(_MMIO(offset), GEN8_RING_PDP_UDW(base, 0));
 854}
 855
 856static int cmd_pdp_mmio_update_handler(struct parser_exec_state *s,
 857				       unsigned int offset, unsigned int index)
 858{
 859	struct intel_vgpu *vgpu = s->vgpu;
 860	struct intel_vgpu_mm *shadow_mm = s->workload->shadow_mm;
 861	struct intel_vgpu_mm *mm;
 862	u64 pdps[GEN8_3LVL_PDPES];
 863
 864	if (shadow_mm->ppgtt_mm.root_entry_type ==
 865	    GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 866		pdps[0] = (u64)cmd_val(s, 2) << 32;
 867		pdps[0] |= cmd_val(s, 4);
 868
 869		mm = intel_vgpu_find_ppgtt_mm(vgpu, pdps);
 870		if (!mm) {
 871			gvt_vgpu_err("failed to get the 4-level shadow vm\n");
 872			return -EINVAL;
 873		}
 874		intel_vgpu_mm_get(mm);
 875		list_add_tail(&mm->ppgtt_mm.link,
 876			      &s->workload->lri_shadow_mm);
 877		*cmd_ptr(s, 2) = upper_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
 878		*cmd_ptr(s, 4) = lower_32_bits(mm->ppgtt_mm.shadow_pdps[0]);
 879	} else {
 880		/* Currently all guests use PML4 table and now can't
 881		 * have a guest with 3-level table but uses LRI for
 882		 * PPGTT update. So this is simply un-testable. */
 883		GEM_BUG_ON(1);
 884		gvt_vgpu_err("invalid shared shadow vm type\n");
 885		return -EINVAL;
 886	}
 887	return 0;
 888}
 889
 890static int cmd_reg_handler(struct parser_exec_state *s,
 891	unsigned int offset, unsigned int index, char *cmd)
 892{
 893	struct intel_vgpu *vgpu = s->vgpu;
 894	struct intel_gvt *gvt = vgpu->gvt;
 895	u32 ctx_sr_ctl;
 896	u32 *vreg, vreg_old;
 897
 898	if (offset + 4 > gvt->device_info.mmio_size) {
 899		gvt_vgpu_err("%s access to (%x) outside of MMIO range\n",
 900				cmd, offset);
 901		return -EFAULT;
 902	}
 903
 904	if (is_init_ctx(s)) {
 905		struct intel_gvt_mmio_info *mmio_info;
 906
 907		intel_gvt_mmio_set_cmd_accessible(gvt, offset);
 908		mmio_info = intel_gvt_find_mmio_info(gvt, offset);
 909		if (mmio_info && mmio_info->write)
 910			intel_gvt_mmio_set_cmd_write_patch(gvt, offset);
 911		return 0;
 912	}
 913
 914	if (!intel_gvt_mmio_is_cmd_accessible(gvt, offset)) {
 915		gvt_vgpu_err("%s access to non-render register (%x)\n",
 916				cmd, offset);
 917		return -EBADRQC;
 918	}
 919
 920	if (!strncmp(cmd, "srm", 3) ||
 921			!strncmp(cmd, "lrm", 3)) {
 922		if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
 923		    offset == 0x21f0 ||
 924		    (IS_BROADWELL(gvt->gt->i915) &&
 925		     offset == i915_mmio_reg_offset(INSTPM)))
 926			return 0;
 927		else {
 928			gvt_vgpu_err("%s access to register (%x)\n",
 929					cmd, offset);
 930			return -EPERM;
 931		}
 932	}
 933
 934	if (!strncmp(cmd, "lrr-src", 7) ||
 935			!strncmp(cmd, "lrr-dst", 7)) {
 936		if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
 937			return 0;
 938		else {
 939			gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
 940			return -EPERM;
 941		}
 942	}
 943
 944	if (!strncmp(cmd, "pipe_ctrl", 9)) {
 945		/* TODO: add LRI POST logic here */
 946		return 0;
 947	}
 948
 949	if (strncmp(cmd, "lri", 3))
 950		return -EPERM;
 951
 952	/* below are all lri handlers */
 953	vreg = &vgpu_vreg(s->vgpu, offset);
 954
 955	if (is_cmd_update_pdps(offset, s) &&
 956	    cmd_pdp_mmio_update_handler(s, offset, index))
 957		return -EINVAL;
 958
 959	if (offset == i915_mmio_reg_offset(DERRMR) ||
 960		offset == i915_mmio_reg_offset(FORCEWAKE_MT)) {
 961		/* Writing to HW VGT_PVINFO_PAGE offset will be discarded */
 962		patch_value(s, cmd_ptr(s, index), VGT_PVINFO_PAGE);
 963	}
 964
 965	if (is_mocs_mmio(offset))
 966		*vreg = cmd_val(s, index + 1);
 967
 968	vreg_old = *vreg;
 969
 970	if (intel_gvt_mmio_is_cmd_write_patch(gvt, offset)) {
 971		u32 cmdval_new, cmdval;
 972		struct intel_gvt_mmio_info *mmio_info;
 973
 974		cmdval = cmd_val(s, index + 1);
 975
 976		mmio_info = intel_gvt_find_mmio_info(gvt, offset);
 977		if (!mmio_info) {
 978			cmdval_new = cmdval;
 979		} else {
 980			u64 ro_mask = mmio_info->ro_mask;
 981			int ret;
 982
 983			if (likely(!ro_mask))
 984				ret = mmio_info->write(s->vgpu, offset,
 985						&cmdval, 4);
 986			else {
 987				gvt_vgpu_err("try to write RO reg %x\n",
 988						offset);
 989				ret = -EBADRQC;
 990			}
 991			if (ret)
 992				return ret;
 993			cmdval_new = *vreg;
 994		}
 995		if (cmdval_new != cmdval)
 996			patch_value(s, cmd_ptr(s, index+1), cmdval_new);
 997	}
 998
 999	/* only patch cmd. restore vreg value if changed in mmio write handler*/
1000	*vreg = vreg_old;
1001
1002	/* TODO
1003	 * In order to let workload with inhibit context to generate
1004	 * correct image data into memory, vregs values will be loaded to
1005	 * hw via LRIs in the workload with inhibit context. But as
1006	 * indirect context is loaded prior to LRIs in workload, we don't
1007	 * want reg values specified in indirect context overwritten by
1008	 * LRIs in workloads. So, when scanning an indirect context, we
1009	 * update reg values in it into vregs, so LRIs in workload with
1010	 * inhibit context will restore with correct values
1011	 */
1012	if (GRAPHICS_VER(s->engine->i915) == 9 &&
1013	    intel_gvt_mmio_is_sr_in_ctx(gvt, offset) &&
1014	    !strncmp(cmd, "lri", 3)) {
1015		intel_gvt_read_gpa(s->vgpu,
1016			s->workload->ring_context_gpa + 12, &ctx_sr_ctl, 4);
1017		/* check inhibit context */
1018		if (ctx_sr_ctl & 1) {
1019			u32 data = cmd_val(s, index + 1);
1020
1021			if (intel_gvt_mmio_has_mode_mask(s->vgpu->gvt, offset))
1022				intel_vgpu_mask_mmio_write(vgpu,
1023							offset, &data, 4);
1024			else
1025				vgpu_vreg(vgpu, offset) = data;
1026		}
1027	}
1028
1029	return 0;
1030}
1031
1032#define cmd_reg(s, i) \
1033	(cmd_val(s, i) & GENMASK(22, 2))
1034
1035#define cmd_reg_inhibit(s, i) \
1036	(cmd_val(s, i) & GENMASK(22, 18))
1037
1038#define cmd_gma(s, i) \
1039	(cmd_val(s, i) & GENMASK(31, 2))
1040
1041#define cmd_gma_hi(s, i) \
1042	(cmd_val(s, i) & GENMASK(15, 0))
1043
1044static int cmd_handler_lri(struct parser_exec_state *s)
1045{
1046	int i, ret = 0;
1047	int cmd_len = cmd_length(s);
1048
1049	for (i = 1; i < cmd_len; i += 2) {
1050		if (IS_BROADWELL(s->engine->i915) && s->engine->id != RCS0) {
1051			if (s->engine->id == BCS0 &&
1052			    cmd_reg(s, i) == i915_mmio_reg_offset(DERRMR))
1053				ret |= 0;
1054			else
1055				ret |= cmd_reg_inhibit(s, i) ? -EBADRQC : 0;
1056		}
1057		if (ret)
1058			break;
1059		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lri");
1060		if (ret)
1061			break;
1062	}
1063	return ret;
1064}
1065
1066static int cmd_handler_lrr(struct parser_exec_state *s)
1067{
1068	int i, ret = 0;
1069	int cmd_len = cmd_length(s);
1070
1071	for (i = 1; i < cmd_len; i += 2) {
1072		if (IS_BROADWELL(s->engine->i915))
1073			ret |= ((cmd_reg_inhibit(s, i) ||
1074				 (cmd_reg_inhibit(s, i + 1)))) ?
1075				-EBADRQC : 0;
1076		if (ret)
1077			break;
1078		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrr-src");
1079		if (ret)
1080			break;
1081		ret |= cmd_reg_handler(s, cmd_reg(s, i + 1), i, "lrr-dst");
1082		if (ret)
1083			break;
1084	}
1085	return ret;
1086}
1087
1088static inline int cmd_address_audit(struct parser_exec_state *s,
1089		unsigned long guest_gma, int op_size, bool index_mode);
1090
1091static int cmd_handler_lrm(struct parser_exec_state *s)
1092{
1093	struct intel_gvt *gvt = s->vgpu->gvt;
1094	int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
1095	unsigned long gma;
1096	int i, ret = 0;
1097	int cmd_len = cmd_length(s);
1098
1099	for (i = 1; i < cmd_len;) {
1100		if (IS_BROADWELL(s->engine->i915))
1101			ret |= (cmd_reg_inhibit(s, i)) ? -EBADRQC : 0;
1102		if (ret)
1103			break;
1104		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "lrm");
1105		if (ret)
1106			break;
1107		if (cmd_val(s, 0) & (1 << 22)) {
1108			gma = cmd_gma(s, i + 1);
1109			if (gmadr_bytes == 8)
1110				gma |= (cmd_gma_hi(s, i + 2)) << 32;
1111			ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1112			if (ret)
1113				break;
1114		}
1115		i += gmadr_dw_number(s) + 1;
1116	}
1117	return ret;
1118}
1119
1120static int cmd_handler_srm(struct parser_exec_state *s)
1121{
1122	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1123	unsigned long gma;
1124	int i, ret = 0;
1125	int cmd_len = cmd_length(s);
1126
1127	for (i = 1; i < cmd_len;) {
1128		ret |= cmd_reg_handler(s, cmd_reg(s, i), i, "srm");
1129		if (ret)
1130			break;
1131		if (cmd_val(s, 0) & (1 << 22)) {
1132			gma = cmd_gma(s, i + 1);
1133			if (gmadr_bytes == 8)
1134				gma |= (cmd_gma_hi(s, i + 2)) << 32;
1135			ret |= cmd_address_audit(s, gma, sizeof(u32), false);
1136			if (ret)
1137				break;
1138		}
1139		i += gmadr_dw_number(s) + 1;
1140	}
1141	return ret;
1142}
1143
1144struct cmd_interrupt_event {
1145	int pipe_control_notify;
1146	int mi_flush_dw;
1147	int mi_user_interrupt;
1148};
1149
1150static const struct cmd_interrupt_event cmd_interrupt_events[] = {
1151	[RCS0] = {
1152		.pipe_control_notify = RCS_PIPE_CONTROL,
1153		.mi_flush_dw = INTEL_GVT_EVENT_RESERVED,
1154		.mi_user_interrupt = RCS_MI_USER_INTERRUPT,
1155	},
1156	[BCS0] = {
1157		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1158		.mi_flush_dw = BCS_MI_FLUSH_DW,
1159		.mi_user_interrupt = BCS_MI_USER_INTERRUPT,
1160	},
1161	[VCS0] = {
1162		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1163		.mi_flush_dw = VCS_MI_FLUSH_DW,
1164		.mi_user_interrupt = VCS_MI_USER_INTERRUPT,
1165	},
1166	[VCS1] = {
1167		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1168		.mi_flush_dw = VCS2_MI_FLUSH_DW,
1169		.mi_user_interrupt = VCS2_MI_USER_INTERRUPT,
1170	},
1171	[VECS0] = {
1172		.pipe_control_notify = INTEL_GVT_EVENT_RESERVED,
1173		.mi_flush_dw = VECS_MI_FLUSH_DW,
1174		.mi_user_interrupt = VECS_MI_USER_INTERRUPT,
1175	},
1176};
1177
1178static int cmd_handler_pipe_control(struct parser_exec_state *s)
1179{
1180	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1181	unsigned long gma;
1182	bool index_mode = false;
1183	unsigned int post_sync;
1184	int ret = 0;
1185	u32 hws_pga, val;
1186
1187	post_sync = (cmd_val(s, 1) & PIPE_CONTROL_POST_SYNC_OP_MASK) >> 14;
1188
1189	/* LRI post sync */
1190	if (cmd_val(s, 1) & PIPE_CONTROL_MMIO_WRITE)
1191		ret = cmd_reg_handler(s, cmd_reg(s, 2), 1, "pipe_ctrl");
1192	/* post sync */
1193	else if (post_sync) {
1194		if (post_sync == 2)
1195			ret = cmd_reg_handler(s, 0x2350, 1, "pipe_ctrl");
1196		else if (post_sync == 3)
1197			ret = cmd_reg_handler(s, 0x2358, 1, "pipe_ctrl");
1198		else if (post_sync == 1) {
1199			/* check ggtt*/
1200			if ((cmd_val(s, 1) & PIPE_CONTROL_GLOBAL_GTT_IVB)) {
1201				gma = cmd_val(s, 2) & GENMASK(31, 3);
1202				if (gmadr_bytes == 8)
1203					gma |= (cmd_gma_hi(s, 3)) << 32;
1204				/* Store Data Index */
1205				if (cmd_val(s, 1) & (1 << 21))
1206					index_mode = true;
1207				ret |= cmd_address_audit(s, gma, sizeof(u64),
1208						index_mode);
1209				if (ret)
1210					return ret;
1211				if (index_mode) {
1212					hws_pga = s->vgpu->hws_pga[s->engine->id];
1213					gma = hws_pga + gma;
1214					patch_value(s, cmd_ptr(s, 2), gma);
1215					val = cmd_val(s, 1) & (~(1 << 21));
1216					patch_value(s, cmd_ptr(s, 1), val);
1217				}
1218			}
1219		}
1220	}
1221
1222	if (ret)
1223		return ret;
1224
1225	if (cmd_val(s, 1) & PIPE_CONTROL_NOTIFY)
1226		set_bit(cmd_interrupt_events[s->engine->id].pipe_control_notify,
1227			s->workload->pending_events);
1228	return 0;
1229}
1230
1231static int cmd_handler_mi_user_interrupt(struct parser_exec_state *s)
1232{
1233	set_bit(cmd_interrupt_events[s->engine->id].mi_user_interrupt,
1234		s->workload->pending_events);
1235	patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1236	return 0;
1237}
1238
1239static int cmd_advance_default(struct parser_exec_state *s)
1240{
1241	return ip_gma_advance(s, cmd_length(s));
1242}
1243
1244static int cmd_handler_mi_batch_buffer_end(struct parser_exec_state *s)
1245{
1246	int ret;
1247
1248	if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1249		s->buf_type = BATCH_BUFFER_INSTRUCTION;
1250		ret = ip_gma_set(s, s->ret_ip_gma_bb);
1251		s->buf_addr_type = s->saved_buf_addr_type;
1252	} else if (s->buf_type == RING_BUFFER_CTX) {
1253		ret = ip_gma_set(s, s->ring_tail);
1254	} else {
1255		s->buf_type = RING_BUFFER_INSTRUCTION;
1256		s->buf_addr_type = GTT_BUFFER;
1257		if (s->ret_ip_gma_ring >= s->ring_start + s->ring_size)
1258			s->ret_ip_gma_ring -= s->ring_size;
1259		ret = ip_gma_set(s, s->ret_ip_gma_ring);
1260	}
1261	return ret;
1262}
1263
1264struct mi_display_flip_command_info {
1265	int pipe;
1266	int plane;
1267	int event;
1268	i915_reg_t stride_reg;
1269	i915_reg_t ctrl_reg;
1270	i915_reg_t surf_reg;
1271	u64 stride_val;
1272	u64 tile_val;
1273	u64 surf_val;
1274	bool async_flip;
1275};
1276
1277struct plane_code_mapping {
1278	int pipe;
1279	int plane;
1280	int event;
1281};
1282
1283static int gen8_decode_mi_display_flip(struct parser_exec_state *s,
1284		struct mi_display_flip_command_info *info)
1285{
1286	struct drm_i915_private *dev_priv = s->engine->i915;
1287	struct plane_code_mapping gen8_plane_code[] = {
1288		[0] = {PIPE_A, PLANE_A, PRIMARY_A_FLIP_DONE},
1289		[1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE},
1290		[2] = {PIPE_A, PLANE_B, SPRITE_A_FLIP_DONE},
1291		[3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE},
1292		[4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE},
1293		[5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE},
1294	};
1295	u32 dword0, dword1, dword2;
1296	u32 v;
1297
1298	dword0 = cmd_val(s, 0);
1299	dword1 = cmd_val(s, 1);
1300	dword2 = cmd_val(s, 2);
1301
1302	v = (dword0 & GENMASK(21, 19)) >> 19;
1303	if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))
1304		return -EBADRQC;
1305
1306	info->pipe = gen8_plane_code[v].pipe;
1307	info->plane = gen8_plane_code[v].plane;
1308	info->event = gen8_plane_code[v].event;
1309	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1310	info->tile_val = (dword1 & 0x1);
1311	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1312	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1313
1314	if (info->plane == PLANE_A) {
1315		info->ctrl_reg = DSPCNTR(info->pipe);
1316		info->stride_reg = DSPSTRIDE(info->pipe);
1317		info->surf_reg = DSPSURF(info->pipe);
1318	} else if (info->plane == PLANE_B) {
1319		info->ctrl_reg = SPRCTL(info->pipe);
1320		info->stride_reg = SPRSTRIDE(info->pipe);
1321		info->surf_reg = SPRSURF(info->pipe);
1322	} else {
1323		drm_WARN_ON(&dev_priv->drm, 1);
1324		return -EBADRQC;
1325	}
1326	return 0;
1327}
1328
1329static int skl_decode_mi_display_flip(struct parser_exec_state *s,
1330		struct mi_display_flip_command_info *info)
1331{
1332	struct drm_i915_private *dev_priv = s->engine->i915;
1333	struct intel_vgpu *vgpu = s->vgpu;
1334	u32 dword0 = cmd_val(s, 0);
1335	u32 dword1 = cmd_val(s, 1);
1336	u32 dword2 = cmd_val(s, 2);
1337	u32 plane = (dword0 & GENMASK(12, 8)) >> 8;
1338
1339	info->plane = PRIMARY_PLANE;
1340
1341	switch (plane) {
1342	case MI_DISPLAY_FLIP_SKL_PLANE_1_A:
1343		info->pipe = PIPE_A;
1344		info->event = PRIMARY_A_FLIP_DONE;
1345		break;
1346	case MI_DISPLAY_FLIP_SKL_PLANE_1_B:
1347		info->pipe = PIPE_B;
1348		info->event = PRIMARY_B_FLIP_DONE;
1349		break;
1350	case MI_DISPLAY_FLIP_SKL_PLANE_1_C:
1351		info->pipe = PIPE_C;
1352		info->event = PRIMARY_C_FLIP_DONE;
1353		break;
1354
1355	case MI_DISPLAY_FLIP_SKL_PLANE_2_A:
1356		info->pipe = PIPE_A;
1357		info->event = SPRITE_A_FLIP_DONE;
1358		info->plane = SPRITE_PLANE;
1359		break;
1360	case MI_DISPLAY_FLIP_SKL_PLANE_2_B:
1361		info->pipe = PIPE_B;
1362		info->event = SPRITE_B_FLIP_DONE;
1363		info->plane = SPRITE_PLANE;
1364		break;
1365	case MI_DISPLAY_FLIP_SKL_PLANE_2_C:
1366		info->pipe = PIPE_C;
1367		info->event = SPRITE_C_FLIP_DONE;
1368		info->plane = SPRITE_PLANE;
1369		break;
1370
1371	default:
1372		gvt_vgpu_err("unknown plane code %d\n", plane);
1373		return -EBADRQC;
1374	}
1375
1376	info->stride_val = (dword1 & GENMASK(15, 6)) >> 6;
1377	info->tile_val = (dword1 & GENMASK(2, 0));
1378	info->surf_val = (dword2 & GENMASK(31, 12)) >> 12;
1379	info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1);
1380
1381	info->ctrl_reg = DSPCNTR(info->pipe);
1382	info->stride_reg = DSPSTRIDE(info->pipe);
1383	info->surf_reg = DSPSURF(info->pipe);
1384
1385	return 0;
1386}
1387
1388static int gen8_check_mi_display_flip(struct parser_exec_state *s,
1389		struct mi_display_flip_command_info *info)
1390{
1391	u32 stride, tile;
1392
1393	if (!info->async_flip)
1394		return 0;
1395
1396	if (GRAPHICS_VER(s->engine->i915) >= 9) {
1397		stride = vgpu_vreg_t(s->vgpu, info->stride_reg) & GENMASK(9, 0);
1398		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) &
1399				GENMASK(12, 10)) >> 10;
1400	} else {
1401		stride = (vgpu_vreg_t(s->vgpu, info->stride_reg) &
1402				GENMASK(15, 6)) >> 6;
1403		tile = (vgpu_vreg_t(s->vgpu, info->ctrl_reg) & (1 << 10)) >> 10;
1404	}
1405
1406	if (stride != info->stride_val)
1407		gvt_dbg_cmd("cannot change stride during async flip\n");
1408
1409	if (tile != info->tile_val)
1410		gvt_dbg_cmd("cannot change tile during async flip\n");
1411
1412	return 0;
1413}
1414
1415static int gen8_update_plane_mmio_from_mi_display_flip(
1416		struct parser_exec_state *s,
1417		struct mi_display_flip_command_info *info)
1418{
1419	struct drm_i915_private *dev_priv = s->engine->i915;
1420	struct intel_vgpu *vgpu = s->vgpu;
1421
1422	set_mask_bits(&vgpu_vreg_t(vgpu, info->surf_reg), GENMASK(31, 12),
1423		      info->surf_val << 12);
1424	if (GRAPHICS_VER(dev_priv) >= 9) {
1425		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(9, 0),
1426			      info->stride_val);
1427		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(12, 10),
1428			      info->tile_val << 10);
1429	} else {
1430		set_mask_bits(&vgpu_vreg_t(vgpu, info->stride_reg), GENMASK(15, 6),
1431			      info->stride_val << 6);
1432		set_mask_bits(&vgpu_vreg_t(vgpu, info->ctrl_reg), GENMASK(10, 10),
1433			      info->tile_val << 10);
1434	}
1435
1436	if (info->plane == PLANE_PRIMARY)
1437		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++;
1438
1439	if (info->async_flip)
1440		intel_vgpu_trigger_virtual_event(vgpu, info->event);
1441	else
1442		set_bit(info->event, vgpu->irq.flip_done_event[info->pipe]);
1443
1444	return 0;
1445}
1446
1447static int decode_mi_display_flip(struct parser_exec_state *s,
1448		struct mi_display_flip_command_info *info)
1449{
1450	if (IS_BROADWELL(s->engine->i915))
1451		return gen8_decode_mi_display_flip(s, info);
1452	if (GRAPHICS_VER(s->engine->i915) >= 9)
1453		return skl_decode_mi_display_flip(s, info);
1454
1455	return -ENODEV;
1456}
1457
1458static int check_mi_display_flip(struct parser_exec_state *s,
1459		struct mi_display_flip_command_info *info)
1460{
1461	return gen8_check_mi_display_flip(s, info);
1462}
1463
1464static int update_plane_mmio_from_mi_display_flip(
1465		struct parser_exec_state *s,
1466		struct mi_display_flip_command_info *info)
1467{
1468	return gen8_update_plane_mmio_from_mi_display_flip(s, info);
1469}
1470
1471static int cmd_handler_mi_display_flip(struct parser_exec_state *s)
1472{
1473	struct mi_display_flip_command_info info;
1474	struct intel_vgpu *vgpu = s->vgpu;
1475	int ret;
1476	int i;
1477	int len = cmd_length(s);
1478	u32 valid_len = CMD_LEN(1);
1479
1480	/* Flip Type == Stereo 3D Flip */
1481	if (DWORD_FIELD(2, 1, 0) == 2)
1482		valid_len++;
1483	ret = gvt_check_valid_cmd_length(cmd_length(s),
1484			valid_len);
1485	if (ret)
1486		return ret;
1487
1488	ret = decode_mi_display_flip(s, &info);
1489	if (ret) {
1490		gvt_vgpu_err("fail to decode MI display flip command\n");
1491		return ret;
1492	}
1493
1494	ret = check_mi_display_flip(s, &info);
1495	if (ret) {
1496		gvt_vgpu_err("invalid MI display flip command\n");
1497		return ret;
1498	}
1499
1500	ret = update_plane_mmio_from_mi_display_flip(s, &info);
1501	if (ret) {
1502		gvt_vgpu_err("fail to update plane mmio\n");
1503		return ret;
1504	}
1505
1506	for (i = 0; i < len; i++)
1507		patch_value(s, cmd_ptr(s, i), MI_NOOP);
1508	return 0;
1509}
1510
1511static bool is_wait_for_flip_pending(u32 cmd)
1512{
1513	return cmd & (MI_WAIT_FOR_PLANE_A_FLIP_PENDING |
1514			MI_WAIT_FOR_PLANE_B_FLIP_PENDING |
1515			MI_WAIT_FOR_PLANE_C_FLIP_PENDING |
1516			MI_WAIT_FOR_SPRITE_A_FLIP_PENDING |
1517			MI_WAIT_FOR_SPRITE_B_FLIP_PENDING |
1518			MI_WAIT_FOR_SPRITE_C_FLIP_PENDING);
1519}
1520
1521static int cmd_handler_mi_wait_for_event(struct parser_exec_state *s)
1522{
1523	u32 cmd = cmd_val(s, 0);
1524
1525	if (!is_wait_for_flip_pending(cmd))
1526		return 0;
1527
1528	patch_value(s, cmd_ptr(s, 0), MI_NOOP);
1529	return 0;
1530}
1531
1532static unsigned long get_gma_bb_from_cmd(struct parser_exec_state *s, int index)
1533{
1534	unsigned long addr;
1535	unsigned long gma_high, gma_low;
1536	struct intel_vgpu *vgpu = s->vgpu;
1537	int gmadr_bytes = vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1538
1539	if (WARN_ON(gmadr_bytes != 4 && gmadr_bytes != 8)) {
1540		gvt_vgpu_err("invalid gma bytes %d\n", gmadr_bytes);
1541		return INTEL_GVT_INVALID_ADDR;
1542	}
1543
1544	gma_low = cmd_val(s, index) & BATCH_BUFFER_ADDR_MASK;
1545	if (gmadr_bytes == 4) {
1546		addr = gma_low;
1547	} else {
1548		gma_high = cmd_val(s, index + 1) & BATCH_BUFFER_ADDR_HIGH_MASK;
1549		addr = (((unsigned long)gma_high) << 32) | gma_low;
1550	}
1551	return addr;
1552}
1553
1554static inline int cmd_address_audit(struct parser_exec_state *s,
1555		unsigned long guest_gma, int op_size, bool index_mode)
1556{
1557	struct intel_vgpu *vgpu = s->vgpu;
1558	u32 max_surface_size = vgpu->gvt->device_info.max_surface_size;
1559	int i;
1560	int ret;
1561
1562	if (op_size > max_surface_size) {
1563		gvt_vgpu_err("command address audit fail name %s\n",
1564			s->info->name);
1565		return -EFAULT;
1566	}
1567
1568	if (index_mode)	{
1569		if (guest_gma >= I915_GTT_PAGE_SIZE) {
1570			ret = -EFAULT;
1571			goto err;
1572		}
1573	} else if (!intel_gvt_ggtt_validate_range(vgpu, guest_gma, op_size)) {
1574		ret = -EFAULT;
1575		goto err;
1576	}
1577
1578	return 0;
1579
1580err:
1581	gvt_vgpu_err("cmd_parser: Malicious %s detected, addr=0x%lx, len=%d!\n",
1582			s->info->name, guest_gma, op_size);
1583
1584	pr_err("cmd dump: ");
1585	for (i = 0; i < cmd_length(s); i++) {
1586		if (!(i % 4))
1587			pr_err("\n%08x ", cmd_val(s, i));
1588		else
1589			pr_err("%08x ", cmd_val(s, i));
1590	}
1591	pr_err("\nvgpu%d: aperture 0x%llx - 0x%llx, hidden 0x%llx - 0x%llx\n",
1592			vgpu->id,
1593			vgpu_aperture_gmadr_base(vgpu),
1594			vgpu_aperture_gmadr_end(vgpu),
1595			vgpu_hidden_gmadr_base(vgpu),
1596			vgpu_hidden_gmadr_end(vgpu));
1597	return ret;
1598}
1599
1600static int cmd_handler_mi_store_data_imm(struct parser_exec_state *s)
1601{
1602	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1603	int op_size = (cmd_length(s) - 3) * sizeof(u32);
1604	int core_id = (cmd_val(s, 2) & (1 << 0)) ? 1 : 0;
1605	unsigned long gma, gma_low, gma_high;
1606	u32 valid_len = CMD_LEN(2);
1607	int ret = 0;
1608
1609	/* check ppggt */
1610	if (!(cmd_val(s, 0) & (1 << 22)))
1611		return 0;
1612
1613	/* check if QWORD */
1614	if (DWORD_FIELD(0, 21, 21))
1615		valid_len++;
1616	ret = gvt_check_valid_cmd_length(cmd_length(s),
1617			valid_len);
1618	if (ret)
1619		return ret;
1620
1621	gma = cmd_val(s, 2) & GENMASK(31, 2);
1622
1623	if (gmadr_bytes == 8) {
1624		gma_low = cmd_val(s, 1) & GENMASK(31, 2);
1625		gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1626		gma = (gma_high << 32) | gma_low;
1627		core_id = (cmd_val(s, 1) & (1 << 0)) ? 1 : 0;
1628	}
1629	ret = cmd_address_audit(s, gma + op_size * core_id, op_size, false);
1630	return ret;
1631}
1632
1633static inline int unexpected_cmd(struct parser_exec_state *s)
1634{
1635	struct intel_vgpu *vgpu = s->vgpu;
1636
1637	gvt_vgpu_err("Unexpected %s in command buffer!\n", s->info->name);
1638
1639	return -EBADRQC;
1640}
1641
1642static int cmd_handler_mi_semaphore_wait(struct parser_exec_state *s)
1643{
1644	return unexpected_cmd(s);
1645}
1646
1647static int cmd_handler_mi_report_perf_count(struct parser_exec_state *s)
1648{
1649	return unexpected_cmd(s);
1650}
1651
1652static int cmd_handler_mi_op_2e(struct parser_exec_state *s)
1653{
1654	return unexpected_cmd(s);
1655}
1656
1657static int cmd_handler_mi_op_2f(struct parser_exec_state *s)
1658{
1659	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1660	int op_size = (1 << ((cmd_val(s, 0) & GENMASK(20, 19)) >> 19)) *
1661			sizeof(u32);
1662	unsigned long gma, gma_high;
1663	u32 valid_len = CMD_LEN(1);
1664	int ret = 0;
1665
1666	if (!(cmd_val(s, 0) & (1 << 22)))
1667		return ret;
1668
1669	/* check inline data */
1670	if (cmd_val(s, 0) & BIT(18))
1671		valid_len = CMD_LEN(9);
1672	ret = gvt_check_valid_cmd_length(cmd_length(s),
1673			valid_len);
1674	if (ret)
1675		return ret;
1676
1677	gma = cmd_val(s, 1) & GENMASK(31, 2);
1678	if (gmadr_bytes == 8) {
1679		gma_high = cmd_val(s, 2) & GENMASK(15, 0);
1680		gma = (gma_high << 32) | gma;
1681	}
1682	ret = cmd_address_audit(s, gma, op_size, false);
1683	return ret;
1684}
1685
1686static int cmd_handler_mi_store_data_index(struct parser_exec_state *s)
1687{
1688	return unexpected_cmd(s);
1689}
1690
1691static int cmd_handler_mi_clflush(struct parser_exec_state *s)
1692{
1693	return unexpected_cmd(s);
1694}
1695
1696static int cmd_handler_mi_conditional_batch_buffer_end(
1697		struct parser_exec_state *s)
1698{
1699	return unexpected_cmd(s);
1700}
1701
1702static int cmd_handler_mi_update_gtt(struct parser_exec_state *s)
1703{
1704	return unexpected_cmd(s);
1705}
1706
1707static int cmd_handler_mi_flush_dw(struct parser_exec_state *s)
1708{
1709	int gmadr_bytes = s->vgpu->gvt->device_info.gmadr_bytes_in_cmd;
1710	unsigned long gma;
1711	bool index_mode = false;
1712	int ret = 0;
1713	u32 hws_pga, val;
1714	u32 valid_len = CMD_LEN(2);
1715
1716	ret = gvt_check_valid_cmd_length(cmd_length(s),
1717			valid_len);
1718	if (ret) {
1719		/* Check again for Qword */
1720		ret = gvt_check_valid_cmd_length(cmd_length(s),
1721			++valid_len);
1722		return ret;
1723	}
1724
1725	/* Check post-sync and ppgtt bit */
1726	if (((cmd_val(s, 0) >> 14) & 0x3) && (cmd_val(s, 1) & (1 << 2))) {
1727		gma = cmd_val(s, 1) & GENMASK(31, 3);
1728		if (gmadr_bytes == 8)
1729			gma |= (cmd_val(s, 2) & GENMASK(15, 0)) << 32;
1730		/* Store Data Index */
1731		if (cmd_val(s, 0) & (1 << 21))
1732			index_mode = true;
1733		ret = cmd_address_audit(s, gma, sizeof(u64), index_mode);
1734		if (ret)
1735			return ret;
1736		if (index_mode) {
1737			hws_pga = s->vgpu->hws_pga[s->engine->id];
1738			gma = hws_pga + gma;
1739			patch_value(s, cmd_ptr(s, 1), gma);
1740			val = cmd_val(s, 0) & (~(1 << 21));
1741			patch_value(s, cmd_ptr(s, 0), val);
1742		}
1743	}
1744	/* Check notify bit */
1745	if ((cmd_val(s, 0) & (1 << 8)))
1746		set_bit(cmd_interrupt_events[s->engine->id].mi_flush_dw,
1747			s->workload->pending_events);
1748	return ret;
1749}
1750
1751static void addr_type_update_snb(struct parser_exec_state *s)
1752{
1753	if ((s->buf_type == RING_BUFFER_INSTRUCTION) &&
1754			(BATCH_BUFFER_ADR_SPACE_BIT(cmd_val(s, 0)) == 1)) {
1755		s->buf_addr_type = PPGTT_BUFFER;
1756	}
1757}
1758
1759
1760static int copy_gma_to_hva(struct intel_vgpu *vgpu, struct intel_vgpu_mm *mm,
1761		unsigned long gma, unsigned long end_gma, void *va)
1762{
1763	unsigned long copy_len, offset;
1764	unsigned long len = 0;
1765	unsigned long gpa;
1766
1767	while (gma != end_gma) {
1768		gpa = intel_vgpu_gma_to_gpa(mm, gma);
1769		if (gpa == INTEL_GVT_INVALID_ADDR) {
1770			gvt_vgpu_err("invalid gma address: %lx\n", gma);
1771			return -EFAULT;
1772		}
1773
1774		offset = gma & (I915_GTT_PAGE_SIZE - 1);
1775
1776		copy_len = (end_gma - gma) >= (I915_GTT_PAGE_SIZE - offset) ?
1777			I915_GTT_PAGE_SIZE - offset : end_gma - gma;
1778
1779		intel_gvt_read_gpa(vgpu, gpa, va + len, copy_len);
1780
1781		len += copy_len;
1782		gma += copy_len;
1783	}
1784	return len;
1785}
1786
1787
1788/*
1789 * Check whether a batch buffer needs to be scanned. Currently
1790 * the only criteria is based on privilege.
1791 */
1792static int batch_buffer_needs_scan(struct parser_exec_state *s)
1793{
1794	/* Decide privilege based on address space */
1795	if (cmd_val(s, 0) & BIT(8) &&
1796	    !(s->vgpu->scan_nonprivbb & s->engine->mask))
1797		return 0;
1798
1799	return 1;
1800}
1801
1802static const char *repr_addr_type(unsigned int type)
1803{
1804	return type == PPGTT_BUFFER ? "ppgtt" : "ggtt";
1805}
1806
1807static int find_bb_size(struct parser_exec_state *s,
1808			unsigned long *bb_size,
1809			unsigned long *bb_end_cmd_offset)
1810{
1811	unsigned long gma = 0;
1812	const struct cmd_info *info;
1813	u32 cmd_len = 0;
1814	bool bb_end = false;
1815	struct intel_vgpu *vgpu = s->vgpu;
1816	u32 cmd;
1817	struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1818		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1819
1820	*bb_size = 0;
1821	*bb_end_cmd_offset = 0;
1822
1823	/* get the start gm address of the batch buffer */
1824	gma = get_gma_bb_from_cmd(s, 1);
1825	if (gma == INTEL_GVT_INVALID_ADDR)
1826		return -EFAULT;
1827
1828	cmd = cmd_val(s, 0);
1829	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1830	if (info == NULL) {
1831		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1832			     cmd, get_opcode(cmd, s->engine),
1833			     repr_addr_type(s->buf_addr_type),
1834			     s->engine->name, s->workload);
1835		return -EBADRQC;
1836	}
1837	do {
1838		if (copy_gma_to_hva(s->vgpu, mm,
1839				    gma, gma + 4, &cmd) < 0)
1840			return -EFAULT;
1841		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1842		if (info == NULL) {
1843			gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1844				     cmd, get_opcode(cmd, s->engine),
1845				     repr_addr_type(s->buf_addr_type),
1846				     s->engine->name, s->workload);
1847			return -EBADRQC;
1848		}
1849
1850		if (info->opcode == OP_MI_BATCH_BUFFER_END) {
1851			bb_end = true;
1852		} else if (info->opcode == OP_MI_BATCH_BUFFER_START) {
1853			if (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)
1854				/* chained batch buffer */
1855				bb_end = true;
1856		}
1857
1858		if (bb_end)
1859			*bb_end_cmd_offset = *bb_size;
1860
1861		cmd_len = get_cmd_length(info, cmd) << 2;
1862		*bb_size += cmd_len;
1863		gma += cmd_len;
1864	} while (!bb_end);
1865
1866	return 0;
1867}
1868
1869static int audit_bb_end(struct parser_exec_state *s, void *va)
1870{
1871	struct intel_vgpu *vgpu = s->vgpu;
1872	u32 cmd = *(u32 *)va;
1873	const struct cmd_info *info;
1874
1875	info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
1876	if (info == NULL) {
1877		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
1878			     cmd, get_opcode(cmd, s->engine),
1879			     repr_addr_type(s->buf_addr_type),
1880			     s->engine->name, s->workload);
1881		return -EBADRQC;
1882	}
1883
1884	if ((info->opcode == OP_MI_BATCH_BUFFER_END) ||
1885	    ((info->opcode == OP_MI_BATCH_BUFFER_START) &&
1886	     (BATCH_BUFFER_2ND_LEVEL_BIT(cmd) == 0)))
1887		return 0;
1888
1889	return -EBADRQC;
1890}
1891
1892static int perform_bb_shadow(struct parser_exec_state *s)
1893{
1894	struct intel_vgpu *vgpu = s->vgpu;
1895	struct intel_vgpu_shadow_bb *bb;
1896	unsigned long gma = 0;
1897	unsigned long bb_size;
1898	unsigned long bb_end_cmd_offset;
1899	int ret = 0;
1900	struct intel_vgpu_mm *mm = (s->buf_addr_type == GTT_BUFFER) ?
1901		s->vgpu->gtt.ggtt_mm : s->workload->shadow_mm;
1902	unsigned long start_offset = 0;
1903
1904	/* get the start gm address of the batch buffer */
1905	gma = get_gma_bb_from_cmd(s, 1);
1906	if (gma == INTEL_GVT_INVALID_ADDR)
1907		return -EFAULT;
1908
1909	ret = find_bb_size(s, &bb_size, &bb_end_cmd_offset);
1910	if (ret)
1911		return ret;
1912
1913	bb = kzalloc(sizeof(*bb), GFP_KERNEL);
1914	if (!bb)
1915		return -ENOMEM;
1916
1917	bb->ppgtt = (s->buf_addr_type == GTT_BUFFER) ? false : true;
1918
1919	/* the start_offset stores the batch buffer's start gma's
1920	 * offset relative to page boundary. so for non-privileged batch
1921	 * buffer, the shadowed gem object holds exactly the same page
1922	 * layout as original gem object. This is for the convience of
1923	 * replacing the whole non-privilged batch buffer page to this
1924	 * shadowed one in PPGTT at the same gma address. (this replacing
1925	 * action is not implemented yet now, but may be necessary in
1926	 * future).
1927	 * for prileged batch buffer, we just change start gma address to
1928	 * that of shadowed page.
1929	 */
1930	if (bb->ppgtt)
1931		start_offset = gma & ~I915_GTT_PAGE_MASK;
1932
1933	bb->obj = i915_gem_object_create_shmem(s->engine->i915,
1934					       round_up(bb_size + start_offset,
1935							PAGE_SIZE));
1936	if (IS_ERR(bb->obj)) {
1937		ret = PTR_ERR(bb->obj);
1938		goto err_free_bb;
1939	}
1940
1941	bb->va = i915_gem_object_pin_map(bb->obj, I915_MAP_WB);
1942	if (IS_ERR(bb->va)) {
1943		ret = PTR_ERR(bb->va);
1944		goto err_free_obj;
1945	}
1946
1947	ret = copy_gma_to_hva(s->vgpu, mm,
1948			      gma, gma + bb_size,
1949			      bb->va + start_offset);
1950	if (ret < 0) {
1951		gvt_vgpu_err("fail to copy guest ring buffer\n");
1952		ret = -EFAULT;
1953		goto err_unmap;
1954	}
1955
1956	ret = audit_bb_end(s, bb->va + start_offset + bb_end_cmd_offset);
1957	if (ret)
1958		goto err_unmap;
1959
1960	i915_gem_object_unlock(bb->obj);
1961	INIT_LIST_HEAD(&bb->list);
1962	list_add(&bb->list, &s->workload->shadow_bb);
1963
1964	bb->bb_start_cmd_va = s->ip_va;
1965
1966	if ((s->buf_type == BATCH_BUFFER_INSTRUCTION) && (!s->is_ctx_wa))
1967		bb->bb_offset = s->ip_va - s->rb_va;
1968	else
1969		bb->bb_offset = 0;
1970
1971	/*
1972	 * ip_va saves the virtual address of the shadow batch buffer, while
1973	 * ip_gma saves the graphics address of the original batch buffer.
1974	 * As the shadow batch buffer is just a copy from the originial one,
1975	 * it should be right to use shadow batch buffer'va and original batch
1976	 * buffer's gma in pair. After all, we don't want to pin the shadow
1977	 * buffer here (too early).
1978	 */
1979	s->ip_va = bb->va + start_offset;
1980	s->ip_gma = gma;
1981	return 0;
1982err_unmap:
1983	i915_gem_object_unpin_map(bb->obj);
1984err_free_obj:
1985	i915_gem_object_put(bb->obj);
1986err_free_bb:
1987	kfree(bb);
1988	return ret;
1989}
1990
1991static int cmd_handler_mi_batch_buffer_start(struct parser_exec_state *s)
1992{
1993	bool second_level;
1994	int ret = 0;
1995	struct intel_vgpu *vgpu = s->vgpu;
1996
1997	if (s->buf_type == BATCH_BUFFER_2ND_LEVEL) {
1998		gvt_vgpu_err("Found MI_BATCH_BUFFER_START in 2nd level BB\n");
1999		return -EFAULT;
2000	}
2001
2002	second_level = BATCH_BUFFER_2ND_LEVEL_BIT(cmd_val(s, 0)) == 1;
2003	if (second_level && (s->buf_type != BATCH_BUFFER_INSTRUCTION)) {
2004		gvt_vgpu_err("Jumping to 2nd level BB from RB is not allowed\n");
2005		return -EFAULT;
2006	}
2007
2008	s->saved_buf_addr_type = s->buf_addr_type;
2009	addr_type_update_snb(s);
2010	if (s->buf_type == RING_BUFFER_INSTRUCTION) {
2011		s->ret_ip_gma_ring = s->ip_gma + cmd_length(s) * sizeof(u32);
2012		s->buf_type = BATCH_BUFFER_INSTRUCTION;
2013	} else if (second_level) {
2014		s->buf_type = BATCH_BUFFER_2ND_LEVEL;
2015		s->ret_ip_gma_bb = s->ip_gma + cmd_length(s) * sizeof(u32);
2016		s->ret_bb_va = s->ip_va + cmd_length(s) * sizeof(u32);
2017	}
2018
2019	if (batch_buffer_needs_scan(s)) {
2020		ret = perform_bb_shadow(s);
2021		if (ret < 0)
2022			gvt_vgpu_err("invalid shadow batch buffer\n");
2023	} else {
2024		/* emulate a batch buffer end to do return right */
2025		ret = cmd_handler_mi_batch_buffer_end(s);
2026		if (ret < 0)
2027			return ret;
2028	}
2029	return ret;
2030}
2031
2032static int mi_noop_index;
2033
2034static const struct cmd_info cmd_info[] = {
2035	{"MI_NOOP", OP_MI_NOOP, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2036
2037	{"MI_SET_PREDICATE", OP_MI_SET_PREDICATE, F_LEN_CONST, R_ALL, D_ALL,
2038		0, 1, NULL},
2039
2040	{"MI_USER_INTERRUPT", OP_MI_USER_INTERRUPT, F_LEN_CONST, R_ALL, D_ALL,
2041		0, 1, cmd_handler_mi_user_interrupt},
2042
2043	{"MI_WAIT_FOR_EVENT", OP_MI_WAIT_FOR_EVENT, F_LEN_CONST, R_RCS | R_BCS,
2044		D_ALL, 0, 1, cmd_handler_mi_wait_for_event},
2045
2046	{"MI_FLUSH", OP_MI_FLUSH, F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2047
2048	{"MI_ARB_CHECK", OP_MI_ARB_CHECK, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2049		NULL},
2050
2051	{"MI_RS_CONTROL", OP_MI_RS_CONTROL, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2052		NULL},
2053
2054	{"MI_REPORT_HEAD", OP_MI_REPORT_HEAD, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2055		NULL},
2056
2057	{"MI_ARB_ON_OFF", OP_MI_ARB_ON_OFF, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2058		NULL},
2059
2060	{"MI_URB_ATOMIC_ALLOC", OP_MI_URB_ATOMIC_ALLOC, F_LEN_CONST, R_RCS,
2061		D_ALL, 0, 1, NULL},
2062
2063	{"MI_BATCH_BUFFER_END", OP_MI_BATCH_BUFFER_END,
2064		F_IP_ADVANCE_CUSTOM | F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2065		cmd_handler_mi_batch_buffer_end},
2066
2067	{"MI_SUSPEND_FLUSH", OP_MI_SUSPEND_FLUSH, F_LEN_CONST, R_ALL, D_ALL,
2068		0, 1, NULL},
2069
2070	{"MI_PREDICATE", OP_MI_PREDICATE, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2071		NULL},
2072
2073	{"MI_TOPOLOGY_FILTER", OP_MI_TOPOLOGY_FILTER, F_LEN_CONST, R_ALL,
2074		D_ALL, 0, 1, NULL},
2075
2076	{"MI_SET_APPID", OP_MI_SET_APPID, F_LEN_CONST, R_ALL, D_ALL, 0, 1,
2077		NULL},
2078
2079	{"MI_RS_CONTEXT", OP_MI_RS_CONTEXT, F_LEN_CONST, R_RCS, D_ALL, 0, 1,
2080		NULL},
2081
2082	{"MI_DISPLAY_FLIP", OP_MI_DISPLAY_FLIP, F_LEN_VAR,
2083		R_RCS | R_BCS, D_ALL, 0, 8, cmd_handler_mi_display_flip},
2084
2085	{"MI_SEMAPHORE_MBOX", OP_MI_SEMAPHORE_MBOX, F_LEN_VAR | F_LEN_VAR_FIXED,
2086		R_ALL, D_ALL, 0, 8, NULL, CMD_LEN(1)},
2087
2088	{"MI_MATH", OP_MI_MATH, F_LEN_VAR, R_ALL, D_ALL, 0, 8, NULL},
2089
2090	{"MI_URB_CLEAR", OP_MI_URB_CLEAR, F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS,
2091		D_ALL, 0, 8, NULL, CMD_LEN(0)},
2092
2093	{"MI_SEMAPHORE_SIGNAL", OP_MI_SEMAPHORE_SIGNAL,
2094		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, 0, 8,
2095		NULL, CMD_LEN(0)},
2096
2097	{"MI_SEMAPHORE_WAIT", OP_MI_SEMAPHORE_WAIT,
2098		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS, ADDR_FIX_1(2),
2099		8, cmd_handler_mi_semaphore_wait, CMD_LEN(2)},
2100
2101	{"MI_STORE_DATA_IMM", OP_MI_STORE_DATA_IMM, F_LEN_VAR, R_ALL, D_BDW_PLUS,
2102		ADDR_FIX_1(1), 10, cmd_handler_mi_store_data_imm},
2103
2104	{"MI_STORE_DATA_INDEX", OP_MI_STORE_DATA_INDEX, F_LEN_VAR, R_ALL, D_ALL,
2105		0, 8, cmd_handler_mi_store_data_index},
2106
2107	{"MI_LOAD_REGISTER_IMM", OP_MI_LOAD_REGISTER_IMM, F_LEN_VAR, R_ALL,
2108		D_ALL, 0, 8, cmd_handler_lri},
2109
2110	{"MI_UPDATE_GTT", OP_MI_UPDATE_GTT, F_LEN_VAR, R_ALL, D_BDW_PLUS, 0, 10,
2111		cmd_handler_mi_update_gtt},
2112
2113	{"MI_STORE_REGISTER_MEM", OP_MI_STORE_REGISTER_MEM,
2114		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2115		cmd_handler_srm, CMD_LEN(2)},
2116
2117	{"MI_FLUSH_DW", OP_MI_FLUSH_DW, F_LEN_VAR, R_ALL, D_ALL, 0, 6,
2118		cmd_handler_mi_flush_dw},
2119
2120	{"MI_CLFLUSH", OP_MI_CLFLUSH, F_LEN_VAR, R_ALL, D_ALL, ADDR_FIX_1(1),
2121		10, cmd_handler_mi_clflush},
2122
2123	{"MI_REPORT_PERF_COUNT", OP_MI_REPORT_PERF_COUNT,
2124		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(1), 6,
2125		cmd_handler_mi_report_perf_count, CMD_LEN(2)},
2126
2127	{"MI_LOAD_REGISTER_MEM", OP_MI_LOAD_REGISTER_MEM,
2128		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2129		cmd_handler_lrm, CMD_LEN(2)},
2130
2131	{"MI_LOAD_REGISTER_REG", OP_MI_LOAD_REGISTER_REG,
2132		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, 0, 8,
2133		cmd_handler_lrr, CMD_LEN(1)},
2134
2135	{"MI_RS_STORE_DATA_IMM", OP_MI_RS_STORE_DATA_IMM,
2136		F_LEN_VAR | F_LEN_VAR_FIXED, R_RCS, D_ALL, 0,
2137		8, NULL, CMD_LEN(2)},
2138
2139	{"MI_LOAD_URB_MEM", OP_MI_LOAD_URB_MEM, F_LEN_VAR | F_LEN_VAR_FIXED,
2140		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL, CMD_LEN(2)},
2141
2142	{"MI_STORE_URM_MEM", OP_MI_STORE_URM_MEM, F_LEN_VAR, R_RCS, D_ALL,
2143		ADDR_FIX_1(2), 8, NULL},
2144
2145	{"MI_OP_2E", OP_MI_2E, F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_BDW_PLUS,
2146		ADDR_FIX_2(1, 2), 8, cmd_handler_mi_op_2e, CMD_LEN(3)},
2147
2148	{"MI_OP_2F", OP_MI_2F, F_LEN_VAR, R_ALL, D_BDW_PLUS, ADDR_FIX_1(1),
2149		8, cmd_handler_mi_op_2f},
2150
2151	{"MI_BATCH_BUFFER_START", OP_MI_BATCH_BUFFER_START,
2152		F_IP_ADVANCE_CUSTOM, R_ALL, D_ALL, 0, 8,
2153		cmd_handler_mi_batch_buffer_start},
2154
2155	{"MI_CONDITIONAL_BATCH_BUFFER_END", OP_MI_CONDITIONAL_BATCH_BUFFER_END,
2156		F_LEN_VAR | F_LEN_VAR_FIXED, R_ALL, D_ALL, ADDR_FIX_1(2), 8,
2157		cmd_handler_mi_conditional_batch_buffer_end, CMD_LEN(2)},
2158
2159	{"MI_LOAD_SCAN_LINES_INCL", OP_MI_LOAD_SCAN_LINES_INCL, F_LEN_CONST,
2160		R_RCS | R_BCS, D_ALL, 0, 2, NULL},
2161
2162	{"XY_SETUP_BLT", OP_XY_SETUP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2163		ADDR_FIX_2(4, 7), 8, NULL},
2164
2165	{"XY_SETUP_CLIP_BLT", OP_XY_SETUP_CLIP_BLT, F_LEN_VAR, R_BCS, D_ALL,
2166		0, 8, NULL},
2167
2168	{"XY_SETUP_MONO_PATTERN_SL_BLT", OP_XY_SETUP_MONO_PATTERN_SL_BLT,
2169		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2170
2171	{"XY_PIXEL_BLT", OP_XY_PIXEL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2172
2173	{"XY_SCANLINES_BLT", OP_XY_SCANLINES_BLT, F_LEN_VAR, R_BCS, D_ALL,
2174		0, 8, NULL},
2175
2176	{"XY_TEXT_BLT", OP_XY_TEXT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2177		ADDR_FIX_1(3), 8, NULL},
2178
2179	{"XY_TEXT_IMMEDIATE_BLT", OP_XY_TEXT_IMMEDIATE_BLT, F_LEN_VAR, R_BCS,
2180		D_ALL, 0, 8, NULL},
2181
2182	{"XY_COLOR_BLT", OP_XY_COLOR_BLT, F_LEN_VAR, R_BCS, D_ALL,
2183		ADDR_FIX_1(4), 8, NULL},
2184
2185	{"XY_PAT_BLT", OP_XY_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2186		ADDR_FIX_2(4, 5), 8, NULL},
2187
2188	{"XY_MONO_PAT_BLT", OP_XY_MONO_PAT_BLT, F_LEN_VAR, R_BCS, D_ALL,
2189		ADDR_FIX_1(4), 8, NULL},
2190
2191	{"XY_SRC_COPY_BLT", OP_XY_SRC_COPY_BLT, F_LEN_VAR, R_BCS, D_ALL,
2192		ADDR_FIX_2(4, 7), 8, NULL},
2193
2194	{"XY_MONO_SRC_COPY_BLT", OP_XY_MONO_SRC_COPY_BLT, F_LEN_VAR, R_BCS,
2195		D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2196
2197	{"XY_FULL_BLT", OP_XY_FULL_BLT, F_LEN_VAR, R_BCS, D_ALL, 0, 8, NULL},
2198
2199	{"XY_FULL_MONO_SRC_BLT", OP_XY_FULL_MONO_SRC_BLT, F_LEN_VAR, R_BCS,
2200		D_ALL, ADDR_FIX_3(4, 5, 8), 8, NULL},
2201
2202	{"XY_FULL_MONO_PATTERN_BLT", OP_XY_FULL_MONO_PATTERN_BLT, F_LEN_VAR,
2203		R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2204
2205	{"XY_FULL_MONO_PATTERN_MONO_SRC_BLT",
2206		OP_XY_FULL_MONO_PATTERN_MONO_SRC_BLT,
2207		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2208
2209	{"XY_MONO_PAT_FIXED_BLT", OP_XY_MONO_PAT_FIXED_BLT, F_LEN_VAR, R_BCS,
2210		D_ALL, ADDR_FIX_1(4), 8, NULL},
2211
2212	{"XY_MONO_SRC_COPY_IMMEDIATE_BLT", OP_XY_MONO_SRC_COPY_IMMEDIATE_BLT,
2213		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2214
2215	{"XY_PAT_BLT_IMMEDIATE", OP_XY_PAT_BLT_IMMEDIATE, F_LEN_VAR, R_BCS,
2216		D_ALL, ADDR_FIX_1(4), 8, NULL},
2217
2218	{"XY_SRC_COPY_CHROMA_BLT", OP_XY_SRC_COPY_CHROMA_BLT, F_LEN_VAR, R_BCS,
2219		D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2220
2221	{"XY_FULL_IMMEDIATE_PATTERN_BLT", OP_XY_FULL_IMMEDIATE_PATTERN_BLT,
2222		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 7), 8, NULL},
2223
2224	{"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
2225		OP_XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT,
2226		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_2(4, 5), 8, NULL},
2227
2228	{"XY_PAT_CHROMA_BLT", OP_XY_PAT_CHROMA_BLT, F_LEN_VAR, R_BCS, D_ALL,
2229		ADDR_FIX_2(4, 5), 8, NULL},
2230
2231	{"XY_PAT_CHROMA_BLT_IMMEDIATE", OP_XY_PAT_CHROMA_BLT_IMMEDIATE,
2232		F_LEN_VAR, R_BCS, D_ALL, ADDR_FIX_1(4), 8, NULL},
2233
2234	{"3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP",
2235		OP_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
2236		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2237
2238	{"3DSTATE_VIEWPORT_STATE_POINTERS_CC",
2239		OP_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2240		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2241
2242	{"3DSTATE_BLEND_STATE_POINTERS",
2243		OP_3DSTATE_BLEND_STATE_POINTERS,
2244		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2245
2246	{"3DSTATE_DEPTH_STENCIL_STATE_POINTERS",
2247		OP_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2248		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2249
2250	{"3DSTATE_BINDING_TABLE_POINTERS_VS",
2251		OP_3DSTATE_BINDING_TABLE_POINTERS_VS,
2252		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2253
2254	{"3DSTATE_BINDING_TABLE_POINTERS_HS",
2255		OP_3DSTATE_BINDING_TABLE_POINTERS_HS,
2256		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2257
2258	{"3DSTATE_BINDING_TABLE_POINTERS_DS",
2259		OP_3DSTATE_BINDING_TABLE_POINTERS_DS,
2260		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2261
2262	{"3DSTATE_BINDING_TABLE_POINTERS_GS",
2263		OP_3DSTATE_BINDING_TABLE_POINTERS_GS,
2264		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2265
2266	{"3DSTATE_BINDING_TABLE_POINTERS_PS",
2267		OP_3DSTATE_BINDING_TABLE_POINTERS_PS,
2268		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2269
2270	{"3DSTATE_SAMPLER_STATE_POINTERS_VS",
2271		OP_3DSTATE_SAMPLER_STATE_POINTERS_VS,
2272		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2273
2274	{"3DSTATE_SAMPLER_STATE_POINTERS_HS",
2275		OP_3DSTATE_SAMPLER_STATE_POINTERS_HS,
2276		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2277
2278	{"3DSTATE_SAMPLER_STATE_POINTERS_DS",
2279		OP_3DSTATE_SAMPLER_STATE_POINTERS_DS,
2280		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2281
2282	{"3DSTATE_SAMPLER_STATE_POINTERS_GS",
2283		OP_3DSTATE_SAMPLER_STATE_POINTERS_GS,
2284		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2285
2286	{"3DSTATE_SAMPLER_STATE_POINTERS_PS",
2287		OP_3DSTATE_SAMPLER_STATE_POINTERS_PS,
2288		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2289
2290	{"3DSTATE_URB_VS", OP_3DSTATE_URB_VS, F_LEN_VAR, R_RCS, D_ALL,
2291		0, 8, NULL},
2292
2293	{"3DSTATE_URB_HS", OP_3DSTATE_URB_HS, F_LEN_VAR, R_RCS, D_ALL,
2294		0, 8, NULL},
2295
2296	{"3DSTATE_URB_DS", OP_3DSTATE_URB_DS, F_LEN_VAR, R_RCS, D_ALL,
2297		0, 8, NULL},
2298
2299	{"3DSTATE_URB_GS", OP_3DSTATE_URB_GS, F_LEN_VAR, R_RCS, D_ALL,
2300		0, 8, NULL},
2301
2302	{"3DSTATE_GATHER_CONSTANT_VS", OP_3DSTATE_GATHER_CONSTANT_VS,
2303		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2304
2305	{"3DSTATE_GATHER_CONSTANT_GS", OP_3DSTATE_GATHER_CONSTANT_GS,
2306		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2307
2308	{"3DSTATE_GATHER_CONSTANT_HS", OP_3DSTATE_GATHER_CONSTANT_HS,
2309		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2310
2311	{"3DSTATE_GATHER_CONSTANT_DS", OP_3DSTATE_GATHER_CONSTANT_DS,
2312		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2313
2314	{"3DSTATE_GATHER_CONSTANT_PS", OP_3DSTATE_GATHER_CONSTANT_PS,
2315		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2316
2317	{"3DSTATE_DX9_CONSTANTF_VS", OP_3DSTATE_DX9_CONSTANTF_VS,
2318		F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2319
2320	{"3DSTATE_DX9_CONSTANTF_PS", OP_3DSTATE_DX9_CONSTANTF_PS,
2321		F_LEN_VAR, R_RCS, D_ALL, 0, 11, NULL},
2322
2323	{"3DSTATE_DX9_CONSTANTI_VS", OP_3DSTATE_DX9_CONSTANTI_VS,
2324		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2325
2326	{"3DSTATE_DX9_CONSTANTI_PS", OP_3DSTATE_DX9_CONSTANTI_PS,
2327		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2328
2329	{"3DSTATE_DX9_CONSTANTB_VS", OP_3DSTATE_DX9_CONSTANTB_VS,
2330		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2331
2332	{"3DSTATE_DX9_CONSTANTB_PS", OP_3DSTATE_DX9_CONSTANTB_PS,
2333		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2334
2335	{"3DSTATE_DX9_LOCAL_VALID_VS", OP_3DSTATE_DX9_LOCAL_VALID_VS,
2336		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2337
2338	{"3DSTATE_DX9_LOCAL_VALID_PS", OP_3DSTATE_DX9_LOCAL_VALID_PS,
2339		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2340
2341	{"3DSTATE_DX9_GENERATE_ACTIVE_VS", OP_3DSTATE_DX9_GENERATE_ACTIVE_VS,
2342		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2343
2344	{"3DSTATE_DX9_GENERATE_ACTIVE_PS", OP_3DSTATE_DX9_GENERATE_ACTIVE_PS,
2345		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2346
2347	{"3DSTATE_BINDING_TABLE_EDIT_VS", OP_3DSTATE_BINDING_TABLE_EDIT_VS,
2348		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2349
2350	{"3DSTATE_BINDING_TABLE_EDIT_GS", OP_3DSTATE_BINDING_TABLE_EDIT_GS,
2351		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2352
2353	{"3DSTATE_BINDING_TABLE_EDIT_HS", OP_3DSTATE_BINDING_TABLE_EDIT_HS,
2354		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2355
2356	{"3DSTATE_BINDING_TABLE_EDIT_DS", OP_3DSTATE_BINDING_TABLE_EDIT_DS,
2357		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2358
2359	{"3DSTATE_BINDING_TABLE_EDIT_PS", OP_3DSTATE_BINDING_TABLE_EDIT_PS,
2360		F_LEN_VAR, R_RCS, D_ALL, 0, 9, NULL},
2361
2362	{"3DSTATE_VF_INSTANCING", OP_3DSTATE_VF_INSTANCING, F_LEN_VAR, R_RCS,
2363		D_BDW_PLUS, 0, 8, NULL},
2364
2365	{"3DSTATE_VF_SGVS", OP_3DSTATE_VF_SGVS, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2366		NULL},
2367
2368	{"3DSTATE_VF_TOPOLOGY", OP_3DSTATE_VF_TOPOLOGY, F_LEN_VAR, R_RCS,
2369		D_BDW_PLUS, 0, 8, NULL},
2370
2371	{"3DSTATE_WM_CHROMAKEY", OP_3DSTATE_WM_CHROMAKEY, F_LEN_VAR, R_RCS,
2372		D_BDW_PLUS, 0, 8, NULL},
2373
2374	{"3DSTATE_PS_BLEND", OP_3DSTATE_PS_BLEND, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2375		8, NULL},
2376
2377	{"3DSTATE_WM_DEPTH_STENCIL", OP_3DSTATE_WM_DEPTH_STENCIL, F_LEN_VAR,
2378		R_RCS, D_BDW_PLUS, 0, 8, NULL},
2379
2380	{"3DSTATE_PS_EXTRA", OP_3DSTATE_PS_EXTRA, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0,
2381		8, NULL},
2382
2383	{"3DSTATE_RASTER", OP_3DSTATE_RASTER, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2384		NULL},
2385
2386	{"3DSTATE_SBE_SWIZ", OP_3DSTATE_SBE_SWIZ, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2387		NULL},
2388
2389	{"3DSTATE_WM_HZ_OP", OP_3DSTATE_WM_HZ_OP, F_LEN_VAR, R_RCS, D_BDW_PLUS, 0, 8,
2390		NULL},
2391
2392	{"3DSTATE_VERTEX_BUFFERS", OP_3DSTATE_VERTEX_BUFFERS, F_LEN_VAR, R_RCS,
2393		D_BDW_PLUS, 0, 8, NULL},
2394
2395	{"3DSTATE_VERTEX_ELEMENTS", OP_3DSTATE_VERTEX_ELEMENTS, F_LEN_VAR,
2396		R_RCS, D_ALL, 0, 8, NULL},
2397
2398	{"3DSTATE_INDEX_BUFFER", OP_3DSTATE_INDEX_BUFFER, F_LEN_VAR, R_RCS,
2399		D_BDW_PLUS, ADDR_FIX_1(2), 8, NULL},
2400
2401	{"3DSTATE_VF_STATISTICS", OP_3DSTATE_VF_STATISTICS, F_LEN_CONST,
2402		R_RCS, D_ALL, 0, 1, NULL},
2403
2404	{"3DSTATE_VF", OP_3DSTATE_VF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2405
2406	{"3DSTATE_CC_STATE_POINTERS", OP_3DSTATE_CC_STATE_POINTERS, F_LEN_VAR,
2407		R_RCS, D_ALL, 0, 8, NULL},
2408
2409	{"3DSTATE_SCISSOR_STATE_POINTERS", OP_3DSTATE_SCISSOR_STATE_POINTERS,
2410		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2411
2412	{"3DSTATE_GS", OP_3DSTATE_GS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2413
2414	{"3DSTATE_CLIP", OP_3DSTATE_CLIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2415
2416	{"3DSTATE_WM", OP_3DSTATE_WM, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2417
2418	{"3DSTATE_CONSTANT_GS", OP_3DSTATE_CONSTANT_GS, F_LEN_VAR, R_RCS,
2419		D_BDW_PLUS, 0, 8, NULL},
2420
2421	{"3DSTATE_CONSTANT_PS", OP_3DSTATE_CONSTANT_PS, F_LEN_VAR, R_RCS,
2422		D_BDW_PLUS, 0, 8, NULL},
2423
2424	{"3DSTATE_SAMPLE_MASK", OP_3DSTATE_SAMPLE_MASK, F_LEN_VAR, R_RCS,
2425		D_ALL, 0, 8, NULL},
2426
2427	{"3DSTATE_CONSTANT_HS", OP_3DSTATE_CONSTANT_HS, F_LEN_VAR, R_RCS,
2428		D_BDW_PLUS, 0, 8, NULL},
2429
2430	{"3DSTATE_CONSTANT_DS", OP_3DSTATE_CONSTANT_DS, F_LEN_VAR, R_RCS,
2431		D_BDW_PLUS, 0, 8, NULL},
2432
2433	{"3DSTATE_HS", OP_3DSTATE_HS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2434
2435	{"3DSTATE_TE", OP_3DSTATE_TE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2436
2437	{"3DSTATE_DS", OP_3DSTATE_DS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2438
2439	{"3DSTATE_STREAMOUT", OP_3DSTATE_STREAMOUT, F_LEN_VAR, R_RCS,
2440		D_ALL, 0, 8, NULL},
2441
2442	{"3DSTATE_SBE", OP_3DSTATE_SBE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2443
2444	{"3DSTATE_PS", OP_3DSTATE_PS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2445
2446	{"3DSTATE_DRAWING_RECTANGLE", OP_3DSTATE_DRAWING_RECTANGLE, F_LEN_VAR,
2447		R_RCS, D_ALL, 0, 8, NULL},
2448
2449	{"3DSTATE_SAMPLER_PALETTE_LOAD0", OP_3DSTATE_SAMPLER_PALETTE_LOAD0,
2450		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2451
2452	{"3DSTATE_CHROMA_KEY", OP_3DSTATE_CHROMA_KEY, F_LEN_VAR, R_RCS, D_ALL,
2453		0, 8, NULL},
2454
2455	{"3DSTATE_DEPTH_BUFFER", OP_3DSTATE_DEPTH_BUFFER, F_LEN_VAR, R_RCS,
2456		D_ALL, ADDR_FIX_1(2), 8, NULL},
2457
2458	{"3DSTATE_POLY_STIPPLE_OFFSET", OP_3DSTATE_POLY_STIPPLE_OFFSET,
2459		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2460
2461	{"3DSTATE_POLY_STIPPLE_PATTERN", OP_3DSTATE_POLY_STIPPLE_PATTERN,
2462		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2463
2464	{"3DSTATE_LINE_STIPPLE", OP_3DSTATE_LINE_STIPPLE, F_LEN_VAR, R_RCS,
2465		D_ALL, 0, 8, NULL},
2466
2467	{"3DSTATE_AA_LINE_PARAMS", OP_3DSTATE_AA_LINE_PARAMS, F_LEN_VAR, R_RCS,
2468		D_ALL, 0, 8, NULL},
2469
2470	{"3DSTATE_GS_SVB_INDEX", OP_3DSTATE_GS_SVB_INDEX, F_LEN_VAR, R_RCS,
2471		D_ALL, 0, 8, NULL},
2472
2473	{"3DSTATE_SAMPLER_PALETTE_LOAD1", OP_3DSTATE_SAMPLER_PALETTE_LOAD1,
2474		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2475
2476	{"3DSTATE_MULTISAMPLE", OP_3DSTATE_MULTISAMPLE_BDW, F_LEN_VAR, R_RCS,
2477		D_BDW_PLUS, 0, 8, NULL},
2478
2479	{"3DSTATE_STENCIL_BUFFER", OP_3DSTATE_STENCIL_BUFFER, F_LEN_VAR, R_RCS,
2480		D_ALL, ADDR_FIX_1(2), 8, NULL},
2481
2482	{"3DSTATE_HIER_DEPTH_BUFFER", OP_3DSTATE_HIER_DEPTH_BUFFER, F_LEN_VAR,
2483		R_RCS, D_ALL, ADDR_FIX_1(2), 8, NULL},
2484
2485	{"3DSTATE_CLEAR_PARAMS", OP_3DSTATE_CLEAR_PARAMS, F_LEN_VAR,
2486		R_RCS, D_ALL, 0, 8, NULL},
2487
2488	{"3DSTATE_PUSH_CONSTANT_ALLOC_VS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_VS,
2489		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2490
2491	{"3DSTATE_PUSH_CONSTANT_ALLOC_HS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_HS,
2492		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2493
2494	{"3DSTATE_PUSH_CONSTANT_ALLOC_DS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_DS,
2495		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2496
2497	{"3DSTATE_PUSH_CONSTANT_ALLOC_GS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_GS,
2498		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2499
2500	{"3DSTATE_PUSH_CONSTANT_ALLOC_PS", OP_3DSTATE_PUSH_CONSTANT_ALLOC_PS,
2501		F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2502
2503	{"3DSTATE_MONOFILTER_SIZE", OP_3DSTATE_MONOFILTER_SIZE, F_LEN_VAR,
2504		R_RCS, D_ALL, 0, 8, NULL},
2505
2506	{"3DSTATE_SO_DECL_LIST", OP_3DSTATE_SO_DECL_LIST, F_LEN_VAR, R_RCS,
2507		D_ALL, 0, 9, NULL},
2508
2509	{"3DSTATE_SO_BUFFER", OP_3DSTATE_SO_BUFFER, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2510		ADDR_FIX_2(2, 4), 8, NULL},
2511
2512	{"3DSTATE_BINDING_TABLE_POOL_ALLOC",
2513		OP_3DSTATE_BINDING_TABLE_POOL_ALLOC,
2514		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2515
2516	{"3DSTATE_GATHER_POOL_ALLOC", OP_3DSTATE_GATHER_POOL_ALLOC,
2517		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2518
2519	{"3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC",
2520		OP_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC,
2521		F_LEN_VAR, R_RCS, D_BDW_PLUS, ADDR_FIX_1(1), 8, NULL},
2522
2523	{"3DSTATE_SAMPLE_PATTERN", OP_3DSTATE_SAMPLE_PATTERN, F_LEN_VAR, R_RCS,
2524		D_BDW_PLUS, 0, 8, NULL},
2525
2526	{"PIPE_CONTROL", OP_PIPE_CONTROL, F_LEN_VAR, R_RCS, D_ALL,
2527		ADDR_FIX_1(2), 8, cmd_handler_pipe_control},
2528
2529	{"3DPRIMITIVE", OP_3DPRIMITIVE, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2530
2531	{"PIPELINE_SELECT", OP_PIPELINE_SELECT, F_LEN_CONST, R_RCS, D_ALL, 0,
2532		1, NULL},
2533
2534	{"STATE_PREFETCH", OP_STATE_PREFETCH, F_LEN_VAR, R_RCS, D_ALL,
2535		ADDR_FIX_1(1), 8, NULL},
2536
2537	{"STATE_SIP", OP_STATE_SIP, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2538
2539	{"STATE_BASE_ADDRESS", OP_STATE_BASE_ADDRESS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2540		ADDR_FIX_5(1, 3, 4, 5, 6), 8, NULL},
2541
2542	{"OP_3D_MEDIA_0_1_4", OP_3D_MEDIA_0_1_4, F_LEN_VAR, R_RCS, D_ALL,
2543		ADDR_FIX_1(1), 8, NULL},
2544
2545	{"OP_SWTESS_BASE_ADDRESS", OP_SWTESS_BASE_ADDRESS,
2546		F_LEN_VAR, R_RCS, D_ALL, ADDR_FIX_2(1, 2), 3, NULL},
2547
2548	{"3DSTATE_VS", OP_3DSTATE_VS, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2549
2550	{"3DSTATE_SF", OP_3DSTATE_SF, F_LEN_VAR, R_RCS, D_ALL, 0, 8, NULL},
2551
2552	{"3DSTATE_CONSTANT_VS", OP_3DSTATE_CONSTANT_VS, F_LEN_VAR, R_RCS, D_BDW_PLUS,
2553		0, 8, NULL},
2554
2555	{"3DSTATE_COMPONENT_PACKING", OP_3DSTATE_COMPONENT_PACKING, F_LEN_VAR, R_RCS,
2556		D_SKL_PLUS, 0, 8, NULL},
2557
2558	{"MEDIA_INTERFACE_DESCRIPTOR_LOAD", OP_MEDIA_INTERFACE_DESCRIPTOR_LOAD,
2559		F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2560
2561	{"MEDIA_GATEWAY_STATE", OP_MEDIA_GATEWAY_STATE, F_LEN_VAR, R_RCS, D_ALL,
2562		0, 16, NULL},
2563
2564	{"MEDIA_STATE_FLUSH", OP_MEDIA_STATE_FLUSH, F_LEN_VAR, R_RCS, D_ALL,
2565		0, 16, NULL},
2566
2567	{"MEDIA_POOL_STATE", OP_MEDIA_POOL_STATE, F_LEN_VAR, R_RCS, D_ALL,
2568		0, 16, NULL},
2569
2570	{"MEDIA_OBJECT", OP_MEDIA_OBJECT, F_LEN_VAR, R_RCS, D_ALL, 0, 16, NULL},
2571
2572	{"MEDIA_CURBE_LOAD", OP_MEDIA_CURBE_LOAD, F_LEN_VAR, R_RCS, D_ALL,
2573		0, 16, NULL},
2574
2575	{"MEDIA_OBJECT_PRT", OP_MEDIA_OBJECT_PRT, F_LEN_VAR, R_RCS, D_ALL,
2576		0, 16, NULL},
2577
2578	{"MEDIA_OBJECT_WALKER", OP_MEDIA_OBJECT_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2579		0, 16, NULL},
2580
2581	{"GPGPU_WALKER", OP_GPGPU_WALKER, F_LEN_VAR, R_RCS, D_ALL,
2582		0, 8, NULL},
2583
2584	{"MEDIA_VFE_STATE", OP_MEDIA_VFE_STATE, F_LEN_VAR, R_RCS, D_ALL, 0, 16,
2585		NULL},
2586
2587	{"3DSTATE_VF_STATISTICS_GM45", OP_3DSTATE_VF_STATISTICS_GM45,
2588		F_LEN_CONST, R_ALL, D_ALL, 0, 1, NULL},
2589
2590	{"MFX_PIPE_MODE_SELECT", OP_MFX_PIPE_MODE_SELECT, F_LEN_VAR,
2591		R_VCS, D_ALL, 0, 12, NULL},
2592
2593	{"MFX_SURFACE_STATE", OP_MFX_SURFACE_STATE, F_LEN_VAR,
2594		R_VCS, D_ALL, 0, 12, NULL},
2595
2596	{"MFX_PIPE_BUF_ADDR_STATE", OP_MFX_PIPE_BUF_ADDR_STATE, F_LEN_VAR,
2597		R_VCS, D_BDW_PLUS, 0, 12, NULL},
2598
2599	{"MFX_IND_OBJ_BASE_ADDR_STATE", OP_MFX_IND_OBJ_BASE_ADDR_STATE,
2600		F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2601
2602	{"MFX_BSP_BUF_BASE_ADDR_STATE", OP_MFX_BSP_BUF_BASE_ADDR_STATE,
2603		F_LEN_VAR, R_VCS, D_BDW_PLUS, ADDR_FIX_3(1, 3, 5), 12, NULL},
2604
2605	{"OP_2_0_0_5", OP_2_0_0_5, F_LEN_VAR, R_VCS, D_BDW_PLUS, 0, 12, NULL},
2606
2607	{"MFX_STATE_POINTER", OP_MFX_STATE_POINTER, F_LEN_VAR,
2608		R_VCS, D_ALL, 0, 12, NULL},
2609
2610	{"MFX_QM_STATE", OP_MFX_QM_STATE, F_LEN_VAR,
2611		R_VCS, D_ALL, 0, 12, NULL},
2612
2613	{"MFX_FQM_STATE", OP_MFX_FQM_STATE, F_LEN_VAR,
2614		R_VCS, D_ALL, 0, 12, NULL},
2615
2616	{"MFX_PAK_INSERT_OBJECT", OP_MFX_PAK_INSERT_OBJECT, F_LEN_VAR,
2617		R_VCS, D_ALL, 0, 12, NULL},
2618
2619	{"MFX_STITCH_OBJECT", OP_MFX_STITCH_OBJECT, F_LEN_VAR,
2620		R_VCS, D_ALL, 0, 12, NULL},
2621
2622	{"MFD_IT_OBJECT", OP_MFD_IT_OBJECT, F_LEN_VAR,
2623		R_VCS, D_ALL, 0, 12, NULL},
2624
2625	{"MFX_WAIT", OP_MFX_WAIT, F_LEN_VAR,
2626		R_VCS, D_ALL, 0, 6, NULL},
2627
2628	{"MFX_AVC_IMG_STATE", OP_MFX_AVC_IMG_STATE, F_LEN_VAR,
2629		R_VCS, D_ALL, 0, 12, NULL},
2630
2631	{"MFX_AVC_QM_STATE", OP_MFX_AVC_QM_STATE, F_LEN_VAR,
2632		R_VCS, D_ALL, 0, 12, NULL},
2633
2634	{"MFX_AVC_DIRECTMODE_STATE", OP_MFX_AVC_DIRECTMODE_STATE, F_LEN_VAR,
2635		R_VCS, D_ALL, 0, 12, NULL},
2636
2637	{"MFX_AVC_SLICE_STATE", OP_MFX_AVC_SLICE_STATE, F_LEN_VAR,
2638		R_VCS, D_ALL, 0, 12, NULL},
2639
2640	{"MFX_AVC_REF_IDX_STATE", OP_MFX_AVC_REF_IDX_STATE, F_LEN_VAR,
2641		R_VCS, D_ALL, 0, 12, NULL},
2642
2643	{"MFX_AVC_WEIGHTOFFSET_STATE", OP_MFX_AVC_WEIGHTOFFSET_STATE, F_LEN_VAR,
2644		R_VCS, D_ALL, 0, 12, NULL},
2645
2646	{"MFD_AVC_PICID_STATE", OP_MFD_AVC_PICID_STATE, F_LEN_VAR,
2647		R_VCS, D_ALL, 0, 12, NULL},
2648	{"MFD_AVC_DPB_STATE", OP_MFD_AVC_DPB_STATE, F_LEN_VAR,
2649		R_VCS, D_ALL, 0, 12, NULL},
2650
2651	{"MFD_AVC_BSD_OBJECT", OP_MFD_AVC_BSD_OBJECT, F_LEN_VAR,
2652		R_VCS, D_ALL, 0, 12, NULL},
2653
2654	{"MFD_AVC_SLICEADDR", OP_MFD_AVC_SLICEADDR, F_LEN_VAR,
2655		R_VCS, D_ALL, ADDR_FIX_1(2), 12, NULL},
2656
2657	{"MFC_AVC_PAK_OBJECT", OP_MFC_AVC_PAK_OBJECT, F_LEN_VAR,
2658		R_VCS, D_ALL, 0, 12, NULL},
2659
2660	{"MFX_VC1_PRED_PIPE_STATE", OP_MFX_VC1_PRED_PIPE_STATE, F_LEN_VAR,
2661		R_VCS, D_ALL, 0, 12, NULL},
2662
2663	{"MFX_VC1_DIRECTMODE_STATE", OP_MFX_VC1_DIRECTMODE_STATE, F_LEN_VAR,
2664		R_VCS, D_ALL, 0, 12, NULL},
2665
2666	{"MFD_VC1_SHORT_PIC_STATE", OP_MFD_VC1_SHORT_PIC_STATE, F_LEN_VAR,
2667		R_VCS, D_ALL, 0, 12, NULL},
2668
2669	{"MFD_VC1_LONG_PIC_STATE", OP_MFD_VC1_LONG_PIC_STATE, F_LEN_VAR,
2670		R_VCS, D_ALL, 0, 12, NULL},
2671
2672	{"MFD_VC1_BSD_OBJECT", OP_MFD_VC1_BSD_OBJECT, F_LEN_VAR,
2673		R_VCS, D_ALL, 0, 12, NULL},
2674
2675	{"MFC_MPEG2_SLICEGROUP_STATE", OP_MFC_MPEG2_SLICEGROUP_STATE, F_LEN_VAR,
2676		R_VCS, D_ALL, 0, 12, NULL},
2677
2678	{"MFC_MPEG2_PAK_OBJECT", OP_MFC_MPEG2_PAK_OBJECT, F_LEN_VAR,
2679		R_VCS, D_ALL, 0, 12, NULL},
2680
2681	{"MFX_MPEG2_PIC_STATE", OP_MFX_MPEG2_PIC_STATE, F_LEN_VAR,
2682		R_VCS, D_ALL, 0, 12, NULL},
2683
2684	{"MFX_MPEG2_QM_STATE", OP_MFX_MPEG2_QM_STATE, F_LEN_VAR,
2685		R_VCS, D_ALL, 0, 12, NULL},
2686
2687	{"MFD_MPEG2_BSD_OBJECT", OP_MFD_MPEG2_BSD_OBJECT, F_LEN_VAR,
2688		R_VCS, D_ALL, 0, 12, NULL},
2689
2690	{"MFX_2_6_0_0", OP_MFX_2_6_0_0, F_LEN_VAR, R_VCS, D_ALL,
2691		0, 16, NULL},
2692
2693	{"MFX_2_6_0_9", OP_MFX_2_6_0_9, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2694
2695	{"MFX_2_6_0_8", OP_MFX_2_6_0_8, F_LEN_VAR, R_VCS, D_ALL, 0, 16, NULL},
2696
2697	{"MFX_JPEG_PIC_STATE", OP_MFX_JPEG_PIC_STATE, F_LEN_VAR,
2698		R_VCS, D_ALL, 0, 12, NULL},
2699
2700	{"MFX_JPEG_HUFF_TABLE_STATE", OP_MFX_JPEG_HUFF_TABLE_STATE, F_LEN_VAR,
2701		R_VCS, D_ALL, 0, 12, NULL},
2702
2703	{"MFD_JPEG_BSD_OBJECT", OP_MFD_JPEG_BSD_OBJECT, F_LEN_VAR,
2704		R_VCS, D_ALL, 0, 12, NULL},
2705
2706	{"VEBOX_STATE", OP_VEB_STATE, F_LEN_VAR, R_VECS, D_ALL, 0, 12, NULL},
2707
2708	{"VEBOX_SURFACE_STATE", OP_VEB_SURFACE_STATE, F_LEN_VAR, R_VECS, D_ALL,
2709		0, 12, NULL},
2710
2711	{"VEB_DI_IECP", OP_VEB_DNDI_IECP_STATE, F_LEN_VAR, R_VECS, D_BDW_PLUS,
2712		0, 12, NULL},
2713};
2714
2715static void add_cmd_entry(struct intel_gvt *gvt, struct cmd_entry *e)
2716{
2717	hash_add(gvt->cmd_table, &e->hlist, e->info->opcode);
2718}
2719
2720/* call the cmd handler, and advance ip */
2721static int cmd_parser_exec(struct parser_exec_state *s)
2722{
2723	struct intel_vgpu *vgpu = s->vgpu;
2724	const struct cmd_info *info;
2725	u32 cmd;
2726	int ret = 0;
2727
2728	cmd = cmd_val(s, 0);
2729
2730	/* fastpath for MI_NOOP */
2731	if (cmd == MI_NOOP)
2732		info = &cmd_info[mi_noop_index];
2733	else
2734		info = get_cmd_info(s->vgpu->gvt, cmd, s->engine);
2735
2736	if (info == NULL) {
2737		gvt_vgpu_err("unknown cmd 0x%x, opcode=0x%x, addr_type=%s, ring %s, workload=%p\n",
2738			     cmd, get_opcode(cmd, s->engine),
2739			     repr_addr_type(s->buf_addr_type),
2740			     s->engine->name, s->workload);
2741		return -EBADRQC;
2742	}
2743
2744	s->info = info;
2745
2746	trace_gvt_command(vgpu->id, s->engine->id, s->ip_gma, s->ip_va,
2747			  cmd_length(s), s->buf_type, s->buf_addr_type,
2748			  s->workload, info->name);
2749
2750	if ((info->flag & F_LEN_MASK) == F_LEN_VAR_FIXED) {
2751		ret = gvt_check_valid_cmd_length(cmd_length(s),
2752						 info->valid_len);
2753		if (ret)
2754			return ret;
2755	}
2756
2757	if (info->handler) {
2758		ret = info->handler(s);
2759		if (ret < 0) {
2760			gvt_vgpu_err("%s handler error\n", info->name);
2761			return ret;
2762		}
2763	}
2764
2765	if (!(info->flag & F_IP_ADVANCE_CUSTOM)) {
2766		ret = cmd_advance_default(s);
2767		if (ret) {
2768			gvt_vgpu_err("%s IP advance error\n", info->name);
2769			return ret;
2770		}
2771	}
2772	return 0;
2773}
2774
2775static inline bool gma_out_of_range(unsigned long gma,
2776		unsigned long gma_head, unsigned int gma_tail)
2777{
2778	if (gma_tail >= gma_head)
2779		return (gma < gma_head) || (gma > gma_tail);
2780	else
2781		return (gma > gma_tail) && (gma < gma_head);
2782}
2783
2784/* Keep the consistent return type, e.g EBADRQC for unknown
2785 * cmd, EFAULT for invalid address, EPERM for nonpriv. later
2786 * works as the input of VM healthy status.
2787 */
2788static int command_scan(struct parser_exec_state *s,
2789		unsigned long rb_head, unsigned long rb_tail,
2790		unsigned long rb_start, unsigned long rb_len)
2791{
2792
2793	unsigned long gma_head, gma_tail, gma_bottom;
2794	int ret = 0;
2795	struct intel_vgpu *vgpu = s->vgpu;
2796
2797	gma_head = rb_start + rb_head;
2798	gma_tail = rb_start + rb_tail;
2799	gma_bottom = rb_start +  rb_len;
2800
2801	while (s->ip_gma != gma_tail) {
2802		if (s->buf_type == RING_BUFFER_INSTRUCTION ||
2803				s->buf_type == RING_BUFFER_CTX) {
2804			if (!(s->ip_gma >= rb_start) ||
2805				!(s->ip_gma < gma_bottom)) {
2806				gvt_vgpu_err("ip_gma %lx out of ring scope."
2807					"(base:0x%lx, bottom: 0x%lx)\n",
2808					s->ip_gma, rb_start,
2809					gma_bottom);
2810				parser_exec_state_dump(s);
2811				return -EFAULT;
2812			}
2813			if (gma_out_of_range(s->ip_gma, gma_head, gma_tail)) {
2814				gvt_vgpu_err("ip_gma %lx out of range."
2815					"base 0x%lx head 0x%lx tail 0x%lx\n",
2816					s->ip_gma, rb_start,
2817					rb_head, rb_tail);
2818				parser_exec_state_dump(s);
2819				break;
2820			}
2821		}
2822		ret = cmd_parser_exec(s);
2823		if (ret) {
2824			gvt_vgpu_err("cmd parser error\n");
2825			parser_exec_state_dump(s);
2826			break;
2827		}
2828	}
2829
2830	return ret;
2831}
2832
2833static int scan_workload(struct intel_vgpu_workload *workload)
2834{
2835	unsigned long gma_head, gma_tail, gma_bottom;
2836	struct parser_exec_state s;
2837	int ret = 0;
2838
2839	/* ring base is page aligned */
2840	if (WARN_ON(!IS_ALIGNED(workload->rb_start, I915_GTT_PAGE_SIZE)))
2841		return -EINVAL;
2842
2843	gma_head = workload->rb_start + workload->rb_head;
2844	gma_tail = workload->rb_start + workload->rb_tail;
2845	gma_bottom = workload->rb_start +  _RING_CTL_BUF_SIZE(workload->rb_ctl);
2846
2847	s.buf_type = RING_BUFFER_INSTRUCTION;
2848	s.buf_addr_type = GTT_BUFFER;
2849	s.vgpu = workload->vgpu;
2850	s.engine = workload->engine;
2851	s.ring_start = workload->rb_start;
2852	s.ring_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2853	s.ring_head = gma_head;
2854	s.ring_tail = gma_tail;
2855	s.rb_va = workload->shadow_ring_buffer_va;
2856	s.workload = workload;
2857	s.is_ctx_wa = false;
2858
2859	if (bypass_scan_mask & workload->engine->mask || gma_head == gma_tail)
2860		return 0;
2861
2862	ret = ip_gma_set(&s, gma_head);
2863	if (ret)
2864		goto out;
2865
2866	ret = command_scan(&s, workload->rb_head, workload->rb_tail,
2867		workload->rb_start, _RING_CTL_BUF_SIZE(workload->rb_ctl));
2868
2869out:
2870	return ret;
2871}
2872
2873static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2874{
2875
2876	unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
2877	struct parser_exec_state s;
2878	int ret = 0;
2879	struct intel_vgpu_workload *workload = container_of(wa_ctx,
2880				struct intel_vgpu_workload,
2881				wa_ctx);
2882
2883	/* ring base is page aligned */
2884	if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma,
2885					I915_GTT_PAGE_SIZE)))
2886		return -EINVAL;
2887
2888	ring_tail = wa_ctx->indirect_ctx.size + 3 * sizeof(u32);
2889	ring_size = round_up(wa_ctx->indirect_ctx.size + CACHELINE_BYTES,
2890			PAGE_SIZE);
2891	gma_head = wa_ctx->indirect_ctx.guest_gma;
2892	gma_tail = wa_ctx->indirect_ctx.guest_gma + ring_tail;
2893	gma_bottom = wa_ctx->indirect_ctx.guest_gma + ring_size;
2894
2895	s.buf_type = RING_BUFFER_INSTRUCTION;
2896	s.buf_addr_type = GTT_BUFFER;
2897	s.vgpu = workload->vgpu;
2898	s.engine = workload->engine;
2899	s.ring_start = wa_ctx->indirect_ctx.guest_gma;
2900	s.ring_size = ring_size;
2901	s.ring_head = gma_head;
2902	s.ring_tail = gma_tail;
2903	s.rb_va = wa_ctx->indirect_ctx.shadow_va;
2904	s.workload = workload;
2905	s.is_ctx_wa = true;
2906
2907	ret = ip_gma_set(&s, gma_head);
2908	if (ret)
2909		goto out;
2910
2911	ret = command_scan(&s, 0, ring_tail,
2912		wa_ctx->indirect_ctx.guest_gma, ring_size);
2913out:
2914	return ret;
2915}
2916
2917static int shadow_workload_ring_buffer(struct intel_vgpu_workload *workload)
2918{
2919	struct intel_vgpu *vgpu = workload->vgpu;
2920	struct intel_vgpu_submission *s = &vgpu->submission;
2921	unsigned long gma_head, gma_tail, gma_top, guest_rb_size;
2922	void *shadow_ring_buffer_va;
2923	int ret;
2924
2925	guest_rb_size = _RING_CTL_BUF_SIZE(workload->rb_ctl);
2926
2927	/* calculate workload ring buffer size */
2928	workload->rb_len = (workload->rb_tail + guest_rb_size -
2929			workload->rb_head) % guest_rb_size;
2930
2931	gma_head = workload->rb_start + workload->rb_head;
2932	gma_tail = workload->rb_start + workload->rb_tail;
2933	gma_top = workload->rb_start + guest_rb_size;
2934
2935	if (workload->rb_len > s->ring_scan_buffer_size[workload->engine->id]) {
2936		void *p;
2937
2938		/* realloc the new ring buffer if needed */
2939		p = krealloc(s->ring_scan_buffer[workload->engine->id],
2940			     workload->rb_len, GFP_KERNEL);
2941		if (!p) {
2942			gvt_vgpu_err("fail to re-alloc ring scan buffer\n");
2943			return -ENOMEM;
2944		}
2945		s->ring_scan_buffer[workload->engine->id] = p;
2946		s->ring_scan_buffer_size[workload->engine->id] = workload->rb_len;
2947	}
2948
2949	shadow_ring_buffer_va = s->ring_scan_buffer[workload->engine->id];
2950
2951	/* get shadow ring buffer va */
2952	workload->shadow_ring_buffer_va = shadow_ring_buffer_va;
2953
2954	/* head > tail --> copy head <-> top */
2955	if (gma_head > gma_tail) {
2956		ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm,
2957				      gma_head, gma_top, shadow_ring_buffer_va);
2958		if (ret < 0) {
2959			gvt_vgpu_err("fail to copy guest ring buffer\n");
2960			return ret;
2961		}
2962		shadow_ring_buffer_va += ret;
2963		gma_head = workload->rb_start;
2964	}
2965
2966	/* copy head or start <-> tail */
2967	ret = copy_gma_to_hva(vgpu, vgpu->gtt.ggtt_mm, gma_head, gma_tail,
2968				shadow_ring_buffer_va);
2969	if (ret < 0) {
2970		gvt_vgpu_err("fail to copy guest ring buffer\n");
2971		return ret;
2972	}
2973	return 0;
2974}
2975
2976int intel_gvt_scan_and_shadow_ringbuffer(struct intel_vgpu_workload *workload)
2977{
2978	int ret;
2979	struct intel_vgpu *vgpu = workload->vgpu;
2980
2981	ret = shadow_workload_ring_buffer(workload);
2982	if (ret) {
2983		gvt_vgpu_err("fail to shadow workload ring_buffer\n");
2984		return ret;
2985	}
2986
2987	ret = scan_workload(workload);
2988	if (ret) {
2989		gvt_vgpu_err("scan workload error\n");
2990		return ret;
2991	}
2992	return 0;
2993}
2994
2995static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx)
2996{
2997	int ctx_size = wa_ctx->indirect_ctx.size;
2998	unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
2999	struct intel_vgpu_workload *workload = container_of(wa_ctx,
3000					struct intel_vgpu_workload,
3001					wa_ctx);
3002	struct intel_vgpu *vgpu = workload->vgpu;
3003	struct drm_i915_gem_object *obj;
3004	int ret = 0;
3005	void *map;
3006
3007	obj = i915_gem_object_create_shmem(workload->engine->i915,
3008					   roundup(ctx_size + CACHELINE_BYTES,
3009						   PAGE_SIZE));
3010	if (IS_ERR(obj))
3011		return PTR_ERR(obj);
3012
3013	/* get the va of the shadow batch buffer */
3014	map = i915_gem_object_pin_map(obj, I915_MAP_WB);
3015	if (IS_ERR(map)) {
3016		gvt_vgpu_err("failed to vmap shadow indirect ctx\n");
3017		ret = PTR_ERR(map);
3018		goto put_obj;
3019	}
3020
3021	i915_gem_object_lock(obj, NULL);
3022	ret = i915_gem_object_set_to_cpu_domain(obj, false);
3023	i915_gem_object_unlock(obj);
3024	if (ret) {
3025		gvt_vgpu_err("failed to set shadow indirect ctx to CPU\n");
3026		goto unmap_src;
3027	}
3028
3029	ret = copy_gma_to_hva(workload->vgpu,
3030				workload->vgpu->gtt.ggtt_mm,
3031				guest_gma, guest_gma + ctx_size,
3032				map);
3033	if (ret < 0) {
3034		gvt_vgpu_err("fail to copy guest indirect ctx\n");
3035		goto unmap_src;
3036	}
3037
3038	wa_ctx->indirect_ctx.obj = obj;
3039	wa_ctx->indirect_ctx.shadow_va = map;
3040	return 0;
3041
3042unmap_src:
3043	i915_gem_object_unpin_map(obj);
3044put_obj:
3045	i915_gem_object_put(obj);
3046	return ret;
3047}
3048
3049static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3050{
3051	u32 per_ctx_start[CACHELINE_DWORDS] = {0};
3052	unsigned char *bb_start_sva;
3053
3054	if (!wa_ctx->per_ctx.valid)
3055		return 0;
3056
3057	per_ctx_start[0] = 0x18800001;
3058	per_ctx_start[1] = wa_ctx->per_ctx.guest_gma;
3059
3060	bb_start_sva = (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
3061				wa_ctx->indirect_ctx.size;
3062
3063	memcpy(bb_start_sva, per_ctx_start, CACHELINE_BYTES);
3064
3065	return 0;
3066}
3067
3068int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
3069{
3070	int ret;
3071	struct intel_vgpu_workload *workload = container_of(wa_ctx,
3072					struct intel_vgpu_workload,
3073					wa_ctx);
3074	struct intel_vgpu *vgpu = workload->vgpu;
3075
3076	if (wa_ctx->indirect_ctx.size == 0)
3077		return 0;
3078
3079	ret = shadow_indirect_ctx(wa_ctx);
3080	if (ret) {
3081		gvt_vgpu_err("fail to shadow indirect ctx\n");
3082		return ret;
3083	}
3084
3085	combine_wa_ctx(wa_ctx);
3086
3087	ret = scan_wa_ctx(wa_ctx);
3088	if (ret) {
3089		gvt_vgpu_err("scan wa ctx error\n");
3090		return ret;
3091	}
3092
3093	return 0;
3094}
3095
3096/* generate dummy contexts by sending empty requests to HW, and let
3097 * the HW to fill Engine Contexts. This dummy contexts are used for
3098 * initialization purpose (update reg whitelist), so referred to as
3099 * init context here
3100 */
3101void intel_gvt_update_reg_whitelist(struct intel_vgpu *vgpu)
3102{
3103	const unsigned long start = LRC_STATE_PN * PAGE_SIZE;
3104	struct intel_gvt *gvt = vgpu->gvt;
3105	struct intel_engine_cs *engine;
3106	enum intel_engine_id id;
3107
3108	if (gvt->is_reg_whitelist_updated)
3109		return;
3110
3111	/* scan init ctx to update cmd accessible list */
3112	for_each_engine(engine, gvt->gt, id) {
3113		struct parser_exec_state s;
3114		void *vaddr;
3115		int ret;
3116
3117		if (!engine->default_state)
3118			continue;
3119
3120		vaddr = shmem_pin_map(engine->default_state);
3121		if (!vaddr) {
3122			gvt_err("failed to map %s->default state\n",
3123				engine->name);
3124			return;
3125		}
3126
3127		s.buf_type = RING_BUFFER_CTX;
3128		s.buf_addr_type = GTT_BUFFER;
3129		s.vgpu = vgpu;
3130		s.engine = engine;
3131		s.ring_start = 0;
3132		s.ring_size = engine->context_size - start;
3133		s.ring_head = 0;
3134		s.ring_tail = s.ring_size;
3135		s.rb_va = vaddr + start;
3136		s.workload = NULL;
3137		s.is_ctx_wa = false;
3138		s.is_init_ctx = true;
3139
3140		/* skipping the first RING_CTX_SIZE(0x50) dwords */
3141		ret = ip_gma_set(&s, RING_CTX_SIZE);
3142		if (ret == 0) {
3143			ret = command_scan(&s, 0, s.ring_size, 0, s.ring_size);
3144			if (ret)
3145				gvt_err("Scan init ctx error\n");
3146		}
3147
3148		shmem_unpin_map(engine->default_state, vaddr);
3149		if (ret)
3150			return;
3151	}
3152
3153	gvt->is_reg_whitelist_updated = true;
3154}
3155
3156int intel_gvt_scan_engine_context(struct intel_vgpu_workload *workload)
3157{
3158	struct intel_vgpu *vgpu = workload->vgpu;
3159	unsigned long gma_head, gma_tail, gma_start, ctx_size;
3160	struct parser_exec_state s;
3161	int ring_id = workload->engine->id;
3162	struct intel_context *ce = vgpu->submission.shadow[ring_id];
3163	int ret;
3164
3165	GEM_BUG_ON(atomic_read(&ce->pin_count) < 0);
3166
3167	ctx_size = workload->engine->context_size - PAGE_SIZE;
3168
3169	/* Only ring contxt is loaded to HW for inhibit context, no need to
3170	 * scan engine context
3171	 */
3172	if (is_inhibit_context(ce))
3173		return 0;
3174
3175	gma_start = i915_ggtt_offset(ce->state) + LRC_STATE_PN*PAGE_SIZE;
3176	gma_head = 0;
3177	gma_tail = ctx_size;
3178
3179	s.buf_type = RING_BUFFER_CTX;
3180	s.buf_addr_type = GTT_BUFFER;
3181	s.vgpu = workload->vgpu;
3182	s.engine = workload->engine;
3183	s.ring_start = gma_start;
3184	s.ring_size = ctx_size;
3185	s.ring_head = gma_start + gma_head;
3186	s.ring_tail = gma_start + gma_tail;
3187	s.rb_va = ce->lrc_reg_state;
3188	s.workload = workload;
3189	s.is_ctx_wa = false;
3190	s.is_init_ctx = false;
3191
3192	/* don't scan the first RING_CTX_SIZE(0x50) dwords, as it's ring
3193	 * context
3194	 */
3195	ret = ip_gma_set(&s, gma_start + gma_head + RING_CTX_SIZE);
3196	if (ret)
3197		goto out;
3198
3199	ret = command_scan(&s, gma_head, gma_tail,
3200		gma_start, ctx_size);
3201out:
3202	if (ret)
3203		gvt_vgpu_err("scan shadow ctx error\n");
3204
3205	return ret;
3206}
3207
3208static int init_cmd_table(struct intel_gvt *gvt)
3209{
3210	unsigned int gen_type = intel_gvt_get_device_type(gvt);
3211	int i;
3212
3213	for (i = 0; i < ARRAY_SIZE(cmd_info); i++) {
3214		struct cmd_entry *e;
3215
3216		if (!(cmd_info[i].devices & gen_type))
3217			continue;
3218
3219		e = kzalloc(sizeof(*e), GFP_KERNEL);
3220		if (!e)
3221			return -ENOMEM;
3222
3223		e->info = &cmd_info[i];
3224		if (cmd_info[i].opcode == OP_MI_NOOP)
3225			mi_noop_index = i;
3226
3227		INIT_HLIST_NODE(&e->hlist);
3228		add_cmd_entry(gvt, e);
3229		gvt_dbg_cmd("add %-30s op %04x flag %x devs %02x rings %02x\n",
3230			    e->info->name, e->info->opcode, e->info->flag,
3231			    e->info->devices, e->info->rings);
3232	}
3233
3234	return 0;
3235}
3236
3237static void clean_cmd_table(struct intel_gvt *gvt)
3238{
3239	struct hlist_node *tmp;
3240	struct cmd_entry *e;
3241	int i;
3242
3243	hash_for_each_safe(gvt->cmd_table, i, tmp, e, hlist)
3244		kfree(e);
3245
3246	hash_init(gvt->cmd_table);
3247}
3248
3249void intel_gvt_clean_cmd_parser(struct intel_gvt *gvt)
3250{
3251	clean_cmd_table(gvt);
3252}
3253
3254int intel_gvt_init_cmd_parser(struct intel_gvt *gvt)
3255{
3256	int ret;
3257
3258	ret = init_cmd_table(gvt);
3259	if (ret) {
3260		intel_gvt_clean_cmd_parser(gvt);
3261		return ret;
3262	}
3263	return 0;
3264}