1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2014-2019 Intel Corporation
  4 */
  5
  6#ifndef _INTEL_GUC_REG_H_
  7#define _INTEL_GUC_REG_H_
  8
  9#include <linux/compiler.h>
 10#include <linux/types.h>
 11
 12#include "i915_reg_defs.h"
 13
 14/* Definitions of GuC H/W registers, bits, etc */
 15
 16#define GUC_STATUS			_MMIO(0xc000)
 17#define   GS_RESET_SHIFT		0
 18#define   GS_MIA_IN_RESET		  (0x01 << GS_RESET_SHIFT)
 19#define   GS_BOOTROM_SHIFT		1
 20#define   GS_BOOTROM_MASK		  (0x7F << GS_BOOTROM_SHIFT)
 21#define   GS_BOOTROM_RSA_FAILED		  (0x50 << GS_BOOTROM_SHIFT)
 22#define   GS_BOOTROM_JUMP_PASSED	  (0x76 << GS_BOOTROM_SHIFT)
 23#define   GS_UKERNEL_SHIFT		8
 24#define   GS_UKERNEL_MASK		  (0xFF << GS_UKERNEL_SHIFT)
 25#define   GS_MIA_SHIFT			16
 26#define   GS_MIA_MASK			  (0x07 << GS_MIA_SHIFT)
 27#define   GS_MIA_CORE_STATE		  (0x01 << GS_MIA_SHIFT)
 28#define   GS_MIA_HALT_REQUESTED		  (0x02 << GS_MIA_SHIFT)
 29#define   GS_MIA_ISR_ENTRY		  (0x04 << GS_MIA_SHIFT)
 30#define   GS_AUTH_STATUS_SHIFT		30
 31#define   GS_AUTH_STATUS_MASK		  (0x03U << GS_AUTH_STATUS_SHIFT)
 32#define   GS_AUTH_STATUS_BAD		  (0x01 << GS_AUTH_STATUS_SHIFT)
 33#define   GS_AUTH_STATUS_GOOD		  (0x02 << GS_AUTH_STATUS_SHIFT)
 34
 35#define SOFT_SCRATCH(n)			_MMIO(0xc180 + (n) * 4)
 36#define SOFT_SCRATCH_COUNT		16
 37
 38#define GEN11_SOFT_SCRATCH(n)		_MMIO(0x190240 + (n) * 4)
 39#define MEDIA_SOFT_SCRATCH(n)		_MMIO(0x190310 + (n) * 4)
 40#define GEN11_SOFT_SCRATCH_COUNT	4
 41
 42#define UOS_RSA_SCRATCH(i)		_MMIO(0xc200 + (i) * 4)
 43#define UOS_RSA_SCRATCH_COUNT		64
 44
 45#define DMA_ADDR_0_LOW			_MMIO(0xc300)
 46#define DMA_ADDR_0_HIGH			_MMIO(0xc304)
 47#define DMA_ADDR_1_LOW			_MMIO(0xc308)
 48#define DMA_ADDR_1_HIGH			_MMIO(0xc30c)
 49#define   DMA_ADDRESS_SPACE_WOPCM	  (7 << 16)
 50#define   DMA_ADDRESS_SPACE_GTT		  (8 << 16)
 51#define DMA_COPY_SIZE			_MMIO(0xc310)
 52#define DMA_CTRL			_MMIO(0xc314)
 53#define   HUC_UKERNEL			  (1<<9)
 54#define   UOS_MOVE			  (1<<4)
 55#define   START_DMA			  (1<<0)
 56#define DMA_GUC_WOPCM_OFFSET		_MMIO(0xc340)
 57#define   GUC_WOPCM_OFFSET_VALID	  (1<<0)
 58#define   HUC_LOADING_AGENT_VCR		  (0<<1)
 59#define   HUC_LOADING_AGENT_GUC		  (1<<1)
 60#define   GUC_WOPCM_OFFSET_SHIFT	14
 61#define   GUC_WOPCM_OFFSET_MASK		  (0x3ffff << GUC_WOPCM_OFFSET_SHIFT)
 62#define GUC_MAX_IDLE_COUNT		_MMIO(0xC3E4)
 63
 64#define HUC_STATUS2             _MMIO(0xD3B0)
 65#define   HUC_FW_VERIFIED       (1<<7)
 66
 67#define GEN11_HUC_KERNEL_LOAD_INFO	_MMIO(0xC1DC)
 68#define   HUC_LOAD_SUCCESSFUL		  (1 << 0)
 69
 70#define GUC_WOPCM_SIZE			_MMIO(0xc050)
 71#define   GUC_WOPCM_SIZE_LOCKED		  (1<<0)
 72#define   GUC_WOPCM_SIZE_SHIFT		12
 73#define   GUC_WOPCM_SIZE_MASK		  (0xfffff << GUC_WOPCM_SIZE_SHIFT)
 74
 75#define GEN8_GT_PM_CONFIG		_MMIO(0x138140)
 76#define GEN9LP_GT_PM_CONFIG		_MMIO(0x138140)
 77#define GEN9_GT_PM_CONFIG		_MMIO(0x13816c)
 78#define   GT_DOORBELL_ENABLE		  (1<<0)
 79
 80#define GEN8_GTCR			_MMIO(0x4274)
 81#define   GEN8_GTCR_INVALIDATE		  (1<<0)
 82
 83#define GEN12_GUC_TLB_INV_CR		_MMIO(0xcee8)
 84#define   GEN12_GUC_TLB_INV_CR_INVALIDATE	(1 << 0)
 85
 86#define GUC_ARAT_C6DIS			_MMIO(0xA178)
 87
 88#define GUC_SHIM_CONTROL		_MMIO(0xc064)
 89#define   GUC_DISABLE_SRAM_INIT_TO_ZEROES	(1<<0)
 90#define   GUC_ENABLE_READ_CACHE_LOGIC		(1<<1)
 91#define   GUC_ENABLE_MIA_CACHING		(1<<2)
 92#define   GUC_GEN10_MSGCH_ENABLE		(1<<4)
 93#define   GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA	(1<<9)
 94#define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	(1<<10)
 95#define   GUC_ENABLE_MIA_CLOCK_GATING		(1<<15)
 96#define   GUC_GEN10_SHIM_WC_ENABLE		(1<<21)
 97
 98#define GUC_SHIM_CONTROL2		_MMIO(0xc068)
 99#define   GUC_IS_PRIVILEGED		(1<<29)
100#define   GSC_LOADS_HUC			(1<<30)
101
102#define GUC_SEND_INTERRUPT		_MMIO(0xc4c8)
103#define   GUC_SEND_TRIGGER		  (1<<0)
104#define GEN11_GUC_HOST_INTERRUPT	_MMIO(0x1901f0)
105#define MEDIA_GUC_HOST_INTERRUPT	_MMIO(0x190304)
106
107#define GEN12_GUC_SEM_INTR_ENABLES	_MMIO(0xc71c)
108#define   GUC_SEM_INTR_ROUTE_TO_GUC	BIT(31)
109#define   GUC_SEM_INTR_ENABLE_ALL	(0xff)
110
111#define GUC_NUM_DOORBELLS		256
112
113/* format of the HW-monitored doorbell cacheline */
114struct guc_doorbell_info {
115	u32 db_status;
116#define GUC_DOORBELL_DISABLED		0
117#define GUC_DOORBELL_ENABLED		1
118
119	u32 cookie;
120	u32 reserved[14];
121} __packed;
122
123#define GEN8_DRBREGL(x)			_MMIO(0x1000 + (x) * 8)
124#define   GEN8_DRB_VALID		  (1<<0)
125#define GEN8_DRBREGU(x)			_MMIO(0x1000 + (x) * 8 + 4)
126
127#define GEN12_DIST_DBS_POPULATED		_MMIO(0xd08)
128#define   GEN12_DOORBELLS_PER_SQIDI_SHIFT	16
129#define   GEN12_DOORBELLS_PER_SQIDI		(0xff)
130#define   GEN12_SQIDIS_DOORBELL_EXIST		(0xffff)
131
132#define DE_GUCRMR			_MMIO(0x44054)
133
134#define GUC_BCS_RCS_IER			_MMIO(0xC550)
135#define GUC_VCS2_VCS1_IER		_MMIO(0xC554)
136#define GUC_WD_VECS_IER			_MMIO(0xC558)
137#define GUC_PM_P24C_IER			_MMIO(0xC55C)
138
139/* GuC Interrupt Vector */
140#define GUC_INTR_GUC2HOST		BIT(15)
141#define GUC_INTR_EXEC_ERROR		BIT(14)
142#define GUC_INTR_DISPLAY_EVENT		BIT(13)
143#define GUC_INTR_SEM_SIG		BIT(12)
144#define GUC_INTR_IOMMU2GUC		BIT(11)
145#define GUC_INTR_DOORBELL_RANG		BIT(10)
146#define GUC_INTR_DMA_DONE		BIT(9)
147#define GUC_INTR_FATAL_ERROR		BIT(8)
148#define GUC_INTR_NOTIF_ERROR		BIT(7)
149#define GUC_INTR_SW_INT_6		BIT(6)
150#define GUC_INTR_SW_INT_5		BIT(5)
151#define GUC_INTR_SW_INT_4		BIT(4)
152#define GUC_INTR_SW_INT_3		BIT(3)
153#define GUC_INTR_SW_INT_2		BIT(2)
154#define GUC_INTR_SW_INT_1		BIT(1)
155#define GUC_INTR_SW_INT_0		BIT(0)
156
157#endif