1/* SPDX-License-Identifier: MIT */
  2/*
  3 * Copyright © 2016-2019 Intel Corporation
  4 */
  5
  6#ifndef _INTEL_GUC_CT_H_
  7#define _INTEL_GUC_CT_H_
  8
  9#include <linux/interrupt.h>
 10#include <linux/spinlock.h>
 11#include <linux/workqueue.h>
 12#include <linux/ktime.h>
 13#include <linux/wait.h>
 14
 15#include "intel_guc_fwif.h"
 16
 17struct i915_vma;
 18struct intel_guc;
 19struct drm_printer;
 20
 21/**
 22 * DOC: Command Transport (CT).
 23 *
 24 * Buffer based command transport is a replacement for MMIO based mechanism.
 25 * It can be used to perform both host-2-guc and guc-to-host communication.
 26 */
 27
 28/** Represents single command transport buffer.
 29 *
 30 * A single command transport buffer consists of two parts, the header
 31 * record (command transport buffer descriptor) and the actual buffer which
 32 * holds the commands.
 33 *
 34 * @lock: protects access to the commands buffer and buffer descriptor
 35 * @desc: pointer to the buffer descriptor
 36 * @cmds: pointer to the commands buffer
 37 * @size: size of the commands buffer in dwords
 38 * @resv_space: reserved space in buffer in dwords
 39 * @head: local shadow copy of head in dwords
 40 * @tail: local shadow copy of tail in dwords
 41 * @space: local shadow copy of space in dwords
 42 * @broken: flag to indicate if descriptor data is broken
 43 */
 44struct intel_guc_ct_buffer {
 45	spinlock_t lock;
 46	struct guc_ct_buffer_desc *desc;
 47	u32 *cmds;
 48	u32 size;
 49	u32 resv_space;
 50	u32 tail;
 51	u32 head;
 52	atomic_t space;
 53	bool broken;
 54};
 55
 56/** Top-level structure for Command Transport related data
 57 *
 58 * Includes a pair of CT buffers for bi-directional communication and tracking
 59 * for the H2G and G2H requests sent and received through the buffers.
 60 */
 61struct intel_guc_ct {
 62	struct i915_vma *vma;
 63	bool enabled;
 64
 65	/* buffers for sending and receiving commands */
 66	struct {
 67		struct intel_guc_ct_buffer send;
 68		struct intel_guc_ct_buffer recv;
 69	} ctbs;
 70
 71	struct tasklet_struct receive_tasklet;
 72
 73	/** @wq: wait queue for g2h chanenl */
 74	wait_queue_head_t wq;
 75
 76	struct {
 77		u16 last_fence; /* last fence used to send request */
 78
 79		spinlock_t lock; /* protects pending requests list */
 80		struct list_head pending; /* requests waiting for response */
 81
 82		struct list_head incoming; /* incoming requests */
 83		struct work_struct worker; /* handler for incoming requests */
 84	} requests;
 85
 86	/** @stall_time: time of first time a CTB submission is stalled */
 87	ktime_t stall_time;
 88};
 89
 90void intel_guc_ct_init_early(struct intel_guc_ct *ct);
 91int intel_guc_ct_init(struct intel_guc_ct *ct);
 92void intel_guc_ct_fini(struct intel_guc_ct *ct);
 93int intel_guc_ct_enable(struct intel_guc_ct *ct);
 94void intel_guc_ct_disable(struct intel_guc_ct *ct);
 95
 96static inline void intel_guc_ct_sanitize(struct intel_guc_ct *ct)
 97{
 98	ct->enabled = false;
 99}
100
101static inline bool intel_guc_ct_enabled(struct intel_guc_ct *ct)
102{
103	return ct->enabled;
104}
105
106#define INTEL_GUC_CT_SEND_NB		BIT(31)
107#define INTEL_GUC_CT_SEND_G2H_DW_SHIFT	0
108#define INTEL_GUC_CT_SEND_G2H_DW_MASK	(0xff << INTEL_GUC_CT_SEND_G2H_DW_SHIFT)
109#define MAKE_SEND_FLAGS(len) ({ \
110	typeof(len) len_ = (len); \
111	GEM_BUG_ON(!FIELD_FIT(INTEL_GUC_CT_SEND_G2H_DW_MASK, len_)); \
112	(FIELD_PREP(INTEL_GUC_CT_SEND_G2H_DW_MASK, len_) | INTEL_GUC_CT_SEND_NB); \
113})
114int intel_guc_ct_send(struct intel_guc_ct *ct, const u32 *action, u32 len,
115		      u32 *response_buf, u32 response_buf_size, u32 flags);
116void intel_guc_ct_event_handler(struct intel_guc_ct *ct);
117
118void intel_guc_ct_print_info(struct intel_guc_ct *ct, struct drm_printer *p);
119
120#endif /* _INTEL_GUC_CT_H_ */