Loading...
Note: File does not exist in v4.6.
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2014-2019 Intel Corporation
4 */
5
6#include "gem/i915_gem_lmem.h"
7#include "gt/intel_gt.h"
8#include "gt/intel_gt_irq.h"
9#include "gt/intel_gt_pm_irq.h"
10#include "gt/intel_gt_regs.h"
11#include "intel_guc.h"
12#include "intel_guc_ads.h"
13#include "intel_guc_capture.h"
14#include "intel_guc_slpc.h"
15#include "intel_guc_submission.h"
16#include "i915_drv.h"
17#include "i915_irq.h"
18
19/**
20 * DOC: GuC
21 *
22 * The GuC is a microcontroller inside the GT HW, introduced in gen9. The GuC is
23 * designed to offload some of the functionality usually performed by the host
24 * driver; currently the main operations it can take care of are:
25 *
26 * - Authentication of the HuC, which is required to fully enable HuC usage.
27 * - Low latency graphics context scheduling (a.k.a. GuC submission).
28 * - GT Power management.
29 *
30 * The enable_guc module parameter can be used to select which of those
31 * operations to enable within GuC. Note that not all the operations are
32 * supported on all gen9+ platforms.
33 *
34 * Enabling the GuC is not mandatory and therefore the firmware is only loaded
35 * if at least one of the operations is selected. However, not loading the GuC
36 * might result in the loss of some features that do require the GuC (currently
37 * just the HuC, but more are expected to land in the future).
38 */
39
40void intel_guc_notify(struct intel_guc *guc)
41{
42 struct intel_gt *gt = guc_to_gt(guc);
43
44 /*
45 * On Gen11+, the value written to the register is passes as a payload
46 * to the FW. However, the FW currently treats all values the same way
47 * (H2G interrupt), so we can just write the value that the HW expects
48 * on older gens.
49 */
50 intel_uncore_write(gt->uncore, guc->notify_reg, GUC_SEND_TRIGGER);
51}
52
53static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
54{
55 GEM_BUG_ON(!guc->send_regs.base);
56 GEM_BUG_ON(!guc->send_regs.count);
57 GEM_BUG_ON(i >= guc->send_regs.count);
58
59 return _MMIO(guc->send_regs.base + 4 * i);
60}
61
62void intel_guc_init_send_regs(struct intel_guc *guc)
63{
64 struct intel_gt *gt = guc_to_gt(guc);
65 enum forcewake_domains fw_domains = 0;
66 unsigned int i;
67
68 GEM_BUG_ON(!guc->send_regs.base);
69 GEM_BUG_ON(!guc->send_regs.count);
70
71 for (i = 0; i < guc->send_regs.count; i++) {
72 fw_domains |= intel_uncore_forcewake_for_reg(gt->uncore,
73 guc_send_reg(guc, i),
74 FW_REG_READ | FW_REG_WRITE);
75 }
76 guc->send_regs.fw_domains = fw_domains;
77}
78
79static void gen9_reset_guc_interrupts(struct intel_guc *guc)
80{
81 struct intel_gt *gt = guc_to_gt(guc);
82
83 assert_rpm_wakelock_held(>->i915->runtime_pm);
84
85 spin_lock_irq(gt->irq_lock);
86 gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
87 spin_unlock_irq(gt->irq_lock);
88}
89
90static void gen9_enable_guc_interrupts(struct intel_guc *guc)
91{
92 struct intel_gt *gt = guc_to_gt(guc);
93
94 assert_rpm_wakelock_held(>->i915->runtime_pm);
95
96 spin_lock_irq(gt->irq_lock);
97 WARN_ON_ONCE(intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) &
98 gt->pm_guc_events);
99 gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
100 spin_unlock_irq(gt->irq_lock);
101
102 guc->interrupts.enabled = true;
103}
104
105static void gen9_disable_guc_interrupts(struct intel_guc *guc)
106{
107 struct intel_gt *gt = guc_to_gt(guc);
108
109 assert_rpm_wakelock_held(>->i915->runtime_pm);
110 guc->interrupts.enabled = false;
111
112 spin_lock_irq(gt->irq_lock);
113
114 gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
115
116 spin_unlock_irq(gt->irq_lock);
117 intel_synchronize_irq(gt->i915);
118
119 gen9_reset_guc_interrupts(guc);
120}
121
122static bool __gen11_reset_guc_interrupts(struct intel_gt *gt)
123{
124 u32 irq = gt->type == GT_MEDIA ? MTL_MGUC : GEN11_GUC;
125
126 lockdep_assert_held(gt->irq_lock);
127 return gen11_gt_reset_one_iir(gt, 0, irq);
128}
129
130static void gen11_reset_guc_interrupts(struct intel_guc *guc)
131{
132 struct intel_gt *gt = guc_to_gt(guc);
133
134 spin_lock_irq(gt->irq_lock);
135 __gen11_reset_guc_interrupts(gt);
136 spin_unlock_irq(gt->irq_lock);
137}
138
139static void gen11_enable_guc_interrupts(struct intel_guc *guc)
140{
141 struct intel_gt *gt = guc_to_gt(guc);
142
143 spin_lock_irq(gt->irq_lock);
144 __gen11_reset_guc_interrupts(gt);
145 spin_unlock_irq(gt->irq_lock);
146
147 guc->interrupts.enabled = true;
148}
149
150static void gen11_disable_guc_interrupts(struct intel_guc *guc)
151{
152 struct intel_gt *gt = guc_to_gt(guc);
153
154 guc->interrupts.enabled = false;
155 intel_synchronize_irq(gt->i915);
156
157 gen11_reset_guc_interrupts(guc);
158}
159
160void intel_guc_init_early(struct intel_guc *guc)
161{
162 struct intel_gt *gt = guc_to_gt(guc);
163 struct drm_i915_private *i915 = gt->i915;
164
165 intel_uc_fw_init_early(&guc->fw, INTEL_UC_FW_TYPE_GUC);
166 intel_guc_ct_init_early(&guc->ct);
167 intel_guc_log_init_early(&guc->log);
168 intel_guc_submission_init_early(guc);
169 intel_guc_slpc_init_early(&guc->slpc);
170 intel_guc_rc_init_early(guc);
171
172 mutex_init(&guc->send_mutex);
173 spin_lock_init(&guc->irq_lock);
174 if (GRAPHICS_VER(i915) >= 11) {
175 guc->interrupts.reset = gen11_reset_guc_interrupts;
176 guc->interrupts.enable = gen11_enable_guc_interrupts;
177 guc->interrupts.disable = gen11_disable_guc_interrupts;
178 if (gt->type == GT_MEDIA) {
179 guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT;
180 guc->send_regs.base = i915_mmio_reg_offset(MEDIA_SOFT_SCRATCH(0));
181 } else {
182 guc->notify_reg = GEN11_GUC_HOST_INTERRUPT;
183 guc->send_regs.base = i915_mmio_reg_offset(GEN11_SOFT_SCRATCH(0));
184 }
185
186 guc->send_regs.count = GEN11_SOFT_SCRATCH_COUNT;
187
188 } else {
189 guc->notify_reg = GUC_SEND_INTERRUPT;
190 guc->interrupts.reset = gen9_reset_guc_interrupts;
191 guc->interrupts.enable = gen9_enable_guc_interrupts;
192 guc->interrupts.disable = gen9_disable_guc_interrupts;
193 guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
194 guc->send_regs.count = GUC_MAX_MMIO_MSG_LEN;
195 BUILD_BUG_ON(GUC_MAX_MMIO_MSG_LEN > SOFT_SCRATCH_COUNT);
196 }
197
198 intel_guc_enable_msg(guc, INTEL_GUC_RECV_MSG_EXCEPTION |
199 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED);
200}
201
202void intel_guc_init_late(struct intel_guc *guc)
203{
204 intel_guc_ads_init_late(guc);
205}
206
207static u32 guc_ctl_debug_flags(struct intel_guc *guc)
208{
209 u32 level = intel_guc_log_get_level(&guc->log);
210 u32 flags = 0;
211
212 if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
213 flags |= GUC_LOG_DISABLED;
214 else
215 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
216 GUC_LOG_VERBOSITY_SHIFT;
217
218 return flags;
219}
220
221static u32 guc_ctl_feature_flags(struct intel_guc *guc)
222{
223 u32 flags = 0;
224
225 if (!intel_guc_submission_is_used(guc))
226 flags |= GUC_CTL_DISABLE_SCHEDULER;
227
228 if (intel_guc_slpc_is_used(guc))
229 flags |= GUC_CTL_ENABLE_SLPC;
230
231 return flags;
232}
233
234static u32 guc_ctl_log_params_flags(struct intel_guc *guc)
235{
236 struct intel_guc_log *log = &guc->log;
237 u32 offset, flags;
238
239 GEM_BUG_ON(!log->sizes_initialised);
240
241 offset = intel_guc_ggtt_offset(guc, log->vma) >> PAGE_SHIFT;
242
243 flags = GUC_LOG_VALID |
244 GUC_LOG_NOTIFY_ON_HALF_FULL |
245 log->sizes[GUC_LOG_SECTIONS_DEBUG].flag |
246 log->sizes[GUC_LOG_SECTIONS_CAPTURE].flag |
247 (log->sizes[GUC_LOG_SECTIONS_CRASH].count << GUC_LOG_CRASH_SHIFT) |
248 (log->sizes[GUC_LOG_SECTIONS_DEBUG].count << GUC_LOG_DEBUG_SHIFT) |
249 (log->sizes[GUC_LOG_SECTIONS_CAPTURE].count << GUC_LOG_CAPTURE_SHIFT) |
250 (offset << GUC_LOG_BUF_ADDR_SHIFT);
251
252 return flags;
253}
254
255static u32 guc_ctl_ads_flags(struct intel_guc *guc)
256{
257 u32 ads = intel_guc_ggtt_offset(guc, guc->ads_vma) >> PAGE_SHIFT;
258 u32 flags = ads << GUC_ADS_ADDR_SHIFT;
259
260 return flags;
261}
262
263static u32 guc_ctl_wa_flags(struct intel_guc *guc)
264{
265 struct intel_gt *gt = guc_to_gt(guc);
266 u32 flags = 0;
267
268 /* Wa_22012773006:gen11,gen12 < XeHP */
269 if (GRAPHICS_VER(gt->i915) >= 11 &&
270 GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 50))
271 flags |= GUC_WA_POLLCS;
272
273 /* Wa_16011759253:dg2_g10:a0 */
274 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_B0))
275 flags |= GUC_WA_GAM_CREDITS;
276
277 /* Wa_14014475959:dg2 */
278 if (IS_DG2(gt->i915))
279 flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
280
281 /*
282 * Wa_14012197797:dg2_g10:a0,dg2_g11:a0
283 * Wa_22011391025:dg2_g10,dg2_g11,dg2_g12
284 *
285 * The same WA bit is used for both and 22011391025 is applicable to
286 * all DG2.
287 */
288 if (IS_DG2(gt->i915))
289 flags |= GUC_WA_DUAL_QUEUE;
290
291 /* Wa_22011802037: graphics version 11/12 */
292 if (IS_GRAPHICS_VER(gt->i915, 11, 12))
293 flags |= GUC_WA_PRE_PARSER;
294
295 /* Wa_16011777198:dg2 */
296 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
297 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
298 flags |= GUC_WA_RCS_RESET_BEFORE_RC6;
299
300 /*
301 * Wa_22012727170:dg2_g10[a0-c0), dg2_g11[a0..)
302 * Wa_22012727685:dg2_g11[a0..)
303 */
304 if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
305 IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_FOREVER))
306 flags |= GUC_WA_CONTEXT_ISOLATION;
307
308 /* Wa_16015675438 */
309 if (!RCS_MASK(gt))
310 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST;
311
312 return flags;
313}
314
315static u32 guc_ctl_devid(struct intel_guc *guc)
316{
317 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
318
319 return (INTEL_DEVID(i915) << 16) | INTEL_REVID(i915);
320}
321
322/*
323 * Initialise the GuC parameter block before starting the firmware
324 * transfer. These parameters are read by the firmware on startup
325 * and cannot be changed thereafter.
326 */
327static void guc_init_params(struct intel_guc *guc)
328{
329 u32 *params = guc->params;
330 int i;
331
332 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32));
333
334 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc);
335 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
336 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
337 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc);
338 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc);
339 params[GUC_CTL_DEVID] = guc_ctl_devid(guc);
340
341 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
342 DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
343}
344
345/*
346 * Initialise the GuC parameter block before starting the firmware
347 * transfer. These parameters are read by the firmware on startup
348 * and cannot be changed thereafter.
349 */
350void intel_guc_write_params(struct intel_guc *guc)
351{
352 struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
353 int i;
354
355 /*
356 * All SOFT_SCRATCH registers are in FORCEWAKE_GT domain and
357 * they are power context saved so it's ok to release forcewake
358 * when we are done here and take it again at xfer time.
359 */
360 intel_uncore_forcewake_get(uncore, FORCEWAKE_GT);
361
362 intel_uncore_write(uncore, SOFT_SCRATCH(0), 0);
363
364 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
365 intel_uncore_write(uncore, SOFT_SCRATCH(1 + i), guc->params[i]);
366
367 intel_uncore_forcewake_put(uncore, FORCEWAKE_GT);
368}
369
370void intel_guc_dump_time_info(struct intel_guc *guc, struct drm_printer *p)
371{
372 struct intel_gt *gt = guc_to_gt(guc);
373 intel_wakeref_t wakeref;
374 u32 stamp = 0;
375 u64 ktime;
376
377 with_intel_runtime_pm(>->i915->runtime_pm, wakeref)
378 stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP);
379 ktime = ktime_get_boottime_ns();
380
381 drm_printf(p, "Kernel timestamp: 0x%08llX [%llu]\n", ktime, ktime);
382 drm_printf(p, "GuC timestamp: 0x%08X [%u]\n", stamp, stamp);
383 drm_printf(p, "CS timestamp frequency: %u Hz, %u ns\n",
384 gt->clock_frequency, gt->clock_period_ns);
385}
386
387int intel_guc_init(struct intel_guc *guc)
388{
389 struct intel_gt *gt = guc_to_gt(guc);
390 int ret;
391
392 ret = intel_uc_fw_init(&guc->fw);
393 if (ret)
394 goto out;
395
396 ret = intel_guc_log_create(&guc->log);
397 if (ret)
398 goto err_fw;
399
400 ret = intel_guc_capture_init(guc);
401 if (ret)
402 goto err_log;
403
404 ret = intel_guc_ads_create(guc);
405 if (ret)
406 goto err_capture;
407
408 GEM_BUG_ON(!guc->ads_vma);
409
410 ret = intel_guc_ct_init(&guc->ct);
411 if (ret)
412 goto err_ads;
413
414 if (intel_guc_submission_is_used(guc)) {
415 /*
416 * This is stuff we need to have available at fw load time
417 * if we are planning to enable submission later
418 */
419 ret = intel_guc_submission_init(guc);
420 if (ret)
421 goto err_ct;
422 }
423
424 if (intel_guc_slpc_is_used(guc)) {
425 ret = intel_guc_slpc_init(&guc->slpc);
426 if (ret)
427 goto err_submission;
428 }
429
430 /* now that everything is perma-pinned, initialize the parameters */
431 guc_init_params(guc);
432
433 /* We need to notify the guc whenever we change the GGTT */
434 i915_ggtt_enable_guc(gt->ggtt);
435
436 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_LOADABLE);
437
438 return 0;
439
440err_submission:
441 intel_guc_submission_fini(guc);
442err_ct:
443 intel_guc_ct_fini(&guc->ct);
444err_ads:
445 intel_guc_ads_destroy(guc);
446err_capture:
447 intel_guc_capture_destroy(guc);
448err_log:
449 intel_guc_log_destroy(&guc->log);
450err_fw:
451 intel_uc_fw_fini(&guc->fw);
452out:
453 intel_uc_fw_change_status(&guc->fw, INTEL_UC_FIRMWARE_INIT_FAIL);
454 i915_probe_error(gt->i915, "failed with %d\n", ret);
455 return ret;
456}
457
458void intel_guc_fini(struct intel_guc *guc)
459{
460 struct intel_gt *gt = guc_to_gt(guc);
461
462 if (!intel_uc_fw_is_loadable(&guc->fw))
463 return;
464
465 i915_ggtt_disable_guc(gt->ggtt);
466
467 if (intel_guc_slpc_is_used(guc))
468 intel_guc_slpc_fini(&guc->slpc);
469
470 if (intel_guc_submission_is_used(guc))
471 intel_guc_submission_fini(guc);
472
473 intel_guc_ct_fini(&guc->ct);
474
475 intel_guc_ads_destroy(guc);
476 intel_guc_capture_destroy(guc);
477 intel_guc_log_destroy(&guc->log);
478 intel_uc_fw_fini(&guc->fw);
479}
480
481/*
482 * This function implements the MMIO based host to GuC interface.
483 */
484int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len,
485 u32 *response_buf, u32 response_buf_size)
486{
487 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
488 struct intel_uncore *uncore = guc_to_gt(guc)->uncore;
489 u32 header;
490 int i;
491 int ret;
492
493 GEM_BUG_ON(!len);
494 GEM_BUG_ON(len > guc->send_regs.count);
495
496 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST);
497 GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST);
498
499 mutex_lock(&guc->send_mutex);
500 intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains);
501
502retry:
503 for (i = 0; i < len; i++)
504 intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]);
505
506 intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1));
507
508 intel_guc_notify(guc);
509
510 /*
511 * No GuC command should ever take longer than 10ms.
512 * Fast commands should still complete in 10us.
513 */
514 ret = __intel_wait_for_register_fw(uncore,
515 guc_send_reg(guc, 0),
516 GUC_HXG_MSG_0_ORIGIN,
517 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN,
518 GUC_HXG_ORIGIN_GUC),
519 10, 10, &header);
520 if (unlikely(ret)) {
521timeout:
522 drm_err(&i915->drm, "mmio request %#x: no reply %x\n",
523 request[0], header);
524 goto out;
525 }
526
527 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
528#define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \
529 FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \
530 FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; })
531
532 ret = wait_for(done, 1000);
533 if (unlikely(ret))
534 goto timeout;
535 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) !=
536 GUC_HXG_ORIGIN_GUC))
537 goto proto;
538#undef done
539 }
540
541 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
542 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header);
543
544 drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n",
545 request[0], reason);
546 goto retry;
547 }
548
549 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) {
550 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header);
551 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header);
552
553 drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n",
554 request[0], error, hint);
555 ret = -ENXIO;
556 goto out;
557 }
558
559 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) {
560proto:
561 drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n",
562 request[0], header);
563 ret = -EPROTO;
564 goto out;
565 }
566
567 if (response_buf) {
568 int count = min(response_buf_size, guc->send_regs.count);
569
570 GEM_BUG_ON(!count);
571
572 response_buf[0] = header;
573
574 for (i = 1; i < count; i++)
575 response_buf[i] = intel_uncore_read(uncore,
576 guc_send_reg(guc, i));
577
578 /* Use number of copied dwords as our return value */
579 ret = count;
580 } else {
581 /* Use data from the GuC response as our return value */
582 ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header);
583 }
584
585out:
586 intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains);
587 mutex_unlock(&guc->send_mutex);
588
589 return ret;
590}
591
592int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
593 const u32 *payload, u32 len)
594{
595 u32 msg;
596
597 if (unlikely(!len))
598 return -EPROTO;
599
600 /* Make sure to handle only enabled messages */
601 msg = payload[0] & guc->msg_enabled_mask;
602
603 if (msg & INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)
604 drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC crash dump notification!\n");
605 if (msg & INTEL_GUC_RECV_MSG_EXCEPTION)
606 drm_err(&guc_to_gt(guc)->i915->drm, "Received early GuC exception notification!\n");
607
608 return 0;
609}
610
611/**
612 * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
613 * @guc: intel_guc structure
614 * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
615 *
616 * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
617 * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
618 * intel_huc_auth().
619 *
620 * Return: non-zero code on error
621 */
622int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
623{
624 u32 action[] = {
625 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
626 rsa_offset
627 };
628
629 return intel_guc_send(guc, action, ARRAY_SIZE(action));
630}
631
632/**
633 * intel_guc_suspend() - notify GuC entering suspend state
634 * @guc: the guc
635 */
636int intel_guc_suspend(struct intel_guc *guc)
637{
638 int ret;
639 u32 action[] = {
640 INTEL_GUC_ACTION_CLIENT_SOFT_RESET,
641 };
642
643 if (!intel_guc_is_ready(guc))
644 return 0;
645
646 if (intel_guc_submission_is_used(guc)) {
647 /*
648 * This H2G MMIO command tears down the GuC in two steps. First it will
649 * generate a G2H CTB for every active context indicating a reset. In
650 * practice the i915 shouldn't ever get a G2H as suspend should only be
651 * called when the GPU is idle. Next, it tears down the CTBs and this
652 * H2G MMIO command completes.
653 *
654 * Don't abort on a failure code from the GuC. Keep going and do the
655 * clean up in santize() and re-initialisation on resume and hopefully
656 * the error here won't be problematic.
657 */
658 ret = intel_guc_send_mmio(guc, action, ARRAY_SIZE(action), NULL, 0);
659 if (ret)
660 DRM_ERROR("GuC suspend: RESET_CLIENT action failed with error %d!\n", ret);
661 }
662
663 /* Signal that the GuC isn't running. */
664 intel_guc_sanitize(guc);
665
666 return 0;
667}
668
669/**
670 * intel_guc_resume() - notify GuC resuming from suspend state
671 * @guc: the guc
672 */
673int intel_guc_resume(struct intel_guc *guc)
674{
675 /*
676 * NB: This function can still be called even if GuC submission is
677 * disabled, e.g. if GuC is enabled for HuC authentication only. Thus,
678 * if any code is later added here, it must be support doing nothing
679 * if submission is disabled (as per intel_guc_suspend).
680 */
681 return 0;
682}
683
684/**
685 * DOC: GuC Memory Management
686 *
687 * GuC can't allocate any memory for its own usage, so all the allocations must
688 * be handled by the host driver. GuC accesses the memory via the GGTT, with the
689 * exception of the top and bottom parts of the 4GB address space, which are
690 * instead re-mapped by the GuC HW to memory location of the FW itself (WOPCM)
691 * or other parts of the HW. The driver must take care not to place objects that
692 * the GuC is going to access in these reserved ranges. The layout of the GuC
693 * address space is shown below:
694 *
695 * ::
696 *
697 * +===========> +====================+ <== FFFF_FFFF
698 * ^ | Reserved |
699 * | +====================+ <== GUC_GGTT_TOP
700 * | | |
701 * | | DRAM |
702 * GuC | |
703 * Address +===> +====================+ <== GuC ggtt_pin_bias
704 * Space ^ | |
705 * | | | |
706 * | GuC | GuC |
707 * | WOPCM | WOPCM |
708 * | Size | |
709 * | | | |
710 * v v | |
711 * +=======+===> +====================+ <== 0000_0000
712 *
713 * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to GuC WOPCM
714 * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
715 * to DRAM. The value of the GuC ggtt_pin_bias is the GuC WOPCM size.
716 */
717
718/**
719 * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
720 * @guc: the guc
721 * @size: size of area to allocate (both virtual space and memory)
722 *
723 * This is a wrapper to create an object for use with the GuC. In order to
724 * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
725 * both some backing storage and a range inside the Global GTT. We must pin
726 * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
727 * range is reserved inside GuC.
728 *
729 * Return: A i915_vma if successful, otherwise an ERR_PTR.
730 */
731struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
732{
733 struct intel_gt *gt = guc_to_gt(guc);
734 struct drm_i915_gem_object *obj;
735 struct i915_vma *vma;
736 u64 flags;
737 int ret;
738
739 if (HAS_LMEM(gt->i915))
740 obj = i915_gem_object_create_lmem(gt->i915, size,
741 I915_BO_ALLOC_CPU_CLEAR |
742 I915_BO_ALLOC_CONTIGUOUS |
743 I915_BO_ALLOC_PM_EARLY);
744 else
745 obj = i915_gem_object_create_shmem(gt->i915, size);
746
747 if (IS_ERR(obj))
748 return ERR_CAST(obj);
749
750 vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
751 if (IS_ERR(vma))
752 goto err;
753
754 flags = PIN_OFFSET_BIAS | i915_ggtt_pin_bias(vma);
755 ret = i915_ggtt_pin(vma, NULL, 0, flags);
756 if (ret) {
757 vma = ERR_PTR(ret);
758 goto err;
759 }
760
761 return i915_vma_make_unshrinkable(vma);
762
763err:
764 i915_gem_object_put(obj);
765 return vma;
766}
767
768/**
769 * intel_guc_allocate_and_map_vma() - Allocate and map VMA for GuC usage
770 * @guc: the guc
771 * @size: size of area to allocate (both virtual space and memory)
772 * @out_vma: return variable for the allocated vma pointer
773 * @out_vaddr: return variable for the obj mapping
774 *
775 * This wrapper calls intel_guc_allocate_vma() and then maps the allocated
776 * object with I915_MAP_WB.
777 *
778 * Return: 0 if successful, a negative errno code otherwise.
779 */
780int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
781 struct i915_vma **out_vma, void **out_vaddr)
782{
783 struct i915_vma *vma;
784 void *vaddr;
785
786 vma = intel_guc_allocate_vma(guc, size);
787 if (IS_ERR(vma))
788 return PTR_ERR(vma);
789
790 vaddr = i915_gem_object_pin_map_unlocked(vma->obj,
791 i915_coherent_map_type(guc_to_gt(guc)->i915,
792 vma->obj, true));
793 if (IS_ERR(vaddr)) {
794 i915_vma_unpin_and_release(&vma, 0);
795 return PTR_ERR(vaddr);
796 }
797
798 *out_vma = vma;
799 *out_vaddr = vaddr;
800
801 return 0;
802}
803
804static int __guc_action_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
805{
806 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = {
807 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) |
808 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) |
809 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, GUC_ACTION_HOST2GUC_SELF_CFG),
810 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) |
811 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len),
812 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, lower_32_bits(value)),
813 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, upper_32_bits(value)),
814 };
815 int ret;
816
817 GEM_BUG_ON(len > 2);
818 GEM_BUG_ON(len == 1 && upper_32_bits(value));
819
820 /* Self config must go over MMIO */
821 ret = intel_guc_send_mmio(guc, request, ARRAY_SIZE(request), NULL, 0);
822
823 if (unlikely(ret < 0))
824 return ret;
825 if (unlikely(ret > 1))
826 return -EPROTO;
827 if (unlikely(!ret))
828 return -ENOKEY;
829
830 return 0;
831}
832
833static int __guc_self_cfg(struct intel_guc *guc, u16 key, u16 len, u64 value)
834{
835 struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
836 int err = __guc_action_self_cfg(guc, key, len, value);
837
838 if (unlikely(err))
839 i915_probe_error(i915, "Unsuccessful self-config (%pe) key %#hx value %#llx\n",
840 ERR_PTR(err), key, value);
841 return err;
842}
843
844int intel_guc_self_cfg32(struct intel_guc *guc, u16 key, u32 value)
845{
846 return __guc_self_cfg(guc, key, 1, value);
847}
848
849int intel_guc_self_cfg64(struct intel_guc *guc, u16 key, u64 value)
850{
851 return __guc_self_cfg(guc, key, 2, value);
852}
853
854/**
855 * intel_guc_load_status - dump information about GuC load status
856 * @guc: the GuC
857 * @p: the &drm_printer
858 *
859 * Pretty printer for GuC load status.
860 */
861void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p)
862{
863 struct intel_gt *gt = guc_to_gt(guc);
864 struct intel_uncore *uncore = gt->uncore;
865 intel_wakeref_t wakeref;
866
867 if (!intel_guc_is_supported(guc)) {
868 drm_printf(p, "GuC not supported\n");
869 return;
870 }
871
872 if (!intel_guc_is_wanted(guc)) {
873 drm_printf(p, "GuC disabled\n");
874 return;
875 }
876
877 intel_uc_fw_dump(&guc->fw, p);
878
879 with_intel_runtime_pm(uncore->rpm, wakeref) {
880 u32 status = intel_uncore_read(uncore, GUC_STATUS);
881 u32 i;
882
883 drm_printf(p, "GuC status 0x%08x:\n", status);
884 drm_printf(p, "\tBootrom status = 0x%x\n",
885 (status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
886 drm_printf(p, "\tuKernel status = 0x%x\n",
887 (status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
888 drm_printf(p, "\tMIA Core status = 0x%x\n",
889 (status & GS_MIA_MASK) >> GS_MIA_SHIFT);
890 drm_puts(p, "Scratch registers:\n");
891 for (i = 0; i < 16; i++) {
892 drm_printf(p, "\t%2d: \t0x%x\n",
893 i, intel_uncore_read(uncore, SOFT_SCRATCH(i)));
894 }
895 }
896}
897
898void intel_guc_write_barrier(struct intel_guc *guc)
899{
900 struct intel_gt *gt = guc_to_gt(guc);
901
902 if (i915_gem_object_is_lmem(guc->ct.vma->obj)) {
903 /*
904 * Ensure intel_uncore_write_fw can be used rather than
905 * intel_uncore_write.
906 */
907 GEM_BUG_ON(guc->send_regs.fw_domains);
908
909 /*
910 * This register is used by the i915 and GuC for MMIO based
911 * communication. Once we are in this code CTBs are the only
912 * method the i915 uses to communicate with the GuC so it is
913 * safe to write to this register (a value of 0 is NOP for MMIO
914 * communication). If we ever start mixing CTBs and MMIOs a new
915 * register will have to be chosen. This function is also used
916 * to enforce ordering of a work queue item write and an update
917 * to the process descriptor. When a work queue is being used,
918 * CTBs are also the only mechanism of communication.
919 */
920 intel_uncore_write_fw(gt->uncore, GEN11_SOFT_SCRATCH(0), 0);
921 } else {
922 /* wmb() sufficient for a barrier if in smem */
923 wmb();
924 }
925}