Loading...
1/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * Freescale DCU drm device driver
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/clk.h>
13#include <linux/regmap.h>
14
15#include <drm/drmP.h>
16#include <drm/drm_atomic.h>
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_crtc.h>
19#include <drm/drm_crtc_helper.h>
20
21#include "fsl_dcu_drm_crtc.h"
22#include "fsl_dcu_drm_drv.h"
23#include "fsl_dcu_drm_plane.h"
24
25static void fsl_dcu_drm_crtc_atomic_begin(struct drm_crtc *crtc,
26 struct drm_crtc_state *old_crtc_state)
27{
28}
29
30static int fsl_dcu_drm_crtc_atomic_check(struct drm_crtc *crtc,
31 struct drm_crtc_state *state)
32{
33 return 0;
34}
35
36static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
37 struct drm_crtc_state *old_crtc_state)
38{
39}
40
41static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
42{
43 struct drm_device *dev = crtc->dev;
44 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
45
46 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
47 DCU_MODE_DCU_MODE_MASK,
48 DCU_MODE_DCU_MODE(DCU_MODE_OFF));
49 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
50 DCU_UPDATE_MODE_READREG);
51}
52
53static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
54{
55 struct drm_device *dev = crtc->dev;
56 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
57
58 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
59 DCU_MODE_DCU_MODE_MASK,
60 DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
61 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
62 DCU_UPDATE_MODE_READREG);
63}
64
65static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
66{
67 struct drm_device *dev = crtc->dev;
68 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
69 struct drm_display_mode *mode = &crtc->state->mode;
70 unsigned int hbp, hfp, hsw, vbp, vfp, vsw, div, index, pol = 0;
71 unsigned long dcuclk;
72
73 index = drm_crtc_index(crtc);
74 dcuclk = clk_get_rate(fsl_dev->clk);
75 div = dcuclk / mode->clock / 1000;
76
77 /* Configure timings: */
78 hbp = mode->htotal - mode->hsync_end;
79 hfp = mode->hsync_start - mode->hdisplay;
80 hsw = mode->hsync_end - mode->hsync_start;
81 vbp = mode->vtotal - mode->vsync_end;
82 vfp = mode->vsync_start - mode->vdisplay;
83 vsw = mode->vsync_end - mode->vsync_start;
84
85 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
86 pol |= DCU_SYN_POL_INV_HS_LOW;
87
88 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
89 pol |= DCU_SYN_POL_INV_VS_LOW;
90
91 regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
92 DCU_HSYN_PARA_BP(hbp) |
93 DCU_HSYN_PARA_PW(hsw) |
94 DCU_HSYN_PARA_FP(hfp));
95 regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
96 DCU_VSYN_PARA_BP(vbp) |
97 DCU_VSYN_PARA_PW(vsw) |
98 DCU_VSYN_PARA_FP(vfp));
99 regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
100 DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
101 DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
102 regmap_write(fsl_dev->regmap, DCU_DIV_RATIO, div);
103 regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
104 regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
105 DCU_BGND_G(0) | DCU_BGND_B(0));
106 regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
107 DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
108 regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
109 DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
110 DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
111 DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
112 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
113 DCU_UPDATE_MODE_READREG);
114 return;
115}
116
117static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
118 .atomic_begin = fsl_dcu_drm_crtc_atomic_begin,
119 .atomic_check = fsl_dcu_drm_crtc_atomic_check,
120 .atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
121 .disable = fsl_dcu_drm_disable_crtc,
122 .enable = fsl_dcu_drm_crtc_enable,
123 .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
124};
125
126static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
127 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
128 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
129 .destroy = drm_crtc_cleanup,
130 .page_flip = drm_atomic_helper_page_flip,
131 .reset = drm_atomic_helper_crtc_reset,
132 .set_config = drm_atomic_helper_set_config,
133};
134
135int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
136{
137 struct drm_plane *primary;
138 struct drm_crtc *crtc = &fsl_dev->crtc;
139 unsigned int i, j, reg_num;
140 int ret;
141
142 primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
143 if (!primary)
144 return -ENOMEM;
145
146 ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
147 &fsl_dcu_drm_crtc_funcs, NULL);
148 if (ret) {
149 primary->funcs->destroy(primary);
150 return ret;
151 }
152
153 drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
154
155 if (!strcmp(fsl_dev->soc->name, "ls1021a"))
156 reg_num = LS1021A_LAYER_REG_NUM;
157 else
158 reg_num = VF610_LAYER_REG_NUM;
159 for (i = 0; i < fsl_dev->soc->total_layer; i++) {
160 for (j = 1; j <= reg_num; j++)
161 regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
162 }
163 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
164 DCU_MODE_DCU_MODE_MASK,
165 DCU_MODE_DCU_MODE(DCU_MODE_OFF));
166 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
167 DCU_UPDATE_MODE_READREG);
168
169 return 0;
170}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 *
5 * Freescale DCU drm device driver
6 */
7
8#include <linux/clk.h>
9#include <linux/regmap.h>
10
11#include <video/videomode.h>
12
13#include <drm/drm_atomic.h>
14#include <drm/drm_atomic_helper.h>
15#include <drm/drm_crtc.h>
16#include <drm/drm_probe_helper.h>
17#include <drm/drm_vblank.h>
18
19#include "fsl_dcu_drm_crtc.h"
20#include "fsl_dcu_drm_drv.h"
21#include "fsl_dcu_drm_plane.h"
22
23static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
24 struct drm_atomic_state *state)
25{
26 struct drm_device *dev = crtc->dev;
27 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
28 struct drm_pending_vblank_event *event = crtc->state->event;
29
30 regmap_write(fsl_dev->regmap,
31 DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG);
32
33 if (event) {
34 crtc->state->event = NULL;
35
36 spin_lock_irq(&crtc->dev->event_lock);
37 if (drm_crtc_vblank_get(crtc) == 0)
38 drm_crtc_arm_vblank_event(crtc, event);
39 else
40 drm_crtc_send_vblank_event(crtc, event);
41 spin_unlock_irq(&crtc->dev->event_lock);
42 }
43}
44
45static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc,
46 struct drm_atomic_state *state)
47{
48 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
49 crtc);
50 struct drm_device *dev = crtc->dev;
51 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
52
53 /* always disable planes on the CRTC */
54 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, true);
55
56 drm_crtc_vblank_off(crtc);
57
58 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
59 DCU_MODE_DCU_MODE_MASK,
60 DCU_MODE_DCU_MODE(DCU_MODE_OFF));
61 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
62 DCU_UPDATE_MODE_READREG);
63 clk_disable_unprepare(fsl_dev->pix_clk);
64}
65
66static void fsl_dcu_drm_crtc_atomic_enable(struct drm_crtc *crtc,
67 struct drm_atomic_state *state)
68{
69 struct drm_device *dev = crtc->dev;
70 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
71
72 clk_prepare_enable(fsl_dev->pix_clk);
73 regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
74 DCU_MODE_DCU_MODE_MASK,
75 DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
76 regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
77 DCU_UPDATE_MODE_READREG);
78
79 drm_crtc_vblank_on(crtc);
80}
81
82static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
83{
84 struct drm_device *dev = crtc->dev;
85 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
86 struct drm_connector *con = &fsl_dev->connector.base;
87 struct drm_display_mode *mode = &crtc->state->mode;
88 unsigned int pol = 0;
89 struct videomode vm;
90
91 clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
92
93 drm_display_mode_to_videomode(mode, &vm);
94
95 /* INV_PXCK as default (most display sample data on rising edge) */
96 if (!(con->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE))
97 pol |= DCU_SYN_POL_INV_PXCK;
98
99 if (vm.flags & DISPLAY_FLAGS_HSYNC_LOW)
100 pol |= DCU_SYN_POL_INV_HS_LOW;
101
102 if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW)
103 pol |= DCU_SYN_POL_INV_VS_LOW;
104
105 regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
106 DCU_HSYN_PARA_BP(vm.hback_porch) |
107 DCU_HSYN_PARA_PW(vm.hsync_len) |
108 DCU_HSYN_PARA_FP(vm.hfront_porch));
109 regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
110 DCU_VSYN_PARA_BP(vm.vback_porch) |
111 DCU_VSYN_PARA_PW(vm.vsync_len) |
112 DCU_VSYN_PARA_FP(vm.vfront_porch));
113 regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
114 DCU_DISP_SIZE_DELTA_Y(vm.vactive) |
115 DCU_DISP_SIZE_DELTA_X(vm.hactive));
116 regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
117 regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
118 DCU_BGND_G(0) | DCU_BGND_B(0));
119 regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
120 DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
121 regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
122 DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
123 DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
124 DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
125 return;
126}
127
128static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
129 .atomic_disable = fsl_dcu_drm_crtc_atomic_disable,
130 .atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
131 .atomic_enable = fsl_dcu_drm_crtc_atomic_enable,
132 .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
133};
134
135static int fsl_dcu_drm_crtc_enable_vblank(struct drm_crtc *crtc)
136{
137 struct drm_device *dev = crtc->dev;
138 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
139 unsigned int value;
140
141 regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
142 value &= ~DCU_INT_MASK_VBLANK;
143 regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
144
145 return 0;
146}
147
148static void fsl_dcu_drm_crtc_disable_vblank(struct drm_crtc *crtc)
149{
150 struct drm_device *dev = crtc->dev;
151 struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
152 unsigned int value;
153
154 regmap_read(fsl_dev->regmap, DCU_INT_MASK, &value);
155 value |= DCU_INT_MASK_VBLANK;
156 regmap_write(fsl_dev->regmap, DCU_INT_MASK, value);
157}
158
159static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
160 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
161 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
162 .destroy = drm_crtc_cleanup,
163 .page_flip = drm_atomic_helper_page_flip,
164 .reset = drm_atomic_helper_crtc_reset,
165 .set_config = drm_atomic_helper_set_config,
166 .enable_vblank = fsl_dcu_drm_crtc_enable_vblank,
167 .disable_vblank = fsl_dcu_drm_crtc_disable_vblank,
168};
169
170int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
171{
172 struct drm_plane *primary;
173 struct drm_crtc *crtc = &fsl_dev->crtc;
174 int ret;
175
176 fsl_dcu_drm_init_planes(fsl_dev->drm);
177
178 primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
179 if (!primary)
180 return -ENOMEM;
181
182 ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
183 &fsl_dcu_drm_crtc_funcs, NULL);
184 if (ret) {
185 primary->funcs->destroy(primary);
186 return ret;
187 }
188
189 drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
190
191 return 0;
192}