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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016 MediaTek Inc.
4 */
5
6#include <linux/delay.h>
7#include <linux/err.h>
8#include <linux/gpio/consumer.h>
9#include <linux/i2c.h>
10#include <linux/module.h>
11#include <linux/of_graph.h>
12#include <linux/pm_runtime.h>
13#include <linux/regmap.h>
14#include <linux/regulator/consumer.h>
15
16#include <drm/display/drm_dp_aux_bus.h>
17#include <drm/display/drm_dp_helper.h>
18#include <drm/drm_bridge.h>
19#include <drm/drm_edid.h>
20#include <drm/drm_mipi_dsi.h>
21#include <drm/drm_of.h>
22#include <drm/drm_panel.h>
23#include <drm/drm_print.h>
24
25#define PAGE0_AUXCH_CFG3 0x76
26#define AUXCH_CFG3_RESET 0xff
27#define PAGE0_SWAUX_ADDR_7_0 0x7d
28#define PAGE0_SWAUX_ADDR_15_8 0x7e
29#define PAGE0_SWAUX_ADDR_23_16 0x7f
30#define SWAUX_ADDR_MASK GENMASK(19, 0)
31#define PAGE0_SWAUX_LENGTH 0x80
32#define SWAUX_LENGTH_MASK GENMASK(3, 0)
33#define SWAUX_NO_PAYLOAD BIT(7)
34#define PAGE0_SWAUX_WDATA 0x81
35#define PAGE0_SWAUX_RDATA 0x82
36#define PAGE0_SWAUX_CTRL 0x83
37#define SWAUX_SEND BIT(0)
38#define PAGE0_SWAUX_STATUS 0x84
39#define SWAUX_M_MASK GENMASK(4, 0)
40#define SWAUX_STATUS_MASK GENMASK(7, 5)
41#define SWAUX_STATUS_NACK (0x1 << 5)
42#define SWAUX_STATUS_DEFER (0x2 << 5)
43#define SWAUX_STATUS_ACKM (0x3 << 5)
44#define SWAUX_STATUS_INVALID (0x4 << 5)
45#define SWAUX_STATUS_I2C_NACK (0x5 << 5)
46#define SWAUX_STATUS_I2C_DEFER (0x6 << 5)
47#define SWAUX_STATUS_TIMEOUT (0x7 << 5)
48
49#define PAGE2_GPIO_H 0xa7
50#define PS_GPIO9 BIT(1)
51#define PAGE2_I2C_BYPASS 0xea
52#define I2C_BYPASS_EN 0xd0
53#define PAGE2_MCS_EN 0xf3
54#define MCS_EN BIT(0)
55
56#define PAGE3_SET_ADD 0xfe
57#define VDO_CTL_ADD 0x13
58#define VDO_DIS 0x18
59#define VDO_EN 0x1c
60
61#define NUM_MIPI_LANES 4
62
63#define COMMON_PS8640_REGMAP_CONFIG \
64 .reg_bits = 8, \
65 .val_bits = 8, \
66 .cache_type = REGCACHE_NONE
67
68/*
69 * PS8640 uses multiple addresses:
70 * page[0]: for DP control
71 * page[1]: for VIDEO Bridge
72 * page[2]: for control top
73 * page[3]: for DSI Link Control1
74 * page[4]: for MIPI Phy
75 * page[5]: for VPLL
76 * page[6]: for DSI Link Control2
77 * page[7]: for SPI ROM mapping
78 */
79enum page_addr_offset {
80 PAGE0_DP_CNTL = 0,
81 PAGE1_VDO_BDG,
82 PAGE2_TOP_CNTL,
83 PAGE3_DSI_CNTL1,
84 PAGE4_MIPI_PHY,
85 PAGE5_VPLL,
86 PAGE6_DSI_CNTL2,
87 PAGE7_SPI_CNTL,
88 MAX_DEVS
89};
90
91enum ps8640_vdo_control {
92 DISABLE = VDO_DIS,
93 ENABLE = VDO_EN,
94};
95
96struct ps8640 {
97 struct drm_bridge bridge;
98 struct drm_bridge *panel_bridge;
99 struct drm_dp_aux aux;
100 struct mipi_dsi_device *dsi;
101 struct i2c_client *page[MAX_DEVS];
102 struct regmap *regmap[MAX_DEVS];
103 struct regulator_bulk_data supplies[2];
104 struct gpio_desc *gpio_reset;
105 struct gpio_desc *gpio_powerdown;
106 struct device_link *link;
107 bool pre_enabled;
108 bool need_post_hpd_delay;
109};
110
111static const struct regmap_config ps8640_regmap_config[] = {
112 [PAGE0_DP_CNTL] = {
113 COMMON_PS8640_REGMAP_CONFIG,
114 .max_register = 0xbf,
115 },
116 [PAGE1_VDO_BDG] = {
117 COMMON_PS8640_REGMAP_CONFIG,
118 .max_register = 0xff,
119 },
120 [PAGE2_TOP_CNTL] = {
121 COMMON_PS8640_REGMAP_CONFIG,
122 .max_register = 0xff,
123 },
124 [PAGE3_DSI_CNTL1] = {
125 COMMON_PS8640_REGMAP_CONFIG,
126 .max_register = 0xff,
127 },
128 [PAGE4_MIPI_PHY] = {
129 COMMON_PS8640_REGMAP_CONFIG,
130 .max_register = 0xff,
131 },
132 [PAGE5_VPLL] = {
133 COMMON_PS8640_REGMAP_CONFIG,
134 .max_register = 0x7f,
135 },
136 [PAGE6_DSI_CNTL2] = {
137 COMMON_PS8640_REGMAP_CONFIG,
138 .max_register = 0xff,
139 },
140 [PAGE7_SPI_CNTL] = {
141 COMMON_PS8640_REGMAP_CONFIG,
142 .max_register = 0xff,
143 },
144};
145
146static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
147{
148 return container_of(e, struct ps8640, bridge);
149}
150
151static inline struct ps8640 *aux_to_ps8640(struct drm_dp_aux *aux)
152{
153 return container_of(aux, struct ps8640, aux);
154}
155
156static bool ps8640_of_panel_on_aux_bus(struct device *dev)
157{
158 struct device_node *bus, *panel;
159
160 bus = of_get_child_by_name(dev->of_node, "aux-bus");
161 if (!bus)
162 return false;
163
164 panel = of_get_child_by_name(bus, "panel");
165 of_node_put(bus);
166 if (!panel)
167 return false;
168 of_node_put(panel);
169
170 return true;
171}
172
173static int _ps8640_wait_hpd_asserted(struct ps8640 *ps_bridge, unsigned long wait_us)
174{
175 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
176 int status;
177 int ret;
178
179 /*
180 * Apparently something about the firmware in the chip signals that
181 * HPD goes high by reporting GPIO9 as high (even though HPD isn't
182 * actually connected to GPIO9).
183 */
184 ret = regmap_read_poll_timeout(map, PAGE2_GPIO_H, status,
185 status & PS_GPIO9, wait_us / 10, wait_us);
186
187 /*
188 * The first time we see HPD go high after a reset we delay an extra
189 * 50 ms. The best guess is that the MCU is doing "stuff" during this
190 * time (maybe talking to the panel) and we don't want to interrupt it.
191 *
192 * No locking is done around "need_post_hpd_delay". If we're here we
193 * know we're holding a PM Runtime reference and the only other place
194 * that touches this is PM Runtime resume.
195 */
196 if (!ret && ps_bridge->need_post_hpd_delay) {
197 ps_bridge->need_post_hpd_delay = false;
198 msleep(50);
199 }
200
201 return ret;
202}
203
204static int ps8640_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
205{
206 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
207 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
208 int ret;
209
210 /*
211 * Note that this function is called by code that has already powered
212 * the panel. We have to power ourselves up but we don't need to worry
213 * about powering the panel.
214 */
215 pm_runtime_get_sync(dev);
216 ret = _ps8640_wait_hpd_asserted(ps_bridge, wait_us);
217 pm_runtime_mark_last_busy(dev);
218 pm_runtime_put_autosuspend(dev);
219
220 return ret;
221}
222
223static ssize_t ps8640_aux_transfer_msg(struct drm_dp_aux *aux,
224 struct drm_dp_aux_msg *msg)
225{
226 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
227 struct regmap *map = ps_bridge->regmap[PAGE0_DP_CNTL];
228 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
229 unsigned int len = msg->size;
230 unsigned int data;
231 unsigned int base;
232 int ret;
233 u8 request = msg->request &
234 ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
235 u8 *buf = msg->buffer;
236 u8 addr_len[PAGE0_SWAUX_LENGTH + 1 - PAGE0_SWAUX_ADDR_7_0];
237 u8 i;
238 bool is_native_aux = false;
239
240 if (len > DP_AUX_MAX_PAYLOAD_BYTES)
241 return -EINVAL;
242
243 if (msg->address & ~SWAUX_ADDR_MASK)
244 return -EINVAL;
245
246 switch (request) {
247 case DP_AUX_NATIVE_WRITE:
248 case DP_AUX_NATIVE_READ:
249 is_native_aux = true;
250 fallthrough;
251 case DP_AUX_I2C_WRITE:
252 case DP_AUX_I2C_READ:
253 break;
254 default:
255 return -EINVAL;
256 }
257
258 ret = regmap_write(map, PAGE0_AUXCH_CFG3, AUXCH_CFG3_RESET);
259 if (ret) {
260 DRM_DEV_ERROR(dev, "failed to write PAGE0_AUXCH_CFG3: %d\n",
261 ret);
262 return ret;
263 }
264
265 /* Assume it's good */
266 msg->reply = 0;
267
268 base = PAGE0_SWAUX_ADDR_7_0;
269 addr_len[PAGE0_SWAUX_ADDR_7_0 - base] = msg->address;
270 addr_len[PAGE0_SWAUX_ADDR_15_8 - base] = msg->address >> 8;
271 addr_len[PAGE0_SWAUX_ADDR_23_16 - base] = (msg->address >> 16) |
272 (msg->request << 4);
273 addr_len[PAGE0_SWAUX_LENGTH - base] = (len == 0) ? SWAUX_NO_PAYLOAD :
274 ((len - 1) & SWAUX_LENGTH_MASK);
275
276 regmap_bulk_write(map, PAGE0_SWAUX_ADDR_7_0, addr_len,
277 ARRAY_SIZE(addr_len));
278
279 if (len && (request == DP_AUX_NATIVE_WRITE ||
280 request == DP_AUX_I2C_WRITE)) {
281 /* Write to the internal FIFO buffer */
282 for (i = 0; i < len; i++) {
283 ret = regmap_write(map, PAGE0_SWAUX_WDATA, buf[i]);
284 if (ret) {
285 DRM_DEV_ERROR(dev,
286 "failed to write WDATA: %d\n",
287 ret);
288 return ret;
289 }
290 }
291 }
292
293 regmap_write(map, PAGE0_SWAUX_CTRL, SWAUX_SEND);
294
295 /* Zero delay loop because i2c transactions are slow already */
296 regmap_read_poll_timeout(map, PAGE0_SWAUX_CTRL, data,
297 !(data & SWAUX_SEND), 0, 50 * 1000);
298
299 regmap_read(map, PAGE0_SWAUX_STATUS, &data);
300 if (ret) {
301 DRM_DEV_ERROR(dev, "failed to read PAGE0_SWAUX_STATUS: %d\n",
302 ret);
303 return ret;
304 }
305
306 switch (data & SWAUX_STATUS_MASK) {
307 case SWAUX_STATUS_NACK:
308 case SWAUX_STATUS_I2C_NACK:
309 /*
310 * The programming guide is not clear about whether a I2C NACK
311 * would trigger SWAUX_STATUS_NACK or SWAUX_STATUS_I2C_NACK. So
312 * we handle both cases together.
313 */
314 if (is_native_aux)
315 msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
316 else
317 msg->reply |= DP_AUX_I2C_REPLY_NACK;
318
319 fallthrough;
320 case SWAUX_STATUS_ACKM:
321 len = data & SWAUX_M_MASK;
322 break;
323 case SWAUX_STATUS_DEFER:
324 case SWAUX_STATUS_I2C_DEFER:
325 if (is_native_aux)
326 msg->reply |= DP_AUX_NATIVE_REPLY_DEFER;
327 else
328 msg->reply |= DP_AUX_I2C_REPLY_DEFER;
329 len = data & SWAUX_M_MASK;
330 break;
331 case SWAUX_STATUS_INVALID:
332 return -EOPNOTSUPP;
333 case SWAUX_STATUS_TIMEOUT:
334 return -ETIMEDOUT;
335 }
336
337 if (len && (request == DP_AUX_NATIVE_READ ||
338 request == DP_AUX_I2C_READ)) {
339 /* Read from the internal FIFO buffer */
340 for (i = 0; i < len; i++) {
341 ret = regmap_read(map, PAGE0_SWAUX_RDATA, &data);
342 if (ret) {
343 DRM_DEV_ERROR(dev,
344 "failed to read RDATA: %d\n",
345 ret);
346 return ret;
347 }
348
349 buf[i] = data;
350 }
351 }
352
353 return len;
354}
355
356static ssize_t ps8640_aux_transfer(struct drm_dp_aux *aux,
357 struct drm_dp_aux_msg *msg)
358{
359 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
360 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
361 int ret;
362
363 pm_runtime_get_sync(dev);
364 ret = ps8640_aux_transfer_msg(aux, msg);
365 pm_runtime_mark_last_busy(dev);
366 pm_runtime_put_autosuspend(dev);
367
368 return ret;
369}
370
371static void ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
372 const enum ps8640_vdo_control ctrl)
373{
374 struct regmap *map = ps_bridge->regmap[PAGE3_DSI_CNTL1];
375 struct device *dev = &ps_bridge->page[PAGE3_DSI_CNTL1]->dev;
376 u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
377 int ret;
378
379 ret = regmap_bulk_write(map, PAGE3_SET_ADD,
380 vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
381
382 if (ret < 0)
383 dev_err(dev, "failed to %sable VDO: %d\n",
384 ctrl == ENABLE ? "en" : "dis", ret);
385}
386
387static int __maybe_unused ps8640_resume(struct device *dev)
388{
389 struct ps8640 *ps_bridge = dev_get_drvdata(dev);
390 int ret;
391
392 ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
393 ps_bridge->supplies);
394 if (ret < 0) {
395 dev_err(dev, "cannot enable regulators %d\n", ret);
396 return ret;
397 }
398
399 gpiod_set_value(ps_bridge->gpio_powerdown, 0);
400 gpiod_set_value(ps_bridge->gpio_reset, 1);
401 usleep_range(2000, 2500);
402 gpiod_set_value(ps_bridge->gpio_reset, 0);
403 /* Double reset for T4 and T5 */
404 msleep(50);
405 gpiod_set_value(ps_bridge->gpio_reset, 1);
406 msleep(50);
407 gpiod_set_value(ps_bridge->gpio_reset, 0);
408
409 /* We just reset things, so we need a delay after the first HPD */
410 ps_bridge->need_post_hpd_delay = true;
411
412 /*
413 * Mystery 200 ms delay for the "MCU to be ready". It's unclear if
414 * this is truly necessary since the MCU will already signal that
415 * things are "good to go" by signaling HPD on "gpio 9". See
416 * _ps8640_wait_hpd_asserted(). For now we'll keep this mystery delay
417 * just in case.
418 */
419 msleep(200);
420
421 return 0;
422}
423
424static int __maybe_unused ps8640_suspend(struct device *dev)
425{
426 struct ps8640 *ps_bridge = dev_get_drvdata(dev);
427 int ret;
428
429 gpiod_set_value(ps_bridge->gpio_reset, 1);
430 gpiod_set_value(ps_bridge->gpio_powerdown, 1);
431 ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
432 ps_bridge->supplies);
433 if (ret < 0)
434 dev_err(dev, "cannot disable regulators %d\n", ret);
435
436 return ret;
437}
438
439static const struct dev_pm_ops ps8640_pm_ops = {
440 SET_RUNTIME_PM_OPS(ps8640_suspend, ps8640_resume, NULL)
441 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
442 pm_runtime_force_resume)
443};
444
445static void ps8640_pre_enable(struct drm_bridge *bridge)
446{
447 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
448 struct regmap *map = ps_bridge->regmap[PAGE2_TOP_CNTL];
449 struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev;
450 int ret;
451
452 pm_runtime_get_sync(dev);
453 ret = _ps8640_wait_hpd_asserted(ps_bridge, 200 * 1000);
454 if (ret < 0)
455 dev_warn(dev, "HPD didn't go high: %d\n", ret);
456
457 /*
458 * The Manufacturer Command Set (MCS) is a device dependent interface
459 * intended for factory programming of the display module default
460 * parameters. Once the display module is configured, the MCS shall be
461 * disabled by the manufacturer. Once disabled, all MCS commands are
462 * ignored by the display interface.
463 */
464
465 ret = regmap_update_bits(map, PAGE2_MCS_EN, MCS_EN, 0);
466 if (ret < 0)
467 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
468
469 /* Switch access edp panel's edid through i2c */
470 ret = regmap_write(map, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
471 if (ret < 0)
472 dev_warn(dev, "failed write PAGE2_MCS_EN: %d\n", ret);
473
474 ps8640_bridge_vdo_control(ps_bridge, ENABLE);
475
476 ps_bridge->pre_enabled = true;
477}
478
479static void ps8640_post_disable(struct drm_bridge *bridge)
480{
481 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
482
483 ps_bridge->pre_enabled = false;
484
485 ps8640_bridge_vdo_control(ps_bridge, DISABLE);
486 pm_runtime_put_sync_suspend(&ps_bridge->page[PAGE0_DP_CNTL]->dev);
487}
488
489static int ps8640_bridge_attach(struct drm_bridge *bridge,
490 enum drm_bridge_attach_flags flags)
491{
492 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
493 struct device *dev = &ps_bridge->page[0]->dev;
494 int ret;
495
496 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
497 return -EINVAL;
498
499 ps_bridge->aux.drm_dev = bridge->dev;
500 ret = drm_dp_aux_register(&ps_bridge->aux);
501 if (ret) {
502 dev_err(dev, "failed to register DP AUX channel: %d\n", ret);
503 return ret;
504 }
505
506 ps_bridge->link = device_link_add(bridge->dev->dev, dev, DL_FLAG_STATELESS);
507 if (!ps_bridge->link) {
508 dev_err(dev, "failed to create device link");
509 ret = -EINVAL;
510 goto err_devlink;
511 }
512
513 /* Attach the panel-bridge to the dsi bridge */
514 ret = drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
515 &ps_bridge->bridge, flags);
516 if (ret)
517 goto err_bridge_attach;
518
519 return 0;
520
521err_bridge_attach:
522 device_link_del(ps_bridge->link);
523err_devlink:
524 drm_dp_aux_unregister(&ps_bridge->aux);
525
526 return ret;
527}
528
529static void ps8640_bridge_detach(struct drm_bridge *bridge)
530{
531 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
532
533 drm_dp_aux_unregister(&ps_bridge->aux);
534 if (ps_bridge->link)
535 device_link_del(ps_bridge->link);
536}
537
538static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
539 struct drm_connector *connector)
540{
541 struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
542 bool poweroff = !ps_bridge->pre_enabled;
543 struct edid *edid;
544
545 /*
546 * When we end calling get_edid() triggered by an ioctl, i.e
547 *
548 * drm_mode_getconnector (ioctl)
549 * -> drm_helper_probe_single_connector_modes
550 * -> drm_bridge_connector_get_modes
551 * -> ps8640_bridge_get_edid
552 *
553 * We need to make sure that what we need is enabled before reading
554 * EDID, for this chip, we need to do a full poweron, otherwise it will
555 * fail.
556 */
557 drm_bridge_chain_pre_enable(bridge);
558
559 edid = drm_get_edid(connector,
560 ps_bridge->page[PAGE0_DP_CNTL]->adapter);
561
562 /*
563 * If we call the get_edid() function without having enabled the chip
564 * before, return the chip to its original power state.
565 */
566 if (poweroff)
567 drm_bridge_chain_post_disable(bridge);
568
569 return edid;
570}
571
572static void ps8640_runtime_disable(void *data)
573{
574 pm_runtime_dont_use_autosuspend(data);
575 pm_runtime_disable(data);
576}
577
578static const struct drm_bridge_funcs ps8640_bridge_funcs = {
579 .attach = ps8640_bridge_attach,
580 .detach = ps8640_bridge_detach,
581 .get_edid = ps8640_bridge_get_edid,
582 .post_disable = ps8640_post_disable,
583 .pre_enable = ps8640_pre_enable,
584};
585
586static int ps8640_bridge_get_dsi_resources(struct device *dev, struct ps8640 *ps_bridge)
587{
588 struct device_node *in_ep, *dsi_node;
589 struct mipi_dsi_device *dsi;
590 struct mipi_dsi_host *host;
591 const struct mipi_dsi_device_info info = { .type = "ps8640",
592 .channel = 0,
593 .node = NULL,
594 };
595
596 /* port@0 is ps8640 dsi input port */
597 in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
598 if (!in_ep)
599 return -ENODEV;
600
601 dsi_node = of_graph_get_remote_port_parent(in_ep);
602 of_node_put(in_ep);
603 if (!dsi_node)
604 return -ENODEV;
605
606 host = of_find_mipi_dsi_host_by_node(dsi_node);
607 of_node_put(dsi_node);
608 if (!host)
609 return -EPROBE_DEFER;
610
611 dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
612 if (IS_ERR(dsi)) {
613 dev_err(dev, "failed to create dsi device\n");
614 return PTR_ERR(dsi);
615 }
616
617 ps_bridge->dsi = dsi;
618
619 dsi->host = host;
620 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
621 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
622 dsi->format = MIPI_DSI_FMT_RGB888;
623 dsi->lanes = NUM_MIPI_LANES;
624
625 return 0;
626}
627
628static int ps8640_bridge_link_panel(struct drm_dp_aux *aux)
629{
630 struct ps8640 *ps_bridge = aux_to_ps8640(aux);
631 struct device *dev = aux->dev;
632 struct device_node *np = dev->of_node;
633 int ret;
634
635 /*
636 * NOTE about returning -EPROBE_DEFER from this function: if we
637 * return an error (most relevant to -EPROBE_DEFER) it will only
638 * be passed out to ps8640_probe() if it called this directly (AKA the
639 * panel isn't under the "aux-bus" node). That should be fine because
640 * if the panel is under "aux-bus" it's guaranteed to have probed by
641 * the time this function has been called.
642 */
643
644 /* port@1 is ps8640 output port */
645 ps_bridge->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
646 if (IS_ERR(ps_bridge->panel_bridge))
647 return PTR_ERR(ps_bridge->panel_bridge);
648
649 ret = devm_drm_bridge_add(dev, &ps_bridge->bridge);
650 if (ret)
651 return ret;
652
653 return devm_mipi_dsi_attach(dev, ps_bridge->dsi);
654}
655
656static int ps8640_probe(struct i2c_client *client)
657{
658 struct device *dev = &client->dev;
659 struct ps8640 *ps_bridge;
660 int ret;
661 u32 i;
662
663 ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
664 if (!ps_bridge)
665 return -ENOMEM;
666
667 ps_bridge->supplies[0].supply = "vdd12";
668 ps_bridge->supplies[1].supply = "vdd33";
669 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
670 ps_bridge->supplies);
671 if (ret)
672 return ret;
673
674 ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
675 GPIOD_OUT_HIGH);
676 if (IS_ERR(ps_bridge->gpio_powerdown))
677 return PTR_ERR(ps_bridge->gpio_powerdown);
678
679 /*
680 * Assert the reset to avoid the bridge being initialized prematurely
681 */
682 ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
683 GPIOD_OUT_HIGH);
684 if (IS_ERR(ps_bridge->gpio_reset))
685 return PTR_ERR(ps_bridge->gpio_reset);
686
687 ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
688 ps_bridge->bridge.of_node = dev->of_node;
689 ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
690
691 /*
692 * In the device tree, if panel is listed under aux-bus of the bridge
693 * node, panel driver should be able to retrieve EDID by itself using
694 * aux-bus. So let's not set DRM_BRIDGE_OP_EDID here.
695 */
696 if (!ps8640_of_panel_on_aux_bus(&client->dev))
697 ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
698
699 /*
700 * Get MIPI DSI resources early. These can return -EPROBE_DEFER so
701 * we want to get them out of the way sooner.
702 */
703 ret = ps8640_bridge_get_dsi_resources(&client->dev, ps_bridge);
704 if (ret)
705 return ret;
706
707 ps_bridge->page[PAGE0_DP_CNTL] = client;
708
709 ps_bridge->regmap[PAGE0_DP_CNTL] = devm_regmap_init_i2c(client, ps8640_regmap_config);
710 if (IS_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]))
711 return PTR_ERR(ps_bridge->regmap[PAGE0_DP_CNTL]);
712
713 for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
714 ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
715 client->adapter,
716 client->addr + i);
717 if (IS_ERR(ps_bridge->page[i]))
718 return PTR_ERR(ps_bridge->page[i]);
719
720 ps_bridge->regmap[i] = devm_regmap_init_i2c(ps_bridge->page[i],
721 ps8640_regmap_config + i);
722 if (IS_ERR(ps_bridge->regmap[i]))
723 return PTR_ERR(ps_bridge->regmap[i]);
724 }
725
726 i2c_set_clientdata(client, ps_bridge);
727
728 ps_bridge->aux.name = "parade-ps8640-aux";
729 ps_bridge->aux.dev = dev;
730 ps_bridge->aux.transfer = ps8640_aux_transfer;
731 ps_bridge->aux.wait_hpd_asserted = ps8640_wait_hpd_asserted;
732 drm_dp_aux_init(&ps_bridge->aux);
733
734 pm_runtime_enable(dev);
735 /*
736 * Powering on ps8640 takes ~300ms. To avoid wasting time on power
737 * cycling ps8640 too often, set autosuspend_delay to 1000ms to ensure
738 * the bridge wouldn't suspend in between each _aux_transfer_msg() call
739 * during EDID read (~20ms in my experiment) and in between the last
740 * _aux_transfer_msg() call during EDID read and the _pre_enable() call
741 * (~100ms in my experiment).
742 */
743 pm_runtime_set_autosuspend_delay(dev, 1000);
744 pm_runtime_use_autosuspend(dev);
745 pm_suspend_ignore_children(dev, true);
746 ret = devm_add_action_or_reset(dev, ps8640_runtime_disable, dev);
747 if (ret)
748 return ret;
749
750 ret = devm_of_dp_aux_populate_bus(&ps_bridge->aux, ps8640_bridge_link_panel);
751
752 /*
753 * If devm_of_dp_aux_populate_bus() returns -ENODEV then it's up to
754 * usa to call ps8640_bridge_link_panel() directly. NOTE: in this case
755 * the function is allowed to -EPROBE_DEFER.
756 */
757 if (ret == -ENODEV)
758 return ps8640_bridge_link_panel(&ps_bridge->aux);
759
760 return ret;
761}
762
763static const struct of_device_id ps8640_match[] = {
764 { .compatible = "parade,ps8640" },
765 { }
766};
767MODULE_DEVICE_TABLE(of, ps8640_match);
768
769static struct i2c_driver ps8640_driver = {
770 .probe_new = ps8640_probe,
771 .driver = {
772 .name = "ps8640",
773 .of_match_table = ps8640_match,
774 .pm = &ps8640_pm_ops,
775 },
776};
777module_i2c_driver(ps8640_driver);
778
779MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
780MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
781MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
782MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
783MODULE_LICENSE("GPL v2");