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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/*
24 * This file defines the private interface between the
25 * AMD kernel graphics drivers and the AMD KFD.
26 */
27
28#ifndef KGD_KFD_INTERFACE_H_INCLUDED
29#define KGD_KFD_INTERFACE_H_INCLUDED
30
31#include <linux/types.h>
32
33struct pci_dev;
34
35#define KFD_INTERFACE_VERSION 1
36
37struct kfd_dev;
38struct kgd_dev;
39
40struct kgd_mem;
41
42enum kgd_memory_pool {
43 KGD_POOL_SYSTEM_CACHEABLE = 1,
44 KGD_POOL_SYSTEM_WRITECOMBINE = 2,
45 KGD_POOL_FRAMEBUFFER = 3,
46};
47
48enum kgd_engine_type {
49 KGD_ENGINE_PFP = 1,
50 KGD_ENGINE_ME,
51 KGD_ENGINE_CE,
52 KGD_ENGINE_MEC1,
53 KGD_ENGINE_MEC2,
54 KGD_ENGINE_RLC,
55 KGD_ENGINE_SDMA1,
56 KGD_ENGINE_SDMA2,
57 KGD_ENGINE_MAX
58};
59
60struct kgd2kfd_shared_resources {
61 /* Bit n == 1 means VMID n is available for KFD. */
62 unsigned int compute_vmid_bitmap;
63
64 /* Compute pipes are counted starting from MEC0/pipe0 as 0. */
65 unsigned int first_compute_pipe;
66
67 /* Number of MEC pipes available for KFD. */
68 unsigned int compute_pipe_count;
69
70 /* Base address of doorbell aperture. */
71 phys_addr_t doorbell_physical_address;
72
73 /* Size in bytes of doorbell aperture. */
74 size_t doorbell_aperture_size;
75
76 /* Number of bytes at start of aperture reserved for KGD. */
77 size_t doorbell_start_offset;
78};
79
80/**
81 * struct kfd2kgd_calls
82 *
83 * @init_gtt_mem_allocation: Allocate a buffer on the gart aperture.
84 * The buffer can be used for mqds, hpds, kernel queue, fence and runlists
85 *
86 * @free_gtt_mem: Frees a buffer that was allocated on the gart aperture
87 *
88 * @get_vmem_size: Retrieves (physical) size of VRAM
89 *
90 * @get_gpu_clock_counter: Retrieves GPU clock counter
91 *
92 * @get_max_engine_clock_in_mhz: Retrieves maximum GPU clock in MHz
93 *
94 * @program_sh_mem_settings: A function that should initiate the memory
95 * properties such as main aperture memory type (cache / non cached) and
96 * secondary aperture base address, size and memory type.
97 * This function is used only for no cp scheduling mode.
98 *
99 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
100 * scheduling mode. Only used for no cp scheduling mode.
101 *
102 * @init_pipeline: Initialized the compute pipelines.
103 *
104 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
105 * sceduling mode.
106 *
107 * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
108 * used only for no HWS mode.
109 *
110 * @hqd_is_occupies: Checks if a hqd slot is occupied.
111 *
112 * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
113 *
114 * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
115 *
116 * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
117 * SDMA hqd slot.
118 *
119 * @get_fw_version: Returns FW versions from the header
120 *
121 * This structure contains function pointers to services that the kgd driver
122 * provides to amdkfd driver.
123 *
124 */
125struct kfd2kgd_calls {
126 int (*init_gtt_mem_allocation)(struct kgd_dev *kgd, size_t size,
127 void **mem_obj, uint64_t *gpu_addr,
128 void **cpu_ptr);
129
130 void (*free_gtt_mem)(struct kgd_dev *kgd, void *mem_obj);
131
132 uint64_t (*get_vmem_size)(struct kgd_dev *kgd);
133 uint64_t (*get_gpu_clock_counter)(struct kgd_dev *kgd);
134
135 uint32_t (*get_max_engine_clock_in_mhz)(struct kgd_dev *kgd);
136
137 /* Register access functions */
138 void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
139 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
140 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
141
142 int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, unsigned int pasid,
143 unsigned int vmid);
144
145 int (*init_pipeline)(struct kgd_dev *kgd, uint32_t pipe_id,
146 uint32_t hpd_size, uint64_t hpd_gpu_addr);
147
148 int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id);
149
150 int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
151 uint32_t queue_id, uint32_t __user *wptr);
152
153 int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd);
154
155 bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
156 uint32_t pipe_id, uint32_t queue_id);
157
158 int (*hqd_destroy)(struct kgd_dev *kgd, uint32_t reset_type,
159 unsigned int timeout, uint32_t pipe_id,
160 uint32_t queue_id);
161
162 bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd);
163
164 int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
165 unsigned int timeout);
166
167 int (*address_watch_disable)(struct kgd_dev *kgd);
168 int (*address_watch_execute)(struct kgd_dev *kgd,
169 unsigned int watch_point_id,
170 uint32_t cntl_val,
171 uint32_t addr_hi,
172 uint32_t addr_lo);
173 int (*wave_control_execute)(struct kgd_dev *kgd,
174 uint32_t gfx_index_val,
175 uint32_t sq_cmd);
176 uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
177 unsigned int watch_point_id,
178 unsigned int reg_offset);
179 bool (*get_atc_vmid_pasid_mapping_valid)(
180 struct kgd_dev *kgd,
181 uint8_t vmid);
182 uint16_t (*get_atc_vmid_pasid_mapping_pasid)(
183 struct kgd_dev *kgd,
184 uint8_t vmid);
185 void (*write_vmid_invalidate_request)(struct kgd_dev *kgd,
186 uint8_t vmid);
187
188 uint16_t (*get_fw_version)(struct kgd_dev *kgd,
189 enum kgd_engine_type type);
190};
191
192/**
193 * struct kgd2kfd_calls
194 *
195 * @exit: Notifies amdkfd that kgd module is unloaded
196 *
197 * @probe: Notifies amdkfd about a probe done on a device in the kgd driver.
198 *
199 * @device_init: Initialize the newly probed device (if it is a device that
200 * amdkfd supports)
201 *
202 * @device_exit: Notifies amdkfd about a removal of a kgd device
203 *
204 * @suspend: Notifies amdkfd about a suspend action done to a kgd device
205 *
206 * @resume: Notifies amdkfd about a resume action done to a kgd device
207 *
208 * This structure contains function callback pointers so the kgd driver
209 * will notify to the amdkfd about certain status changes.
210 *
211 */
212struct kgd2kfd_calls {
213 void (*exit)(void);
214 struct kfd_dev* (*probe)(struct kgd_dev *kgd, struct pci_dev *pdev,
215 const struct kfd2kgd_calls *f2g);
216 bool (*device_init)(struct kfd_dev *kfd,
217 const struct kgd2kfd_shared_resources *gpu_resources);
218 void (*device_exit)(struct kfd_dev *kfd);
219 void (*interrupt)(struct kfd_dev *kfd, const void *ih_ring_entry);
220 void (*suspend)(struct kfd_dev *kfd);
221 int (*resume)(struct kfd_dev *kfd);
222};
223
224int kgd2kfd_init(unsigned interface_version,
225 const struct kgd2kfd_calls **g2f);
226
227#endif /* KGD_KFD_INTERFACE_H_INCLUDED */
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/*
24 * This file defines the private interface between the
25 * AMD kernel graphics drivers and the AMD KFD.
26 */
27
28#ifndef KGD_KFD_INTERFACE_H_INCLUDED
29#define KGD_KFD_INTERFACE_H_INCLUDED
30
31#include <linux/types.h>
32#include <linux/bitmap.h>
33#include <linux/dma-fence.h>
34
35struct pci_dev;
36struct amdgpu_device;
37
38#define KGD_MAX_QUEUES 128
39
40struct kfd_dev;
41struct kgd_mem;
42
43enum kfd_preempt_type {
44 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
45 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
46 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE
47};
48
49struct kfd_vm_fault_info {
50 uint64_t page_addr;
51 uint32_t vmid;
52 uint32_t mc_id;
53 uint32_t status;
54 bool prot_valid;
55 bool prot_read;
56 bool prot_write;
57 bool prot_exec;
58};
59
60struct kfd_cu_info {
61 uint32_t num_shader_engines;
62 uint32_t num_shader_arrays_per_engine;
63 uint32_t num_cu_per_sh;
64 uint32_t cu_active_number;
65 uint32_t cu_ao_mask;
66 uint32_t simd_per_cu;
67 uint32_t max_waves_per_simd;
68 uint32_t wave_front_size;
69 uint32_t max_scratch_slots_per_cu;
70 uint32_t lds_size;
71 uint32_t cu_bitmap[4][4];
72};
73
74/* For getting GPU local memory information from KGD */
75struct kfd_local_mem_info {
76 uint64_t local_mem_size_private;
77 uint64_t local_mem_size_public;
78 uint32_t vram_width;
79 uint32_t mem_clk_max;
80};
81
82enum kgd_memory_pool {
83 KGD_POOL_SYSTEM_CACHEABLE = 1,
84 KGD_POOL_SYSTEM_WRITECOMBINE = 2,
85 KGD_POOL_FRAMEBUFFER = 3,
86};
87
88/**
89 * enum kfd_sched_policy
90 *
91 * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
92 * scheduling. In this scheduling mode we're using the firmware code to
93 * schedule the user mode queues and kernel queues such as HIQ and DIQ.
94 * the HIQ queue is used as a special queue that dispatches the configuration
95 * to the cp and the user mode queues list that are currently running.
96 * the DIQ queue is a debugging queue that dispatches debugging commands to the
97 * firmware.
98 * in this scheduling mode user mode queues over subscription feature is
99 * enabled.
100 *
101 * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
102 * subscription feature disabled.
103 *
104 * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
105 * set the command processor registers and sets the queues "manually". This
106 * mode is used *ONLY* for debugging proposes.
107 *
108 */
109enum kfd_sched_policy {
110 KFD_SCHED_POLICY_HWS = 0,
111 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
112 KFD_SCHED_POLICY_NO_HWS
113};
114
115struct kgd2kfd_shared_resources {
116 /* Bit n == 1 means VMID n is available for KFD. */
117 unsigned int compute_vmid_bitmap;
118
119 /* number of pipes per mec */
120 uint32_t num_pipe_per_mec;
121
122 /* number of queues per pipe */
123 uint32_t num_queue_per_pipe;
124
125 /* Bit n == 1 means Queue n is available for KFD */
126 DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
127
128 /* SDMA doorbell assignments (SOC15 and later chips only). Only
129 * specific doorbells are routed to each SDMA engine. Others
130 * are routed to IH and VCN. They are not usable by the CP.
131 */
132 uint32_t *sdma_doorbell_idx;
133
134 /* From SOC15 onward, the doorbell index range not usable for CP
135 * queues.
136 */
137 uint32_t non_cp_doorbells_start;
138 uint32_t non_cp_doorbells_end;
139
140 /* Base address of doorbell aperture. */
141 phys_addr_t doorbell_physical_address;
142
143 /* Size in bytes of doorbell aperture. */
144 size_t doorbell_aperture_size;
145
146 /* Number of bytes at start of aperture reserved for KGD. */
147 size_t doorbell_start_offset;
148
149 /* GPUVM address space size in bytes */
150 uint64_t gpuvm_size;
151
152 /* Minor device number of the render node */
153 int drm_render_minor;
154
155 bool enable_mes;
156};
157
158struct tile_config {
159 uint32_t *tile_config_ptr;
160 uint32_t *macro_tile_config_ptr;
161 uint32_t num_tile_configs;
162 uint32_t num_macro_tile_configs;
163
164 uint32_t gb_addr_config;
165 uint32_t num_banks;
166 uint32_t num_ranks;
167};
168
169#define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
170
171/**
172 * struct kfd2kgd_calls
173 *
174 * @program_sh_mem_settings: A function that should initiate the memory
175 * properties such as main aperture memory type (cache / non cached) and
176 * secondary aperture base address, size and memory type.
177 * This function is used only for no cp scheduling mode.
178 *
179 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
180 * scheduling mode. Only used for no cp scheduling mode.
181 *
182 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
183 * sceduling mode.
184 *
185 * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
186 * used only for no HWS mode.
187 *
188 * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
189 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
190 *
191 * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
192 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
193 *
194 * @hqd_is_occupies: Checks if a hqd slot is occupied.
195 *
196 * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
197 *
198 * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
199 *
200 * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
201 * SDMA hqd slot.
202 *
203 * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
204 * Only used for no cp scheduling mode
205 *
206 * @set_vm_context_page_table_base: Program page table base for a VMID
207 *
208 * @invalidate_tlbs: Invalidate TLBs for a specific PASID
209 *
210 * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
211 *
212 * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
213 * IH ring entry. This function allows the KFD ISR to get the VMID
214 * from the fault status register as early as possible.
215 *
216 * @get_cu_occupancy: Function pointer that returns to caller the number
217 * of wave fronts that are in flight for all of the queues of a process
218 * as identified by its pasid. It is important to note that the value
219 * returned by this function is a snapshot of current moment and cannot
220 * guarantee any minimum for the number of waves in-flight. This function
221 * is defined for devices that belong to GFX9 and later GFX families. Care
222 * must be taken in calling this function as it is not defined for devices
223 * that belong to GFX8 and below GFX families.
224 *
225 * This structure contains function pointers to services that the kgd driver
226 * provides to amdkfd driver.
227 *
228 */
229struct kfd2kgd_calls {
230 /* Register access functions */
231 void (*program_sh_mem_settings)(struct amdgpu_device *adev, uint32_t vmid,
232 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
233 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
234
235 int (*set_pasid_vmid_mapping)(struct amdgpu_device *adev, u32 pasid,
236 unsigned int vmid);
237
238 int (*init_interrupts)(struct amdgpu_device *adev, uint32_t pipe_id);
239
240 int (*hqd_load)(struct amdgpu_device *adev, void *mqd, uint32_t pipe_id,
241 uint32_t queue_id, uint32_t __user *wptr,
242 uint32_t wptr_shift, uint32_t wptr_mask,
243 struct mm_struct *mm);
244
245 int (*hiq_mqd_load)(struct amdgpu_device *adev, void *mqd,
246 uint32_t pipe_id, uint32_t queue_id,
247 uint32_t doorbell_off);
248
249 int (*hqd_sdma_load)(struct amdgpu_device *adev, void *mqd,
250 uint32_t __user *wptr, struct mm_struct *mm);
251
252 int (*hqd_dump)(struct amdgpu_device *adev,
253 uint32_t pipe_id, uint32_t queue_id,
254 uint32_t (**dump)[2], uint32_t *n_regs);
255
256 int (*hqd_sdma_dump)(struct amdgpu_device *adev,
257 uint32_t engine_id, uint32_t queue_id,
258 uint32_t (**dump)[2], uint32_t *n_regs);
259
260 bool (*hqd_is_occupied)(struct amdgpu_device *adev,
261 uint64_t queue_address, uint32_t pipe_id,
262 uint32_t queue_id);
263
264 int (*hqd_destroy)(struct amdgpu_device *adev, void *mqd,
265 enum kfd_preempt_type reset_type,
266 unsigned int timeout, uint32_t pipe_id,
267 uint32_t queue_id);
268
269 bool (*hqd_sdma_is_occupied)(struct amdgpu_device *adev, void *mqd);
270
271 int (*hqd_sdma_destroy)(struct amdgpu_device *adev, void *mqd,
272 unsigned int timeout);
273
274 int (*wave_control_execute)(struct amdgpu_device *adev,
275 uint32_t gfx_index_val,
276 uint32_t sq_cmd);
277 bool (*get_atc_vmid_pasid_mapping_info)(struct amdgpu_device *adev,
278 uint8_t vmid,
279 uint16_t *p_pasid);
280
281 /* No longer needed from GFXv9 onward. The scratch base address is
282 * passed to the shader by the CP. It's the user mode driver's
283 * responsibility.
284 */
285 void (*set_scratch_backing_va)(struct amdgpu_device *adev,
286 uint64_t va, uint32_t vmid);
287
288 void (*set_vm_context_page_table_base)(struct amdgpu_device *adev,
289 uint32_t vmid, uint64_t page_table_base);
290 uint32_t (*read_vmid_from_vmfault_reg)(struct amdgpu_device *adev);
291
292 void (*get_cu_occupancy)(struct amdgpu_device *adev, int pasid,
293 int *wave_cnt, int *max_waves_per_cu);
294 void (*program_trap_handler_settings)(struct amdgpu_device *adev,
295 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr);
296};
297
298#endif /* KGD_KFD_INTERFACE_H_INCLUDED */